Light-emitting element and display device

Abstract

The invention provides a light emitting element and a display device. The light emitting element includes: a semiconductor layer including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer, and defining at least one groove recessed downward from one surface of the first semiconductor layer; a first protective layer on a side surface of the semiconductor layer, on a top surface of the first semiconductor layer, and on the third semiconductor layer and on an inner surface of the semiconductor layer in the recess; and a wavelength conversion layer containing wavelength conversion particles in the recess.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0197321, filed with the Korean Intellectual Property Office on December 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a light - emitting element and a display device. Background art

[0004] With the development of multimedia technology, the importance of display devices has been steadily increasing. Along with this trend, various types of display devices have been used, such as organic light - emitting displays (OLEDs), liquid - crystal displays (LCDs), etc.

[0005] A display device is a device for displaying an image and includes a display panel, such as an organic light - emitting display panel or a liquid - crystal display panel. The light - emitting display panel may include a light - emitting element (e.g., a light - emitting diode (LED)). Examples of light - emitting diodes include an organic light - emitting diode (OLED) using an organic material as a light - emitting material and an inorganic light - emitting diode using an inorganic material as a light - emitting material. Summary of the invention

[0006] Aspects of the present disclosure provide a light - emitting element and a display device capable of securing a wavelength - converting material and a method of increasing the height of its partition walls.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments, a light - emitting element includes: a semiconductor layer including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer, and defining at least one groove recessed downward from one surface of the first semiconductor layer; a first protective layer on a side surface of the semiconductor layer, on a top surface of the first semiconductor layer, and in the groove on the third semiconductor layer and on an inner surface of the semiconductor layer; and a wavelength - conversion layer including wavelength - conversion particles in the groove.

[0009] The groove may penetrate the first semiconductor layer and the active layer and may be in at least a part of the second semiconductor layer or the third semiconductor layer.

[0010] The light - emitting element may further include a groove reflective layer on the first protective layer in the groove.

[0011] The light-emitting element may further include an external reflection layer that surrounds side surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer on the first semiconductor layer.

[0012] The light-emitting element may further include a second protective layer that is above the groove and covers the external reflection layer.

[0013] The groove may have a cubic shape, a cylindrical shape, or a shape having different respective widths at its top and bottom.

[0014] The area of the groove in a plan view may be about 50% or less of the area of the light-emitting element in the plan view.

[0015] The light-emitting element may further include a first contact electrode that contacts the first semiconductor layer and a second contact electrode that contacts the second semiconductor layer.

[0016] According to one or more embodiments, a display device includes a substrate and a light-emitting element. A pixel electrode layer is provided on the substrate. The light-emitting element is above the pixel electrode layer and includes: a semiconductor layer; a first wavelength conversion layer in a groove that is recessed downward from a surface of one of the semiconductor layers in the semiconductor layer; and a first protective layer on side surfaces of the semiconductor layer, on a top surface of a first light-emitting element in the light-emitting element, and above one of the semiconductor layers and on an inner surface of the semiconductor layer in the groove.

[0017] The semiconductor layer may include a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer. The groove penetrates the first semiconductor layer and the active layer and is in at least a part of the second semiconductor layer or the third semiconductor layer.

[0018] The light-emitting element may further include a groove reflection layer on the first protective layer in the groove.

[0019] The semiconductor layer may include a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer. The light-emitting element further includes an external reflection layer that surrounds side surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer on the first protective layer, and a second protective layer that is above the groove and covers the external reflection layer.

[0020] The groove may have a cubic shape, a cylindrical shape, or a shape having different widths at the top and bottom.

[0021] The semiconductor layer may include a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer. The area of the groove in a plan view is about 50% or less of the area of the light-emitting element in the plan view.

[0022] The semiconductor layer may include a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer. Among them, the first light-emitting element includes a first contact electrode contacting the first semiconductor layer and a second contact electrode contacting the second semiconductor layer. And among them, the pixel electrode layer includes a pixel electrode connected to the first contact electrode and a common electrode spaced apart from the pixel electrode and connected to the second contact electrode.

[0023] The display device may further include a common electrode on the first light-emitting element. Among them, the semiconductor layer includes a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer. Among them, the pixel electrode layer includes a pixel electrode. And among them, the first light-emitting element further includes a contact electrode connecting the first semiconductor layer to the pixel electrode.

[0024] The display device may further include a second wavelength conversion layer above the light-emitting element. Among them, the first wavelength conversion layer includes a light-transmitting pattern or a wavelength conversion pattern. And among them, the second wavelength conversion layer includes another light-transmitting pattern or another wavelength conversion pattern overlapping with the first wavelength conversion layer.

[0025] The light-emitting element may include a first light-emitting element configured to emit light in a first wavelength band, a second light-emitting element configured to emit light in a second wavelength band, and a third light-emitting element configured to emit light in a third wavelength band. Among them, the first wavelength conversion layer of the first light-emitting element is configured to convert light with a wavelength other than the first wavelength band into light in the first wavelength band. Among them, the first wavelength conversion layer of the second light-emitting element is configured to convert light with a wavelength other than the second wavelength band into light in the second wavelength band. And among them, the first wavelength conversion layer of the third light-emitting element is configured to convert light with a wavelength other than the third wavelength band into light in the third wavelength band.

[0026] The display device may further include: a first color filter for transmitting only the first light in the first wavelength band in the first emission region; a second color filter for transmitting only the light in the second wavelength band in the second emission region; and a third color filter for transmitting only the light in the third wavelength band in the third emission region. Among them, the light-emitting element is configured to emit the first light and includes a first light-emitting element in the first emission region, a second light-emitting element in the second emission region, and a third light-emitting element in the third emission region. And among them, the first wavelength conversion layer of the light-emitting element includes a fourth wavelength conversion pattern, and the fourth wavelength conversion pattern includes fourth wavelength conversion particles configured to convert the first light into fourth light.

[0027] The light-emitting element may be configured to emit first light in a first wavelength band, and includes a first light-emitting element in a first emission region, a second light-emitting element in a second emission region, and a third light-emitting element in a third emission region. Wherein, the first wavelength conversion layer of the second light-emitting element includes a first wavelength conversion pattern, and the first wavelength conversion pattern includes first wavelength conversion particles for converting the first light into second light. Wherein, the first wavelength conversion layer of the third light-emitting element includes a second wavelength conversion pattern, and the second wavelength conversion pattern includes second wavelength conversion particles for converting the first light into third light. And wherein, the second wavelength conversion layer of the first emission region includes a light-transmitting pattern, and the light-transmitting pattern includes a base resin and a scatterer for scattering light.

[0028] The display device may further include: a first color filter in the first emission region and configured to transmit only the first light in the first wavelength band; a second color filter in the second emission region and configured to transmit only the second light in the second wavelength band; and a third color filter in the third emission region and configured to transmit only the third light in the third wavelength band. Wherein, the light-emitting element includes a first light-emitting element configured to emit the first light, a second light-emitting element configured to emit the second light, and a third light-emitting element configured to emit the third light. And wherein, the first wavelength conversion layer of the light-emitting element includes a fourth wavelength conversion pattern, and the fourth wavelength conversion pattern includes fourth wavelength conversion particles configured to convert the first light into fourth light.

[0029] According to the light-emitting element and the display device according to the embodiment, by filling the groove formed in the light-emitting element with a light conversion material, light conversion can be effectively performed.

[0030] However, the aspects of the present disclosure are not limited to the above aspects, and various other effects are included in this specification. Description of the Drawings

[0031] By referring to the drawings and describing the embodiments of the present disclosure in detail, the above and other aspects of the present disclosure will become more obvious. In the drawings:

[0032] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 is a layout view showing a display device according to one or more embodiments;

[0034] Figure 3 is a block diagram showing a display device according to one or more embodiments;

[0035] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments;

[0036] Figure 5 shows an equivalent circuit diagram of sub-pixels according to one or more other embodiments;

[0037] Figure 6 shows a layout diagram of pixels in a display area according to one or more embodiments;

[0038] Figure 7 shows a cross-sectional view of an example of a display panel taken along line B - B' of Figure 6 ;

[0039] Figure 8 shows a detailed cross-sectional view of an example of area A of Figure 7 ;

[0040] Figure 9 shows a diagram of an example of a light-emitting element according to another modification of Figure 8 ;

[0041] Figure 10 and Figure 11 show a cross-sectional view in detail of an example of area A of Figure 7 according to one or more other embodiments;

[0042] Figure 12 、 Figure 13 and Figure 14 show a cross-sectional view of an example of a display panel taken along line B - B' of Figure 6 according to one or more other embodiments;

[0043] Figure 15 show a cross-sectional view of an example of a display panel taken along line B - B' of Figure 6 according to one or more other embodiments;

[0044] Figure 16 shows a cross-sectional view of the configuration of a light-emitting element of Figure 15 ;

[0045] Figure 17 show a cross-sectional view of an example of a display panel taken along line B - B' of Figure 6 according to yet one or more other embodiments;

[0046] Figure 18 shows a cross-sectional view of the configuration of a light-emitting element of Figure 17 ;

[0047] Figures 19 to 30 shows a cross-sectional view of a method for manufacturing a display device according to one or more embodiments;

[0048] Figure 31is a diagram schematically showing a virtual reality device including a display device according to one or more embodiments;

[0049] Figure 32 is a diagram schematically showing a smart device including a display device according to one or more embodiments;

[0050] Figure 33 is a diagram schematically showing a vehicle including a display device according to one or more embodiments; and

[0051] Figure 34 is a diagram schematically showing a transparent display device including a display device according to one or more embodiments. Detailed Embodiments

[0052] Aspects of some embodiments of the present disclosure and methods of implementing the same can be more easily understood by referring to the detailed description of the embodiments and the drawings. The embodiments are provided as examples so that the present disclosure will be thorough and complete, and aspects of the present disclosure will be fully conveyed to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand aspects of the present disclosure may be omitted. Unless otherwise indicated, throughout the drawings and the written description, the same reference numerals, characters, or combinations thereof represent the same elements, and thus, their repeated description may be omitted.

[0053] The described embodiments can have various modifications and can be implemented in different forms, and should not be construed as limited to the embodiments shown herein. When describing the embodiments, the use of "able to", "can", or "may not" corresponds to one or more embodiments of the present disclosure.

[0054] Based on the overall content of the present disclosure, those of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents, and substitutions within the spirit and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure can be partially or wholly combined with each other, and various interlocks and drives are possible technically, and each embodiment can be implemented independently of each other or can be implemented in association with each other, unless otherwise stated or implied.

[0055] In the drawings, for clarity and / or for the purpose of description, the relative dimensions of elements, layers, and regions may be exaggerated. Further, the use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Thus, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements, unless there is a description.

[0056] In this document, various embodiments are described with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments in accordance with the concepts of the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the shapes of the illustrated elements, layers, or regions, but include deviations in shape due to, for example, manufacturing.

[0057] For example, an implantation region shown as rectangular will generally have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed.

[0058] For ease of explanation, spatially relative terms such as "below", "beneath", "lower", "underside", "under", "above", "upper", "upside" etc. may be used herein to describe the relationship of one element or feature to another (or others) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath", or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can include both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this means that the first part is disposed at the upper or lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0059] In addition, the phrase "in a plan view" means observing the object part from above, and the phrase "in a schematic cross-sectional view" means observing a schematic cross-section taken by vertically cutting the object part from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" can include laminating, facing or being oriented towards, extending over, covering or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separate from", "arranged side by side with", or "offset from", as well as any other suitable equivalents as would be understood and appreciated by one of ordinary skill in the art. The terms "face" and "be oriented towards" can mean that the first object can be directly or indirectly opposite the second object. In cases where a third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite each other, although still facing each other.

[0060] It will be understood that when an element, layer, region or component is referred to as being "formed" "on", "over", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, directly over, directly connected to or directly coupled to the other element, layer, region or component, or indirectly formed on, indirectly over, indirectly connected to or indirectly coupled to the other element, layer, region or component, such that there can be one or more intervening elements, layers, regions or components. Further, this can generally refer to direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors, capacitors, etc. When describing an embodiment, unless explicitly described as a direct connection, the expression of connection means an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component or on another component without an intermediate component.

[0061] In addition, in this specification, when forming a part of a layer, film, region, plate, etc. on another part, the forming direction is not limited to the upper direction, but includes forming the part on a side surface or in a lower direction. Conversely, when forming a part of a layer, film, region, plate, etc. "under" another part, this includes not only the case where the part is "directly" "below" the other part, but also the case where there is another part between the part and the other part. On the other hand, other expressions such as "between", "directly between", or "adjacent to" and "directly adjacent to" that describe the relationship between components can be similarly interpreted. It will be understood that when an element or layer is said to be "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0062] For the purposes of this disclosure, expressions such as "at least one of...", "any one of...", or "one or more of..." when following a list of elements modify the entire list of elements, rather than individual elements in the list. For example, "at least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, an expression such as "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of", "one of...", and other prepositional phrases when following a list of elements modify the entire list of elements, rather than individual elements in the list.

[0063] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are only used to distinguish one element, member, component, region, zone, layer, section, or part from another element, member, component, region, zone, layer, section, or part. Thus, the first element, first component, first region, first layer, or first section described below may be referred to as the second element, second component, second region, second layer, or second section without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0064] In an example, the DR1 axis, DR2 axis, and / or DR3 axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0065] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "has", "having", "includes", and "including" specify the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0066] When one or more embodiments can be implemented differently, the specific process order may be performed differently from the stated order. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the stated order.

[0067] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" can include a range of ±5% of the corresponding value. Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0068] In some embodiments, well-known structures and devices may be described in the drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that these functional blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. These may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Functional blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled with software to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Additionally, each functional block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs functions different from the functions of the dedicated hardware. Further, in some embodiments, a functional block, unit, and / or module may be physically divided into two or more interacting separate functional blocks, units, and / or modules without departing from the scope of the present disclosure. Additionally, in some embodiments, functional blocks, units, and / or modules may be physically combined into more complex functional blocks, units, and / or modules without departing from the scope of the present disclosure.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0070] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0071] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0072] Reference Figure 1 , the display device 10 is a device for displaying moving images or still images. The display device 10 can be used as various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) device, and a display screen of portable electronic devices such as a mobile phone, a smartphone, a tablet personal computer (PC), a smartwatch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC).

[0073] The display device 10 can be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micron or nano light-emitting diode (LED). In the following description, it is assumed that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for simplicity of description, hereinafter, an ultra-small light-emitting diode is referred to as a micro light-emitting diode.

[0074] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0075] In a plan view, the display panel 100 may be formed in a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a curvature (e.g., a predetermined curvature), or may be right-angled. The planar shape of the display panel 100 is not limited to a rectangular shape and may be formed in another polygonal shape, a circular shape, or an elliptical shape. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed flexibly so that it can be curved, bent, folded, or curled.

[0076] The substrate SUB of the display panel 100 (see Figure 7 ) may include a main region MA and a sub-region SBA.

[0077] The main area MA may include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may include a plurality of pixels for displaying the image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0078] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. Although the sub-area SBA is shown as being unfolded in Figure 1 , the sub-area SBA may be bent to be disposed on the bottom surface of the display panel 100. When the sub-area SBA is bent, it may overlap with the main area MA in the third direction DR3 that is the thickness direction of the display panel 100. The display driving circuit 250 may be disposed in the sub-area SBA.

[0079] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but the present disclosure is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 by a chip on film (COF) method.

[0080] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Accordingly, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, a timing signal, and a driving voltage through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0081] Figure 2 is a layout diagram showing a display device according to one or more embodiments. In Figure 2 , the sub-area SBA is shown as being unfolded without being bent.

[0082] Referring to Figure 2 , the display panel 100 may include a main area MA and a sub-area SBA.

[0083] The main area MA may include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be located at the center of the main area MA.

[0084] The display area DA may include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub-pixels SPX. A pixel PX may be defined as the smallest unit pixel group capable of representing a white gray level.

[0085] The non-display area NDA may be positioned adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may surround the display area DA (e.g., in a plan view). The non-display area NDA may be an edge area of the display panel 100.

[0086] The first scan driver SDC1 and the second scan driver SDC2 may be located in the non-display area NDA. The first scan driver SDC1 may be located at one side (e.g., the left side) of the display panel 100, while the second scan driver SDC2 may be located at the other side (e.g., the right side) of the display panel 100, but the present disclosure is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal input from the display driving circuit 250, may generate a scan signal in response to the scan control signal, and may output the generated scan signal to the scan line.

[0087] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be substantially equal to or less than the length of the main region MA in the first direction DR1. The sub-region SBA may be foldable to be located under the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0088] The sub-region SBA may include a connection region CA, a pad region PA, and a bending region BA.

[0089] The connection region CA is a region that protrudes from one side of the main region MA in the second direction DR2. One side of the connection region CA may contact the non-display area NDA of the main region MA, while the other side of the connection region CA may contact the bending region BA.

[0090] The pad region PA is the region in which the pads PD and the display driving circuit 250 are located. The display driving circuit 250 can be attached to the driving pads of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pads PD of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad region PA can contact the bending region BA.

[0091] The bending region BA is the region that is bent. When the bending region BA is bent, the pad region PA can be located under the connection region CA and the main region MA. The bending region BA can be located between the connection region CA and the pad region PA. One side of the bending region BA can contact the connection region CA, and the other side of the bending region BA can contact the pad region PA.

[0092] The non-display power line NVSL can be located in the non-display region NDA, the connection region CA, the bending region BA, and the pad region PA. The non-display power line NVSL can be located at the four sides of the display region DA in the non-display region NDA. The non-display power line NVSL can surround at least three sides of the display region DA, or can be adjacent to at least three sides of the display region DA. For example, the non-display power line NVSL can be at the left side, the upper side, and the right side of the display region DA, and can be located in at least a part of the lower side. In addition, the non-display power line NVSL can be located outside the first scan driver SDC1 and outside the second scan driver SDC2. For example, the non-display power line NVSL can be at the left side of the first scan driver SDC1 and at the right side of the second scan driver SDC2. The non-display power line NVSL can be located at the edges of the first scan driver SDC1 and the substrate SUB and at the edges of the second scan driver SDC2 and the substrate SUB. Alternatively, the non-display power line NVSL can overlap with the first scan driver SDC1 and the second scan driver SDC2.

[0093] The non-display power line NVSL can be located at the left edge and the right edge in the connection region CA and the bending region BA. The non-display power line NVSL can be connected to the pads PD adjacent to one side edge among the pads PD in the pad region PA, and connected to the pads PD adjacent to the other side edge among the pads PD in the pad region PA. The non-display power line NVSL can receive the second driving voltage VSS from a power supply circuit 500 located on the circuit board 300 (as used herein, "located on..." can mean "above...") (for example, see Figure 3 ).

[0094] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0095] ReferenceFigure 3 , the display area DA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0096] The plurality of pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 while being arranged in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 while being arranged in the first direction DR1. The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0097] Each of the plurality of sub-pixels SPX can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of initialization scan lines GIL, any one of the plurality of bias scan lines GBL, any one of the plurality of emission control lines EL, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SPX can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and can emit light from its light emitting element according to the data voltage.

[0098] The non-display area NDA includes a first scan driver SDC1, a second scan driver SDC2, and a display driving circuit 250.

[0099] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a transmit signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the transmit signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS of the timing control circuit 251, and may sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS, and may sequentially output them to the control scan lines GCL. The initialization scan signal output unit 613 may generate initialization scan signals in response to the scan timing control signal SCS, and may sequentially output them to the initialization scan lines GIL. The bias scan signal output unit 614 may generate bias scan signals according to the scan timing control signal SCS, and may sequentially output them to the bias scan lines GBL. The transmit signal output unit 615 may generate transmit control signals according to the scan timing control signal SCS, and may sequentially output them to the transmit control lines EL.

[0100] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252.

[0101] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into analog data voltages in response to the data timing control signal DCS, and outputs them to the data lines DL. In this case, the sub-pixels SPX may be selected by the write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data voltages may be provided to the selected sub-pixels SPX.

[0102] The timing control circuit 251 may receive digital video data DATA and timing signals from the outside. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0103] The power supply circuit 500 may generate a plurality of panel driving voltages based on an external power voltage. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and supply them to the display panel 100.

[0104] Figure 4 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0105] Reference Figure 4 , the sub-pixel SPX according to one or more embodiments may be connected to scan lines GWL, GIL, GCL, and GBL, an emission control line EL, and a data line DL. For example, the sub-pixel SPX may be connected to a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, an emission control line EL, and a data line DL.

[0106] The sub-pixel SPX according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

[0107] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0108] The light-emitting element LE may be a micro light-emitting diode element. The light-emitting element LE may emit light according to the driving current. The emission amount of the light-emitting element LE may be proportional to the driving current. The anode electrode of the light-emitting element LE may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and its cathode electrode may be connected to a second power line VSL to which a second power voltage is applied.

[0109] The capacitor C1 is formed between the gate electrode of the driving transistor DT and a first power line VDL to which a first power voltage is applied. The first power voltage may be a voltage having a level higher than the level of the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode thereof may be connected to the first power line VDL.

[0110] As Figure 4As shown, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can all be formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layers of the driving transistor DT and each of the first transistor ST1 to the sixth transistor ST6 can be formed of polysilicon.

[0111] The gate electrode of the second transistor ST2 can be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 can be connected to the control scan line GCL. The gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL. Since the first transistor ST1 to the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on when a scan signal and an emission signal of a low gate voltage are applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 can be connected to the initialization voltage line VIL. A parasitic capacitor Cel can be formed between the anode electrode and the cathode electrode of the light-emitting element LE.

[0112] Figure 5 is an equivalent circuit diagram showing a sub-pixel according to one or more other embodiments.

[0113] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be configured as p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be configured as n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 configured as p-type MOSFETs can be formed of polysilicon, while the active layer of each of the first transistor ST1 and the third transistor ST3 configured as n-type MOSFETs can be formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of an oxide semiconductor can be located at different corresponding layers.

[0114] Since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, when a control scan signal of a high gate voltage is applied to the control scan line GCL, the first transistor ST1 can be turned on, and when an initialization scan signal is applied to the initialization scan line GIL, the third transistor ST3 can be turned on. In contrast, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on when an emission signal and a scan signal of a low gate voltage are applied to each of the write scan line GWL, the bias scan line GBL, and the emission control line EL.

[0115] Alternatively, in one or more embodiments, the fourth transistor ST4 may be formed as an n-type MOSFET. In this case, the active layer of the fourth transistor ST4 may also be formed of an oxide semiconductor. When the fourth transistor ST4 is formed as an n-type MOSFET, the fourth transistor ST4 can be turned on when a bias scan signal of a high gate voltage is applied to the bias scan line GBL.

[0116] Alternatively, in one or more embodiments, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT may all be formed as n-type MOSFETs. In this case, the active layer of each of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 may be formed of an oxide semiconductor.

[0117] Figure 6 is a layout diagram of pixels in a display area according to one or more embodiments.

[0118] Reference Figure 6 , the display area DA may include a plurality of pixels PX. The pixel PX may include a plurality of light-emitting elements LE, and may be defined as the smallest light-emitting unit capable of displaying white light by combining the light emitted by the plurality of light-emitting elements LE.

[0119] Each of the pixels PX may include a plurality of sub-pixels that emit light, for example, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may respectively include a plurality of emission regions EA1, EA2, and EA3 that emit light. Although each of the plurality of pixels PX is shown to include three emission regions EA1, EA2, and EA3, the present disclosure is not limited thereto. For example, each of the plurality of pixels PX may include four emission regions.

[0120] Each of the plurality of emission regions EA1, EA2, and EA3 may include a light-emitting element LE that emits light. The plurality of emission regions EA1, EA2, and EA3 may include light-emitting elements LE1, LE2, and LE3 that emit light of different respective wavelengths, but the present disclosure is not limited thereto. For example, each of the plurality of emission regions EA1, EA2, and EA3 may include a light-emitting element LE that emits first light. When the plurality of emission regions EA1, EA2, and EA3 include light-emitting elements LE that emit the same first light, the color or wavelength of the emission regions may be changed by a wavelength conversion layer and / or a color filter. This will be described later.

[0121] Although the light-emitting element LE is shown as having a quadrilateral planar shape, the present specification is not limited thereto. For example, the light-emitting element LE may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a quadrilateral shape.

[0122] The first emission region EA1, the second emission region EA2, and the third emission region EA3 may be alternately arranged in a first direction DR1. For example, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be arranged in the first direction DR1 in the order of the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0123] The first emission region EA1 may be arranged in a second direction DR2. The second emission region EA2 may be arranged in the second direction DR2. The third emission region EA3 may be arranged in the second direction DR2.

[0124] The plurality of emission regions EA1, EA2, and EA3 may be separated by partition walls PW. The partition walls PW may surround the light-emitting element LE (e.g., in a plan view). In a plan view, the partition walls PW may have a mesh shape, a net shape, or a grid shape.

[0125] Figure 6 Each of the emission regions EA1, EA2, and EA3 defined by the partition walls PW is shown as having a rectangular shape in a plan view, but the present disclosure is not limited thereto. For example, each of the emission regions EA1, EA2, and EA3 defined by the partition walls PW may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a rectangular shape.

[0126] Figure 7 is a cross-sectional view showing an example of a display panel taken along line B-B'. Figure 6 is a detailed cross-sectional view showing an example of region A. Figure 8 is showing Figure 7 an example of region A. Figure 9 is a view showing an example of a light-emitting element according to another modification. Figure 8 of

[0127] Reference Figure 7 and Figure 8 The substrate SUB can be made of an insulating material such as glass or a polymer resin. When the substrate SUB is made of a polymer resin, it can be a flexible substrate that can be stretched. The polymer resin can include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The barrier layer BR can be located on the substrate SUB. The barrier layer BR can protect the elements located thereon from moisture that penetrates through the substrate SUB.

[0128] The first active layer ACT1 can include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 can be a region that overlaps with the first gate electrode G1 in a third direction DR3, which is the thickness direction of the substrate SUB. The first source region S1 can be located at one side of the first channel region CHA1, and the first drain region D1 can be located at the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 can be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 can be regions that have conductivity by ion-doping a silicon semiconductor.

[0129] The first gate insulating layer 131 can be located on / above the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1. The first gate insulating layer 131 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0130] The first gate metal layer can be located on the first gate insulating layer 131. The first gate metal layer can include the first gate electrode G1 of the first thin film transistor TFT1 and the first capacitor electrode CAE1. The first gate electrode G1 can overlap with the first active layer ACT1 in the third direction DR3. Figure 7 It is shown that the first gate electrode G1 and the first capacitor electrode CAE1 are spaced apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 can be connected to each other. The first gate metal layer can be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0131] The second gate insulating layer 132 can be located on the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The second gate insulating layer 132 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0132] The second gate metal layer may be located on the second gate insulating layer 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 in a third direction DR3. Since the second gate insulating layer 132 has a dielectric constant (e.g., a predetermined dielectric constant), a capacitor C1 may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating layer 132 located therebetween (see Figure 5 ). The second gate metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0133] The first interlayer insulating layer 141 may be located on the second capacitor electrode CAE2. The first interlayer insulating layer 141 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0134] The second thin film transistor TFT2 may be located on the first interlayer insulating layer 141. The second thin film transistor TFT2 may be Figure 5 either the first transistor ST1 or the third transistor ST3 shown in

[0135] The second active layer ACT2 of the second thin film transistor TFT2 may be located on the first interlayer insulating layer 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0136] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in a third direction DR3. The second source region S2 may be located on one side of the second channel region CHA2, while the second drain region D2 may be located on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in a third direction DR3. The second source region S2 and the second drain region D2 may be regions having conductivity by ion-doping an oxide semiconductor.

[0137] The third gate insulating layer 133 may be located on the second active layer ACT2 of the second thin film transistor TFT2. The third gate insulating layer 133 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0138] The third gate metal layer may be located on the third gate insulating layer 133. The third gate metal layer may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3. The third gate metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0139] The second interlayer insulating layer 142 may be located on the second gate electrode G2 of the second thin film transistor TFT2. The second interlayer insulating layer 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0140] The first data metal layer may be located on the second interlayer insulating layer 142. The first data metal layer may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source connection hole PCT1 that penetrates the first gate insulating layer 131, the second gate insulating layer 132, the first interlayer insulating layer 141, the third gate insulating layer 133, and the second interlayer insulating layer 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection hole BCT1 that penetrates the second interlayer insulating layer 142 and the third gate insulating layer 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection hole BCT2 that penetrates the second interlayer insulating layer 142 and the third gate insulating layer 133. The first data metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the first data metal layer may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0141] On the first source connection electrode SBE3, the second source connection electrode SBE1, and the third source connection electrode SBE2, a first organic layer 160 can be positioned to planarize the step portions caused by the first thin film transistor TFT1 and the second thin film transistor TFT2. The first organic layer 160 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0142] A second data metal layer can be located on the first organic layer 160. The second data metal layer can include a fourth source connection electrode SBE4 and a second power line VSL (see Figure 5 ). The fourth source connection electrode SBE4 can be connected to the first source connection electrode SBE3 through a second pixel connection hole PCT2 that penetrates the first organic layer 160. The second data metal layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the second data metal layer can include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0143] A second organic layer 180 can be located on the fourth source connection electrode SBE4. The second organic layer 180 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0144] The pixel electrode PXE and the common electrode CE can be located on the second organic layer 180. The pixel electrode PXE and the common electrode CE can be positioned separately from each other.

[0145] The pixel electrode layer PXL can include the pixel electrode PXE and the common electrode CE in each of them. The pixel electrode PXE can be referred to as an anode electrode, and the common electrode CE can be referred to as a cathode electrode.

[0146] The pixel electrode PXE can be connected to the fourth source connection electrode SBE4 through a connection hole that penetrates the second organic layer 180. The pixel electrode PXE can be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Accordingly, the voltage controlled by the first thin film transistor TFT1 can be applied to the pixel electrode PXE.

[0147] The common electrode CE can be commonly connected to adjacent sub-pixels. One end of the common electrode CE can be connected to the second power line VSL (see Figure 4 or Figure 5 ). Accordingly, a second driving voltage VSS can be applied to the common electrode CE.

[0148] The pixel electrode layer PXL can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. When the pixel electrode layer PXL is made of a metal material with a high reflectivity, such as aluminum (Al), among the light emitted from the active layer MQW of the light-emitting element LE, the light traveling in the downward direction with respect to the light-emitting element LE can be reflected from the pixel electrode PXE and the common electrode CE and travel in the upward direction with respect to the light-emitting element LE. Therefore, since the light loss from the light-emitting element LE can be reduced, the light efficiency of the light-emitting element LE can be improved.

[0149] The light-emitting element LE can be located on the pixel electrode layer PXL. Although a lateral-type micro LED is disclosed in which both the first contact electrode CTE1 and the second contact electrode CTE2 protrude from the top surface of the light-emitting element LE and current flows in the lateral direction, the present disclosure is not limited thereto. For example, the first contact electrode CTE1 and the second contact electrode CTE2 can be located only on one surface of the light-emitting element LE.

[0150] Each of the plurality of light-emitting elements LE can be made of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements LE can have a length of several μm to several hundred μm in each of a first direction DR1, a second direction DR2, and a third direction DR3. For example, each of the plurality of light-emitting elements LE can have a length of about 100 μm or less in each of the first direction DR1, the second direction DR2, and the third direction DR3.

[0151] Each of the plurality of light-emitting elements LE can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light-emitting elements LE can be transferred onto the display panel 100 by an electrostatic method using an electrostatic head or an imprint method using an elastic polymer material such as PDMS or silicone resin as a transfer substrate.

[0152] The plurality of emission regions EA1, EA2, and EA3 can respectively include light-emitting elements LE1, LE2, and LE3 that emit light of different wavelengths. For example, the first emission region EA1 can include a first light-emitting element LE1 that emits first light, and the first light can be light in the blue wavelength band. The blue wavelength band can be in the range of about 370 nm to about 460 nm, but the embodiments of this specification are not limited thereto.

[0153] The second emission region EA2 may include a second light-emitting element LE2 that emits a second light, and the second light may be light in the green wavelength band. The green wavelength band may be in the range of about 480 nm to about 560 nm, but embodiments of the present specification are not limited thereto.

[0154] The third emission region EA3 may include a third light-emitting element LE3 that emits a third light. The third light may be light in the red wavelength band. The red wavelength band may be in the range of about 600 nm to about 750 nm, but embodiments of the present specification are not limited thereto.

[0155] Each of the light-emitting elements LE includes a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, an undoped semiconductor layer (also referred to as a third semiconductor layer) SEM3, a first wavelength conversion layer QDL1, QDL2, or QDL3, a first protective layer INS1, a first reflective layer RF1, a second protective layer INS2, a first contact electrode CTE1, and a second contact electrode CTE2.

[0156] The undoped semiconductor layer SEM3 may be located on the pixel electrode layer PXL. The undoped semiconductor layer SEM3 may be formed as a semiconductor layer that is not doped with an n-type dopant or a p-type dopant, that is, an undoped semiconductor layer. For example, the undoped semiconductor layer SEM3 may be any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN that is not doped with a dopant. For example, the undoped semiconductor layer SEM3 may be GaN that is not doped with a dopant.

[0157] The second semiconductor layer SEM2 may be located on the undoped semiconductor layer SEM3. The second semiconductor layer SEM2 may be any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN that is doped with an n-type dopant such as Si, Ge, Se, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si.

[0158] The active layer MQW may be located on the second semiconductor layer SEM2. The active layer MQW may emit light by coupling electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0159] The active layer MQW may include a material having a single quantum well structure or a multi - quantum well structure. When the active layer MQW includes a material having a multi - quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. At this time, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the present disclosure is not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large bandgap and a semiconductor material having a small bandgap are alternately stacked, and may include other group - III to group - V semiconductor materials according to the wavelength band of the emitted light.

[0160] When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer MQW may shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer MQW may shift to the blue wavelength band. For example, the active layer MQW of a light - emitting element LE that emits first light (light in the blue wavelength band) may contain about 10 wt% to about 20 wt% of indium (In).

[0161] The first semiconductor layer SEM1 may be located on the active layer MQW. The first semiconductor layer SEM1 may be any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with a p - type dopant such as Mg, Zn, Ca, or Ba. For example, the first semiconductor layer SEM1 may be p - GaN doped with p - type Mg.

[0162] The electron blocking layer may be located between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer for suppressing or preventing too many electrons from flowing into the active layer MQW. For example, the electron blocking layer may be AlGaN or p - AlGaN doped with p - type Mg. The electron blocking layer may be omitted.

[0163] The superlattice layer may be located between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for reducing the stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0164] The light-emitting element LE may include a groove LE-S that is recessed downward from the top surface of the first semiconductor layer SEM1. The light-emitting element LE may include one or more grooves LE-S. The groove LE-S may penetrate the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2, and may be located in at least a part of the third semiconductor layer SEM3 or defined by at least a part of the third semiconductor layer SEM3, but the present disclosure is not limited thereto. In another modification, the groove LE-S may penetrate the first semiconductor layer SEM1 and the active layer MQW, and may be located in at least a part of the second semiconductor layer SEM2. When viewed from the top of the light-emitting element LE, the area of the groove LE-S may be about 50% or less of the area of the light-emitting element LE.

[0165] The groove LE-S may have a shape similar to that of the light-emitting element LE. For example, when the light-emitting element LE is a rectangular parallelepiped or a cube, the groove LE-S may also have a rectangular parallelepiped shape or a cube shape. In addition, when the light-emitting element LE is cylindrical, the groove LE-S may also have a cylindrical shape, but the present disclosure is not limited thereto.

[0166] The first protective layer INS1 is used to protect the outer surface of the light-emitting element LE. The first protective layer INS1 may be located on the entire surface of the light-emitting element LE except for the bottom of the light-emitting element LE. The first protective layer INS1 may surround the groove LE-S and the side surfaces of the plurality of semiconductor layers SEM1, MQW, SEM2, and SEM3. For example, the first protective layer INS1 may be located on the top surface of the first semiconductor layer SEM1, the side surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3, and the bottom surface S-B and the side surface S-W of the groove LE-S. Since the side surface S-W is the inner surface of the groove LE-S, it may also be referred to as the inner side surface. The first protective layer INS1 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0167] The first reflective layer RF1 may be located above the bottom surface S-B of the groove LE-S and the side surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. For the sake of simplicity of description, the first reflective layer RF1 located above the bottom surface S-B of the groove LE-S may be referred to as the groove reflective layer, and the first reflective layer RF1 located above the side surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 may be referred to as the external reflective layer.

[0168] The first reflective layer RF1 may include a metallic material having a high reflectivity, such as aluminum (Al). The thickness of the first reflective layer RF1 may be about 0.1 μm.

[0169] In another modification, as Figure 9 shown, the first reflective layer RF1 may be omitted.

[0170] The first wavelength conversion layers QDL1, QDL2, and QDL3 may be located in the space formed by the groove LE-S. The first wavelength conversion layers QDL1, QDL2, and QDL3 may include different wavelength conversion patterns for different emission regions. For example, the first wavelength conversion layers QDL1, QDL2, and QDL3 may include a first wavelength conversion pattern WCL1 in the first emission region EA1, a second wavelength conversion pattern WCL2 in the second emission region EA2, and a third wavelength conversion pattern WCL3 in the third emission region EA3, respectively.

[0171] The first wavelength conversion pattern WCL1, the second wavelength conversion pattern WCL2, and the third wavelength conversion pattern WCL3 may be located in the grooves LE-S formed in the corresponding light-emitting elements LE. For example, the first wavelength conversion pattern WCL1 may be located in the groove LE-S of the first light-emitting element LE1. The second wavelength conversion pattern WCL2 may be located in the groove LE-S of the second light-emitting element LE2. The third wavelength conversion pattern WCL3 may be located in the groove LE-S of the third light-emitting element LE3.

[0172] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmissive organic material. For example, the first base resin BRS1 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0173] The first wavelength conversion particles WCP1 convert light of different wavelengths incident from the first light-emitting element LE1 in the first emission region EA1 into first light. The first wavelength conversion particles WCP1 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. Examples of quantum dots may include group-IV nanocrystals, II-VI compound nanocrystals, III-V compound nanocrystals, IV-VI compound nanocrystals, and combinations thereof.

[0174] Quantum dots (QDs) may include a core and a shell that coats the core. The core may be, for example, at least one of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InP, InAs, InSb, SiC, Ca, Se, In, P, Fe, Pt, Ni, Co, Al, Ag, Au, Cu, FePt, Fe2O3, Fe3O4, Si, and Ge, but is not limited thereto. The shell may include, for example, at least one of ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, GaSe, InN, InP, InAs, InSb, TlN, TlP, TlAs, TlSb, PbS, PbSe, and PbTe, but is not limited thereto.

[0175] The first wavelength conversion layers QDL1, QDL2, and QDL3 may further include a scatterer for scattering light of the light emitting element LE in a random direction. In this case, the scatterer may include metal oxide particles or organic particles. For example, the metal oxide may be titanium oxide (TiO2), zirconium oxide (ZrO2), silicon dioxide (SiO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO x , which may be ZnO and / or ZnO2) or tin oxide (SnO2). In addition, the organic particles may include an acrylic resin or a urethane-based resin. The diameter of the scatterer may be several nanometers to several tens of nanometers.

[0176] Through the first wavelength conversion pattern WCL1, the color purity of the first light emitted from the first light emitting element LE1 and passing through the first wavelength conversion pattern WCL1 is improved.

[0177] The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second wavelength conversion particles WCP2 convert light of different wavelengths incident from the second light emitting element LE2 in the second emission region EA2 into second light. The second wavelength conversion particles WCP2 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. Through the second wavelength conversion pattern WCL2, the color purity of the second light emitted from the second light emitting element LE2 and passing through the second wavelength conversion pattern WCL2 is improved.

[0178] The third wavelength conversion pattern WCL3 may include a third base resin BRS3 and third wavelength conversion particles WCP3. The third wavelength conversion particles WCP3 convert light of different wavelengths incident from the third light-emitting element LE3 in the third emission region EA3 into third light. The third wavelength conversion particles WCP3 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. Through the third wavelength conversion pattern WCL3, the color purity of the third light emitted from the third light-emitting element LE3 and passing through the third wavelength conversion pattern WCL3 is improved. When each wavelength conversion particle is made of a fluorescent material or a phosphorescent material, the second protective layer INS2 may be omitted because the fluorescent or phosphorescent material is moisture-resistant.

[0179] The second protective layer INS2 may be located on one surface of the light-emitting element LE where the groove LE-S is provided, and on the side surface of the light-emitting element LE.

[0180] The second protective layer INS2 may be used to seal the top surfaces of the first wavelength conversion layers QDL1, QDL2, and QDL3. The second protective layer INS2 may be located on the first reflective layer RF1 positioned on the side surface of the light-emitting element LE. For example, the second protective layer INS2 may be located above the top surface of the first semiconductor layer SEM1 of the light-emitting element LE and above the side surfaces of each of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the undoped semiconductor layer SEM3. The second protective layer INS2 may be made of the same material as the first protective layer INS1. For example, the second protective layer INS2 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0181] The first contact electrode CTE1 and the second contact electrode CTE2 may be located at the top surface of the light-emitting element LE. The first contact electrode CTE1 may extend from the top surface of the light-emitting element LE to be located at one of its side surfaces. The second contact electrode CTE2 may extend from the top surface of the light-emitting element LE to be located at one of its side surfaces.

[0182] The first contact electrode CTE1 may contact the first semiconductor layer SEM1 at the top surface of the light-emitting element LE. To this end, the top surface of the light-emitting element LE may include a first hole exposing the first semiconductor layer SEM1. The first contact electrode CTE1 may be electrically connected to the first semiconductor layer SEM1 exposed by the first hole.

[0183] The first contact electrode CTE1 may be electrically connected to the pixel electrode PXE. The first contact electrode CTE1 may directly contact the pixel electrode PXE, but the present disclosure is not limited thereto. The first contact electrode CTE1 may be connected to the pixel electrode PXE via a separate connection electrode.

[0184] The second contact electrode CTE2 may contact the second semiconductor layer SEM2 at the top surface of the light-emitting element LE. To this end, the top surface of the light-emitting element LE may include a second hole exposing the second semiconductor layer SEM2. The second contact electrode CTE2 may be electrically connected to the second semiconductor layer SEM2 exposed by the second hole.

[0185] The second contact electrode CTE2 may be electrically connected to the common electrode CE. The second contact electrode CTE2 may directly contact the common electrode CE, but the present disclosure is not limited thereto. The second contact electrode CTE2 may be connected to the common electrode CE via a separate connection electrode.

[0186] Since the first contact electrode CTE1 and the second contact electrode CTE2 are located at the top surface of the light-emitting element LE, they may be transparent electrodes. For example, the first contact electrode CTE1 and the second contact electrode CTE2 may be made of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0187] The partition wall PW is located between the plurality of light-emitting elements LE and between the second wavelength conversion layers WDL. The partition wall PW may separate the plurality of emission regions EA1, EA2, and EA3 and the non-emission region NEA. The partition wall PW may be formed in a grid pattern throughout the display area DA. In addition, the partition wall PW may not overlap with the plurality of emission regions EA1, EA2, and EA3 and may overlap with the non-emission region NEA.

[0188] The partition wall PW may be used to provide a space for forming the second wavelength conversion layer WDL. That is, the partition wall PW may define the region of the second wavelength conversion layer WDL. The partition wall PW may include an organic insulating material having a thickness (e.g., a predetermined thickness). The organic insulating material may include, for example, an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. In one or more embodiments, the partition wall PW is shown to be made of a single layer between the plurality of light-emitting elements LE and between the second wavelength conversion layers WDL, but the present disclosure is not limited thereto. For example, the partition wall PW may include a first partition wall between the plurality of light-emitting elements LE and a second partition wall between the second wavelength conversion layers WDL.

[0189] The second reflective layer RF2 is located on the side surface of the space of the second wavelength conversion layer WDL formed in the partition wall PW to be described later. The second reflective layer RF2 may be located on the side surface of each of the partition wall PW and the second wavelength conversion layer WDL. That is, one surface of the second reflective layer RF2 may contact the side surface of the second wavelength conversion layer WDL, and the other surface thereof may contact the partition wall PW. The second reflective layer RF2 may overlap with the emission region. The second reflective layer RF2 may include a metal material having a high reflectivity, such as aluminum (Al). The thickness of the second reflective layer RF2 may be about 0.1 μm. The first reflective layer RF1 and the second reflective layer RF2 may be formed of the same material, but are not limited thereto. Alternatively, the second reflective layer RF2 may include M (M is an integer of 2 or more) pairs of a first layer and a second layer having different refractive indexes to be used as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be alternately positioned. The first layer and the second layer may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0190] The second reflective layer RF2 may reduce or prevent light color mixing between the emission regions EA1, EA2, and EA3.

[0191] The second wavelength conversion layer WDL includes different wavelength conversion patterns for different emission regions, but includes the same wavelength conversion patterns as the wavelength conversion patterns of the first wavelength conversion layers QDL1, QDL2, and QDL3 located in the same emission region. For example, the second wavelength conversion layer WDL may include a first wavelength conversion pattern WCL1 in the first emission region EA1, a second wavelength conversion pattern WCL2 in the second emission region EA2, and a third wavelength conversion pattern WCL3 in the third emission region EA3.

[0192] The capping layer CAP may be located on the partition wall PW and the second wavelength conversion layer WDL. The capping layer CAP may be used to protect the wavelength conversion particles WCP1, WCP2, and WCP3 of the second wavelength conversion layer WDL from moisture penetration.

[0193] The color filter layer CFL may be located on the capping layer CAP. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, a third color filter CF3, and an outer coating 193.

[0194] The first color filter CF1 may be located on the second wavelength conversion layer WDL in the first emission region EA1. The first color filter CF1 may transmit first light and may block or absorb light of different wavelengths. For example, the first color filter CF1 may transmit light in the blue wavelength band and may absorb or block light in the green wavelength band and the red wavelength band. Accordingly, the first emission region EA1 of the first sub-pixel SPX1 may emit first light (light in the blue wavelength band).

[0195] The second color filter CF2 may be located on the second wavelength conversion layer WDL in the second emission region EA2. The second color filter CF2 may transmit second light and may block or absorb light of different wavelengths. For example, the second color filter CF2 may transmit light in the green wavelength band and may absorb or block light in the blue wavelength band and the red wavelength band. Accordingly, the second emission region EA2 of the second sub-pixel SPX2 may emit second light (light in the green wavelength band).

[0196] The third color filter CF3 may be located on the second wavelength conversion layer WDL in the third emission region EA3. The third color filter CF3 located in the third emission region EA3 may transmit third light (light in the red wavelength band) and may absorb or block light of other wavelengths. For example, the third color filter CF3 may transmit light in the red wavelength band and may absorb or block light in the green wavelength band and the blue wavelength band. Accordingly, the third emission region EA3 of the third sub-pixel SPX3 may emit third light (light in the red wavelength band).

[0197] An area where the first color filter CF1, the second color filter CF2, and the third color filter CF3 overlap may be used to block light. An area where the first color filter CF1, the second color filter CF2, and the third color filter CF3 overlap may overlap with the partition wall PW.

[0198] The outer coating 193 may be located on the plurality of color filters CF1, CF2, and CF3. The outer coating 193 may be directly located on the color filter layer CFL. The outer coating 193 may be entirely located in the display area DA and may have a flat surface. The outer coating 193 may flatten a stepped portion formed by the color filter layer CFL located thereunder. The outer coating 193 may include a light-transmitting organic material.

[0199] Hereinafter, reference will be made to Figure 10 and Figure 11 to describe a light-emitting element according to one or more other embodiments.

[0200] Figure 10 and Figure 11 are cross-sectional views showing in detail an example of region A of Figure 7 according to one or more other embodiments.

[0201] Reference Figure 10 and Figure 11 , the first light-emitting element LE1 is different from the first light-emitting element LE1 of Figure 8 and Figure 9 in that the groove LE-S of the first light-emitting element LE1 is formed to have different upper and lower widths. A redundant description of components already described in one or more embodiments corresponding to Figure 8 and Figure 9 will be omitted.

[0202] Reference Figure 10 , the first light-emitting element LE1 is different from the first light-emitting element LE1 of Figure 8 in that the groove LE-S of the first light-emitting element LE1 is formed to have a structure in which the width increases in the downward direction.

[0203] The first wavelength conversion layer QDL1 is formed to have a structure in which the width increases downward. The width of the first wavelength conversion layer QDL1 may gradually increase in the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. Compared with the active layer MQW in one or more embodiments corresponding to Figure 8 , the active layer MQW in one or more embodiments corresponding to Figure 10 can ensure a relatively large area.

[0204] On the other hand, referring to Figure 11 , the first wavelength conversion layer QDL1 is formed to have a structure in which the width decreases in the downward direction. The width of the first wavelength conversion layer QDL1 may gradually decrease in the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. The structure in which the first wavelength conversion layer QDL1 becomes narrower downward may be advantageous in terms of process. In the structure that becomes narrower downward, the first reflection layer RF1 may be omitted.

[0205] Figures 12 to 14 is a cross-sectional view showing an example of a display panel taken along line B-B' of Figure 6 according to one or more other embodiments.

[0206] Reference Figure 12 , the shown display panel is different from the display panels described in reference Figure 7 and Figure 8 in that the light-emitting elements LE located in different sub-pixels emit the same first light, for example, blue light. It is different from the light-emitting elements LE of Figure 7 and Figure 8 . A redundant description of components already described in one or more embodiments corresponding to Figure 7 and Figure 8Redundant descriptions of components already described in one or more embodiments.

[0207] Reference Figure 12 , each of the plurality of emission regions EA1, EA2, and EA3 may include a light-emitting element LE that emits first light. The first light may be light in a blue wavelength band. The blue wavelength band may be in the range of about 370 nm to about 460 nm, but embodiments of the present specification are not limited thereto.

[0208] The first emission region EA1 may include a first light-emitting element LE1, a light-transmitting pattern TPL, and a first color filter CF1. The first light-emitting element LE1, the light-transmitting pattern TPL, and the first color filter CF1 may overlap in a third direction DR3. The first light-emitting element LE1 may be different from the first light-emitting element LE1 described in reference Figure 7 in that it does not include a first wavelength conversion layer. The light-transmitting pattern TPL may transmit the first light output from the first light-emitting element LE1 without conversion, and the first color filter CF1 may transmit the first light. Thus, each in the first emission region EA1 may emit the first light.

[0209] The light-transmitting pattern TPL may transmit incident light. The light-transmitting pattern TPL may transmit the first light without conversion, which is blue light emitted from the first light-emitting element LE1 located in the first emission region EA1. The light-transmitting pattern TPL may include a first base resin BRS1 and a scatterer SCP dispersed in the first base resin BRS1.

[0210] In one or more embodiments, a first wavelength conversion pattern may be positioned instead of the light-transmitting pattern TPL. The first wavelength conversion pattern may include a blue phosphor.

[0211] Each in the second emission region EA2 may include a second light-emitting element LE2, a second wavelength conversion layer WDL, and a second color filter CF2. The second light-emitting element LE2, the second wavelength conversion layer WDL, and the second color filter CF2 may overlap in a third direction DR3. The second light-emitting element LE2 may include a first wavelength conversion layer QDL1. The first wavelength conversion layer QDL1 of the second light-emitting element LE2 may include a second wavelength conversion pattern WCL2. Thus, the second wavelength conversion pattern WCL2 converts a part of the first light output from the second light-emitting element LE2 into second light. For example, the second light may be light in a green wavelength band. The second wavelength conversion layer WDL converts the first light not converted by the first wavelength conversion layer QDL1 into second light. The second color filter CF2 may transmit the second light. Thus, each in the second emission region EA2 may emit the second light.

[0212] Each of the third emission regions EA3 may include a third light-emitting element LE3, a second wavelength conversion layer WDL, and a third color filter CF3. The third light-emitting element LE3, the second wavelength conversion layer WDL, and the third color filter CF3 may overlap in a third direction DR3. The third light-emitting element LE3 may include a first wavelength conversion layer QDL2. The first wavelength conversion layer QDL2 of the third light-emitting element LE3 may include a third wavelength conversion pattern WCL3. Accordingly, the third wavelength conversion pattern WCL3 converts a part of the first light output from the third light-emitting element LE3 into third light. For example, the third light may be light in a red wavelength band. The second wavelength conversion layer WDL converts the first light not converted by the first wavelength conversion layer QDL2 into third light. The third color filter CF3 may transmit the third light. Accordingly, each of the third emission regions EA3 may emit the third light.

[0213] Reference Figure 13 , the shown display panel is different from the display panel described in Reference Figure 7 and Figure 8 in that the first wavelength conversion layers QDL1, QDL2, and QDL3 and the second wavelength conversion layer WDL located in different sub-pixels have the same wavelength conversion particles. It is different from Figure 7 and Figure 8 in terms of the light-emitting element LE. A redundant description of the components already described in one or more embodiments corresponding to Figure 7 and Figure 8 will be omitted.

[0214] Reference Figure 13 , the first emission region EA1 may include a first light-emitting element LE1, a second wavelength conversion layer WDL, and a first color filter CF1. The first light-emitting element LE1 emits first light, and the first light-emitting element LE1 has a first wavelength conversion layer QDL1. The first light is light in a blue wavelength band.

[0215] The first wavelength conversion layer QDL1 and the second wavelength conversion layer WDL may include a fourth wavelength conversion pattern WCL4. The fourth wavelength conversion pattern WCL4 may include a first base resin BRS1 and fourth wavelength conversion particles WCP4. The fourth wavelength conversion particles WCP4 convert the light output from the light-emitting element LE into fourth light. For example, the fourth wavelength conversion pattern WCL4 may convert the first light output from the first light-emitting element LE1 into fourth light. The fourth wavelength conversion particles WCP4 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0216] Therefore, the first color filter CF1 of the first emission region EA1 can transmit only the first light from white light as the fifth light, the second color filter CF2 of the second emission region EA2 can transmit only the second light from white light as the fifth light, and the third color filter CF3 of the third emission region EA3 can transmit only the third light from white light as the fifth light.

[0217] In another modification, even when the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 emit the first light (e.g., light in a blue wavelength band), the first wavelength conversion layers QDL1, QDL2, and QDL3 and the second wavelength conversion layer WDL can also have the fourth wavelength conversion pattern WCL4. For example, the first light output from the light-emitting elements LE of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be converted into the fourth light and emitted. For example, the fourth light can be light in a yellow wavelength band. The fourth light can be light in both a green wavelength band and a red wavelength band. That is, the fourth light can be a mixture of the second light and the third light. The first color filter CF1 of the first emission region EA1 transmits the first light, the second color filter CF2 of the second emission region EA2 transmits the second light, and the third color filter CF3 of the third emission region EA3 transmits the third light.

[0218] Reference Figure 14 , the shown display panel is different from the display panel described in reference Figure 7 and Figure 8 in that the second wavelength conversion layer located in different sub-pixels is omitted. It is different from the light-emitting elements LE of Figure 7 and Figure 8 . The redundant description of the components already described in one or more embodiments corresponding to Figure 7 and Figure 8 will be omitted.

[0219] The color filter layer CFL can be located on the partition wall PW and the light-emitting element LE in each of the emission regions EA1, EA2, and EA3. For example, the first color filter CF1 can be located on the first light-emitting element LE1 of the first emission region EA1 without the second wavelength conversion layer. The second color filter CF2 can be located on the second light-emitting element LE2 in the second emission region EA2 without the second wavelength conversion layer. The third color filter CF3 can be located on the third light-emitting element LE3 in the third emission region EA3 without the second wavelength conversion layer. One or more embodiments corresponding to Figure 14 have the advantage of being able to reduce the thickness of the display panel.

[0220] Figure 15 is a cross-sectional view showing an example of a display panel taken along line B-B' of Figure 6 according to one or more other embodiments.Figure 16 is a cross-sectional view showing the arrangement of the light-emitting elements Figure 15 . Figure 16 is a detailed cross-sectional view showing an example of region B Figure 15 .

[0221] Referring to Figure 15 and Figure 16 , the display panel shown is different from the display panel described in reference Figure 7 and Figure 8 in that the light-emitting element LE has a first contact electrode CTE1 and a second contact electrode CTE2 that face the pixel electrode layer PXL and extend to the side surface of the light-emitting element LE. Redundant descriptions of components that have been described in one or more embodiments corresponding to Figure 7 and Figure 8 will be omitted.

[0222] Referring to Figure 15 , the substrate SUB can be a semiconductor substrate, such as a silicon substrate. For example, the substrate SUB can be a CMOS substrate, but is not limited thereto. For example, the substrate SUB can be formed of an insulating material such as glass or a polymer resin. When the substrate SUB is made of a polymer resin, it can be a flexible substrate that can be stretched. The polymer resin can include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0223] Each of the plurality of light-emitting elements LE includes a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, an undoped semiconductor layer SEM3, a first wavelength conversion layer QDL1, a first protective layer INS1, a second protective layer INS2, a first contact electrode CTE1, and a second contact electrode CTE2.

[0224] The first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the undoped semiconductor layer SEM3 can be stacked in this order. A current diffusion layer or the like can be additionally located on the first semiconductor layer SEM1. The current diffusion layer can be a layer that improves light extraction efficiency and can be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) that can transmit light.

[0225] The first contact electrode CTE1 can be located in an opening that exposes the first semiconductor layer SEM1 to contact the first semiconductor layer SEM1. The second contact electrode CTE2 can be located in an opening that exposes the second semiconductor layer SEM2 to contact the second semiconductor layer SEM2.

[0226] The first contact electrode CTE1 may be located on the pixel electrode PXE, and the second contact electrode CTE2 may be located on the common electrode CE. The first contact electrode CTE1 may be electrically connected to the pixel electrode PXE. The first contact electrode CTE1 may be directly connected to the pixel electrode PXE, or may be connected to the pixel electrode PXE via a connection electrode. The second contact electrode CTE2 may be electrically connected to the common electrode CE. The second contact electrode CTE2 may be directly connected to the common electrode CE, or may be connected to the common electrode CE via a connection electrode.

[0227] The first contact electrode CTE1 and the second contact electrode CTE2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0228] Figure 17 is a cross-sectional view showing an example of a display panel taken along line B-B' according to yet another one or more other embodiments, and Figure 6 is a cross-sectional view showing an example of a display panel taken along line B-B' according to yet another one or more other embodiments, and Figure 18 is a cross-sectional view showing Figure 17 the configuration of the light-emitting element. Figure 18 is a cross-sectional view showing Figure 17 a detailed cross-sectional view of an example of region C.

[0229] Referring to Figure 17 the display panel shown is different from the display panel referred to in Figure 15 and Figure 16 in that the light-emitting element LE is a vertical light-emitting element, the light-emitting element LE is located on the pixel electrode PXE, and the common electrode CE is located on the light-emitting element LE. A redundant description of components that have been described in one or more embodiments corresponding to Figure 7 and Figure 8 will be omitted.

[0230] The pixel electrode PXE may be located on the second organic layer 180. The pixel electrode PXE may be connected to the fourth source connection electrode SBE4 through a connection hole penetrating the second organic layer 180. The pixel electrode PXE may be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Accordingly, a voltage controlled by the first thin-film transistor TFT1 may be applied to the pixel electrode PXE.

[0231] The pixel electrode PXE may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0232] The light-emitting element LE may be located on the pixel electrode PXE. The pixel electrode PXE may have a width greater than the width of the light-emitting element LE, but the present disclosure is not limited thereto.

[0233] The contact electrodes CTE1 and CTE2 of the light-emitting element LE may directly contact the top of the pixel electrode PXE. The contact electrodes CTE1 and CTE2 may directly contact the first semiconductor layer SEM1. Accordingly, the contact electrodes CTE1 and CTE2 may electrically connect the pixel electrode PXE to the light-emitting element LE.

[0234] The common electrode CE is located on the light-emitting element LE. The common electrode CE may include a transparent conductive material (TCO) capable of transmitting light, such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0235] Figures 19 to 30 is a cross-sectional view showing a method for manufacturing a display device according to one or more embodiments.

[0236] Figures 19 to 30 is a cross-sectional view showing a structure corresponding to the formation order of the respective layers of the display device 10. Figures 19 to 30 Mainly shows the manufacturing process of the light-emitting element LE, and these generally may correspond to Figure 7 of the cross-sectional view. In addition, the drawings show one or more embodiments corresponding to Figures 5 to 8 In addition, hereinafter, the first emission region EA1 of the display device 10 will be mainly described.

[0237] Refer to Figures 19 to 26 , and a plurality of light-emitting elements LE having a first wavelength conversion layer QDL1 are formed on the base substrate BSUB.

[0238] For example, a base substrate BSUB is prepared. The base substrate BSUB may be a sapphire substrate (Al2O3) or a silicon wafer containing silicon. However, the present disclosure is not limited thereto, and in one or more embodiments, the case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0239] A plurality of semiconductor material layers SEML3, SEML2, MQWL, and SEML1 are formed on the base substrate BSUB. At Figures 19 to 30In this case, the electron blocking layer and the superlattice layer are omitted. Multiple semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, the semiconductor material layer can be formed using one of electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, and metal-organic chemical vapor deposition (MOCVD). Metal-organic chemical vapor deposition (MOCVD) is preferably used. However, the present disclosure is not limited thereto.

[0240] Precursor materials for forming the multiple semiconductor material layers can be selected to form target materials within a generally selectable range without any limitation. For example, the precursor material can be a metal precursor including an alkyl group (such as methyl or ethyl). Examples of the precursor material can include, but are not limited to, trimethylgallium Ga(CH3)3, trimethylaluminum Al(CH3)3, and triethyl phosphate (C2H5)3PO4.

[0241] For example, referring to Figure 19 , an undoped semiconductor material layer SEML3 is formed on a base substrate BSUB. The undoped semiconductor material layer SEML3 can be a semiconductor layer without a doped dopant, that is, an undoped semiconductor layer. For example, the undoped semiconductor material layer SEML3 can be undoped GaN without a doped dopant.

[0242] After that, a second semiconductor material layer SEML2, an active material layer MQWL, and a first semiconductor material layer SEML1 are sequentially formed on the undoped semiconductor material layer SEML3.

[0243] Next, referring to Figures 19 to 21 , the multiple semiconductor material layers SEML3, SEML2, MQWL, and SEML1 are etched using a mask MP1, and the multiple semiconductor material layers SEML3, SEML2, MQWL, and SEML1 are partially etched to form a groove LE-S. To obtain a light-emitting element LE that does not include the groove LE-S, the process of partially etching the multiple semiconductor material layers SEML3, SEML2, MQWL, and SEML1 is omitted.

[0244] The semiconductor material layer can be etched by a conventional method. For example, the process of etching the semiconductor material layer can be performed by a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method, etc. The dry etching method can be applied to vertical etching because anisotropic etching can be performed. In the case of using the above etching techniques, Cl2 or O2 can be used as an etchant. However, the present disclosure is not limited thereto.

[0245] Through these processes, a plurality of light-emitting elements LE can be obtained. Accordingly, the plurality of light-emitting elements LE are formed to include an undoped semiconductor layer SEM3 having a groove LE-S, a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1.

[0246] Reference Figure 22 , a first protective layer INS1 is formed on the outer surface of the plurality of light-emitting elements LE having the groove LE-S.

[0247] For example, the first protective layer INS1 is formed to cover the light-emitting element LE. Accordingly, the first protective layer INS1 can be formed not only on the outer surface of the light-emitting element LE, but also on the bottom surface and the side surface of the groove LE-S.

[0248] Next, reference Figure 23 , a first reflective layer RF1 is formed on the bottom surface S-B of the groove LE-S and the outer surface of the light-emitting element LE.

[0249] For example, after a mask is formed on the groove LE-S of the light-emitting element LE, a large voltage difference is generated in the third direction DR3, and the first reflective layer RF1 is etched with an etching material. In this case, the etching material can be moved in the third direction DR3 by voltage control, that is, moved from the top to the bottom to etch the first reflective layer RF1. Accordingly, the first reflective layer RF1 located on the horizontal plane defined by the first direction DR1 and the second direction DR2 can be removed, while the first reflective layer RF1 located on the vertical plane defined by the third direction DR3 cannot be removed. Thereafter, the first reflective layer RF1 can be formed on the bottom surface S-B of the groove LE-S using the mask.

[0250] Next, reference Figure 24 , a first wavelength conversion layer QDL1, QDL2, and QDL3 is formed in the groove LE-S. The first wavelength conversion layer QDL1, QDL2, and QDL3 can be respectively formed in a plurality of grooves LE-S. The first wavelength conversion layer QDL1, QDL2, and QDL3 can be formed to fill the groove LE-S of the light-emitting element LE. For example, the groove LE-S of the first light-emitting element LE1 can be filled with a solution in which first wavelength conversion particles WCP1 are mixed with a first base resin BRS1. The groove LE-S of the second light-emitting element LE2 can be filled with a solution in which second wavelength conversion particles WCP2 are mixed with a second base resin BRS2. The groove LE-S of the third light-emitting element LE3 can be filled with a solution in which third wavelength conversion particles WCP3 are mixed with a third base resin BRS3. The first wavelength conversion layer QDL1, QDL2, and QDL3 can be formed by solution processes such as, but not limited to, inkjet printing, imprinting using a mixed solution.

[0251] Next, as shown in Figure 25 a second protective layer INS2 is formed to cover the outer surface of the light-emitting element LE. For example, the second protective layer INS2 is formed to cover the light-emitting element LE. Thus, it may be formed to cover not only the outer surface of the light-emitting element LE but also the top surfaces of the first wavelength conversion layers QDL1, QDL2, and QDL3.

[0252] Next, as shown in Figure 26 a first contact electrode CTE1 and a second contact electrode CTE2 are formed at the light-emitting element LE.

[0253] To this end, a first opening OP1 is formed to expose the top surface of the first semiconductor layer SEM1 from one surface of the light-emitting element LE. The first opening OP1 may be formed to penetrate the first protective layer INS1 and the second protective layer INS2 such that the first semiconductor layer SEM1 is exposed from one surface of the light-emitting element LE. Similarly, a second opening OP2 is formed to expose the top surface of the second semiconductor layer SEM2 from one surface of the light-emitting element LE. The second opening OP2 may be formed to penetrate the first protective layer INS1 and the second protective layer INS2 such that the second semiconductor layer SEM2 is exposed from one surface of the light-emitting element LE.

[0254] Next, referring to Figures 27 to 29 the light-emitting element LE can be transferred onto the pixel electrode layer PXL on the substrate SUB.

[0255] First, as shown in Figure 27 a transfer substrate SPL is aligned above the light-emitting element LE. The transfer substrate SPL may be configured with a support layer and an adhesion-promoting layer located on the support layer. The support layer may be made of a transparent material having mechanical stability that allows light to pass through. The material of the support layer may include transparent polymers such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The adhesion-promoting layer may contain an adhesion-promoting material for adhering to the light-emitting element LE. For example, the adhesion-promoting material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesion-promoting material may be a material whose viscosity changes with the application of ultraviolet (UV) light or heat, and thus the adhesion-promoting layer can be easily separated from the light-emitting element LE.

[0256] The light-emitting element LE is separated from the base substrate BSUB by irradiating the base substrate BSUB with a laser (first laser). The base substrate BSUB is separated from each of the undoped semiconductor layers SEM3 of the plurality of light-emitting elements LE.

[0257] The process of separating the base substrate BSUB can be a laser lift-off (LLO) process. In the laser lift-off process using a laser, a KrF excimer laser (e.g., with a wavelength of about 248 nm) can be used as the source. In the laser lift-off process using a laser, a KrF excimer laser (e.g., with a wavelength of about 248 nm) can be used as the source. Irradiate the energy density of the excimer laser in the range of about 550 mJ / cm 2 to about 950 mJ / cm 2 , and the incident area can be in the range of about 50×50 μm 2 to about 1×1 cm 2 , but the present disclosure is not limited thereto. By irradiating the laser to the base substrate BSUB, the base substrate BSUB can be separated from the light-emitting element LE.

[0258] Thereafter, as shown in Figure 28 and Figure 29 , the light-emitting element LE can be selectively transferred onto the substrate SUB.

[0259] Prepare a substrate SUB on which a pixel electrode PXE and a common electrode CE are positioned. A plurality of light-emitting elements LE are located on the pixel electrode PXE and the common electrode CE, and one ends of a first contact electrode CTE1 and a second contact electrode CTE2 are respectively located on the pixel electrode PXE and the common electrode CE. In this case, the first contact electrode CTE1 can be connected to the pixel electrode PXE via a separate connection electrode, and the second contact electrode CTE2 can be connected to the common electrode CE via a separate connection electrode. By applying heat and pressure or irradiating a laser to the connection electrode, the light-emitting element LE is bonded to the pixel electrode PXE and the common electrode CE. Then, separate the transfer substrate SPL as shown in Figure 29 .

[0260] Refer to Figure 30, a partition wall PW is formed between multiple light-emitting elements LE. The partition wall PW can be formed to be higher than the multiple light-emitting elements LE. A second reflective layer RF2 is formed on the inner surface of the partition wall PW to be higher than the light-emitting elements LE. Next, a second wavelength conversion layer WDL is formed in the space formed by the partition wall PW. In each emission region, the second wavelength conversion layer WDL can be formed of the same material as the overlapping first wavelength conversion layers QDL1, QDL2, or QDL3. For example, similar to the first wavelength conversion layer QDL1, the second wavelength conversion layer WDL in the first emission region EA1 can be formed by filling a solution in which first wavelength conversion particles WCP1 are mixed with a first base resin BRS1. Similar to the first wavelength conversion layer QDL2, the second wavelength conversion layer WDL in the second emission region EA2 can be formed by filling a solution in which second wavelength conversion particles WCP2 are mixed with a second base resin BRS2. Similar to the first wavelength conversion layer QDL3, the second wavelength conversion layer WDL in the third emission region EA3 can be formed by filling a solution in which third wavelength conversion particles WCP3 are mixed with a third base resin BRS3.

[0261] Next, a capping layer CAP is formed on the partition wall PW, the second reflective layer RF2, and the second wavelength conversion layer WDL, and color filters CF1, CF2, and CF3 are formed on the capping layer CAP. The first color filter CF1 can be formed by an optical process. The first color filter CF1 can have a thickness of about 1 μm or less, but is not limited thereto. Similarly, the other color filters are also formed by a patterning process to overlap the openings respectively. After that, an outer coating 193 is formed on the color filters CF1, CF2, and CF3.

[0262] Figure 31 FIG. is a diagram showing a virtual reality device including a display device according to one or more embodiments. Figure 31 FIG. shows a virtual reality device 1 in which a display device 10 according to one or more embodiments is used.

[0263] Reference Figure 31 , the virtual reality device 1 according to one or more embodiments can be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments can include a display device 10, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, a left leg 30a and a right leg 30b, a reflection member 40, and a display device housing 50.

[0264] Figure 31The virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted band that can be mounted on the head without the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Figure 31 The examples shown in and can be applied to various forms and various electronic devices.

[0265] The display device housing 50 can accommodate the display device 10 and the reflective member 40. The image displayed on the display device 10 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10 through the right eye.

[0266] Figure 31 The display device housing 50 is shown to be located at the right end of the support frame 20. However, one or more embodiments of the present disclosure are not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20. In this case, the image displayed on the display device 10 may be reflected from the reflective member 40 and provided to the left eye of the user via the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be located at each of the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10 via both the left eye and the right eye.

[0267] Figure 32 is a diagram illustrating a smart device including a display device according to one or more embodiments.

[0268] refer to Figure 32 , the display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of the smart devices.

[0269] Figure 33 is a diagram illustrating a vehicle including a display device according to one or more embodiments. Figure 33 A vehicle in which a display device according to one or more embodiments is used is shown.

[0270] refer to Figure 33 The display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, to a central dashboard of a vehicle, or to a CID (Central Information Display) located on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments may be applied to each interior mirror display that replaces each of the side mirrors of the vehicle.

[0271] Figure 34 FIG. is a diagram showing a transparent display device including a display device according to one or more embodiments.

[0272] Reference Figure 34 , the display device 10 according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM thereon. Thus, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10, but also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 7 the substrate SUB of the display device 10 shown in may include a light-transmitting portion that can transmit light or may be made of a material that can transmit light.

[0273] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the embodiments of the present disclosure are disclosed only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A light emitting element, comprising: A semiconductor layer including a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, and defining at least one groove recessed downward from one surface of the first semiconductor layer; a first protective layer on the side surfaces of the semiconductor layer, on the top surface of the first semiconductor layer, and in the groove on the third semiconductor layer and on the inner surface of the semiconductor layer; as well as The wavelength conversion layer contains wavelength conversion particles in the grooves.

2. The light-emitting element according to claim 1, wherein The groove penetrates the first semiconductor layer and the active layer and is in at least a portion of the second semiconductor layer or the third semiconductor layer. 3 . The light emitting element according to claim 1 , further comprising a groove reflective layer on the first protection layer in the groove. 4 . The light emitting element according to claim 3 , further comprising an external reflective layer surrounding side surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer on the first protective layer.

5. The light emitting element according to claim 4, wherein A second protection layer is also included above the groove and covering the outer reflective layer.

6. The light-emitting element according to claim 1, wherein The groove has a cubic shape, a cylindrical shape, or a shape having different respective widths at the top and the bottom thereof.

7. The light-emitting element according to claim 1, wherein An area of ​​the groove in a plan view is 50% or less of an area of ​​the light emitting element in a plan view.

8. The light emitting element according to claim 1, further comprising: a first contact electrode, contacting the first semiconductor layer; as well as The second contact electrode contacts the second semiconductor layer.

9. A display device, comprising: A substrate, on which the pixel electrode layer is arranged; as well as A light emitting element is above the pixel electrode layer and comprises: Semiconductor layer; a first wavelength conversion layer in a groove recessed in a downward direction from one surface of one of the semiconductor layers; and A first protective layer is on side surfaces of the semiconductor layer, on a top surface of a first light emitting element among the light emitting elements, and in the groove over one of the semiconductor layers and on an inner surface of the semiconductor layer.

10. The display device according to claim 9, wherein: The semiconductor layer includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, and The groove penetrates the first semiconductor layer and the active layer and is in at least a portion of the second semiconductor layer or the third semiconductor layer.

11. The display device according to claim 9, wherein: The light emitting element further includes a groove reflective layer on the first protection layer in the groove.

12. The display device according to claim 11, wherein: The semiconductor layer includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, Wherein, the light emitting element further comprises: an external reflective layer surrounding side surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer on the first protective layer; and A second protection layer is above the groove and covers the outer reflective layer.

13. The display device according to claim 9, wherein: The groove has a cubic shape, a cylindrical shape, or a shape having different widths at the top and the bottom.

14. The display device according to claim 9, wherein: The semiconductor layer includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, and The area of ​​the groove in the plan view is 50% or less of the area of ​​the light emitting element in the plan view.

15. The display device according to claim 9, wherein: The semiconductor layer includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, The first light emitting element includes a first contact electrode contacting the first semiconductor layer and a second contact electrode contacting the second semiconductor layer, and The pixel electrode layer includes a pixel electrode connected to the first contact electrode, and a common electrode spaced apart from the pixel electrode and connected to the second contact electrode.

16. The display device according to claim 9, further comprising a common electrode on the first light emitting element, in, The semiconductor layer includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, Wherein, the pixel electrode layer includes a pixel electrode, and The first light emitting element further includes a contact electrode connecting the first semiconductor layer to the pixel electrode.

17. The display device according to claim 9, further comprising a second wavelength conversion layer above the light emitting element, in, The first wavelength conversion layer includes a light-transmitting pattern or a wavelength conversion pattern, and The second wavelength conversion layer includes another light-transmitting pattern or another wavelength conversion pattern overlapping with the first wavelength conversion layer.

18. The display device according to claim 9, wherein: The light emitting elements include the first light emitting element configured to emit light of a first wavelength band, the second light emitting element configured to emit light of a second wavelength band, and the third light emitting element configured to emit light of a third wavelength band, wherein the first wavelength conversion layer of the first light emitting element is configured to convert light of wavelengths other than the first wavelength band into light of the first wavelength band, wherein the first wavelength conversion layer of the second light emitting element is configured to convert light of a wavelength other than the second wavelength band into light of the second wavelength band, and The first wavelength conversion layer of the third light emitting element is configured to convert light of a wavelength other than the third wavelength band into light of the third wavelength band.

19. The display device according to claim 9, further comprising: a first color filter, in the first emission region, for transmitting only the first light of the first wavelength band; a second color filter, in the second emission region, for transmitting only light of a second wavelength band; as well as a third color filter, in the third emission region, for transmitting only light of a third wavelength band, wherein the light emitting element is configured to emit the first light and includes the first light emitting element in the first emission area, the second light emitting element in the second emission area, and the third light emitting element in the third emission area, and The first wavelength conversion layer of the light-emitting element includes a fourth wavelength conversion pattern, and the fourth wavelength conversion pattern includes fourth wavelength conversion particles configured to convert the first light into fourth light.

20. The display device according to claim 17, wherein: The light emitting element is configured to emit first light of a first wavelength band and includes the first light emitting element in a first emission region, a second light emitting element in a second emission region, and a third light emitting element in a third emission region, The first wavelength conversion layer of the second light-emitting element includes a first wavelength conversion pattern, and the first wavelength conversion pattern includes first wavelength conversion particles for converting the first light into second light. wherein the first wavelength conversion layer of the third light emitting element comprises a second wavelength conversion pattern, wherein the second wavelength conversion pattern comprises second wavelength conversion particles for converting the first light into third light, and The second wavelength conversion layer of the first emission region includes a light-transmitting pattern, and the light-transmitting pattern includes a base resin and a scatterer for scattering light.

21. The display device according to claim 9, further comprising: a first color filter in the first emission region and transmitting only the first light of the first wavelength band; a second color filter in the second emission region and transmitting only second light of a second wavelength band; as well as a third color filter in the third emission region and transmitting only third light of a third wavelength band, wherein the light emitting element comprises the first light emitting element configured to emit the first light, the second light emitting element configured to emit the second light, and the third light emitting element configured to emit the third light, and The first wavelength conversion layer of the light-emitting element includes a fourth wavelength conversion pattern, and the fourth wavelength conversion pattern includes fourth wavelength conversion particles configured to convert the first light into fourth light.

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