Display device and display panel

Abstract

The invention provides a display device and a display panel. The display device includes a driving circuit configured to drive a display panel. The display panel includes a plurality of light-emitting elements. The display panel comprises a first substrate and a second substrate, wherein a driving circuit is arranged on the first surface of the first substrate; a light-emitting element is arranged on the top of the second substrate; and a heat sink disposed between the first substrate and the second substrate. The heat sink includes a path pattern through which the liquid metal flows.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0193880, filed on December 28, 2023, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical field

[0003] Embodiments relate to a display device, and more particularly, to a display device and a display panel including a heat sink in which a path pattern through which liquid metal flows can be provided between substrates to improve heat dissipation performance. Background art

[0004] With the development of the information society, the demand for various types of display devices for displaying images has been increasing. In this regard, various display devices, such as liquid crystal display (LCD) devices and organic light - emitting display devices, have recently been widely used.

[0005] Among these display devices, since an LCD device does not emit light by itself, an LCD device needs to be provided with a backlight unit to emit light to its bottom (or back). Due to the additional backlight unit, the thickness of the LCD device increases. There are limitations in implementing the display device in various designs, such as flexible or circular designs. In addition, the brightness and response speed of the LCD device may decrease.

[0006] A display device having a self - light - emitting element can be designed to be thinner than a display device in which a light source is provided, and can be advantageously implemented as a flexible and foldable display device.

[0007] Display devices having self - light - emitting elements include organic light - emitting display devices including an organic material as a light - emitting layer and micro - LED display devices using micro - light - emitting diodes (LEDs) as light - emitting elements. Self - light - emitting devices such as organic light - emitting display devices or micro - LED display devices do not require a separate light source, and thus can be implemented as thinner or more versatile display devices.

[0008] Therefore, in recent years, research and development of display devices using micro - sized micro - LEDs as light - emitting elements have been carried out, and such display devices have received attention as next - generation display devices due to their high definition and high reliability.

[0009] In such a micro - LED display device, micro - LEDs are transferred to a first substrate, a circuit including transistors is formed on a second substrate, and the first substrate and the second substrate are joined to each other. In the process of joining the edges of the first substrate and the second substrate using a sealant, a gap equal to the sealant must be maintained between the first substrate and the second substrate so that the image quality can be reliably displayed.

[0010] Therefore, the heat generated during the driving of the display device may remain in the internal space between the first substrate and the second substrate, resulting in deterioration of the display panel or the driving circuit and affecting the image quality or service life of the display device.

[0011] In particular, a large amount of heat may be generated in the area where the driving circuit is located, resulting in obvious deterioration of the display panel. Summary of the Invention

[0012] In response to this, the inventors of the present disclosure have invented a display device and a display panel with improved heat dissipation performance.

[0013] An embodiment can provide a display device and a display panel including a heat sink, and a path pattern for flowing liquid metal can be provided between the substrates to improve heat dissipation performance.

[0014] An embodiment can also provide a display device and a display panel in which the density of the path pattern for flowing liquid metal in the area generating high-temperature heat can be increased to effectively improve heat dissipation performance.

[0015] An embodiment can also provide a display device and a display panel that can use a flow voltage to control the fluidity of the liquid metal flowing along the path pattern to control the heat dissipation performance based on the position.

[0016] An embodiment can provide a display device including: a display panel including a plurality of light-emitting elements; and a driving circuit configured to drive the display panel. The display panel may include: a first substrate on which a driving circuit is provided on a first surface thereof; a second substrate on which light-emitting elements are provided on a top thereof; and a heat sink provided between the first substrate and the second substrate and including a path pattern for flowing liquid metal.

[0017] An embodiment can provide a display panel including: a first substrate on which a driving circuit is provided on a first surface thereof; a second substrate on which light-emitting elements are provided on a top thereof; and a heat sink provided between the first substrate and the second substrate and including a path pattern for flowing liquid metal.

[0018] An embodiment can provide a display device including: a plurality of display panels arranged adjacent to each other; and a plurality of driving circuits configured to drive the display panels respectively. Each display panel may include: a first substrate on which a driving circuit is provided on a first surface thereof; a second substrate on which light-emitting elements are provided on a top thereof; and a heat sink provided between the first substrate and the second substrate and including a path pattern for flowing liquid metal.

[0019] According to an embodiment, a display device and a display panel may have improved heat dissipation performance.

[0020] According to an embodiment, a heat sink having a path pattern through which a liquid metal flows may be disposed between substrates to improve heat dissipation performance and achieve effects of low power consumption and reduced greenhouse gases.

[0021] According to an embodiment, the density of the path pattern through which the liquid metal flows may be increased in a region where high-temperature heat is generated to effectively improve heat dissipation performance.

[0022] According to an embodiment, a flow voltage may be used to control the fluidity of the liquid metal flowing along the path pattern to control heat dissipation performance based on position. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0024] Figure 1 shows a schematic configuration of a display device according to an embodiment;

[0025] Figure 2 is a perspective view showing a display device according to an embodiment;

[0026] Figure 3 is a perspective view schematically showing a display panel according to an embodiment;

[0027] Figure 4 shows an example of a single sub-pixel circuit in a display device according to an embodiment;

[0028] Figure 5 is a cross-sectional view specifically showing the structure of a display device according to an embodiment;

[0029] Figure 6 is a plan view conceptually showing the structure of a heat sink disposed between a first substrate and a second substrate in a display device according to an embodiment;

[0030] Figure 7 is a signal waveform diagram showing an example of the operation of a flow voltage pad in a display device according to an embodiment;

[0031] Figures 8 to 11 is a perspective view showing an example of a manufacturing process of a display panel according to an embodiment;

[0032] Figure 12 is Figure 11 a magnified perspective view of part B of;

[0033] Figure 13 is along Figure 12 a cross-sectional view taken along line A-A' of;

[0034] Figure 14 It is a signal waveform diagram showing another example of the operation of a flow voltage pad in a display device according to an embodiment;

[0035] Figure 15 It shows an example of a signal line connection configuration on the back surface of a display in a display device according to an embodiment;

[0036] Figure 16 It schematically shows a tiled display device in which a plurality of display panels are arranged adjacent to each other; and

[0037] Figure 17 It shows, as an example, a case where a display panel of a display device according to an embodiment has different path patterns in a high-temperature region and a low-temperature region. Detailed Description of Specific Embodiments

[0038] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of examples or embodiments of the present invention, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown by way of example, and the same reference numerals and symbols may be used to refer to the same or similar components even when they are shown in different drawings. In addition, in the following description of examples or embodiments of the present invention, when it is determined that a detailed description of well-known functions and components added herein may make the subject matter in some embodiments of the present invention less clear, such description will be omitted. Terms such as "comprising", "having", "including", "constituting", "consisting of", and "formed of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0039] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present invention. Each of these terms does not define the essence, order, sequence, or quantity, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0040] When referring to a first element being "connected or coupled to", "contacting or overlapping", etc. a second element, it should be understood that the first element can not only be "directly connected or coupled to" or "directly contacting or overlapping" the second element, but also a third element may be "interposed" between the first element and the second element, or the first element and the second element may be "connected or coupled", "contacting or overlapping", etc. with each other through a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacting or overlapping", etc. with each other.

[0041] When relative time terms (such as "after", "subsequently", "next", "before", etc.) are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, process, or manufacturing method, these terms can be used to describe a non - continuous or non - sequential process or operation, unless used in conjunction with the terms "directly" or "immediately".

[0042] In addition, when referring to any dimension, relative size, etc., the numerical value or corresponding information of an element or feature (e.g., level, range, etc.) should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0043] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 Schematic configuration of a display device according to an embodiment is shown.

[0045] Referring to Figure 1 , a display device 100 according to an embodiment may include: a display panel 110 having a plurality of gate lines GL, a plurality of data lines DL connected thereto, and a plurality of sub - pixels SP arranged in a matrix form; a gate driving circuit 120 configured to drive the gate lines GL; a data driving circuit 130 configured to provide a data voltage through the data lines DL; a timing controller 140 controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0046] The display panel 110 displays an image in a display area based on a gate signal transmitted from the gate driving circuit 120 through the gate lines GL and a data voltage transmitted from the data driving circuit 130 through the data lines DL.

[0047] The gate signal transmitted by the gate driving circuit 120 may include a scan signal serving as a control signal for driving the sub - pixels, a light emission signal serving as a control signal for the light emission operation of the light - emitting elements, or a sensing signal serving as a control signal for sensing the voltage of a specific node.

[0048] The display panel 110 may include a plurality of pixels arranged in a matrix form, and each pixel includes sub - pixels SP of different colors, such as white sub - pixels, red sub - pixels, green sub - pixels, and blue sub - pixels. Each sub - pixel SP may be defined by the data lines DL and the gate lines GL.

[0049] A single sub-pixel SP may include: a thin-film transistor TFT disposed in an area where a single data line DL intersects with a single gate line GL; a light-emitting element (e.g., a micro LED) that emits light using a data voltage; and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0050] For example, in the case where a display device 100 with a resolution of 2160X3840 includes three sub-pixels SP, namely a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, there may be 2160 gate lines GL, and a total of 11520 data lines DL provided by 3840 data lines DL (3840X3 = 11520) respectively connected to the three (RGB) sub-pixels SP, and each sub-pixel SP may be disposed at the intersection of the gate line GL and the data line DL.

[0051] The gate driving circuit 120 is controlled by the timing controller 140 and controls the driving timing of the sub-pixels SP by sequentially outputting gate signals to the gate lines GL provided on the display panel 110.

[0052] In the case where the display device 100 with a resolution of 2160X3840 sequentially outputs gate signals to 2160 gate lines (GL) from the first gate line to the 2160th gate line, this may be referred to as 2160-phase driving. In another example, in the case where gate signals are sequentially output to the first four gate lines from the first gate line to the fourth gate line, and then gate signals are sequentially output to the next four gate lines from the fifth gate line to the eighth gate line (i.e., gate signals are sequentially output to each gate line group including four gate lines GL), this may be referred to as four-phase driving. In other words, the case of sequentially outputting gate signals to each gate line group including N gate lines GL may be referred to as N-phase operation.

[0053] In this case, the gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs), which may be located only on the first side or two opposite sides of the display panel 110 according to the driving system. In another example, the gate driving circuit 120 may be embedded in the border of the display panel 110 to have an in-panel gate (GIP) structure.

[0054] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Thereafter, according to the application timing of the gate signal, the data voltage is output to the data line DL through the gate line GL respectively, so that each sub-pixel SP connected to the data line DL displays a light-emitting signal with a brightness corresponding to the data voltage.

[0055] Similarly, the data driving circuit 130 may include one or more source driving integrated circuits (SDICs), which may be connected to the bonding pads of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed on the display panel 110.

[0056] In some cases, each source driving integrated circuit may be integrated on the display panel 110. Additionally, each source driving integrated circuit may be implemented in a chip on film (COF) manner. In this case, each source driving integrated circuit may be mounted on a circuit film and electrically connected to the data lines DL of the display panel 110 through the circuit film.

[0057] The timing controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. In other words, the timing controller 140 controls the gate driving circuit 120 to output gate signals according to the timing implemented for each frame, and on the other hand, transmits the image data DATA received from the outside to the data driving circuit 130.

[0058] Here, the timing controller 140 receives several timing signals (including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK), and the image data DATA from an external host system 200.

[0059] The host system 200 may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device.

[0060] Therefore, the timing controller 140 generates control signals by using the various timing signals received from the host system 200, and transmits the control signals to the gate driving circuit 120 and the data driving circuit 130.

[0061] For example, the timing controller 140 outputs various gate control signals (including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE) to control the gate driving circuit 120. The gate start pulse GSP controls the timing at which the gate driving integrated circuit of the gate driving circuit 120 starts to operate. Additionally, the gate clock GCLK is a clock signal commonly input to the gate driving integrated circuit to control the shift timing of the gate signals. Additionally, the gate output enable signal GOE specifies the timing information of the gate driving integrated circuit.

[0062] The timing controller 140 also outputs various data control signals (including a source start pulse SSP, a source clock SCLK, and a source output enable signal SOE) to control the data driving circuit 130. Here, the source start pulse SSP controls the timing at which the source driver integrated circuit of the data driving circuit 130 starts data sampling. The source clock SCLK is a clock signal that controls the timing of data sampling by the source driver integrated circuit. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0063] Such a display device 100 may include a power management circuit 150 that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or controls the various voltages or currents supplied to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc.

[0064] The power management circuit 150 regulates the DC input voltage Vin provided from the host system 200 to generate the power required to drive the display panel 100, the gate driving circuit 120, and the data driving circuit 130.

[0065] On the other hand, the sub-pixel SP may be located at the intersection of the gate line GL and the data line DL, and a light-emitting element may be provided in each sub-pixel SP. For example, a micro-LED display device may include light-emitting elements (e.g., micro-LEDs) in the sub-pixels SP respectively, and may display an image by controlling the current flowing through the light-emitting elements using a data voltage.

[0066] Such a display device 100 may be various types of devices, such as a micro-LED display, a liquid crystal display, an organic light-emitting display, a plasma display panel, etc.

[0067] Figure 2 is a perspective view showing a display device according to an embodiment.

[0068] Referring to Figure 2 , a display device 100 according to an embodiment is shown configured to implement one or more source driver integrated circuits SDIC included in the data driving circuit 130 and one or more gate driver integrated circuits GDIC included in the gate driving circuit 120 using an in-panel gate (GIP) structure among various structures (e.g., TAB, COG, and COF structures).

[0069] Each gate driver integrated circuit GDIC included in the gate driving circuit 120 may be mounted on the gate film GF, and a first side of the gate film GF may be electrically connected to the display panel 110. In addition, wirings (or signal lines) for electrically connecting the gate driver integrated circuit GDIC to the display panel 110 may be provided on top of the gate film GF.

[0070] Similarly, the source driver integrated circuit (SDIC) included in the data driving circuit 130 can be mounted on the source film SF, and the first side of each source film SF can be electrically connected to the display panel 110. In addition, wirings for electrically connecting the source driver integrated circuit SDIC and the display panel 110 can be provided on the top of the source film SF.

[0071] Such a display device 100 can include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) on which control components and various electronic devices are mounted for circuit connection between the source driver integrated circuit SDIC and other devices.

[0072] Here, the source printed circuit board SPCB can be connected to the second side of the source film SF on which the source driver integrated circuit SDIC is mounted. That is, the source film SF on which the source driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110 on the first side and to the source printed circuit board SPCB on the second side.

[0073] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 can supply a driving voltage or current to the display panel 110, the data driving circuit 130, the gate driving circuit 120, etc., or control the voltage or current supplied to the display panel 110, the data driving circuit 130, the gate driving circuit 120, etc.

[0074] The source printed circuit board SPCB and the control printed circuit board CPCB can be circuit-connected through at least one connection member. The connection member can include, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. In this case, the connection member connecting the source printed circuit board SPCB and the control printed circuit board CPCB can vary according to the size and type of the display device 100. In addition, the source printed circuit board SPCB and the control printed circuit board CPCB can be integrated and implemented on a single printed circuit board.

[0075] In the display device 100 having the above configuration, the power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through a flexible printed circuit or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided to emit light or sense a specific sub-pixel SP in the display panel 110 through the source driver integrated circuit SDIC.

[0076] In this case, each sub-pixel SP arranged in the display panel 110 of the display device 100 may include a micro LED as a light-emitting element and circuit elements (such as driving transistors) to drive the micro LED.

[0077] The type and number of circuit elements of each sub-pixel (SP) may vary according to the function provided by the sub-pixel SP, the design of the sub-pixel SP, and the like.

[0078] Hereinafter, a display device using a micro LED as a light-emitting element will be described as an example.

[0079] Figure 3 is a perspective view schematically showing a display panel according to an embodiment.

[0080] Referring to Figure 3 , the display panel 110 according to an embodiment may include a substrate SUS and a plurality of micro LEDs mLED mounted on the substrate SUB.

[0081] The substrate SUB may include a transparent material, such as glass, and a plurality of pixels Pixel are formed on the substrate SUB. In each pixel Pixel, a plurality of micro LEDs mLED1, mLED2, and mLED3 for driving the micro LED, a plurality of transistors, and signal lines may be formed.

[0082] In the display panel 110, in a state where the driving transistor for driving the micro LED mLED is turned on, the micro LED mLED is turned on by using the data voltage applied through the data line DL to display an image.

[0083] In this regard, three micro LEDs mLED1, mLED2, and mLED3 that respectively emit red light, green light, and blue light may be mounted on each pixel Pixel of the substrate SUB, and the data voltage causes each of the micro LEDs mLED1, mLED2, and mLED3 to emit light of a corresponding color.

[0084] Here, a region where the red micro LED mLED1, the green micro LED mLED2, or the blue micro LED mLED3 is separately provided may be a sub-pixel SP. Therefore, a single pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0085] The micro LEDs mLED1, mLED2, and mLED3 located on the display panel 110 may be fabricated by a process separate from the transistor process on the substrate SUB.

[0086] For example, in the micro-LED display device 100, the transistors and various signal lines provided on the substrate SUB are formed by photolithography, but the micro-LEDs mLED1, mLED2, and mLED3 are fabricated through a separate process and can be prepared by transferring the separately prepared micro-LEDs mLED1, mLED2, and mLED3 onto the substrate SUB.

[0087] The micro-LED mLED is a light-emitting diode with a size of 10 μm to 100 μm and can be prepared by growing a thin film of an inorganic material (such as Al, Ga, N, P, As, or In) on a sapphire substrate or a silicon (Si) substrate and then cutting and dividing the sapphire substrate or the silicon substrate. Since the micro-LED mLED is prepared in a micro size in this way, the micro-LED mLED can be transferred onto a flexible substrate formed of, for example, plastic, enabling the preparation of a flexible display device. In addition, since the micro-LED mLED is formed by growing a thin film of an inorganic material, its manufacturing process can be simplified and its yield can be increased compared to an organic light-emitting layer.

[0088] Furthermore, since the separately separated micro-LEDs mLED are transferred onto a large substrate SUB, a large display device can be easily manufactured. Therefore, compared with a light-emitting element using an organic material, the micro-LED mLED formed of an inorganic material has the advantages of high brightness, long lifespan, and low manufacturing cost.

[0089] Figure 4 An example of a single sub-pixel circuit in a display device according to an embodiment is shown.

[0090] Referring to Figure 4 , the sub-pixel circuit of the display device 100 according to an embodiment may include a micro-LED mLED, a driving transistor DRT, a plurality of switching transistors T1 to T5, and a storage capacitor Cst.

[0091] The driving transistor DRT and the plurality of switching transistors T1 to T5 included in the sub-pixel circuit may be implemented as PMOS low-temperature polycrystalline silicon (LTPS) transistors to achieve the required response characteristics.

[0092] In another example, at least one of the switching transistors T1 to T5 may be implemented as an NMOS oxide transistor or a PMOS oxide transistor with good cut-off leakage current characteristics, and the remaining switching transistors may be implemented as PMOS LTPS transistors with good response characteristics.

[0093] The micro-LED mLED emits light using a driving current regulated by the gate-source voltage Vgs of the driving transistor DRT. The anode of the micro-LED mLED is connected to the fourth node P4, and the cathode of the micro-LED mLED is connected to the low-potential pixel voltage EVSS.

[0094] The driving transistor DRT controls the current flowing through the micro LED mLED according to the gate-source voltage Vgs. The gate of the driving transistor DRT is connected to the second node P2, the drain (or source) is connected to the driving voltage line providing the high-potential pixel voltage EVDD, and the source (or drain) is connected to the third node P3.

[0095] The sub-pixel circuit may include a first switching transistor T1 to a fifth switching transistor T5 and a storage capacitor Cst, through which the gate-source voltage Vgs can be sampled to compensate for the threshold voltage or mobility of the driving transistor DRT.

[0096] The first switching transistor T1 is connected to the data line DL and the first node P1, and is switched according to the first scan signal (SCAN1). In the first switching transistor T1, the gate is connected to the first gate line to which the first scan signal SCAN1 is applied, the drain (or source) is connected to the data line DL, and the source (or drain) is connected to the first node P1.

[0097] The second switching transistor T2 is connected to the second node P2 and the third node P3, and is switched according to the second scan signal SCAN2. In the second switching transistor T2, the gate is connected to the second gate line to which the second scan signal SCAN2 is applied, the drain (or source) is connected to the third node P3, and the source (or drain) is connected to the second node P2.

[0098] In the second switching transistor T2, one electrode is connected to the gate of the driving transistor DRT, so the second switching transistor T2 is required to have good cut-off current characteristics. Therefore, the second switching transistor T2 can be designed to have a double-gate structure to reduce the cut-off leakage current.

[0099] In the double-gate structure, the first gate and the second gate are connected to each other to have the same potential, and compared with the single-gate structure, the channel length of the double-gate structure is increased. The longer channel length can increase the resistance and reduce the cut-off leakage current, thereby achieving the stability of operation. However, the second switching transistor T2 can also be implemented with a single-gate structure, and in this case, the second switching transistor T2 can be implemented as an oxide transistor.

[0100] The third switching transistor T3 is connected to the first node P1 and the reference voltage line to which the reference voltage Vref is applied, and is switched according to the light-emitting signal EM. In the third switching transistor T3, the gate is connected to the third gate line to which the light-emitting signal EM is applied, the drain (or source) is connected to the first node P1, and the source (or drain) is connected to the reference voltage line.

[0101] The fourth switching transistor T4 is connected to the third node P3 and the fourth node P4 (i.e., the anode of the light-emitting element ED), and is switched according to the light-emitting signal EM. In the fourth switching transistor T4, the gate is connected to the third gate line to which the light-emitting signal EM is applied, the drain (or source) is connected to the third node P3, and the source (or drain) is connected to the fourth node P4. Since the fourth switching transistor T4 controls the driving current flowing to the micro LED mLED, the fourth switching transistor T4 may be referred to as a light-emitting control transistor.

[0102] The fifth switching transistor T5 is connected to the fourth node P4 and the reference voltage line, and is switched according to the second scan signal SCAN2. In the fifth switching transistor T5, the gate is connected to the second gate line to which the second scan signal SCAN2 is applied, the drain (or source) is connected to the fourth node P4, and the source (or drain) is connected to the reference voltage line.

[0103] The storage capacitor Cst is connected to the first node P1 and the second node P2.

[0104] The structure of the above sub-pixel circuit is provided as an example in a 6T1C structure including six (6) transistors and one (1) capacitor, for illustrative purposes only, and may also include one or more transistors, or in some cases one or more capacitors. In another example, each sub-pixel SP may have the same structure, and a part of the sub-pixels SP in the sub-pixel SP may have different structures.

[0105] Figure 5 is a cross-sectional view specifically showing the structure of a display device according to an embodiment.

[0106] Referring to Figure 5 , the display device 100 according to an embodiment may include thin film transistors TFTs provided in the display area DA of the substrate 111 and pads 152 and 153 provided in the pad area PA of the substrate 111.

[0107] The substrate 111 includes a first substrate 111a and a second substrate 111b that can be joined to each other by a sealant 155 provided in the pad area PA. In this case, each of the first substrate 111a and the second substrate 111b may be formed of a transparent material such as, but not limited to, glass, or may be formed of other transparent materials. For example, the first substrate 111a and the second substrate 111b may include a flexible transparent material. In addition, the first substrate 111a and the second substrate 111b may be formed of the same material, or may be formed of different materials.

[0108] In addition, a heat sink 119 having a path pattern through which liquid metal flows may be provided in the display area DA between the first substrate 111a and the second substrate 111b. Liquid metal that can flow by using an electrokinetic voltage may be injected into the path pattern formed in the heat sink 119. The path pattern formed in the heat sink 119 may include a plurality of separate paths, and the shape of the path pattern may vary according to the position of the display panel 110.

[0109] The thin film transistor TFT may include a gate 101 formed over the second substrate 111b, a gate insulating layer 112 covering the gate 101 over the entire area of the second substrate 111b, a semiconductor layer 103 formed on the gate insulating layer 112, a source 105 formed over the semiconductor layer 103, and a drain 107.

[0110] The gate 101 may be formed of a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al), or an alloy of the foregoing metals.

[0111] The gate insulating layer 112 may include a single layer formed of an inorganic insulating material (e.g., silicon oxide (SiOx) or silicon nitride (SiNx)), or a stacked structure of multiple layers formed of silicon oxide (SiOx) and silicon nitride (SiNx).

[0112] The semiconductor layer 103 may include an amorphous semiconductor (e.g., amorphous silicon), or may include an oxide semiconductor such as indium gallium zinc oxide (IGZO), titanium oxide (TiO2), zinc oxide (ZnO), tungsten oxide (WO3), or tin oxide (SnO2). When the semiconductor layer 103 is formed of an oxide semiconductor, the size of the thin film transistor TFT may be reduced, the driving power may be lowered, and the electron mobility may be increased.

[0113] Each of the source 105 and the drain 107 may be formed of a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al), or an alloy of the foregoing metals.

[0114] The drain 107 may be used as a first electrode to apply a signal to the micro LED mLED.

[0115] The first pad 152 provided in the pad area PA may be formed of a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al), or an alloy of the foregoing metals. The first pad 152 may be formed by a process different from that of the gate 101 of the thin film transistor TFT, but for simplicity of the process, it may be formed by the same process as the gate 101. In this case, the first pad 152 may be formed over the gate insulating layer 112.

[0116] The first pad 152 can be formed by a process different from that of the source 105 and drain 107 of the thin film transistor TFT, but for simplicity of the process, it can be formed by the same process as the source 105 and drain 107.

[0117] The second electrode 109 is formed over the gate insulating layer 112 of the display area DA. The second electrode 109 can be formed of a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al), or an alloy of the foregoing metals, and can be formed by the same process as the drain 107 of the thin film transistor TFT.

[0118] The first insulating layer 114 is formed over the second substrate 111b on which the thin film transistor TFT is formed, and the micro LED mLED is disposed over the first insulating layer 114 in the display area DA. Removal of a part of the first insulating layer 114 and the disposition of the micro LED mLED are shown here, but the micro LED mLED can also be disposed without removing the first insulating layer 114.

[0119] The first insulating layer 114 can include an organic layer (e.g., photoacrylic), or can be formed as a stacked structure of an inorganic layer / organic layer or a stacked structure of an inorganic layer / organic layer / inorganic layer.

[0120] The second insulating layer 116 is formed over the first insulating layer 114 on which the micro LED mLED is mounted.

[0121] The second insulating layer 116 can include an organic layer (e.g., photoacrylic), or can include a stacked structure of an inorganic layer / organic layer or a stacked structure of an inorganic layer / organic layer / inorganic layer. The second insulating layer 116 covers the top region of the micro LED mLED.

[0122] The first contact hole 114a and the second contact hole 114b are respectively formed in the first insulating layer 114 and the second insulating layer 116 over the thin film transistor TFT and the second electrode 109 such that the drain 107 of the thin film transistor TFT and the second electrode 109 are exposed to the outside. In addition, the third contact hole 116a and the fourth contact hole 116b are respectively formed in the second insulating layer 116 over the first microelectrode 141 and the second microelectrode 143 of the micro LED mLED such that the first microelectrode 141 and the second microelectrode 143 are exposed to the outside.

[0123] The first connection electrode 117a and the second connection electrode 117b are formed over the second insulating layer 116, and the first connection electrode 117a and the second connection electrode 117b each contain a transparent metal oxide such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), or indium gallium oxide (IGO).

[0124] The first connection electrode 117a is electrically connected to the drain 107 of the thin film transistor TFT and the first microelectrode 141 through the first contact hole 114a and the third contact hole 116a. The second connection electrode 117b is electrically connected to the second electrode 109 and the second microelectrode 143 through the second contact hole 114b and the fourth contact hole 116b.

[0125] The control module 170 is disposed on the bottom surface of the first substrate 111a in the display area DA. The control module 170 may be a control printed circuit board CPCB on which a timing controller 140, a memory (such as an EEPROM), a power management circuit 150 for driving the micro LED mLED, and various signal lines are formed, or a printed circuit board on which a gate driving circuit 120 or a data driving circuit 130 for applying a gate signal or a data signal to the gate line and the data line is provided.

[0126] In addition, a signal line 151 is formed above the bottom surface of the first substrate 111a to electrically connect the second pad 153 and the control module 170.

[0127] A first through hole 113a penetrating from the top surface to the bottom surface is formed in the first substrate 111a, and a second through hole 113b penetrating from the top surface to the bottom surface is formed in the second substrate 111b. The first through hole 113a and the second through hole 113b may be formed at the same position, or may be spaced apart from each other by a predetermined distance.

[0128] The first through hole 113a may be formed in the area where the first pad 152 is provided, and the second through hole 113b may be formed in the area where the second pad 153 is provided.

[0129] Connection lines 154 may be respectively formed in the first through hole 113a and the second through hole 113b. The connection lines 154 electrically connect the first pad 152 and the second pad 153, so that the signal output by the control module 170 is transmitted to the first pad 152 on the top surface of the second substrate 111b through the second pad 153 and the connection lines 154, and then the thin film transistor TFT is turned on through the gate line and the data line.

[0130] When the thin film transistor TFT is turned on, a signal is provided to the micro LED mLED through the thin film transistor TFT and the second electrode 109, so that the micro LED mLED emits light.

[0131] A connection pattern 154a may be formed between the first substrate 111a and the second substrate 111b to connect the connection lines 154 formed in the first through-hole 113a and the second through-hole 113b. When the first through-hole 113a and the second through-hole 113b are formed at the same position, the connection pattern 154a only connects the connection lines 154 formed in the first through-hole 113a and the second through-hole 113b. When the first through-hole 113a and the second through-hole 113b are formed at different positions, the connection pattern 154a may be formed in the shape of a signal line with a predetermined length between the first substrate 111a and the second substrate 111b to connect the connection lines 154 formed in the first through-hole 113a and the second through-hole 113b.

[0132] A plurality of first through-holes 113a and a plurality of second through-holes 113b may be formed to be connected one-to-one to a plurality of gate pads and a plurality of data pads provided on the top surface of the second substrate 111b.

[0133] The connection lines 154 may be formed by laminating a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al), or an alloy thereof by sputtering and then etching. In another example, the connection lines 154 may be formed by introducing a viscous liquid metal into the first through-hole 113a and the second through-hole 113b.

[0134] The connection lines 154 may fill the entire first through-hole 113a and the second through-hole 113b, or may be formed with a predetermined thickness on the inner circumferential surface of the first through-hole 113a and the second through-hole 113b. When the connection lines 154 are only formed on the inner circumferential surface of the first through-hole 113a and the second through-hole 113b, the inside of the first through-hole 113a and the second through-hole 113b may be filled with an insulating material, such as an inorganic material or an organic material.

[0135] In addition, a buffer layer 118 including an inorganic material or an organic material may be formed above the top surface of the second substrate 111b to cover the micro-LED mLED and the first pad 152 on the top surface of the second substrate 111b.

[0136] In the display device 100 of the present disclosure, a heat sink 119 having a path pattern for allowing a liquid metal to flow may be provided between the first substrate 111a and the second substrate 111b, thereby improving the heat dissipation performance of the display panel 110 and bringing effects of low power consumption and reduction of greenhouse gases.

[0137] Figure 6 It is a plan view conceptually showing the structure of a heat sink provided between a first substrate and a second substrate in a display device according to an embodiment.

[0138] Refer to Figure 6, the display device 100 according to an embodiment may include a heat sink 119 located between a first substrate 111a and a second substrate 111b to cool the heat dissipated (or radiated) from the micro LED mLED.

[0139] The heat sink 119 may include a sheet body 211, a liquid metal inlet 212 provided on a first side of the sheet body 211 for injecting liquid metal, a path pattern 213 for allowing the liquid metal to flow along the surface of the sheet body 211, a first flow voltage pad 214a for applying a voltage to the liquid metal inlet 212, and a second flow voltage pad 214b connected to one end of the path pattern 213.

[0140] The heat sink 119 may be disposed between the first substrate 111a and the second substrate 111b of the display panel 110. The sheet body 211 may be formed of polyimide or may be formed of an adhesive material capable of bonding the first substrate 111a and the second substrate 111b.

[0141] The sheet body 211 may be formed of a transparent material to minimize the reduction in the brightness of the micro LED mLED.

[0142] The liquid metal inlet 212 is a part for injecting liquid metal to transfer the heat generated in the high-temperature region of the display panel 110 to the low-temperature region. The liquid metal inlet 212 may be disposed in the region of the display panel 110 that generates high-temperature heat. For example, the liquid metal inlet 212 may be disposed at a position adjacent to the driving circuit.

[0143] In another example, when the display device 100 is provided with a cooling system, the liquid metal inlet 212 may be disposed at a position adjacent to the cooling system.

[0144] The liquid metal may be formed of gallium metal, a gallium-indium eutectic alloy, or a gallium-indium-tin alloy (Galinstan).

[0145] The gallium-indium eutectic alloy is an alloy of gallium and indium with a constant mass ratio, and its resistivity is not much different from that of a metal. This gallium-indium eutectic alloy is in a liquid phase state above 15.3 °C and thus has great flexibility.

[0146] The gallium-indium-tin alloy is an alloy of gallium, indium, and tin, which has a low melting point of -19 °C and is thus in a liquid state at room temperature.

[0147] The path pattern 213 has a groove structure engraved on the upper surface of the sheet body 211 to allow the liquid metal to flow through. The path pattern 213 may be formed in various shapes and may extend in a zigzag pattern along the space between adjacent heat-dissipating (or heat-radiating) micro LEDs mLED.

[0148] The path pattern 213 may be formed as a single pattern on the display panel 110 or may be formed as multiple separate patterns.

[0149] A first flow voltage pad 214a that can apply a flow voltage to the flow of the liquid metal is provided at a position adjacent to the liquid metal inlet 212. In addition, a second flow voltage pad 214b is provided on the second side of the path pattern 213.

[0150] For example, when a positive (+) voltage is applied to the first flow voltage pad 214a and a negative (-) voltage is applied to the second flow voltage pad 214b, the liquid metal will migrate from the liquid metal inlet 212 to the second flow voltage pad 214b.

[0151] Therefore, the liquid metal that has absorbed the heat generated near the liquid metal inlet 212 can flow along the path pattern 213 to the cooler second flow voltage pad 214b, thereby reducing the heat temperature in the hot region.

[0152] When the liquid metal flows to the second flow voltage pad 214b and its temperature decreases, the flow of the liquid metal back to the liquid metal inlet 212 can be controlled by changing the potential of the second flow voltage pad 214b to a (+) voltage and changing the potential of the first flow voltage pad 214a to a (-) voltage.

[0153] In this way, the heat generated in the high-temperature region of the display panel 110 can be absorbed by the liquid metal and move along the path pattern 213 to the low-temperature region, thereby achieving the effect of dissipating the heat generated in the high-temperature region of the display panel 110 to the low-temperature region.

[0154] Figure 7 It is a signal waveform diagram showing an example of the operation of the flow voltage pad in the display device according to the embodiment.

[0155] Refer to Figure 7 , the display device 100 according to the embodiment may include a heat sink 119 located between the first substrate 111a and the second substrate 111b to cool the heat dissipated from the micro LED mLED.

[0156] In this case, a path pattern 213 through which the liquid metal flows is provided in the heat sink 119. A first flow voltage pad 214a may be provided at a position adjacent to the liquid metal inlet 212 of the path pattern 213, and through which a flow voltage can be applied to the flow of the liquid metal, and a second flow voltage pad 214b may be provided at one end of the path pattern 213.

[0157] In this state, during the first period T1, a high voltage HV with a (+) level is applied to the first fluid voltage pad 214a, and a low voltage LV with a (-) level is applied to the second fluid voltage pad 214b. Therefore, during the first period T1, the liquid metal flows from the liquid metal inlet 212 to the second fluid voltage pad 214b located at the end of the path pattern 213.

[0158] In this case, the first period T1 can be determined by the first velocity VL1 at which the liquid metal flows along the length LP from the liquid metal inlet 212 to the end of the path pattern 213. That is to say, the first period T1 can be determined as the length LP of the path pattern divided by the first velocity VL1 of the liquid metal.

[0159] During the first period T1, when the liquid metal reaches the end of the path pattern 213, the liquid metal dissipates its internal heat.

[0160] After the first period T1, during the second period T2, a low voltage LV with a (-) level is applied to the first fluid voltage pad 214a, and a high voltage HV with a (+) level is applied to the second fluid voltage pad 214b. Therefore, during the second period T2, the liquid metal flows from the second fluid voltage pad 214b located at the end of the path pattern 213 to the liquid metal inlet 212.

[0161] In this case, the second period T2 can be determined by the second velocity VL2 at which the liquid metal flows along the length LP of the path pattern 213. That is to say, the second period T2 can be determined as the length LP of the path pattern divided by the second velocity VL2 of the liquid metal.

[0162] In this way, the liquid metal absorbs heat from the high-temperature region during the first period T1 and dissipates heat while flowing to the low-temperature region, and then flows back to the high-temperature region to absorb heat during the second period T2, thereby achieving the effect of dissipating the heat absorbed from the high-temperature region to the low-temperature region.

[0163] In addition, here it is shown that a single first fluid voltage pad 214a and a single second fluid voltage pad 214b are respectively provided at opposite ends of the path pattern 213, but a plurality of fluid voltage pads can also be provided at the middle position of the path pattern 213 to precisely control the flow path and flow velocity of the liquid metal.

[0164] The present disclosure is not limited to a display device including a micro-LED mLED or a display device having a tiled structure, but is applicable to any display device having a structure in which a path pattern through which liquid metal can flow can be provided and a heat sink 119 is provided between the first substrate 111a and the second substrate 111b.

[0165] Figures 8 to 11 is a perspective view showing an example of a manufacturing process of a display panel according to an embodiment.

[0166] First, in the display panel 110 according to the embodiment, a heat sink 119 is formed on the first substrate 111a, as Figure 8 shown.

[0167] The heat sink 119 has a liquid metal inlet 212 for injecting liquid metal and a path pattern 213 through which the liquid metal can flow.

[0168] The liquid metal inlet 212 can be set adjacent to a position where high-temperature heat is generated in the display panel 110. Additionally, when the display panel 110 is disposed in a cooling system, the liquid metal inlet 212 can be set adjacent to the cooling system. The main body of the heat sink 119 can be formed of polyimide.

[0169] In this case, an adhesive can be provided around at least a part of the heat sink 119 such that the heat sink 119 can be formed smaller than the first substrate 111a.

[0170] Next, as Figure 9 shown, a sealant 155 is provided around the heat sink 119, and liquid metal is injected into the liquid metal inlet 212.

[0171] The sealant 155 can be used to seal the peripheral portion of the heat sink 119 while bonding the lower first substrate 111a and the upper second substrate 111b. Thus, the sealant 155 can be formed of an adhesive material.

[0172] The liquid metal injected into the liquid metal inlet 212 can be formed of gallium metal, gallium-indium eutectic alloy, gallium-indium-tin alloy, etc.

[0173] As Figure 10 shown, a plurality of flow voltage pads 214 can be provided on the second substrate 111b to control the flow of the liquid metal. The flow voltage pads 214 can be provided at positions corresponding to the liquid metal inlet 212 and at positions corresponding to the ends of the path pattern 213.

[0174] In addition, flow voltage pads 214 can also be provided at main bending points where the direction of the path pattern 213 changes to effectively control the flow direction and flow velocity of the liquid metal.

[0175] According to the flow direction of the liquid metal, a (+) flow voltage or a (-) flow voltage can be applied. Therefore, the flow voltage pad 214 can control the voltage level applied to the flow voltage pad 214, or the flow voltage pad 214 can be arranged to be divided into a high-potential flow voltage pad to which a (+) flow voltage is applied and a low-potential flow voltage pad to which a (-) flow voltage is applied.

[0176] The flow voltage pad 214 is shown here as being provided on the second substrate 111b, but the flow voltage pad 214 can also be provided on the first substrate 111a.

[0177] After the second substrate 111b is prepared, the first substrate 111a and the second substrate 111b are joined to each other to cover the heat sink 119, as Figure 11 shown. The first substrate 111a and the second substrate 111b can be joined by a sealant 155 provided at the peripheral portion of the heat sink 119.

[0178] In this case, an adhesive layer such as an optically clear adhesive (OCA) can also be provided between the heat sink 119 having the liquid metal path pattern 213 and the second substrate 111b to prevent leakage of the liquid metal.

[0179] Figure 12 is Figure 11 an enlarged perspective view of part B of Figure 13 is a cross-sectional view taken along the line A-A' of Figure 12 shown.

[0180] Referring to Figure 12 and Figure 13 , the display device 100 of the present disclosure can include a heat sink 119 having a path pattern 213 through which liquid metal flows, and provided between the first substrate 111a and the second substrate 111b of the display panel 110.

[0181] The path pattern 213 includes engraved grooves formed in the sheet body 211, and the engraved grooves can extend in a zigzag pattern between the micro LEDs mLEDs located above it.

[0182] The flow voltage pad 214 can be provided at the end or the bend of the path pattern 213, and a flow voltage is applied to the flow voltage pad 214 here to control the flow of the liquid metal. The flow voltage pad 214 can be provided on the first substrate 111a, or can be provided on the second substrate 111b.

[0183] The flow voltage pads located at the ends of the path pattern 213 can be configured such that a (+) voltage and a (-) voltage can be selectively applied to individual pads, or can include a high-potential flow voltage pad 214b-1 to which a high-potential flow voltage having a (+) level is applied and a low-potential flow voltage pad 214b-2 to which a low-potential flow voltage having a (-) level is applied.

[0184] In addition, the flow voltage pads 214b-1 and 214b-2 located at the ends of the path pattern 213 can be arranged to surround the side surface of the second substrate 111b, and can overlap with the sealant 155 located therebelow and a part of the path pattern 213.

[0185] Figure 14 is a signal waveform diagram showing another example of the operation of the flow voltage pads in the display device according to the embodiment.

[0186] Refer to Figure 14 According to an embodiment, the display device 100 may include a heat sink 119 disposed between the first substrate 111a and the second substrate 111b to cool the heat dissipated from the micro LED mLED.

[0187] In this case, a path pattern 213 through which liquid metal flows is provided in the heat sink 119. A first high-potential flow voltage pad 214a-1 and a first low-potential flow voltage pad 214a-2 capable of applying a flow voltage to the flow of the liquid metal can be provided at a position adjacent to the liquid metal inlet 212 of the path pattern 213, and a second high-potential flow voltage pad 214b-1 and a second low-potential flow voltage pad 214b-2 can be provided at the end of the path pattern 213.

[0188] Here, the high-potential flow voltage pads 214a-1 and 214b-1 are pads to which a high voltage HV having a (+) level is applied, and the low-potential flow voltage pads 214a-2 and 214a-2 are pads to which a low voltage LV having a (-) level is applied.

[0189] In this state, within the first time period T1, a high voltage HV having a (+) level is applied to the first high-potential flow voltage pad 214a-1, while the first low-potential flow voltage pad 214a-2 is maintained at the ground level. In addition, a low voltage LV having a (-) level is applied to the second low-potential flow voltage pad 214b-2, while the second high-potential flow voltage pad 214b-1 is maintained at the ground level. Therefore, during the first time period T1, the liquid metal flows from the liquid metal inlet 212 to the second flow voltage pads 214b-1 and 214b-2 located at the end of the path pattern 213.

[0190] In this case, the first period T1 can be determined by a first velocity VL1 of the liquid metal flowing along a length LP from the liquid metal inlet 212 to an end of the path pattern 213. That is to say, the first period T1 can be determined as the length LP of the path pattern divided by the first velocity VL1 of the liquid metal.

[0191] During the first period T1, when the liquid metal reaches the end of the path pattern 213, the liquid metal dissipates internal heat.

[0192] After the first period T1, during a second period T2, a low voltage LV having a (-) level is applied to the first low-potential flow voltage pad 214a-2, while the first high-potential flow voltage pad 214a-1 is kept at the ground level. In addition, a high voltage HV having a (+) level is applied to the second high-potential flow voltage pad 214b-1, while the second low-potential flow voltage pad 214b-2 is kept at the ground level. Accordingly, during the second period T2, the liquid metal flows from the second flow voltage pads 214b-1 and 214b-2 located at the end of the path pattern 213 toward the liquid metal inlet 212.

[0193] In this case, the second period T2 can be determined by a second velocity VL2 of the liquid metal flowing along the length LP of the path pattern 213. That is to say, the second period T2 can be determined as the length LP of the path pattern divided by the second velocity VL2 of the liquid metal.

[0194] In such a manner, the liquid metal dissipates the heat absorbed from the high-temperature region while flowing toward the low-temperature region during the first period T1, and then flows back to the high-temperature region to absorb heat during the second period T2, thereby achieving the effect of dissipating the heat absorbed from the high-temperature region to the low-temperature region.

[0195] Figure 15 An example of a signal line connection configuration on the back surface of a display in a display device according to an embodiment is shown.

[0196] Refer to Figure 15 , a display device 100 according to an embodiment may have a driving voltage line DVL that transmits a driving voltage to a driving voltage pad DP and a flow voltage line FVL that transmits a flow voltage to a flow voltage pad 214, wherein the driving voltage line DVL and the flow voltage line FVL are provided on the back surface of a first substrate 111a.

[0197] That is, the driving voltage line DVL extending through the printed circuit board (PCB) bonded to the first substrate 111a may be connected to the driving voltage pad DP located on the first side of the display panel 110 along the back surface of the first substrate 111a, and the flowing voltage line FVL may be connected to the flowing voltage pad 214 located on the second side of the display panel 110 along the back surface of the first substrate 111a.

[0198] A first high-potential flowing voltage pad 214a-1 and a first low-potential flowing voltage pad 214a-2 capable of applying a flowing voltage to the flow of the liquid metal may be provided at positions adjacent to the liquid metal inlet 212, and a second high-potential flowing voltage pad 214b-1 and a second low-potential flowing voltage pad 214b-2 may be provided at the ends of the path pattern 213. In addition, a third high-potential flowing voltage pad 214c-1 and a third low-potential flowing voltage pad 214c-2 may be provided at the main bending points where the direction of the path pattern 213 changes.

[0199] In this case, the flow of the liquid metal can be more effectively controlled by controlling the voltages of the third high-potential flowing voltage pad 214c-1 and the third low-potential flowing voltage pad 214c-2 according to the position of the flowing liquid metal.

[0200] Here, the high-potential flowing voltage pads 214a-1, 214b-1, and 214c-1 are pads to which a high voltage HV having a (+) level is applied, and the low-potential flowing voltage pads 214a-2, 214a-2, and 214c-2 are pads to which a low voltage LV having a (-) level is applied.

[0201] The printed circuit board may be a source printed circuit board on which a data driving circuit is installed, or may be a control printed circuit board on which a timing controller is installed.

[0202] The printed circuit board may be disposed adjacent to the short side of the display panel 110. In this case, the first side provided with the driving voltage pad DP may be the long side of the display panel 110, and the second side provided with the flowing voltage pad 214 may be the short side of the display panel 110.

[0203] Therefore, the flowing voltage pad 214 is provided on the short side of the display panel 110 adjacent to the printed circuit board on which the driving circuit is installed, and the path pattern 213 provided in the heat sink 119 may be referred to as a structure extending along the long side of the display panel 110.

[0204] As described above, forming the flowing voltage pad 214 in the area adjacent to the printed circuit board can move the heat generated by the printed circuit board along the path pattern 213 of the heat sink 119 to a low-temperature area (e.g., away from the printed circuit board), thereby achieving heat dissipation performance.

[0205] In the display device 100 of the present disclosure, the path pattern 213 included in the heat sink 119 may be configured such that different path patterns are provided in the region where high-temperature heat is generated and the region where low-temperature heat is generated.

[0206] Figure 16 It is a tiled display device schematically showing a plurality of display panels arranged adjacent to each other.

[0207] Refer to Figure 16 , a tiled display device is provided by splicing a plurality of display panels 110a, 110b, 110c, and 110d in regions A, B, C, and D respectively so that the display panels 110a, 110b, 110c, and 110d are in contact with each other.

[0208] In this case, the display panels 110a, 110b, 110c, and 110d are provided with gate drive circuits 120a, 120b, 120c, and 120d and data drive circuits 130a, 130b, 130c, and 130d in their peripheral portions, and each of them is controlled by a timing controller (not shown).

[0209] For example, the first display panel 110a provided in region A may include a first lower substrate 10a and a first upper substrate 20a. On the first lower substrate 10a, an array of thin film transistors is provided in the display region, and a first gate drive circuit 120a and a first data drive circuit 130a are provided in the non-display region. A light emitting element, such as a micro LED, is provided on the first upper substrate 20a. In addition, a heat sink having a path pattern through which liquid metal flows may be provided between the first lower substrate 10a and the first upper substrate 20a.

[0210] The second display panel 110b provided in region B may include a second lower substrate 10b and a second upper substrate 20b. On the second lower substrate 10b, an array of thin film transistors is provided in the display region, and a second gate drive circuit 120b and a second data drive circuit 130b are provided in the non-display region. A light emitting element, such as a micro LED, is provided on the second upper substrate 20b. In addition, a heat sink having a path pattern through which liquid metal flows may be provided between the second lower substrate 10b and the second upper substrate 20b.

[0211] The third display panel 110c disposed in region C may include a third lower substrate 10c and a third upper substrate 20c. On the third lower substrate 10c, an array of thin film transistors is disposed in the display region, and a third gate driving circuit 120c and a third data driving circuit 130c are disposed in the non-display region. On the third upper substrate 20c, light-emitting elements, such as micro LEDs, are disposed. In addition, a heat sink having a path pattern through which liquid metal flows may be disposed between the third lower substrate 10c and the third upper substrate 20c.

[0212] The fourth display panel 110d disposed in region D may include a fourth lower substrate 10d and a fourth upper substrate 20d. On the fourth lower substrate 10d, an array of thin film transistors is disposed in the display region, and a fourth gate driving circuit 120d and a fourth data driving circuit 130d are disposed in the non-display region. On the fourth upper substrate 20d, light-emitting elements, such as micro LEDs, are disposed. In addition, a heat sink having a path pattern through which liquid metal flows may be disposed between the fourth lower substrate 10d and the fourth upper substrate 20d.

[0213] In the tiled display device, the display panels 110a, 110b, 110c, and 110d are disposed adjacent to each other in a portion where the gate driving circuits 120a, 120b, 120c, and 120d or the data driving circuits 130a, 130b, 130c, and 130d are not provided.

[0214] In such a tiled display device, the region adjacent to the driving circuit may be a hot region TA1 where high-temperature heat is generated, and the region where the display panels are adjacent to each other may be a cold region TA2 where low-temperature heat is generated.

[0215] The display device of the present disclosure can achieve effective heat dissipation performance by changing the density of the path patterns through which liquid metal flows in the high-temperature region and the low-temperature region of the display panel, respectively.

[0216] Figure 17 As an example, a case where the display panel of the display device according to the embodiment has different path patterns in the high-temperature region and the low-temperature region is shown.

[0217] Refer to Figure 17 , the display device 100 according to the embodiment may include a heat sink 119 located between the first substrate 111a and the second substrate 111b to cool the heat dissipated from the micro LED mLED.

[0218] The heat sink 119 may include a fin body 211, a liquid metal inlet 212 provided at a side portion of the fin body 211 for injecting liquid metal, a path pattern 213 for allowing the liquid metal to flow along the surface of the fin body 211, a first flow voltage pad 214a for applying a voltage to the liquid metal inlet 212, and a second flow voltage pad 214b connected to an end of the path pattern 213.

[0219] Each liquid metal inlet 212 is a portion for injecting liquid metal to absorb heat generated by the display panel 110. In this case, the liquid metal inlets 212 may be respectively provided in the high-temperature region TA1 and the low-temperature region TA2.

[0220] The liquid metal that absorbs heat generated in the high-temperature region TA1 may flow along a longer path pattern 213a to increase heat dissipation. To this end, the path pattern 213a provided in the high-temperature region TA1 may be densely arranged such that the path pattern 213b provided in the low-temperature region TA2 has a shorter path than the path pattern 213a provided in the high-temperature region TA1. For example, the path pattern 213a provided in the high-temperature region TA1 may be arranged to extend through the space between the micro LEDs mLEDs in each row, while the path pattern 213b provided in the low-temperature region TA2 may be arranged to extend through the space between two rows of micro LEDs mLEDs.

[0221] In addition, a first flow voltage pad 214a capable of applying a flow voltage to control the flow of the liquid metal is provided at a position adjacent to the liquid metal inlet 212, and a second flow voltage pad 214b is provided on a second side of the path patterns 213a and 213b.

[0222] For example, when a (+) voltage is applied to the first flow voltage pad 214a and a (-) voltage is applied to the second flow voltage pad 214b, the liquid metal flows from the liquid metal inlet 212 to the second flow voltage pad 214b.

[0223] Therefore, the liquid metal that has absorbed heat generated near the liquid metal inlet 212 can dissipate heat by flowing along the path patterns 213a and 213b to the second flow voltage pad 214b.

[0224] When the liquid metal flows to the second flow voltage pad 214b and its temperature decreases, the liquid metal can be made to flow back to the liquid metal inlet 212 by changing the potential of the second flow voltage pad 214b to a (+) voltage and changing the potential of the first flow voltage pad 214a to a (-) voltage.

[0225] A brief review of the above embodiments is given below.

[0226] A display device according to the present disclosure may include: a display panel including a plurality of light-emitting elements; and a driving circuit configured to drive the display panel. The display panel may include: a first substrate on a first surface of which the driving circuit is provided; a second substrate on a top of which the light-emitting elements are provided; and a heat sink provided between the first substrate and the second substrate and including a path pattern through which liquid metal flows.

[0227] Each of the light-emitting elements may be a micro light-emitting diode.

[0228] The path pattern may extend in a zigzag pattern along a space between the light-emitting elements.

[0229] The heat sink may include a liquid metal inlet through which the liquid metal is injected.

[0230] The liquid metal inlet may be located in a high-temperature region of the display panel.

[0231] The liquid metal may include gallium, a gallium-indium eutectic alloy, or a gallium-indium-tin alloy.

[0232] The second substrate may include: a first flow voltage pad configured to apply a first flow voltage to the liquid metal inlet; and a second flow voltage pad configured to apply a second flow voltage to one end of the path pattern.

[0233] In the display device, during a first period, a high voltage having a positive (+) level may be applied to the first flow voltage pad, a low voltage having a negative (-) level may be applied to the second flow voltage pad, and during a second period, a low voltage having a (-) level may be applied to the first flow voltage pad, and a high voltage having a (+) level may be applied to the second flow voltage pad.

[0234] The second substrate may include: a first high-potential flow voltage pad configured to apply a high voltage having a (+) level to the liquid metal inlet; a first low-potential flow voltage pad configured to apply a low voltage having a (-) level to the liquid metal inlet; a second high-potential flow voltage pad configured to apply a high voltage having a (+) level to an end of the path pattern; and a second low-potential flow voltage pad configured to apply a low voltage having a (-) level to an end of the path pattern.

[0235] During a first period, a high voltage having a (+) level may be applied to the first high-potential flow voltage pad, a low voltage having a (-) level may be applied to the second low-potential flow voltage pad, and during a second period, a low voltage having a (-) level may be applied to the first low-potential flow voltage pad, and a high voltage having a (+) level may be applied to the second high-potential flow voltage pad.

[0236] The second substrate may further include a third flow voltage pad, which is disposed at a bending point where the direction of the path pattern changes.

[0237] The display panel may further include a sealant disposed at a peripheral portion of the heat sink to bond the first substrate and the second substrate.

[0238] The path pattern may include: a first path pattern disposed in a high-temperature region of the display panel; and a second path pattern disposed in a low-temperature region of the display panel and separated from the first path pattern.

[0239] The high-temperature region may be adjacent to the driving circuit.

[0240] The first path pattern may have a higher density than the second path pattern.

[0241] The display device may further include an adhesive layer disposed between the heat sink and the second substrate.

[0242] In addition, the display panel according to the present disclosure may include: a first substrate having a driving circuit disposed on a first surface thereof; a second substrate having a light-emitting element disposed on a top thereof; and a heat sink disposed between the first substrate and the second substrate and including a path pattern through which liquid metal flows.

[0243] In addition, the display device according to the present disclosure may include: a plurality of display panels disposed adjacent to each other; and a plurality of driving circuits configured to drive the display panels respectively. Each of the display panels may include: a first substrate having a driving circuit disposed on a first surface thereof; a second substrate having a light-emitting element disposed on a top thereof; and a heat sink disposed between the first substrate and the second substrate and including a path pattern through which liquid metal flows.

[0244] The path pattern may include: a first path pattern disposed in a high-temperature region; and a second path pattern disposed in a low-temperature region and separated from the first path pattern.

[0245] The high-temperature region may be adjacent to the driving circuit, and the low-temperature region may be adjacent to the display panel.

[0246] The first path pattern may have a higher density than the second path pattern.

[0247] The above description is presented to enable those skilled in the art to make and use the inventive concept, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present invention, and the general principles defined herein can be applied to other embodiments and applications. The above description and drawings provide examples of the inventive concept for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the inventive concept of the present invention.

Claims

1. A display device, comprising: A display panel including a plurality of light emitting elements; a driving circuit configured to drive the display panel, Wherein, the display panel comprises: a first substrate, wherein the driving circuit is disposed on a first surface of the first substrate; a second substrate having the plurality of light emitting elements on a top thereof; and The heat sink is located between the first substrate and the second substrate, and includes a path pattern for liquid metal to flow through.

2. The display device according to claim 1, wherein: Each of the plurality of light emitting elements includes a micro light emitting diode.

3. The display device according to claim 1, wherein: The path pattern extends in a zigzag pattern along the spaces between the light emitting elements.

4. The display device according to claim 1, wherein: The heat sink comprises a liquid metal inlet, and the liquid metal is injected through the liquid metal inlet.

5. The display device according to claim 4, wherein: The liquid metal inlet is arranged in a region adjacent to the driving circuit.

6. The display device according to claim 1, wherein: The liquid metal includes gallium, gallium-indium eutectic alloy or gallium-indium-tin alloy.

7. The display device according to claim 4, wherein: The second substrate comprises: A first flowing voltage pad configured to apply a first flowing voltage to the liquid metal inlet; and The second flow voltage pad is configured to apply a second flow voltage to one end of the path pattern.

8. The display device according to claim 7, wherein: During a first period, a high voltage having a positive level is applied to the first flowing voltage pad, a low voltage having a negative level is applied to the second flowing voltage pad, and During a second period, a low voltage having a negative level is applied to the first flowing voltage pad, and a high voltage having a positive level is applied to the second flowing voltage pad.

9. The display device according to claim 8, wherein: The first time period is determined by a first speed at which the liquid metal flows along a length from the liquid metal inlet to an end of the path pattern, and The second time period is determined by a second speed at which the liquid metal flows along the length of the path pattern.

10. The display device according to claim 4, wherein: The second substrate comprises: a first high potential flow voltage pad configured to apply a high voltage having a positive level to the liquid metal inlet; a first low potential flow voltage pad configured to apply a low voltage having a negative level to the liquid metal inlet; a second high potential flowing voltage pad configured to apply a high voltage having a positive level to an end portion of the path pattern; and The second low potential flowing voltage pad is configured to apply a low voltage having a negative level to the end portion of the path pattern.

11. The display device according to claim 10, wherein: During a first period, a high voltage having a positive level is applied to the first high potential flowing voltage pad, a low voltage having a negative level is applied to the second low potential flowing voltage pad, and During the second period, a low voltage having a negative level is applied to the first low potential flowing voltage pad, and a high voltage having a positive level is applied to the second high potential flowing voltage pad.

12. The display device according to claim 11, wherein: During the first period, the first low potential flowing voltage pad and the second high potential flowing voltage pad are maintained at a ground level, and Wherein, during the second period, the first high potential flowing voltage pad and the second low potential flowing voltage pad are maintained at the ground level.

13. The display device according to claim 11, wherein: The first time period is determined by a first speed at which the liquid metal flows along a length from the liquid metal inlet to an end of the path pattern, and The second time period is determined by a second speed at which the liquid metal flows along the length of the path pattern.

14. The display device according to claim 7, wherein: The second substrate further includes a third voltage flow pad disposed at a bending point where a direction of the path pattern changes.

15. The display device according to claim 1, wherein: The display panel further includes a sealant located at a peripheral portion of the heat sink, the sealant bonding the first substrate to the second substrate.

16. The display device according to claim 1, wherein: The path pattern includes: A first path pattern is located in a high temperature area of ​​the display panel; and The second path pattern is located in a low temperature region of the display panel and is separated from the first path pattern. The temperature of the low temperature region is lower than that of the high temperature region.

17. The display device according to claim 16, wherein: The high temperature region is adjacent to the driving circuit.

18. The display device according to claim 16, wherein: The first path pattern has a higher density than a density of the second path pattern. 19 . The display device according to claim 1 , further comprising an adhesive layer disposed between the heat sink and the second substrate.

20. A display panel, comprising: a first substrate, wherein a driving circuit is provided on a first surface of the first substrate; A second substrate, wherein a light emitting element is provided on the top of the second substrate; as well as The heat sink is located between the first substrate and the second substrate, and includes a path pattern for liquid metal to flow through.

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