Display device

Abstract

A display device according to an embodiment of the present disclosure may include: a display area including a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit disposed in the second display area; a first pixel electrode of a first light emitting element disposed in the first display area; and a connection line electrically connecting the first pixel electrode and the first pixel circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device. Background Art

[0002] With the advancement of technology, a display device may provide a photographing function and various sensing functions in addition to an image display function. Accordingly, the display device needs to be equipped with electronic devices such as a camera and a detection sensor (which may also be referred to as a light receiving device or a sensor).

[0003] Since the electronic device may receive light from the front of the display device, the electronic device needs to be installed in a position where light can be received. Accordingly, the camera (e.g., a camera lens) and the detection sensor need to be installed to be exposed to the front of the display device. As a result, a bezel of the display device may become larger, or the camera or the detection sensor may be installed in a notch or a physical hole formed in a display area of the display panel.

[0004] Accordingly, since the display device is equipped with electronic devices such as a camera and a detection sensor that receive light from the front and perform specific functions, a bezel on the front of the display device may become larger, or restrictions may occur in the front design of the display device.

[0005] In addition, in the case where the display device includes an electronic device, undesired image quality degradation may occur depending on a structure for accommodating the electronic device.

[0006] The description provided in the background art section should not be assumed to be prior art merely because it is mentioned in the background art section or is associated with the related art section. The background art section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0007] Accordingly, the present disclosure relates to a display device that substantially eliminates one or more problems caused by limitations and disadvantages of the related art.

[0008] One aspect of the present disclosure is to provide a display device having a light transmissive structure that allows an electronic device located under a display panel to normally receive light without exposing the light receiving electronic device to the front.

[0009] Another aspect of the present disclosure is to provide a display device having a line structure that can increase a transmittance of a region that needs to transmit light within a display area.

[0010] Still another aspect of the present disclosure is to provide a display device having a unique connection structure that increases a transmittance of a region that needs to transmit light within a display area between a pixel circuit and a light emitting element.

[0011] Additional features and aspects of the present disclosure will be set forth in part in the following description, and in part will become apparent from the description, or can be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept can be realized and obtained by the structures pointed out in the written description or structures derivable therefrom, as well as the appended claims and the drawings.

[0012] A display device according to an embodiment of the present disclosure may include: a display area including a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit disposed in the second display area; a first pixel electrode of a first light-emitting element disposed in the first display area; and a connection line electrically connecting the first pixel electrode and the first pixel circuit.

[0013] The connection line may include a first connection line and a second connection line. The first connection line is disposed in the first display area and the second display area and includes a first transparent metal. The second connection line is disposed in the second display area, is disposed to contact an upper surface of the first connection line, and includes a first metal.

[0014] A display device according to an embodiment of the present disclosure may include: a substrate including a display area for displaying an image and a non-display area for not displaying an image. The display area includes a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit disposed on the substrate and in the second display area; a first pixel electrode of a first light-emitting element disposed on the substrate and in the first display area; and a connection line electrically connecting the first pixel electrode and the first pixel circuit.

[0015] In the display device according to an embodiment of the present disclosure, the connection line may be a single metal layer in the first display area and may be multiple metal layers in the second display area.

[0016] The connection line may include a first connection line and a second connection line. The first connection line is disposed in the first display area and the second display area and includes a first transparent metal. The second connection line is disposed in the second display area, is disposed to contact an upper surface of the first connection line, and includes a first metal.

[0017] The single metal layer may include a first transparent metal, and the multiple metal layers may include a first transparent metal and a first metal.

[0018] According to an embodiment of the present disclosure, a display device having a light-transmitting structure may be provided. The light-transmitting structure allows an electronic device located below the display panel to normally receive light (e.g., visible light, infrared light, or ultraviolet light, etc.) without exposing the light-receiving electronic device to the front.

[0019] According to an embodiment of the present disclosure, a display device having a line structure can be provided, and the line structure can increase the transmittance of a region that requires transmitted light (hereinafter referred to as an optical region) within a display region.

[0020] According to an embodiment of the present disclosure, a display device having a unique connection structure can be provided, and the unique connection structure increases the transmittance of a region that requires transmitted light within a display region between a pixel circuit and a light-emitting element.

[0021] According to an embodiment of the present disclosure, through process optimization for forming a single metal layer and multiple metal layers at one time, a display device with reduced manufacturing cost can be provided.

[0022] The effects of the present disclosure are not limited to the effects described above, and other effects not described will be clearly understood by those skilled in the art from the following description.

[0023] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings may be included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain various principles of the present disclosure.

[0025] Figure 1A 、 Figure 1B and Figure 1C illustrate examples of a display device according to an embodiment of the present disclosure.

[0026] Figure 2 illustrate examples of a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0027] Figure 3 schematically illustrate examples of a display panel according to an embodiment of the present disclosure.

[0028] Figure 4 schematically illustrate examples of a first type of first optical region and a normal region surrounding the first optical region in a display panel according to an embodiment of the present disclosure.

[0029] Figure 5 and Figure 6 illustrate examples of light-emitting elements and pixel circuits for driving the light-emitting elements provided in each of a first display region to a third display region in a display panel according to an embodiment of the present disclosure.

[0030] Figure 7 and Figure 8is an example illustrating a planar view and a cross-sectional view of a connection structure between a first light-emitting element in a first display region and a first pixel circuit in a second display region in a display panel according to an embodiment of the present disclosure.

[0031] Figure 9 and Figure 10 is an example illustrating a planar view and a cross-sectional view of a connection structure between two first light-emitting elements in a first display region and a first pixel circuit in a second display region in a display panel according to an embodiment of the present disclosure.

[0032] Figure 11 Illustrates an example of a process for forming a connection line in a display panel according to an embodiment of the present disclosure.

[0033] Figure 12 Illustrates an example of a layer stack of a display panel according to an embodiment of the present disclosure.

[0034] Figures 13 to 16 Illustrates an example of a vertical structure in a first display region to a third display region in a display panel according to an embodiment of the present disclosure.

[0035] Figure 17 Illustrates an example of a vertical structure in a first display region and a second display region of a display panel according to an embodiment of the present disclosure.

[0036] Figure 18 Illustrates an example of an arrangement structure of horizontal lines and vertical lines in a display panel according to an embodiment of the present disclosure.

[0037] Figure 19 Illustrates an example of a structure of a connection line in a first display region of a display panel according to an embodiment of the present disclosure.

[0038] Figure 20 Schematically illustrates an example of a second optical region of a first type and a normal region surrounding the second optical region in a display panel according to an embodiment of the present disclosure.

[0039] Figure 21 Schematically illustrates an example of a second optical region of a second type and a normal region surrounding the second optical region in a display panel according to an embodiment of the present disclosure.

[0040] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The relative dimensions and depictions of these elements may be exaggerated for clarity, illustration, and convenience. Detailed Description

[0041] In the following, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When assigning reference numerals to the components of each figure, the same or similar reference numerals may be assigned to the same components even if they are shown in different figures. When it is determined that the subject matter of the present disclosure is unclear, the detailed description of known technologies or functions may be skipped. As used herein, when a component "comprises", "has" another component or "consists of" another component, other components may be added to the component, unless the component "only" comprises, has another component or only "consists of" another component. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a specific order. Similar reference numerals refer to similar elements throughout. The names of the corresponding elements used in the following description may be chosen only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0042] Advantages and features of the present disclosure and methods for realizing them will become clear by referring to the following example embodiments described in detail in conjunction with the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that the present disclosure may be sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of the present disclosure. In addition, the present disclosure will be defined only by the scope of the appended claims. Any implementation described herein as an "example" need not be construed as being preferred or advantageous over other implementations.

[0043] The shapes, sizes, proportions, angles, quantities, etc. illustrated in the drawings depicting various example embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the figures.

[0044] When interpreting an element, the element is interpreted as including an error range or tolerance range, even though there is no explicit description of such error or tolerance range.

[0045] Designations such as "first", "second", "A", "B", "(a)" and "(b)" may be used to describe the components of the present disclosure. These designations are provided only to distinguish one component from another, and the nature, order or quantity of the components is not limited by the designations.

[0046] When describing the positional relationship between components, when two or more components are described as "connected", "coupled" or "linked", these two or more components can be directly "connected", "coupled" or "linked", or another component can intervene. Here, the other components can be included in one or more of the two or more components that are "connected", "coupled" or "linked" to each other.

[0047] When describing the positional relationship, for example, when using terms such as "on", "above", "below", "over", "under", "beneath", "lower", "adjacent", "close" or "next to", "beside", "alongside" to describe the positional relationship between two parts, one or more other parts can be arranged between the two parts, unless more restrictive terms such as "immediately", "directly" or "closely" are used. For example, when a structure is described as being "on", "above", "under", "over", "beneath", "below", "adjacent" to another structure, "close" to another structure or "next to" another structure, "beside" another structure, "alongside" another structure, this description should be interpreted to include the case where the structures are in contact with each other and the case where a third structure is arranged or inserted therebetween. In addition, terms such as "left", "right", "top", "bottom", "downward", "upward", "upper", "lower" etc. refer to any reference system.

[0048] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first element, the second element and the third element" covers the combination of all three listed elements, the combination of any two of the three elements, and each individual element (the first element, the second element or the third element).

[0049] When using terms such as "after", "next", "following after" and "before" to describe the time flow relationship related to components, operation methods and manufacturing methods, non - continuous relationships can be included unless terms such as "only", "immediately" or "directly" are used.

[0050] When a component is specified by a value or its corresponding information (e.g., level), the value or the corresponding information can be interpreted to include tolerances that may arise due to various factors (e.g., process factors, internal or external influences, or noise).

[0051] The features in various embodiments of the present disclosure can be partially or wholly coupled or combined with each other, and can interoperate and drive with each other in various ways as can be fully understood by those skilled in the art technically. The embodiments of the present disclosure can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0052] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as will be understood by one of ordinary skill in the art.

[0053] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In addition, all components of each display device according to all embodiments of the present disclosure are operatively connected and configured.

[0054] Figure 1A , Figure 1B and Figure 1C A display device 100 according to an embodiment of the present disclosure is illustrated.

[0055] Reference Figure 1A , Figure 1B and Figure 1C , a display device 100 according to an embodiment of the present disclosure may include a display panel 110 for displaying an image and one or more electronic devices 11 and 12 .

[0056] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0057] A plurality of sub-pixels and a plurality of signal lines for driving the plurality of sub-pixels may be disposed in the display area DA.

[0058] The non-display area NDA may be an area outside the display area DA. Various signal lines may be disposed in the non-display area NDA, and various driving circuits may be connected thereto. The non-display area NDA may be bent so as not to be visible from the front, or may be shielded by a housing (not shown). The non-display area NDA may also be referred to as a frame or a frame area.

[0059] Reference Figure 1A , Figure 1B and Figure 1C In the display device 100 according to an embodiment of the present disclosure, one or more electronic devices 11 and 12 may be provided and installed separately from the display panel 110, and may be electronic components located at a lower portion of the display panel 110 (eg, opposite to the viewing surface).

[0060] Light can enter the front surface (e.g., the viewing side) of the display panel 110, pass through the display panel 110, and can be delivered to one or more electronic devices 11 and 12 located below the display panel 110 (e.g., opposite the viewing surface). For example, the light passing through the display panel 110 can include visible light, infrared light, or ultraviolet light.

[0061] One or more electronic devices 11 and 12 can be devices that receive the light passing through the display panel 110 and perform a predetermined operation using the received light. For example, one or more electronic devices 11 and 12 can include one or more of imaging devices such as cameras (e.g., image sensors), and detection sensors such as proximity sensors and illuminance sensors. Here, for example, the detection sensor can be an infrared sensor.

[0062] Referring to Figure 1A 、 Figure 1B and Figure 1C In the display panel 110 according to an embodiment of the present disclosure, the display area DA can include a normal area NA and one or more optical areas OA1 and OA2. One or more optical areas OA1 and OA2 can be areas that overlap with one or more electronic devices 11 and 12.

[0063] According to Figure 1A an example of, the display area DA can include a normal area NA and a first optical area OA1. At least a part of the first optical area OA1 can overlap with the first electronic device 11.

[0064] According to Figure 1B an example of, the display area DA can include a normal area NA, a first optical area OA1, and a second optical area OA2. In Figure 1B the example of, the normal area NA can be present between the first optical area OA1 and the second optical area OA2. Here, at least a part of the first optical area OA1 can overlap with the first electronic device 11, and at least a part of the second optical area OA2 can overlap with the second electronic device 12.

[0065] According to Figure 1C an example of, the display area DA can include a normal area NA, a first optical area OA1, and a second optical area OA2. In Figure 1C the example of, there is no normal area NA between the first optical area OA1 and the second optical area OA2. For example, the first optical area OA1 and the second optical area OA2 can be in contact with each other. Here, at least a part of the first optical area OA1 can overlap with the first electronic device 11, and at least a part of the second optical area OA2 can overlap with the second electronic device 12.

[0066] One or more optical regions OA1 and OA2 need to include both an image display structure and a light transmissive structure. For example, since one or more optical regions OA1 and OA2 are part of the display region DA, a light emitting region for sub-pixels for image display needs to be provided in one or more optical regions OA1 and OA2. Additionally, a light transmissive structure needs to be formed in one or more optical regions OA1 and OA2 to transmit light to one or more electronic devices 11 and 12.

[0067] One or more electronic devices 11 and 12 are devices that need to receive light, and can be located behind (e.g., below or opposite the viewing surface) the display panel 110, and receive light passing through the display panel 110. One or more electronic devices 11 and 12 may not be exposed to the front (e.g., the viewing side) of the display panel 110. Thus, when a user views the front of the display device 100, the electronic devices 11 and 12 may be invisible to the user.

[0068] For example, the first electronic device 11 can be a camera, and the second electronic device 12 can be a detection sensor such as a proximity sensor or an illuminance sensor. For example, the detection sensor can be an infrared sensor for detecting infrared rays. Alternatively, the first electronic device 11 can be a detection sensor, and the second electronic device 12 can be a camera.

[0069] Hereinafter, for ease of explanation, a case where the first electronic device 11 is a camera and the second electronic device 12 is an infrared-based detection sensor is illustrated. Here, the camera can be a camera lens or an image sensor.

[0070] In the case where the first electronic device 11 is a camera, the camera can be located behind (e.g., below) the display panel 110, but can be a front camera for photographing the front direction of the display panel 110. Thus, a user can view the viewing surface of the display panel 110, and take a photo or a selfie using a camera that is invisible on the viewing surface.

[0071] The normal region NA and one or more optical regions OA1 and OA2 can be regions capable of displaying an image. However, the normal region NA can be a region where a light transmissive structure does not need to be formed, and one or more optical regions OA1 and OA2 can be regions where a light transmissive structure needs to be formed.

[0072] Therefore, one or more optical regions OA1 and OA2 need to have a transmittance higher than a specific level, and the normal region NA can have no light transmissivity or can have a low transmittance lower than a specific level.

[0073] For example, one or more optical regions OA1 and OA2 and the normal region NA may have different values for the following items: resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure, etc.

[0074] For example, the number of sub-pixels per unit area in one or more optical regions OA1 and OA2 may be less than the number of sub-pixels per unit area in the normal region NA. For example, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the normal region NA. Here, the number of sub-pixels per unit area may have the same meaning as resolution, pixel density, or pixel integration. For example, the unit of the number of sub-pixels per unit area may be PPI (pixels per inch), and PPI represents the number of pixels within 1 inch.

[0075] For example, the number of sub-pixels per unit area in the first optical region OA1 may be less than the number of sub-pixels per unit area in the normal region NA. The number of sub-pixels per unit area in the second optical region OA2 may be greater than or equal to the number of sub-pixels per unit area in the first optical region OA1 and may be less than the number of sub-pixels per unit area in the normal region NA.

[0076] In addition, as a method of increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, the differential pixel density design method described above may be applied. According to the differential pixel density design method, the display panel 110 may be designed such that the number of sub-pixels per unit area of at least one of the first optical region OA1 and the second optical region OA2 is less than the number of sub-pixels per unit area of the normal region NA.

[0077] However, in some cases, a differential pixel size design method may be applied as another method of increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2. According to the differential pixel size design method, the display panel 110 may be designed such that the number of sub-pixels per unit area of at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of sub-pixels per unit area of the normal region NA, but such that the size of each sub-pixel SP (e.g., the size of the light-emitting region) provided in at least one of the first optical region OA1 and the second optical region OA2 is smaller than the size of each sub-pixel SP (e.g., the size of the light-emitting region) placed in the normal region NA.

[0078] In the following, for the sake of explanation, an example will be given of applying the differential pixel density design method among two methods (for example, the differential pixel density design method and the differential pixel size design method) to increase the transmittance of at least one of the first optical region OA1 and the second optical region OA2. Therefore, in the following, a small number of sub-pixels per unit area may correspond to a small sub-pixel size, and a large number of sub-pixels per unit area may correspond to a large sub-pixel size.

[0079] The first optical region OA1 may have various shapes such as circular, oval, square, hexagonal, or octagonal. The second optical region OA2 may have various shapes such as circular, oval, square, hexagonal, or octagonal. The first optical region OA1 and the second optical region OA2 may have the same shape or different shapes.

[0080] Referring to Figure 1C , in the case where the first optical region OA1 and the second optical region OA2 are in contact, the entire optical region including the first optical region OA1 and the second optical region OA2 may also have various shapes such as circular, oval, square, hexagonal, or octagonal.

[0081] In the display device 100 according to an embodiment of the present disclosure, if the first electronic device 11 hidden at the bottom of the display panel 110 without being exposed to the outside is a camera, the display device 100 according to an embodiment of the present disclosure may be referred to as a display device applying UDC (Under Display Camera) technology.

[0082] Therefore, in the display device 100 according to an embodiment of the present disclosure, it may not be necessary to form a notch or a camera hole for exposing the camera in the display panel 110, so that the area of the display area DA is not reduced. Therefore, the size of the bezel area can be reduced, design limitations can be eliminated, and the design freedom can be increased.

[0083] In the display device 100 according to an embodiment of the present disclosure, although one or more electronic devices 11 and 12 are hidden behind the display panel 110, one or more electronic devices 11 and 12 need to be able to receive light normally and perform their designated functions normally.

[0084] In addition, in the display device 100 according to an embodiment of the present disclosure, although one or more electronic devices 11 and 12 are hidden behind the display panel 110 and positioned to overlap with the display area DA, normal image display functions need to be available in one or more optical regions OA1 and OA2 in the display area DA that overlap with one or more electronic devices 11 and 12.

[0085] Since the first optical region OA1 mentioned above is designed as a transmissive region, the image display characteristics in the first optical region OA1 can be different from those in the normal region NA.

[0086] In addition, when designing the first optical region OA1 to improve the image display characteristics, there may be a possibility that the transmittance of the first optical region OA1 can be reduced.

[0087] Therefore, an embodiment of the present disclosure can provide the first optical region OA1 having the following structure, which can prevent or reduce the image quality deviation between the first optical region OA1 and the normal region NA, and improve the transmittance of the first optical region OA1.

[0088] In addition, an embodiment of the present disclosure can also provide the second optical region OA2 having the following structure for the second optical region OA2 other than the first optical region OA1, which can improve the image quality in the second optical region OA2 and improve the transmittance in the second optical region OA2.

[0089] In addition, in the display device 100 according to an embodiment of the present disclosure, the first optical region OA1 and the second optical region OA2 are similar in that they are transmissive regions, but their usage examples can be different. Therefore, in the display device 100 according to an embodiment of the present disclosure, the structures of the first optical region OA1 and the second optical region OA2 can be designed differently.

[0090] Figure 2 The system configuration diagram of the display device 100 according to an embodiment of the present disclosure is illustrated.

[0091] Referring to Figure 2 , the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image.

[0092] The display driving circuit may be a circuit for driving the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230, and a display controller 240.

[0093] The display panel 110 may include a display region DA for displaying an image and a non-display region NDA that does not display an image. The non-display region NDA may be a region outside the display region DA, and may also be referred to as a border region. All or part of the non-display region NDA may be a region visible from the front of the display device 100, or may be bent and invisible from the front of the display device 100.

[0094] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Additionally, the display panel 110 may also include various types of signal lines to drive the plurality of sub-pixels SP.

[0095] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element. For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting element is implemented as an organic light-emitting diode (OLED). For another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is implemented as an inorganic-based light-emitting diode. For another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is implemented with quantum dots, and the quantum dots are self-emitting semiconductor crystals.

[0096] The structure of each sub-pixel among the plurality of sub-pixels SP may vary depending on the type of the display device 100. For example, if the display device 100 is a self-emitting display device in which the sub-pixel SP emits light by itself, each sub-pixel SP may include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0097] For example, various types of signal lines may include a plurality of data lines DL that transmit data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL that transmit gate signals (also referred to as scan signals).

[0098] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction.

[0099] The data driving circuit 220 is a circuit for driving the plurality of data lines DL and may output data signals to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving the plurality of gate lines GL and may output gate signals to the plurality of gate lines GL.

[0100] The display controller 240 may be a device for controlling the data driving circuit 220 and the gate driving circuit 230 and may control the driving timing of the plurality of data lines DL and the driving timing of the plurality of gate lines GL.

[0101] The display controller 240 may provide a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220, and may provide a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230.

[0102] The display controller 240 may receive input image data from the host system 250 and provide the image data to the data driving circuit 220 based on the input image data.

[0103] The data driving circuit 220 may receive image data in digital form from the display controller 240 and convert the received image data into an analog data signal to output to a plurality of data lines DL.

[0104] The gate driving circuit 230 may receive a first gate voltage corresponding to a conductive level voltage and a second gate voltage corresponding to a cut-off level voltage, as well as various gate driving control signals GCS, and may generate a gate signal and provide the generated gate signal to a plurality of gate lines GL.

[0105] For example, the data driving circuit 220 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to bonding pads of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0106] The gate driving circuit 230 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to bonding pads of the display panel 110 using a chip on glass (COG) or chip on board (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method. Alternatively, the gate driving circuit 230 may be an in-panel gate (GIP) type and may be formed in a non-display area NDA of the display panel 110. The gate driving circuit 230 may be disposed on or connected to a substrate. For example, if the gate driving circuit 230 is of the GIP type, the gate driving circuit 230 may be disposed in the non-display area NDA of the substrate. If the gate driving circuit 230 is of the chip on glass (COG) type, chip on film (COF) type, etc., the gate driving circuit 230 may be connected to the substrate.

[0107] In addition, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in a display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be arranged not to overlap with the sub-pixels SP, or may be arranged to partially overlap or completely overlap with the sub-pixels SP.

[0108] The data driving circuit 220 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 220 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more sides among the four sides of the display panel 110.

[0109] The gate driving circuit 230 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 230 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to two or more sides among the four sides of the display panel 110.

[0110] The display controller 240 may be implemented as a component separate from the data driving circuit 220, or may be integrated with the data driving circuit 220 and implemented as an integrated circuit.

[0111] The display controller 240 may be a timing controller used in conventional display technologies, or may be a control device capable of further performing other control functions including the timing controller, or may be a control device different from the timing controller, or may be a control device other than the timing controller, or may be a circuit within the control device. The display controller 240 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0112] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit.

[0113] The display controller 240 may transmit and receive signals with the data driving circuit 220 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI).

[0114] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit for detecting the occurrence of a touch by a touch object such as a finger or a pen, or for detecting a touch position by sensing the touch sensor.

[0115] The touch sensing circuit may include: a touch driving circuit 260 for driving and sensing a touch sensor to generate and output touch sensing data, and a touch controller 270 for detecting the occurrence of a touch or detecting a touch position using the touch sensing data.

[0116] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit 260.

[0117] The touch sensor may exist in the form of a touch panel outside the display panel 110, or may exist inside the display panel 110. If the touch sensor exists in the form of a touch panel outside the display panel 110, the touch sensor may be referred to as an external type. If the touch sensor is of the external type, the touch panel and the display panel 110 may be separately manufactured and combined together during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0118] If the touch sensor exists inside the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0119] The touch driving circuit 260 may provide a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0120] The touch sensing circuit may perform touch sensing using a self - capacitance sensing method or a mutual - capacitance sensing method.

[0121] If the touch sensing circuit performs touch sensing using the self - capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (such as a finger, a pen, etc.). According to the self - capacitance sensing method, each of the plurality of touch electrodes may be used as a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 may drive a part or all of the plurality of touch electrodes and sense a part or all of the plurality of touch electrodes.

[0122] If the touch sensing circuit performs touch sensing using the mutual - capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes. According to the mutual - capacitance sensing method, the plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit may drive the driving touch electrodes and sense the sensing touch electrodes.

[0123] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or as one device. In addition, the touch driving circuit 260 and the data driving circuit 220 may be implemented as separate devices or as one device.

[0124] The display device 100 may further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0125] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smart phone or a tablet, or a monitor or a television of various sizes, but is not limited thereto, and may be various types and sizes of displays capable of displaying information or images.

[0126] As described above, in the display panel 110, the display area DA may include a normal area NA and one or more optical areas OA1 and OA2. The normal area NA and the one or more optical areas OA1 and OA2 may be areas capable of displaying images. However, the normal area NA is an area where a light-transmitting structure does not need to be formed, and the one or more optical areas OA1 and OA2 are areas where a light-transmitting structure needs to be formed.

[0127] As described above, the display area DA in the display panel 110 may include one or more optical areas OA1 and OA2 and the normal area NA. However, for ease of explanation, an example will be given in which the display area DA includes the first optical area OA1 and the second optical area OA2 (as Figure 1B and Figure 1C ).

[0128] Figure 3 A display panel according to an embodiment of the present disclosure is schematically illustrated.

[0129] Referring to Figure 3 , a plurality of sub-pixels SP may be provided in the display area DA of the display panel 110. The plurality of sub-pixels SP may be provided in the normal area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0130] Referring to Figure 3 , each of the plurality of sub-pixels SP may include a light-emitting element ED and a sub-pixel circuit SPC configured to drive the light-emitting element ED.

[0131] Referring to Figure 3 , the sub-pixel circuit SPC may include a driving transistor DT for driving the light-emitting element ED, a scanning transistor ST for transmitting a data voltage Vdata to the driving transistor DT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0132] The driving transistor DT may include a first node N1, a second node N2, and a third node N3.

[0133] The first node N1 may be a node electrically connected to the light-emitting element ED. The second node N2 may be a node connected to the scanning transistor ST. The third node N3 may be a node connected to the driving voltage line VDDL.

[0134] The first node N1 may be electrically connected to the pixel electrode PE of the light-emitting element ED. The data voltage VDATA may be applied to the second node N2. The driving voltage VDD may be applied to the third node N3.

[0135] The first node N1 may be a source node or a drain node, the second node N2 may be a gate node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, in the driving transistor DT, the case where the first node N1 is a source node, the second node N2 is a gate node, and the third node N3 is a drain node will be exemplified.

[0136] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0137] The pixel electrode PE may be an electrode provided in each sub-pixel SP. For example, the pixel electrode PE may be directly or indirectly (via another transistor) electrically connected to the first node N1 of the driving transistor DT of each sub-pixel SP.

[0138] The common electrode CE may be an electrode commonly provided in a plurality of sub-pixels SP. For example, the common electrode CE may be electrically connected to the base voltage line VSSL. The base voltage VSS, which is a type of common driving voltage, may be applied to the common electrode CE through the base voltage line VSSL.

[0139] For example, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. Alternatively, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode. Hereinafter, for ease of explanation, it is assumed that the pixel electrode PE is an anode electrode and the common electrode CE is a cathode electrode.

[0140] The intermediate layer EL may include a light-emitting layer EML and a common intermediate layer EL_COM.

[0141] For example, the light-emitting layer EML may be provided in each of a plurality of sub-pixels SP. As another example, the light-emitting layer EML may be commonly provided in a plurality of sub-pixels SP.

[0142] The light-emitting layer EML can be disposed in each light-emitting region EA, and the common intermediate layer EL_COM can be commonly disposed above a plurality of light-emitting regions EA and non-light-emitting regions.

[0143] The common intermediate layer EL_COM can include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 can be disposed between the pixel electrode PE and the light-emitting layer EML, and can include at least one layer (e.g., an organic layer).

[0144] For example, the first common intermediate layer COM1 can include a hole injection layer HIL and a hole transport layer HTL. The second common intermediate layer COM2 can include an electron transport layer ETL, an electron injection layer EIL, etc.

[0145] The hole injection layer can inject holes from the pixel electrode PE into the hole transport layer, the hole transport layer can transport holes to the light-emitting layer EML, while the electron injection layer can inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport electrons to the light-emitting layer EML.

[0146] Each light-emitting element ED can include an overlapping portion of the pixel electrode PE, the light-emitting layer EML in the intermediate layer EL, and the common electrode CE. A predetermined light-emitting region EA can be formed by each light-emitting element ED. For example, the light-emitting region EA can be defined as the region where the pixel electrode PE, the light-emitting layer EML in the intermediate layer EL, and the common electrode CE overlap.

[0147] For example, the light-emitting element ED can be an organic light-emitting diode (OLED) based on organic materials, an inorganic light-emitting diode based on inorganic materials, or a quantum dot light-emitting element. In the case where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL in the light-emitting element ED can include an organic layer containing organic materials.

[0148] The scan transistor ST can control its on-off through a scan signal SC, which is a type of gate signal, applied via a scan signal line SCL, which is a type of gate line, and can be electrically connected between the second node N2 of the driving transistor DT and the data line DL.

[0149] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

[0150] The sub-pixel circuit SPC can have a 2T-1C structure, which includes two transistors DT and ST and one capacitor Cst, as Figure 3As shown, but the present disclosure is not limited thereto, and in some cases may also include one or more transistors, or one or more capacitors. For example, 3T1C, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, 8T2C structures, etc. are also possible. And the sub-pixel circuit SPC may include more or fewer transistors and capacitors.

[0151] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that may exist as an internal capacitor between the first node N1 and the second node N2 of the driving transistor DT. Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0152] Circuit elements within each sub-pixel SP (especially, the light-emitting element ED implemented with an organic light-emitting diode (OLED) containing an organic material) may be vulnerable to external moisture or oxygen. Therefore, an encapsulation layer ENCAP may be provided on the display panel 110 to prevent or reduce oxygen from penetrating into the circuit elements (especially the light-emitting element ED). The encapsulation layer ENCAP may be provided to cover the light-emitting element ED.

[0153] Referring to Figure 3 , the display device 100 according to an embodiment of the present disclosure may include, for sensing a user's touch: a touch sensor layer TSL including a plurality of sensor electrodes, a touch driving circuit 260 configured to sense the plurality of sensor electrodes, and a touch controller 270 configured to determine the presence or absence of a touch or touch coordinates using the sensing result (e.g., touch sensing data) of the touch driving circuit 260.

[0154] The touch sensor layer TSL may be embedded in the display panel 110. For example, the touch sensor layer TSL may be provided on the encapsulation layer 200 within the display panel 110.

[0155] The display panel 110 may further include a plurality of touch pads TP electrically connected to the touch driving circuit 260, and a plurality of touch wirings for electrically connecting the plurality of sensor electrodes included in the touch sensor layer TSL to the plurality of touch pads TP connected to the touch driving circuit 260.

[0156] Figure 4 Schematically illustrated are a first optical region OA1 of a first type in a display panel according to an embodiment of the present disclosure and a normal region NA surrounding the first optical region.

[0157] Referring to Figure 4, the display panel 110 according to an embodiment of the present disclosure may include a display area DA for displaying an image and a non-display area NDA for not displaying an image.

[0158] Referring to Figure 4 , the display area DA may include a transmissive first optical area OA1 and a normal area NA surrounding the first optical area OA1.

[0159] The first optical area OA1 may have a first type of structure. That the first optical area OA1 is of the first type may mean that a first optical border area OBA1 is provided outside the first optical area OA1, and light-emitting elements are located in the first optical area OA1, but a pixel circuit SPC is not provided.

[0160] In an embodiment of the present disclosure, the first optical border area OBA1 may be regarded as a part of the normal area NA.

[0161] For example, when the first optical area OA1 is of the first type, the display area DA may include the first optical area OA1, the normal area NA located outside the first optical area OA1, and the first optical border area OBA1 as an area between the first optical area OA1 and the normal area NA.

[0162] Referring to Figure 4 , the first optical area OA1 may be an area overlapping with the first electronic device 11 and is a transmissive area through which light required for the operation of the first electronic device 11 can pass.

[0163] Here, the light passing through the first optical area OA1 may include light of a single band or light of various bands. For example, the light passing through the first optical area OA1 may include one or more types of light, such as visible light, infrared light, or ultraviolet light.

[0164] The first electronic device 11 may receive the light passing through the first optical area OA1 and perform a predetermined operation using the received light. Here, the light received by the first electronic device 11 through the first optical area OA1 may include at least one of visible light, infrared light, or ultraviolet light.

[0165] For example, when the first electronic device 11 is a camera, the light passing through the first optical area OA1 and utilized by the first electronic device 11 may include visible light. For another example, if the first electronic device 11 is an infrared-based sensor, the light passing through the first optical area OA1 and utilized by the first electronic device 11 may include infrared light (also known as infrared rays).

[0166] Referring to Figure 4, the first optical border area OBA1 can be an area located outside the first optical area OA1. The normal area NA can be an area located outside the first optical border area OBA1. The first optical border area OBA1 can be disposed between the first optical area OA1 and the normal area NA.

[0167] For example, the first optical border area OBA1 can be located only on the outer edge of a part of the first optical area OA1, or can be disposed outside the entire edge of the first optical area OA1.

[0168] When the first optical border area OBA1 is disposed outside the entire edge of the first optical area OA1, the first optical border area OBA1 can have an annular shape surrounding the first optical area OA1.

[0169] For example, the first optical area OA1 can have various shapes such as circular, oval, polygonal, or irregular shapes. The first optical border area OBA1 can have various annular shapes (e.g., circular annular shape, elliptical annular shape, polygonal annular shape, or irregular annular shape, etc.) surrounding the first optical area OA1 having various shapes.

[0170] Referring to Figure 4 , the display area DA can include a plurality of light-emitting areas EA. Since the first optical area OA1, the first optical border area OBA1, and the normal area NA are areas included in the display area DA, each of the first optical area OA1, the first optical border area OBA1, and the normal area NA can include a plurality of light-emitting areas EA.

[0171] For example, the plurality of light-emitting areas EA can include a first-color light-emitting area that emits light of a first color, a second-color light-emitting area that emits light of a second color, and a third-color light-emitting area that emits light of a third color.

[0172] At least one of the first-color light-emitting area, the second-color light-emitting area, and the third-color light-emitting area can have an area size different from that of other areas.

[0173] The first color, the second color, and the third color can be different colors and can be various colors. For example, the first color, the second color, and the third color can include red, green, and blue.

[0174] Hereinafter, for the sake of convenience of explanation, the case where the first color is red, the second color is green, and the third color is blue will be described as an example, however, this is not limited thereto.

[0175] If the first color is red, the second color is green, and the third color is blue, the area of the blue light-emitting region EA_B can be the largest among the area of the red light-emitting region EA_R, the area of the green light-emitting region EA_G, and the area of the blue light-emitting region EA_B.

[0176] The light-emitting element ED provided in the red light-emitting region EA_R may include an intermediate layer EL that emits red light. The light-emitting element ED provided in the green light-emitting region EA_G may include an intermediate layer EL that emits green light. The light-emitting element ED provided in the blue light-emitting region EA_B may include an intermediate layer EL that emits blue light.

[0177] Among the intermediate layer EL that emits red light, the intermediate layer EL that emits green light, and the intermediate layer EL that emits blue light, the organic material contained in the intermediate layer EL that emits blue light may be most likely to undergo material deterioration.

[0178] By designing the area of the blue light-emitting region EA_B to be the largest, the current density supplied to the light-emitting element ED provided in the blue light-emitting region EA_B can be minimized. Therefore, the degree of deterioration of the light-emitting element ED provided in the blue light-emitting region EA_B may be similar to the degree of deterioration of the light-emitting element ED provided in the red light-emitting region EA_R and the light-emitting element ED provided in the green light-emitting region EA_G.

[0179] Therefore, the deterioration deviation between the light-emitting element ED provided in the red light-emitting region EA_R, the light-emitting element ED provided in the green light-emitting region EA_G, and the light-emitting element ED provided in the blue light-emitting region EA_B can be eliminated or reduced, thereby improving the image quality. In addition, since the deterioration difference between the light-emitting element ED provided in the red light-emitting region EA_R, the light-emitting element ED provided in the green light-emitting region EA_G, and the light-emitting element ED provided in the blue light-emitting region EA_B can be eliminated or reduced, an effect of reducing the life deviation between the light-emitting element ED provided in the red light-emitting region EA_R, the light-emitting element ED provided in the green light-emitting region EA_G, and the light-emitting element ED provided in the blue light-emitting region EA_B can be provided.

[0180] Refer to Figure 4 , the first optical region OA1 is a transmissive region and needs to have a high transmittance. Therefore, the common electrode CE may include a plurality of common electrode holes CH in the first optical region OA1. For example, in the first optical region OA1, the common electrode CE may include a plurality of common electrode holes CH.

[0181] Refer to Figure 4, the common electrode CE may not include the common electrode hole CH in the normal area NA. For example, in the normal area NA, the common electrode CE may not include the common electrode hole CH.

[0182] In addition, the common electrode CE may not include the common electrode hole CH in the first optical border area OBA1. For example, in the first optical border area OBA1, the common electrode CE may not include the common electrode hole CH.

[0183] In the first optical area OA1, the multiple common electrode holes CH formed in the common electrode CE may also be referred to as multiple first transmission areas TA1 or multiple openings. Here, in Figure 4 , one common electrode hole CH has a circular shape, but the common electrode hole CH may have various shapes such as an oval shape, a polygonal shape, or an irregular shape in addition to the circular shape.

[0184] Referring to Figure 4 , the second optical area OA2 may be set adjacent to the first optical area OA1. The arrangement of the light-emitting area EA in the second optical area OA2 will be described in more detail later.

[0185] In the following description, for the sake of convenience of explanation, the first optical area OA1 may be referred to as the first display area OA1, and the first optical border area OBA1 may be referred to as the second display area OBA1. In addition, the normal area NA may be referred to as the third display area NA, and the second optical area OA2 may be referred to as the fourth display area OA2.

[0186] Figure 5 The first light-emitting element to the third light-emitting element ED1, ED2, and ED3, and the first pixel circuit to the third pixel circuit SPC1, SPC2, and SPC3 for driving the first light-emitting element to the third light-emitting element ED1, ED2, and ED3 are illustrated.

[0187] However, as Figure 3 shown, each of the first pixel circuit to the third pixel circuit SPC1, SPC2, and SPC3 may include a transistor DT and ST and a storage capacitor Cst. However, for the sake of convenience of explanation, each of the pixel circuits SPC1, SPC2, SPC3, and SPC4 is simply represented as driving transistors DT1, DT2, DT3, and DT4.

[0188] Referring to Figure 5, the first display area to the third display areas OA1, OBA1, and NA may have not only positional differences but also structural differences. As a structural difference, pixel circuits SPC1, SPC2, and SPC3 may be provided in the second display area OBA1 and the third display area NA, but no pixel circuit may be provided in the first display area OA1. For example, transistors DT1, DT2, and DT3 may be provided in the second display area OBA1 and the third display area NA, but no transistor may be provided in the first display area OA1.

[0189] The transistors DT and ST and the storage capacitor Cst included in the pixel circuits SPC1, SPC2, and SPC3 may be components that can reduce the transmittance. Therefore, since the pixel circuits SPC1, SPC2, and SPC3 are not provided in the first display area OA1, the transmittance of the first display area OA1 can be further increased.

[0190] The pixel circuits SPC1, SPC2, and SPC3 are provided only in the third display area NA and the second display area OBA1, but light-emitting elements ED1, ED2, and ED3 may be provided in all of the first display area to the third display areas OA1, OBA1, and NA.

[0191] Refer to Figure 5 , the first light-emitting element ED1 may be provided in the first display area OA1, but the first pixel circuit SPC1 for driving the first light-emitting element ED1 may not be provided in the first display area OA1.

[0192] Refer to Figure 5 , the first pixel circuit SPC1 for driving the first light-emitting element ED1 provided in the first display area OA1 may not be provided in the first display area OA1, but may be provided in the second display area OBA1.

[0193] Hereinafter, the first display area to the third display areas OA1, OBA1, and NA will be described in more detail.

[0194] Refer to Figure 5 , the plurality of light-emitting areas EA included in the display panel 110 according to an embodiment of the present disclosure include a first light-emitting area EA1, a second light-emitting area EA2, and a third light-emitting area EA3. Here, the first light-emitting area EA1 may be included in the first display area OA1, the second light-emitting area EA2 may be included in the second display area OBA1, and the third light-emitting area EA3 may be included in the third display area NA. Hereinafter, it is assumed that the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 are light-emitting areas of the same color.

[0195] Refer to Figure 5, the display panel 110 according to an embodiment of the present disclosure may include a first light-emitting element ED1 disposed in the first display area OA1 and having a first light-emitting area EA1, a second light-emitting element ED2 disposed in the second display area OBA1 and having a second light-emitting area EA2, and a third light-emitting element ED3 disposed in the third display area NA and having a third light-emitting area EA3.

[0196] Refer to Figure 5 , the display panel 110 according to an embodiment of the present disclosure may include a first pixel circuit SPC1 configured to drive the first light-emitting element ED1, a second pixel circuit SPC2 configured to drive the second light-emitting element ED2, and a third pixel circuit SPC3 configured to drive the third light-emitting element ED3.

[0197] Refer to Figure 5 , the first pixel circuit SPC1 may include a first driving transistor DT1. The second pixel circuit SPC2 may include a second driving transistor DT2. The third pixel circuit SPC3 may include a third driving transistor DT3.

[0198] Refer to Figure 5 , the first pixel circuit SPC1 may be connected to a first pixel electrode PE1 of the first light-emitting element ED1, the second pixel circuit SPC2 may be connected to a second pixel electrode PE2 of the second light-emitting element ED2, and the third pixel circuit SPC3 may be connected to a third pixel electrode PE3 of the third light-emitting element ED3.

[0199] Refer to Figure 5 , in the display panel 110 according to an embodiment of the present disclosure, the second pixel circuit SPC2 may be disposed in the second display area OBA1 where the second light-emitting element ED2 is disposed, and the third pixel circuit SPC3 may be disposed in the third display area NA where the third light-emitting element ED3 is disposed.

[0200] Refer to Figure 5 , in the display panel 110 according to an embodiment of the present disclosure, the first pixel circuit SPC1 may not be disposed in the first display area OA1 where the first light-emitting element ED1 is disposed, but may be disposed in the second display area OBA1 located outside the first display area OA1. Therefore, the transmittance of the first display area OA1 can be increased.

[0201] Refer to Figure 5 , the display panel 110 according to an embodiment of the present disclosure may further include a connection line CL, and the connection line CL electrically connects the first pixel circuit SPC1 disposed in the second display area OBA1 and the first light-emitting element ED1 disposed in the first display area OA1.

[0202] The connection line CL can electrically extend the pixel electrode PE of the first light-emitting element ED1 to the first node N1 of the first driving transistor DT1 in the first pixel circuit SPC1.

[0203] As described above, in the display panel 110 according to an embodiment of the present disclosure, the first pixel circuit SPC1 for driving the first light-emitting element ED1 provided in the first display area OA1 may be provided in the second display area OBA1 instead of in the first display area OA1.

[0204] In an embodiment of the present disclosure, the structure of connecting the pixel electrode of the first light-emitting element ED1 in the first display area OA1 and the first pixel circuit SPC1 in the second display area OBA1 through the connection line CL may be referred to as a pixel electrode extension structure. In the case where the pixel electrode is an anode electrode, the pixel electrode extension structure may also be referred to as an anode extension structure.

[0205] Therefore, the first type of the first display area OA1 may also be referred to as a "pixel electrode extension type" or an "anode extension type".

[0206] If the display panel 110 according to an embodiment of the present disclosure has a pixel electrode extension structure, all or a part of the connection line CL may be provided in the first display area OA1, and the connection line CL may include a transparent line. Therefore, even if the connection line CL is provided in the first display area OA1, a reduction in the transmittance of the first display area OA1 can be prevented or reduced.

[0207] As described above, the first sub-pixel circuit SPC1 provided in the second display area OBA1 can drive one first light-emitting element ED1 provided in the first display area OA1. Such a driving method and a circuit connection method may be referred to as a one-to-one (1:1) driving method and a one-to-one (1:1) circuit connection method. Here, in this specification, the 1:1 driving method and the 1:1 circuit connection method are used with the same meaning.

[0208] Therefore, the number of sub-pixel circuits provided in the second display area OBA1 can be significantly increased. The structure of the second display area OBA1 can become complicated, and the aperture ratio (or light-emitting area) of the second display area OBA1 can be reduced.

[0209] In order to increase the aperture ratio (or light-emitting area) of the second display area OBA1, although having a pixel electrode extension structure (e.g., an anode extension structure), the display device 100 according to an embodiment of the present disclosure may have a 1:N (N is a natural number of 2 or more) driving method and a 1:N circuit connection method. Here, in this specification, the 1:N driving method may be used with the same meaning as the 1:N circuit connection method.

[0210] According to the 1:N driving method, the first sub-pixel circuit SPC1 provided in the second display area OBA1 can simultaneously operate two or more light-emitting elements ED1 provided in the first display area OA1.

[0211] Figure 6 The first light-emitting element to the third light-emitting element ED1_1 to ED1_N, ED2, and ED3, and the first sub-pixel circuit to the third sub-pixel circuit SPC1, SPC2, and SPC3 for driving the first light-emitting element to the third light-emitting element ED1_1 to ED1_N, ED2, and ED3 are illustrated.

[0212] Refer to Figure 6 , N first light-emitting elements ED1_1 to ED1_N (N is a natural number of 2 or more) arranged in the first display area OA1 can be driven by one first sub-pixel circuit SPC1 arranged in the second display area OBA1.

[0213] For this purpose, one first sub-pixel circuit SPC1 can be connected to N first pixel electrodes PE1_1 to PE1_N of N first light-emitting elements ED1_1 to ED1_N. For example, the N first pixel electrodes PE1_1 to PE1_N of N first light-emitting elements ED1_1 to ED1_N can be electrically connected to each other.

[0214] Therefore, although the display panel 110 has a pixel electrode extension structure (for example, an anode extension structure), the number of sub-pixel circuits SPC provided in the second display area OBA1 can be reduced, thereby increasing the opening and light-emitting area of the second display area OBA1.

[0215] Refer to Figure 6 , the N first light-emitting elements ED1_1 to ED1_N driven together by one first sub-pixel circuit SPC1 can be light-emitting elements that emit light of the same color and light-emitting elements adjacent in the row or column direction. For example, the N first light-emitting elements ED1_1 to ED1_N can be driven together by one first sub-pixel circuit SPC1 to form N first light-emitting areas EA1_1 to EA1_N that emit light of the same color.

[0216] Refer to Figure 6 , the connection line CL can connect one first sub-pixel circuit SPC1 provided in the second display area OBA1 to N first light-emitting elements ED1_1 to ED1_N provided in the first display area OA1.

[0217] Figure 7 and Figure 8It is a plan view and a cross-sectional view of a connection structure between a first light-emitting element ED1 in a first display area OA1 and a first pixel circuit SPC1 in a second display area OBA1 in a display panel 110 according to an embodiment of the present disclosure. However, Figure 7 and Figure 8 illustrates a 1:1 driving method in which one first pixel circuit SPC1 drives one first light-emitting element ED1.

[0218] Referring to Figure 7 , the display area DA of the display panel 110 according to an embodiment of the present disclosure may include a first display area OA1 capable of transmitting light, a second display area OBA1 located outside the first display area OA1, and a third display area NA located outside the second display area OBA1.

[0219] Referring to Figure 7 , the first light-emitting element ED1 may be disposed in the first display area OA1, and the first pixel circuit SPC1 for driving the first light-emitting element ED1 may not be disposed in the first display area OA1 but in the second display area OBA1.

[0220] Referring to Figure 7 , the first pixel circuit SPC1 may include a first driving transistor DT1 to which a driving voltage VDD is applied. The first light-emitting element ED1 may include a first pixel electrode PE1 disposed in the first display area OA1. A ground voltage VSS may be applied to the common electrode CE of the first light-emitting element ED1.

[0221] Referring to Figure 7 , the display panel 110 according to an embodiment of the present disclosure may include a connection line CL that electrically connects the first pixel electrode PE1 and the first pixel circuit SPC1 so that the first pixel circuit SPC1 disposed in the second display area OBA1 drives the first light-emitting element ED1 disposed in the first display area OA1.

[0222] Referring to Figure 7 and Figure 8 , the connection line CL may include a first connection line CL_L1 and a second connection line CL_L2.

[0223] The first connection line CL_L1 may be disposed in the first display area OA1 and the second display area OBA1 and may include a first transparent metal TM_GM.

[0224] The second connection line CL_L2 may be disposed in the second display area OBA1, may be disposed to contact the upper surface of the first connection line CL_L1, and may include a first metal GM.

[0225] Referring toFigure 8 The first metal GM included in the second connection line CL_L2 may be a metal included in a transistor / capacitor pattern provided in the second display area OBA1 and the normal area NA.

[0226] The first transparent metal TM_GM included in the first connection line CL_L1 may be a transparent metal included in a transistor / capacitor pattern provided in the second display area OBA1 and the normal area NA.

[0227] The transistor / capacitor pattern may include at least one of a source electrode, a drain electrode, and a gate electrode included in a transistor, or may include at least one of electrodes included in a capacitor.

[0228] The first transparent metal TM_GM may be a transparent metal directly provided under the first metal GM. For example, the upper surface of the first transparent metal TM_GM and the lower surface of the first metal GM may be in contact.

[0229] As described above, the first electronic device 11 may overlap with the first display area OA1 and may receive light passing through the first display area OA1. The light received by the first electronic device 11 may include visible light, infrared light, or ultraviolet light.

[0230] Referring to Figure 7 and Figure 8 According to an embodiment of the present disclosure, the display device 100 may include a substrate SUB, a first light-emitting element ED1, and a first pixel circuit SPC1 for driving the first light-emitting element ED1.

[0231] The substrate SUB may include a display area DA for displaying an image and a non-display area NDA for not displaying an image.

[0232] The display area DA may include a first display area OA1 capable of transmitting light, a second display area OBA1 located outside the first display area OA1, and a third display area NA located outside the second display area OBA1.

[0233] The first pixel circuit SPC1 may be provided on the substrate SUB and may be provided in the second display area OBA1.

[0234] The first light-emitting element ED1 and the first pixel electrode PE1 included therein may be provided on the substrate SUB and may be provided in the first display area OA1.

[0235] Referring to Figure 7 and Figure 8 According to an embodiment of the present disclosure, the display device 100 may include a connection line CL electrically connecting the first pixel electrode PE1 and the first pixel circuit SPC1.

[0236] Reference Figure 7 and Figure 8 In Figure 8 , the connection line CL may be a single metal layer in the first display area OA1 and may be multiple metal layers in the second display area OBA1.

[0237] Reference Figure 7 and Figure 8 The single metal layer may include a first transparent metal TM_GM, and the multiple metal layers may include the first transparent metal TM_GM and a first metal GM.

[0238] For example, the connection line CL may include: a first connection line CL_L1 disposed in the first display area OA1 and the second display area OBA1 and including the first transparent metal TM_GM; and a second connection line CL_L2 disposed in the second display area OBA1, in contact with the upper surface of the first connection line CL_L1, and including the first metal GM.

[0239] This corresponds to a 1:1 driving method in which one of the first pixel circuits SPC1 drives one first light-emitting element ED1.

[0240] Figure 9 and Figure 10 Figure 10 and Figure 9 are a plan view and a cross-sectional view of a connection structure between two first light-emitting elements ED1 in the first display area OA1 and one first pixel circuit SPC1 in the second display area OBA1 in the display panel 110 according to an embodiment of the present disclosure. However, Figure 9 and Figure 10 Figure 10 illustrates a 1:N (N = 2) driving method in which one of the first pixel circuits SPC1 drives two first light-emitting elements ED1.

[0241] In the following description, descriptions of the same content as that of Figure 8 and Figure 9 will be omitted or may be briefly provided, and the description will mainly focus on the content different from that of Figure 8 and Figure 9

[0242] Reference Figure 9 and Figure 10 According to an embodiment of the present disclosure, the display device 100 may further include another first pixel electrode PE1a of another first light-emitting element ED1a disposed in the first display area OA1, and an extended connection line ECL for connecting the first pixel electrode PE1 to the another first pixel electrode PE1a.

[0243] Reference Figure 9 and Figure 10, the extended connection line ECL can be disposed in the first display area OA1. The extended connection line ECL can include a transparent metal and can include a second transparent metal TM_SDM different from the first transparent metal TM_GM.

[0244] Refer to Figure 10 , the second transparent metal TM_SDM included in the extended connection line ECL can be the transparent metal included in the transistor / capacitor pattern disposed in the second display area OBA1 and the normal area NA.

[0245] The transistor / capacitor pattern can include at least one of a source electrode, a drain electrode, and a gate electrode included in the transistor, or can include at least one of the electrodes included in the capacitor.

[0246] Figure 11 Illustrated is a process for forming a connection line CL in a display panel 110 according to an embodiment of the present disclosure.

[0247] Refer to Figure 11 , in a first step (S10), a first transparent metal TM_GM and a first metal GM can be deposited in regions A, B, and C. The first metal GM can be deposited on the first transparent metal TM_GM.

[0248] Region A can be a region where the first metal GM and the first transparent metal TM_GM are retained, region B can be a region where the first transparent metal TM_GM is retained, and region C can be a region where the first metal GM and the first transparent metal TM_GM are removed.

[0249] Region A can correspond to the second display area OBA1, and region B can correspond to the first display area OA1.

[0250] Refer to Figure 11 , in the first step (S10), a photoresist PR can be placed in region A, and a halftone photoresist H / T PR can be placed in region B.

[0251] Refer to Figure 11 , in a second step (S20), the halftone photoresist H / T PR in region B can be ashed, and a first etching process can be performed. During the first etching process, the first metal GM and the first transparent metal TM_GM in region C can be etched.

[0252] Refer to Figure 11 , in a third step (S30), the photoresist PR in region A can be stripped, and a second etching process can be performed. During the second etching process, the first metal GM in region B can be etched.

[0253] After the third step (S30), the first transparent metal TM_GM and the first metal GM may remain in the region A corresponding to the second display region OBA1, and only the first transparent metal TM_GM may remain in the region B corresponding to the first display region OA1. Accordingly, a connection line CL may be formed, and the connection line CL includes a first connection line CL_L1 disposed in the first display region OA1 and the second display region OBA1 and including the first transparent metal TM_GM, and a second connection line CL_L2 disposed in the second display region OBA1 and contacting the upper surface of the first connection line CL_L1 and including the first metal GM.

[0254] Figure 12 Illustrated is a layer stack of a display panel 110 according to an embodiment of the present disclosure.

[0255] Reference will be made to Figure 12 Describe the layer stack of the display panel 110 according to an embodiment of the present disclosure. The layer stack of the display panel 110 may include insulating layers (BUF1, GI1, ILD1, BUF2, GI2, ILD2, PLN1, PLN2, BK, PAS1, PCL, and PAS2) having various functions, metal layers (BSM, GM1, GM2, GM3, SDM1, SDM2, and PM) having various functions, and transparent metal layers (TM_GM1, TM_GM2, TM_GM3, TM_SDM1, and TM_SDM2) having various functions. It should be noted that Figure 12 Or (as will be described below) Figures 13 to 16 The illustrated layer stack is provided by way of example only, and the present disclosure is not limited thereto. For example, one or more of the insulating layer, the metal layer, or the transparent metal layer may be omitted or replaced by other layers or elements.

[0256] In the specification, a metal layer (BSM, GM1, GM2, GM3, SDM1, SDM2, and PM) provided with an opaque metal may also be referred to as a metal (BSM, GM1, GM2, GM3, SDM1, SDM2, and PM). A transparent metal layer (TM_GM1, TM_GM2, TM_GM3, TM_SDM1, and TM_SDM2) provided with a transparent metal may also be referred to as a transparent metal (TM_GM1, TM_GM2, TM_GM3, TM_SDM1, and TM_SDM2). Additionally, the transparent metal layer or transparent metal described herein may also be referred to as a transparent conductive material / electrode / wire / pattern, which may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto. Similarly, the metal or opaque metal described herein may also be referred to as an opaque or non-transparent conductive material / electrode / wire / pattern, but the present disclosure is not limited thereto.

[0257] Referring to Figure 12 , the display panel 110 may include a substrate SUB, and the substrate SUB may include a first substrate SUB1, a substrate intermediate layer INTL, and a second substrate SUB2. Each of the first substrate SUB1 and the second substrate SUB2 may be a polyimide substrate, and the substrate intermediate layer INTL may be an inorganic layer and may block moisture penetration.

[0258] Referring to Figure 12 , a lower shielding metal BSM may be provided on the substrate SUB.

[0259] A first buffer layer BUF1 may be provided on the lower shielding metal BSM. The first buffer layer BUF1 may include a multi-buffer layer MBUF and an active buffer layer ABUF. A first gate insulating layer GI1 may be provided on the first buffer layer BUF1.

[0260] Referring to Figure 12 , a first transparent gate metal TM_GM1 and a first gate metal GM1 may be provided on the first gate insulating layer GI1.

[0261] The first transparent gate metal TM_GM1 may be provided on the first gate insulating layer GI1, and the first gate metal GM1 may be provided on the first transparent gate metal TM_GM1 and simultaneously contact the upper surface of the first transparent gate metal TM_GM1.

[0262] A first interlayer insulating layer ILD1 may be provided on the first gate metal GM1.

[0263] Reference Figure 12 The second transparent gate metal TM_GM2 and the second gate metal GM2 may be disposed on the first interlayer insulating layer ILD1.

[0264] The second transparent gate metal TM_GM2 may be disposed on the first interlayer insulating layer ILD1, and the second gate metal GM2 may be disposed on the second transparent gate metal TM_GM2 and simultaneously contact the upper surface of the second transparent gate metal TM_GM2.

[0265] The second buffer layer BUF2 may be disposed on the second gate metal GM2. The second gate insulating layer GI2 may be disposed on the second buffer layer BUF2.

[0266] Reference Figure 12 The third transparent gate metal TM_GM3 and the third gate metal GM3 may be disposed on the second gate insulating layer GI2.

[0267] The third transparent gate metal TM_GM3 may be disposed on the second gate insulating layer GI2, and the third gate metal GM3 may be disposed on the third transparent gate metal TM_GM3 and simultaneously contact the upper surface of the third transparent gate metal TM_GM3.

[0268] The second interlayer insulating layer ILD2 may be disposed on the third gate metal GM3.

[0269] Reference Figure 12 The first transparent source-drain metal TM_SDM1 and the first source-drain metal SDM1 may be disposed on the second interlayer insulating layer ILD2.

[0270] The first transparent source-drain metal TM_SDM1 may be disposed on the second interlayer insulating layer ILD2, and the first source-drain metal SDM1 may be disposed on the first transparent source-drain metal TM_SDM1 and simultaneously contact the upper surface of the first transparent source-drain metal TM_SDM1.

[0271] The first planarization layer PLN1 may be disposed to simultaneously cover the first transparent source-drain metal TM_SDM1 and the first source-drain metal SDM1.

[0272] Reference Figure 12 The second transparent source-drain metal TM_SDM2 and the second source-drain metal SDM2 may be disposed on the first planarization layer PLN1.

[0273] The second transparent source-drain metal TM_SDM2 may be disposed on the first planarization layer PLN1, and the second source-drain metal SDM2 may be disposed on the second transparent source-drain metal TM_SDM2 and simultaneously contact the upper surface of the second transparent source-drain metal TM_SDM2.

[0274] The second planarization layer PLN2 may be disposed to simultaneously cover the second transparent source-drain metal TM_SDM2 and the second source-drain metal SDM2.

[0275] Referring Figure 12 , the pixel electrode metal PM may be disposed on the second planarization layer PLN2.

[0276] The bank BK may be disposed on the pixel electrode metal PM.

[0277] The encapsulation layer ENCAP may be disposed on the bank BK.

[0278] The encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2. For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 may include an inorganic layer, and the second encapsulation layer PCL may include an organic layer.

[0279] Referring Figure 12 , the gate metal GM may include a first gate metal GM1, a second gate metal GM2, and a third gate metal GM3. The transparent gate metal TM_GM may include a first transparent gate metal TM_GM1, a second transparent gate metal TM_GM2, and a third transparent gate metal TM_GM3.

[0280] Referring Figure 12 , the source-drain metal SDM may include a first source-drain metal SDM1 and a second source-drain metal SDM2. The transparent source-drain metal TM_SDM may include a first transparent source-drain metal TM_SDM1 and a second transparent source-drain metal TM_SDM2.

[0281] Figures 13 to 16 Illustrated is the vertical structure in the first display region to the third display regions OA1, OBA1, and NA in the display panel 110 according to an embodiment of the present disclosure.

[0282] Figure 13 and Figure 14 Illustrated are respectively the vertical structures in the third display region NA and the second display region OBA1 of the display panel 110 according to an embodiment of the present disclosure, and Figure 15 and 16 Illustrated is the vertical structure in the first display region OA1 of the display panel 110 according to an embodiment of the present disclosure.

[0283] When referring to Figures 13 to 16 to describe the vertical structure, Figures 13 to 16 the layer stack structure in Figure 12 is the same as or similar to the layer stack structure in Figures 13 to 16 Therefore, when referring to Figure 12 to describe the vertical structure,

[0284] Referring to Figure 13 , the normal area NA may include a third light-emitting element ED3, transistors TR1 and TR2 for driving the third light-emitting element ED3, and a storage capacitor Cst.

[0285] Referring to Figure 13 , the third light-emitting element ED3 may include a third pixel electrode PE3, an intermediate layer EL, and a common electrode CE, and may form a third light-emitting area EA3.

[0286] Referring to Figure 13 , the transistors TR1 and TR2 for driving the third light-emitting element ED3 may include a first transistor TR1 and a second transistor TR2 having different active layers.

[0287] Referring to Figure 13 , the first active layer ACT1 of the first transistor TR1 may be disposed between a first buffer layer BUF1 and a first gate insulating layer GI1, and the second active layer ACT2 of the second transistor TR2 may be disposed between a second buffer layer BUF2 and a second gate insulating layer GI2.

[0288] Referring to Figure 13 , the first transistor TR1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0289] Each of the first gate electrode G1, the first source electrode S1, and the first drain electrode D1 may have a double-electrode structure including a transparent metal and a metal.

[0290] The first gate electrode G1 may be disposed between the first gate insulating layer GI1 and the first interlayer insulating layer ILD1. The first gate electrode G1 may include: a first lower gate electrode G1d including a first transparent gate metal TM_GM1 and a first upper gate electrode G1u including a first gate metal GM1.

[0291] The first source electrode S1 may be disposed between the second interlayer insulating layer ILD2 and the first planarization layer PLN1. The first source electrode S1 may include: a first lower source electrode S1d including a first transparent source-drain metal TM_SDM1 and a first upper source electrode S1u including a first source-drain metal SDM1.

[0292] The first drain electrode D1 can be disposed between the second interlayer insulating layer ILD2 and the first planarization layer PLN1. The first drain electrode D1 can include a first lower drain electrode D1d and a first upper drain electrode D1u. The first lower drain electrode D1d includes a first transparent source-drain metal TM_SDM1, and the first upper drain electrode D1u includes a first source-drain metal SDM1.

[0293] Referring to Figure 13 , the second transistor TR2 can include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0294] Each of the second gate electrode G2, the second source electrode S2, and the second drain electrode D2 can have a double electrode structure including a transparent metal and a metal.

[0295] The second gate electrode G2 can be disposed between the second gate insulating layer GI2 and the second interlayer insulating layer ILD2. The second gate electrode G2 can include: a second lower gate electrode G2d including a third transparent gate metal TM_GM3 and a second upper gate electrode G2u including a third gate metal GM3.

[0296] The second source electrode S2 can be disposed between the second interlayer insulating layer ILD2 and the first planarization layer PLN1. The second source electrode S2 can include: a second lower source electrode S2d including a first transparent source-drain metal TM_SDM1 and a second upper source electrode S2u including a first source-drain metal SDM1.

[0297] The second drain electrode D2 can be disposed between the second interlayer insulating layer ILD2 and the first planarization layer PLN1. The second drain electrode D2 can include: a second lower drain electrode D2d including a first transparent source-drain metal TM_SDM1 and a second upper drain electrode D2u including a first source-drain metal SDM1.

[0298] Referring to Figure 13 , the storage capacitor Cst can include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0299] The first capacitor electrode CAPE1 can be disposed between the first gate insulating layer GI1 and the first interlayer insulating layer ILD1. The first capacitor electrode CAPE1 can include: a first lower capacitor electrode E1d including a first transparent gate metal TM_GM1 and a first upper capacitor electrode E1u including a first gate metal GM1.

[0300] The second capacitor electrode CAPE2 can be disposed between the first interlayer insulating layer ILD1 and the second buffer layer BUF2. The second capacitor electrode CAPE2 can include: a second lower capacitor electrode E2d including a second transparent gate metal TM_GM2 and a second upper capacitor electrode GEu including a second gate metal GM2.

[0301] The second capacitor electrode CAPE2 can be electrically connected to the second source electrode S2. The upper surface of the second upper capacitor electrode GEu can contact the lower surface of the second lower source electrode S2d.

[0302] Referring to Figure 13 , the bottom shield metal BSM can be disposed under the first active layer ACT1 while overlapping at least a part (e.g., the channel formation region) of the first active layer ACT1.

[0303] The bottom shield metal BSM can be disposed between the substrate SUB and the first buffer layer BUF1. The bottom shield metal BSM can include a single metal layer or multiple metal layers.

[0304] Referring to Figure 13 , the bottom metal layer BML can be disposed under the second active layer ACT2 while overlapping at least a part (e.g., the channel formation region) of the second active layer ACT2.

[0305] The bottom metal layer BML can be disposed between the first interlayer insulating layer ILD1 and the second buffer layer BUF2. The bottom metal layer BML can include: a lower bottom metal layer BMLd including a second transparent gate metal TM_GM2 and an upper bottom metal layer BMLu including a second gate metal GM2.

[0306] Referring to Figure 13 , the source electrode S2 of the second transistor TR2 can be electrically connected to the third pixel electrode PE3. For example, the source electrode S2 of the second transistor TR2 can be electrically connected to the third pixel electrode PE3 through a relay electrode RE.

[0307] The relay electrode RE can have a double electrode structure including a transparent metal and a metal.

[0308] The relay electrode RE can be disposed between the first planarization layer PLN1 and the second planarization layer PLN2. The relay electrode RE can include: a second lower relay electrode REd including a second transparent source-drain metal TM_SDM2 and a second upper relay electrode REu including a second source-drain metal SDM2.

[0309] The bank BK can be disposed on the third pixel electrode PE3. The spacer SPCR can be disposed on the bank BK.

[0310] The intermediate layer EL can be disposed on the bank portion BK. The bank portion BK can have an opening, and the intermediate layer EL can contact the upper surface of the third pixel electrode PE3 at the opening of the bank portion BK. The common electrode CE can be disposed on the intermediate layer EL.

[0311] The region where the third pixel electrode PE3, the intermediate layer EL, and the common electrode CE overlap and contact each other can correspond to the opening of the bank portion BK, and the third light-emitting region EA3 can be formed.

[0312] The encapsulation layer ENCAP can be disposed on the common electrode CE. A cover layer can be further disposed between the common electrode CE and the encapsulation layer ENCAP.

[0313] The encapsulation layer ENCAP can include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2. For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can include an inorganic layer, and the second encapsulation layer PCL can include an organic layer.

[0314] Refer to Figure 14 , the vertical structure of the second display region OBA1 can be substantially the same as or similar to Figure 13 the vertical structure of the third display region NA shown.

[0315] Refer to Figure 14 , the second display region OBA1 can include a second light-emitting element ED2 and transistors TR1 and TR2 for driving the second light-emitting element ED2.

[0316] The second light-emitting element ED2 can include a second pixel electrode PE2, an intermediate layer EL, and a common electrode CE, and the second light-emitting region EA2 can be formed.

[0317] The first transistor TR1 and the second transistor TR2 for driving the second light-emitting element ED2 can have the same structure as Figure 13 the first transistor TR1 and the second transistor TR2 for driving the third light-emitting element ED3 in

[0318] In the second display region OBA1, in addition to the transistors TR1 and TR2 for driving the second light-emitting element ED2 disposed in the second display region OBA1, transistors for driving the first light-emitting element ED1 disposed in the first display region OA1 can also be disposed.

[0319] This will be referred to later Figure 17 to describe the structure in which the transistors for driving the first light-emitting element ED1 disposed in the first display region OA1 are disposed in the second display region OBA1.

[0320] Refer to Figure 15 andFigure 16 Among them, the first display area OA1 overlapping with the first electronic device 11 may include a first light-emitting element ED1.

[0321] The first light-emitting element ED1 may include a first pixel electrode PE1, an intermediate layer EL, and a common electrode CE, and may form a first light-emitting area EA1.

[0322] Referring to Figure 15 and Figure 16 Among the first connection line CL_L1 and the second connection line CL_L2 included in the connection line CL, the first connection line CL_L1 provided in the first display area OA1 may include at least one of a first transparent gate metal TM_GM1, a second transparent gate metal TM_GM2, and a third transparent gate metal TM_GM3.

[0323] For example, among the multiple first connection lines CL_L1 included in the multiple connection lines CL, some first connection lines may include the first transparent gate metal TM_GM1, some other first connection lines may include the second transparent gate metal TM_GM2, and another part may include the third transparent gate metal TM_GM3.

[0324] Referring to Figure 15 the extended connection line ECL may include at least one of a first transparent source-drain metal TM_SDM1 and a second transparent source-drain metal TM_SDM2.

[0325] Referring to Figure 16 the extended connection line ECL may include at least one of a first source-drain metal SDM1 and a second transparent source-drain metal TM_SDM2.

[0326] Alternatively, the extended connection line ECL may include at least one of a first transparent source-drain metal TM_SDM1 and a second source-drain metal SDM2. Alternatively, the extended connection line ECL may include at least one of a first source-drain metal SDM1 and a second source-drain metal SDM2.

[0327] Referring to Figure 15 and Figure 16 the first connection line CL_L1 may be electrically connected to the first pixel electrode PE1 through the extended connection line ECL.

[0328] In addition, two first pixel electrodes PE1 provided in the first display area OA may be electrically connected through the extended connection line ECL.

[0329] The vertical structure of each of the first display area to the third display area OA1, OBA1, and NA described above will be described again.

[0330] The storage capacitor Cst can be disposed in the second display area OBA1 and the third display area NA included in the display area DA, and can include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0331] The first metal GM included in the second connection line CL_L2 among the connection lines CL can include the metal GM (e.g., the first gate metal GM1 and the second gate metal GM2) included in at least one of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2.

[0332] The first capacitor electrode CAPE1 can include: a first lower capacitor electrode E1d including a first transparent gate metal TM_GM1, and a first upper capacitor electrode E1u disposed to contact the upper surface of the first lower capacitor electrode E1d and including the first gate metal GM1.

[0333] The second capacitor electrode CAPE2 can include: a second lower capacitor electrode E2d including a second transparent gate metal TM_GM2, and a second upper capacitor electrode E2u disposed to contact the upper surface of the second lower capacitor electrode E2d and including the second gate metal GM2.

[0334] The first transparent metal TM_GM included in the first connection line CL_L1 among the connection lines CL can include the first transparent gate metal TM_GM1 or the second transparent gate metal TM_GM2.

[0335] The first metal GM included in the second connection line CL_L2 among the connection lines CL can include the first gate metal GM1 or the third gate metal GM3.

[0336] A plurality of transistors TR1 and TR2 can be disposed in the second display area OBA1 and the third display area NA included in the display area DA, and can include gate electrodes G1 and G2, source electrodes S1 and S2, and drain electrodes D1 and D2.

[0337] The gate electrodes G1 and G2 of each of the plurality of transistors TR1 and TR2 can include the first gate metal GM1 or the third gate metal GM3.

[0338] The first metal GM included in the second connection line CL_L2 among the connection lines CL can include the first gate metal GM1 or the third gate metal GM3.

[0339] The gate electrodes G1 and G2 of each of the plurality of transistors TR1 and TR2 can include lower gate electrodes G1d and G2d and upper gate electrodes G1u and G2u.

[0340] The lower gate electrodes G1d and G2d may include a first transparent gate metal TM_GM1 or a third transparent gate metal TM_GM3.

[0341] The upper gate electrodes G1u and G2u may be arranged to contact the upper surfaces of the lower gate electrodes G1d and G2d, and may include a first gate metal GM1 or a third gate metal GM3.

[0342] The first transparent metal TM_GM included in the first connection line CL_L1 among the connection lines CL may include a first transparent gate metal TM_GM1 or a third transparent gate metal TM_GM3.

[0343] The first metal GM included in the second connection line CL_L2 among the connection lines CL may include a first gate metal GM1 or a third gate metal GM3.

[0344] The plurality of transistors TR1 and TR2 may include a first transistor TR1, which includes a first active layer ACT1 made of a silicon-based semiconductor material, and a first gate electrode G1 including a first gate metal GM1.

[0345] In this case, the first metal GM included in the second connection line CL_L2 among the connection lines CL may include a first gate metal GM1.

[0346] For example, the first active layer ACT1 may include low-temperature polycrystalline silicon (LTPS), and the first transistor TR1 may be a low-temperature polycrystalline silicon transistor.

[0347] The plurality of transistors TR1 and TR2 may include a second transistor TR2, which includes a second active layer ACT2 made of an oxide-based semiconductor material, and a second gate electrode G2 including a third gate metal GM3.

[0348] In this case, the first metal GM included in the second connection line CL_L2 among the connection lines CL may include a third gate metal GM3.

[0349] For example, the second active layer ACT2 may include an oxide semiconductor material, and the second transistor TR2 may be an oxide semiconductor transistor.

[0350] The first pixel circuit SPC1 and the transistors TR1 and TR2 included therein may be arranged in a second display area OBA1 and a third display area NA included in the display area DA, and may include gate electrodes G1 and G2, source electrodes S1 and S2, and drain electrodes D1 and D2.

[0351] The source electrodes S1 and S2 may include: upper source electrodes S1u and S2u including a first source-drain metal SDM1, and lower source electrodes S1d and S2d disposed below the upper source electrodes S1u and S2u, in contact with the upper source electrodes S1u and S2u, and including a first transparent source-drain metal TM_SDM1.

[0352] The drain electrodes D1 and D2 may include: upper drain electrodes D1u and D2u including a first source-drain metal SDM1, and lower drain electrodes D1d and D2d disposed below the upper drain electrodes D1u and D2u, in contact with the upper drain electrodes D1u and D2u, and including a first transparent source-drain metal TM_SDM1.

[0353] The relay electrode RE may electrically connect the second source electrode S2 or the second drain electrode D2 of the second transistor TR2 to the first pixel electrode PE1.

[0354] The relay electrode RE may include: an upper relay electrode REu including a second source-drain metal SDM2, and a lower relay electrode Red disposed below the upper relay electrode REu, in contact with the upper relay electrode REu, and including a second transparent source-drain metal TM_SDM2.

[0355] The second transparent metal TM_SDM included in the extension connection line ECL may include the first transparent source-drain metal TM_SDM1.

[0356] Alternatively, the second transparent metal TM_SDM included in the extension connection line ECL may include the second transparent source-drain metal TM_SDM2.

[0357] Figure 17 The vertical structures in the first display area OA1 and the second display area OBA1 of the display panel 110 according to an embodiment of the present disclosure are illustrated.

[0358] However, Figure 17 the vertical structure of the second display area OBA1 in Figure 14 is the same as or similar to the vertical structure of the second display area OBA1 in Figure 17 The vertical structure of the first display area OA1 in Figure 15 is the same as or similar to the vertical structure of the first display area OA1 in Figure 14 and Figure 15 Therefore, in the following description, the differences from

[0359] Refer to Figure 17, the second light-emitting element ED2 may be disposed in the second display area OBA1. The second light-emitting element ED2 may include a second pixel electrode PE2, an intermediate layer EL, and a common electrode CE, and may form a second light-emitting area EA2 at an opening of the bank BK.

[0360] A pixel circuit for driving the second light-emitting element ED2 and transistors (e.g., the second transistor TR2) included therein may be disposed in the second display area OBA1.

[0361] Refer to Figure 17 , the first light-emitting element ED1 may be disposed in the first display area OA1. The first light-emitting element ED1 may include a first pixel electrode PE1, an intermediate layer EL, and a common electrode CE, and may form a first light-emitting area EA1 at an opening of the bank BK.

[0362] A pixel circuit for driving the first light-emitting element ED1 and transistors (e.g., the first transistor TR1) included therein may be disposed in the second display area OBA1.

[0363] Refer to Figure 17 , a connection line CL may electrically connect the first transistor TR1 disposed in the second display area OBA1 and the first pixel electrode PE1 disposed in the first display area OA1.

[0364] Refer to Figure 17 , the connection line CL may include a first connection line CL_L1 and a second connection line CL_L2.

[0365] Refer to Figure 17 , the first connection line CL_L1 may include a first transparent metal and may be disposed in both the first display area OA1 and the second display area OBA1. The second connection line CL_L2 may include a first metal and may be disposed in the second display area OBA1.

[0366] Refer to Figure 17 , among the first connection line CL_L1 and the second connection line CL_L2, the first connection line CL_L1 may be disposed in the first display area OA1. In the second display area OBA1, the second connection line CL_L2 may be disposed on the first connection line CL_L1.

[0367] The first metal included in the second connection line CL_L2 may include at least one of a first gate metal to a third gate metal GM1, GM2, and GM3. The first transparent metal included in the first connection line CL_L1 may include at least one of a first transparent gate metal to a third transparent gate metal TM_GM1, TM_GM2, and TM_GM3.

[0368] According toFigure 17 In an example, the first metal included in the second connection line CL_L2 may include a third gate metal GM3. The first transparent metal included in the first connection line CL_L1 may include a third transparent gate metal TM_GM3.

[0369] A part of the second connection line CL_L2 may be connected to the first source electrode S1 or the first drain electrode D1 of the first transistor TR1.

[0370] Another part of the second connection line CL_L2 may be electrically connected to the first pixel electrode PE1 through an extended connection line ECL.

[0371] The extended connection line ECL may be at least one pattern that electrically connects two or more first pixel electrodes PE1 disposed in the first display area OA1 to each other.

[0372] In addition, the extended connection line ECL may be at least one pattern capable of electrically connecting at least one first pixel electrode PE1 disposed in the first display area OA1 and a connection line CL extending from the second display area OBA1 to the first display area OA1.

[0373] For example, referring to Figure 17 , the extended connection line ECL may include: a first line part including a first transparent source-drain metal TM_SDM1 and a second line part including a second transparent source-drain metal TM_SDM2.

[0374] Referring to Figure 17 , a touch sensor layer TSL may be disposed on the encapsulation layer ENCAP.

[0375] Referring to Figure 17 , the touch sensor layer TSL may include a sensor buffer layer S-BUF on the encapsulation layer ENCAP, a plurality of bridge metals BRG on the sensor buffer layer S-BUF, a sensor interlayer insulation layer S-ILD on the plurality of bridge metals BRG, a plurality of touch sensor metals TSM on the sensor interlayer insulation layer S-ILD, and a sensor protection layer S-PAC on the plurality of touch sensor metals TSM.

[0376] The sensor buffer layer S-BUF may be an inorganic layer or an organic layer, and may be omitted or replaced by another layer.

[0377] The sensor interlayer insulation layer S-ILD may be an inorganic layer or an organic layer.

[0378] A touch electrode (e.g., a touch sensor) may be a grid-type electrode. Thus, two or more of the plurality of touch sensor metals TSM may be electrically connected to each other to form a touch electrode (e.g., a touch sensor). Two or more touch sensor metals TSM may be electrically connected to each other through a bridging metal BRG.

[0379] Figure 18 Illustrated is an arrangement structure of a horizontal line HSL and a vertical line VSL in a display panel 110 according to an embodiment of the present disclosure.

[0380] Referring Figure 18 , various signal lines arranged on a display panel 110 according to an embodiment of the present disclosure may include a horizontal line provided in a display area DA, extending in a horizontal direction and including a horizontal line metal, and a vertical line VSL provided in the display area DA, extending in a vertical direction and including a vertical line metal different from the horizontal line metal.

[0381] The horizontal line HSL may include a gate line GL, and the gate line GL includes a scan signal line SCL, a light emission control signal line, and the like.

[0382] The horizontal line HSL may include not only the gate line GL but also a power line for transmitting various direct current (DC) voltages having a constant voltage level. For example, the DC voltage may include at least one of a driving voltage VDD, an anode reset voltage (or a pixel electrode reset voltage), an initialization voltage, and a bias voltage.

[0383] The vertical line VSL may include a data line DL and a connection line CL, and may also include various DC voltage lines.

[0384] The horizontal line HSL and the vertical line VSL may not be provided in the first display area OA1, but may be provided in the second display area OBA1 and the third display area NA. Specifically, the horizontal line HSL and the vertical line VSL may be provided while bypassing the first display area OA1.

[0385] The horizontal line HSL and the vertical line VSL may cross and overlap each other in the third display area NA and the second display area OBA1. Therefore, the horizontal line metal of the horizontal line HSL and the vertical line metal of the vertical line VSL need to be located in different layers.

[0386] For example, in a pixel circuit area within the second display area OBA1 and the third display area NA, the vertical line metal may include a second source-drain metal SDM2, and the horizontal line metal may include all metals other than the second source-drain metal SDM2 (e.g., GM1, GM2, GM3, SDM1, etc.).

[0387] Alternatively, in the case where the vertical line VSL and the horizontal line HSL have a multi-layer line structure including a plurality of metal layers (e.g., a double-line structure including a transparent metal and a metal), within the pixel circuit regions in the second display region OBA1 and the third display region NA, the vertical line metal may include a first vertical line metal (e.g., an opaque vertical line metal) and a second vertical line metal (e.g., a transparent vertical line metal), and the horizontal line metal may include a first horizontal line metal (e.g., an opaque horizontal line metal) and a second horizontal line metal (e.g., a transparent horizontal line metal).

[0388] In this case, the first vertical line metal (e.g., an opaque vertical line metal) may include the second source-drain metal SDM2, and the second vertical line metal (e.g., a transparent vertical line metal) may include the second transparent source-drain metal SDM2. The first horizontal line metal (e.g., an opaque horizontal line metal) may include at least one of all metals (e.g., GM1, GM2, GM3, SDM1, etc.) other than the second source-drain metal SDM2, and the second horizontal line metal (e.g., a transparent horizontal line metal) may include at least one of all transparent metals (e.g., TM_GM1, TM_GM2, TM_GM3, TM_SDM1, etc.) other than the second transparent source-drain metal (TM_SDM2).

[0389] For another example, in the link region (e.g., the region between two adjacent pixel circuit regions) in the second display region OBA1 other than the pixel circuit region, the horizontal line metal may include at least one of the first source-drain metal SDM1 and the second source-drain metal SDM2, and the vertical line metal may include at least one of the first gate metal GM1, the second gate metal GM2, and the third gate metal GM3.

[0390] Alternatively, when the vertical line VSL and the horizontal line HSL have a multi-layer line structure including a plurality of metal layers (e.g., a double-line structure including a transparent metal and a metal), within the link region (e.g., the region between two adjacent pixel circuit regions) in the second display region OBA1 other than the pixel circuit region, the vertical line metal may include a first vertical line metal (e.g., an opaque vertical line metal) and a second vertical line metal (e.g., a transparent vertical line metal), and the horizontal line metal may include a first horizontal line metal (e.g., an opaque horizontal line metal) and a second horizontal line metal (e.g., a transparent horizontal line metal).

[0391] In this case, the first horizontal line metal (e.g., opaque horizontal line metal) may include at least one of a first source-drain metal SDM1 and a second source-drain metal SDM2, and the second horizontal line metal (e.g., transparent horizontal line metal) may include at least one of a first transparent source-drain metal TM_SDM1 and a second transparent source-drain metal TM_SDM2. In addition, the first vertical line metal (e.g., opaque vertical line metal) may include at least one of a first gate metal GM1, a second gate metal GM2, and a third gate metal GM3, and the second vertical line metal (e.g., transparent vertical line metal) may include at least one of a first transparent gate metal TM_GM1, a second transparent gate metal TM_GM2, and a third transparent gate metal TM_GM3.

[0392] The connection line CL may be a type of vertical line VSL and may have a local multi-layer line structure (or local single-layer line structure).

[0393] More specifically, the connection line CL may have a single-layer line structure including a single metal layer in the first display area OA1 and a multi-layer line structure including a plurality of metal layers in the second display area OBA1. For example, the connection line CL may include a first connection line CL_L1 in the first display area OA1 and may include a first connection line CL_L1 and a second connection line CL_L2 in the second display area OBA1.

[0394] For example, the second connection line CL_L2 may include at least one of the vertical line metals. For example, the second connection line CL_L2 may include at least one of a first gate metal GM1, a second gate metal GM2, and a third gate metal GM3. The first connection line CL_L1 may include at least one of the vertical line metals. For example, the first connection line CL_L1 may include at least one of a first transparent gate metal TM_GM1, a second transparent gate metal TM_GM2, and a third transparent gate metal TM_GM3.

[0395] According to the above examples of the types of line metals, for example, according to the examples of the types of horizontal line metals and vertical line metals, the layer in which the first transparent metal TM_GM included in the first connection line CL_L1 is disposed may be located below the layer in which the horizontal line metals (e.g., SDM1, SDM2) are disposed, and the first metal GM included in the second connection line CL_L2 may include at least one of the vertical line metals (e.g., GM1, GM2, and GM3).

[0396] Figure 19 Illustrated is the structure of the connection line CL in the first display area OA1 of the display panel 110 according to an embodiment of the present disclosure.

[0397] Reference Figure 19 A plurality of connection lines CL can electrically connect a plurality of first pixel circuits SPC1 provided in the second display area OBA1 and a plurality of first pixel electrodes PE1 provided in the first display area OA1.

[0398] Reference Figure 19 A plurality of connection lines CL can be tied together and arranged as a bundle GR_CL.

[0399] Reference Figure 19 A bundle GR_CL can be arranged in a straight line shape within the second display area OBA1, but can be arranged in a curved shape or meanderingly within the first display area OA1.

[0400] Reference Figure 19 Within the first display area OA1, a bundle GR_CL can be arranged meanderingly while avoiding the light-emitting areas EA_R, EA_G, and EA_B and the common electrode holes CH. The common electrode holes CH can be a transmissive area or a transparent area.

[0401] Reference Figure 19 Within the first display area OA1, as the distance from the second display area OBA1 increases, the size of a bundle GR_CL can become smaller. For example, the farther away from the second display area OBA1, the smaller the size of a bundle GR_CL becomes. Therefore, when a plurality of connection lines CL are tied together and arranged as a bundle GR_CL, the optoelectronic device provided below the first display area OA can have a larger (better) value of the MTF (modulation transfer function) parameter than when the plurality of connection lines CL are not tied together, and the glare phenomenon can be reduced or prevented. In addition, when the bundle is arranged meanderingly within the first display area OA1 or when the size of a bundle GR_CL becomes smaller as its distance from the second display area OBA1 increases, the value of the MTF parameter can be further increased and the glare phenomenon can be further reduced.

[0402] Figure 20 Schematically illustrated are a second optical area OA2 of a first type in a display panel 110 according to an embodiment of the present disclosure and a normal area NA surrounding the second optical area.

[0403] Reference Figure 20 The display area DA may further include a fourth display area OA2 and a fifth display area OBA2 that are located outside the second display area OBA1 and allow light to pass through. The fifth display area OBA2 may be located between the fourth display area OA2 and the third display area NA.

[0404] The fourth display area OA2 may be a second optical area OA2 that overlaps with the second electronic device 12. The fourth display area OA2 may include a plurality of second transmissive areas TA2. The plurality of second transmissive areas TA2 may overlap with a plurality of common electrode holes CH formed in the common electrode CE.

[0405] Referring to Figure 20 , the fourth display area OA2 may have a first type of structure.

[0406] The fact that the fourth display area OA2, which is the second optical area OA2, is of the first type may mean that a fifth display area OBA2 corresponding to the second optical border area OBA2 is provided outside the fourth display area OA2, and may refer to a type in which light-emitting elements ED are provided in the fourth display area OA2 but pixel circuits SPC are not provided.

[0407] The fourth display area OA2 having a first type of structure may include a plurality of light-emitting areas EA. The plurality of light-emitting areas EA may include a plurality of red light-emitting areas EA_R that emit red light, a plurality of green light-emitting areas EA_G that emit green light, and a plurality of blue light-emitting areas EA_B that emit blue light.

[0408] Referring to Figure 20 , two or more light-emitting elements may be provided in the fourth display area OA2 having a first type of structure. Pixel circuits and transistors included therein are not provided in the fourth display area OA2.

[0409] In addition, two or more light-emitting elements may be provided in the first display area OA1 having a first type of structure. Pixel circuits and transistors included therein are not provided in the first display area OA1.

[0410] Referring to Figure 20 , a pixel circuit including transistors for driving two or more light-emitting elements provided in the fourth display area OA2 may be provided in the fifth display area OBA2 instead of the fourth display area OA2.

[0411] Similarly, a pixel circuit including transistors for driving two or more light-emitting elements provided in the first display area OA1 having a first type of structure may not be provided in the first display area OA1, but may be provided in the second display area OBA1.

[0412] The first electronic device 11 may overlap with the first display area OA1 and may perform a first operation using first light in a first wavelength band among the light passing through the first display area OA1.

[0413] The second electronic device 12 may overlap with the fourth display region OA2 and may perform a second operation using second light in a second wavelength band different from the first wavelength band among the light passing through the fourth display region OA2.

[0414] In the above, the descriptions of the first display region OA1 and the second display region OBA1 as the first optical region OA1 and the first optical border region OBA1 can be equivalently applied to the fourth display region OA2 and the fifth display region OBA2 as the second optical region OA2 and the second optical border region OBA2. However, the transmittance of the fourth display region OA2 as the second optical region OA2 may be different from the transmittance of the first display region OA1 as the first optical region OA1.

[0415] Figure 21 Schematically illustrated is a second type of second optical region and a normal region surrounding the second optical region in a display panel 110 according to an embodiment of the present disclosure.

[0416] Refer to Figure 21 , the display region DA may include the fourth display region OA2 as the second optical region OA2. When the fourth display region OA2 has a second type of structure, the fourth display region OA2 may include a plurality of transmissive regions TA2 and non-transmissive regions NTA. Here, the second type may also be referred to as a hole type.

[0417] In the fourth display region OA2, the non-transmissive region NTA may be a region other than the plurality of transmissive regions TA2.

[0418] Refer to Figure 21 , the non-transmissive region NTA may include a plurality of light-emitting regions EA. A plurality of light-emitting elements ED for the plurality of light-emitting regions EA may be provided in the non-transmissive region NTA.

[0419] A plurality of pixel circuits SPC may be provided in the fourth display region OA2 as the second optical region OA2. A plurality of pixel circuits SPC for driving the plurality of light-emitting elements ED may be provided in the non-transmissive region NTA in the fourth display region OA2. This is different from the fact that a plurality of pixel circuits SPC are not provided in the first display region OA1 as the first optical region OA1 and having a first type of structure.

[0420] Therefore, the transistors DT and ST and the storage capacitor Cst may not be provided in the first display region OA1 as the first optical region OA1, and the transistors DT and ST and the storage capacitor Cst may be provided in the fourth display region OA4 as the second optical region OA2.

[0421] For example, two or more light-emitting elements ED may be provided in a first display area OA1 that serves as a first optical area OA1, and two or more light-emitting elements ED may be provided in a non-transmissive area NTA of a fourth display area OA4 that serves as a second optical area OA2. In contrast, transistors may not be provided in the first display area OA1 that serves as the first optical area OA1, and transistors may be provided in the fourth display area OA4 that serves as the second optical area OA2.

[0422] Referring Figure 21 , the arrangement of the light-emitting area EA in the fourth display area OA4 that serves as the second optical area OA2 may be the same as or similar to the arrangement of the light-emitting area EA in the normal area NA, and may be the same as or similar to the arrangement of the light-emitting area EA in the first display area OA1 that serves as the first optical area OA1.

[0423] Referring Figure 21 , the area size of each of the plurality of light-emitting areas EA included in the fourth display area OA4 that serves as the second optical area OA2 may be the same as or similar to the area size of each of the plurality of light-emitting areas EA included in the normal area NA.

[0424] In addition, the area size of each of the plurality of light-emitting areas EA included in the fourth display area OA4 that serves as the second optical area OA2 may be the same as or similar to the area size of each of the plurality of light-emitting areas EA included in the first display area OA1 that serves as the first optical area OA1.

[0425] All or part of the first optical area OA1 may overlap with the first electronic device 11, and all or part of the second optical area OA2 may overlap with the second electronic device 12.

[0426] The transmittance of the first optical area OA1 and the second optical area OA2 may be higher than the transmittance of the normal area NA.

[0427] For example, the first optical electronic device 11 may be a camera, and the second optical electronic device 12 may be a sensor different from the camera.

[0428] For example, the first optical electronic device 11 may be a device that receives visible light and performs a specified operation, and the second optical electronic device 12 may be a device that receives light other than visible light (e.g., infrared rays, ultraviolet rays) and performs a specified operation.

[0429] For example, if the first optoelectronic device 11 is a device that requires a larger amount of light than the second optoelectronic device 12, the transmittance of the first optical region OA1 may be greater than or equal to the transmittance of the second optical region OA2. In addition, the electronic device or optoelectronic device described herein may also be referred to as an optical sensor, an optical element, an optical device, etc., and the present disclosure is not limited thereto.

[0430] Referring to Figure 21 , the display area DA may further include a fourth display area OA2 located outside the second display area OBA1. The fourth display area OA2 may include two or more transmissive areas TA2 and non-transmissive areas NTA.

[0431] Hereinafter, the characteristics of the first display area OA1 of the first optical region OA1 as the first type and the fourth display area OA2 of the second optical region OA2 as the second type will be briefly described.

[0432] Two or more light-emitting elements may be provided in the first display area OA1, and two or more light-emitting elements may be provided in the fourth display area OA2.

[0433] The pixel circuit and the transistors included therein may not be provided in the first display area OA1, and the pixel circuit and the transistors included therein may be provided in the fourth display area OA2.

[0434] The first electronic device 11 may overlap with the first display area OA1 and may perform a first operation using the first light in the first wavelength band among the light passing through the first display area OA1.

[0435] The second electronic device 12 may overlap with the fourth display area OA2 and may perform a second operation using the second light in the second wavelength band different from the first wavelength band among the light transmitted through the fourth display area OA2.

[0436] The embodiments of the present disclosure described above are briefly described as follows.

[0437] A display device according to an embodiment of the present disclosure may include: a display area including a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit provided in the second display area; a first pixel electrode of a first light-emitting element provided in the first display area; and a connection line electrically connecting the first pixel electrode and the first pixel circuit.

[0438] The connection line may include: a first connection line provided in the first display area and the second display area and including a first transparent metal; and a second connection line provided in the second display area, provided to contact the upper surface of the first connection line, and including a first metal.

[0439] A display device according to an embodiment of the present disclosure may include: a substrate including a display area for displaying an image and a non-display area for not displaying an image, the display area including a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit disposed on the substrate and in the second display area; a first pixel electrode of a first light-emitting element disposed on the substrate and in the first display area; and a connection line electrically connecting the first pixel electrode and the first pixel circuit.

[0440] In the display device according to an embodiment of the present disclosure, the connection line may be a single metal layer in the first display area and may be multiple metal layers in the second display area.

[0441] The connection line may include: a first connection line disposed in the first display area and the second display area and including a first transparent metal; and a second connection line disposed in the second display area, disposed to contact an upper surface of the first connection line, and including a first metal.

[0442] The single metal layer may include a first transparent metal, and the multiple metal layers may include a first transparent metal and a first metal.

[0443] The above description and the drawings provide examples of the technical idea of the present disclosure for illustrative purposes only. Various modifications, additions, and substitutions to the embodiments of the present disclosure will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments.

[0444] Cross-reference to related applications

[0445] This application claims the benefit and priority of Korean Patent Application No. 10-2023-0195659, filed in Korea on December 28, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: A display area, the display area comprising a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit, wherein the first pixel circuit is arranged in the second display area; a first pixel electrode of a first light emitting element, wherein the first pixel electrode of the first light emitting element is disposed in the first display area; as well as a connecting line, the connecting line electrically connecting the first pixel electrode and the first pixel circuit, Wherein, the display area further includes a third display area located outside the second display area, Wherein, the connecting line includes: a first connection line, the first connection line being disposed in the first display area and the second display area and comprising a first transparent metal; and A second connection line is disposed in the second display area, is disposed to contact an upper surface of the first connection line, and includes a first metal. 2 . The display device according to claim 1 , further comprising an optical sensor overlapping the first display area and receiving light passing through the first display area.

3. The display device according to claim 1, further comprising a common electrode, wherein the common electrode is commonly disposed in the first display area and the second display area. in, The common electrode includes one or more openings in the first display area.

4. The display device according to claim 3, in, A plurality of pixel circuits are arranged in the second display area, The connection lines are formed as a plurality of connection lines electrically connecting the plurality of pixel circuits and the plurality of pixel electrodes. wherein the plurality of connecting wires are tied together and arranged into a bundle, and The one beam is arranged in a zigzag manner while avoiding the one or more openings in the first display area.

5. The display device according to claim 4, wherein: The size of the one beam becomes smaller as the distance from the second display area increases.

6. The display device according to claim 1, further comprising: a storage capacitor disposed in the second display area and including a first capacitor electrode and a second capacitor electrode, Herein, the first metal is a metal included in at least one of the first capacitor electrode and the second capacitor electrode.

7. The display device according to claim 6, in, The first capacitor electrode comprises: a first lower capacitor electrode comprising a first transparent gate metal; and a first upper capacitor electrode disposed in contact with an upper surface of the first lower capacitor electrode and comprising a first gate metal, Wherein, the second capacitor electrode comprises: a second lower capacitor electrode, the second lower capacitor electrode comprising a second transparent gate metal; and a second upper capacitor electrode disposed in contact with an upper surface of the second lower capacitor electrode and comprising a second gate metal, Wherein, the first transparent metal includes the first transparent gate metal or the second transparent gate metal, and The first metal includes the first gate metal or the second gate metal.

8. The display device according to claim 1, further comprising: a plurality of transistors disposed in the second display area and including a gate electrode, a source electrode, and a drain electrode, Wherein, the gate electrode comprises a first gate metal or a third gate metal, and The first metal includes the first gate metal or the third gate metal.

9. The display device according to claim 8, wherein: The gate electrode comprises: a lower gate electrode, the lower gate electrode comprising a first transparent gate metal or a third transparent gate metal; and an upper gate electrode, the upper gate electrode being arranged to contact an upper surface of the lower gate electrode and comprising the first gate metal or the third gate metal, The first transparent metal includes the first transparent gate metal or the third transparent gate metal.

10. The display device according to claim 8, wherein: The plurality of transistors include a first transistor including an active layer made of a silicon-based semiconductor material and a gate electrode including the first gate metal, and Wherein, the first metal includes the first gate metal.

11. The display device according to claim 8, wherein: The plurality of transistors include a second transistor including an active layer made of an oxide-based semiconductor material and a gate electrode including the third gate metal, and Wherein, the first metal includes the third gate metal.

12. The display device according to claim 1, further comprising: another pixel electrode of another light emitting element, wherein the another pixel electrode of the another light emitting element is arranged in the first display area; as well as An extended connection line is provided in the first display area and connects the first pixel electrode and the another pixel electrode.

13. The display device according to claim 12, wherein: The extended connection line includes a second transparent metal different from the first transparent metal.

14. The display device according to claim 13, wherein: The first pixel circuit includes a transistor, which is disposed in the second display area and includes a gate electrode, a source electrode, and a drain electrode. Wherein, the source electrode comprises: an upper source electrode, the upper source electrode comprising a first source-drain metal; and a lower source electrode disposed below the upper source electrode, in contact with the upper source electrode and comprising a first transparent source-drain metal, Wherein, the drain electrode comprises: an upper drain electrode, the upper drain electrode comprising the first source-drain metal; and a lower drain electrode disposed below the upper drain electrode, in contact with the upper drain electrode and including the first transparent source-drain metal, and Wherein, the second transparent metal includes the first transparent source-drain metal.

15. The display device according to claim 13, further comprising a relay electrode, the relay electrode being electrically connected to a second pixel electrode of a second light emitting element disposed in the second display area, in, The relay electrode comprises: an upper relay electrode, the upper relay electrode comprising a second source-drain metal; and a lower relay electrode disposed below the upper relay electrode, in contact with the upper relay electrode and comprising a second transparent source-drain metal, and Wherein, the second transparent metal includes the second transparent source-drain metal.

16. The display device according to claim 1, in, A horizontal line is disposed in the display area, extends in a first direction and includes a horizontal line metal, wherein a vertical line is disposed in the display area, extends in a second direction different from the first direction and includes a vertical line metal different from the horizontal line metal, and The layer on which the first transparent metal is disposed is located below the layer on which the horizontal line metal is disposed.

17. The display device according to claim 1, in, A horizontal line is disposed in the display area, extends in a first direction and includes a horizontal line metal, wherein a vertical line is disposed in the display area, extends in a second direction different from the first direction and includes a vertical line metal different from the horizontal line metal, and Wherein, the first metal includes the vertical line metal.

18. The display device according to claim 16 or 17, wherein: The horizontal line and the vertical line are disposed while bypassing the first display area.

19. A display device, comprising: A substrate, the substrate comprising a display area for displaying an image and a non-display area for not displaying an image, the display area comprising a first display area capable of transmitting light and a second display area located outside the first display area; a first pixel circuit, the first pixel circuit being disposed on the substrate and in the second display area; a first pixel electrode of a first light emitting element, wherein the first pixel electrode of the first light emitting element is disposed on the substrate and in the first display area; as well as a connecting line, the connecting line electrically connecting the first pixel electrode and the first pixel circuit, The connection line is a single metal layer in the first display area and is a plurality of metal layers in the second display area.

20. The display device according to claim 19, wherein: The connecting line comprises: a first connection line, the first connection line being disposed in the first display area and the second display area and comprising a first transparent metal; and a second connection line, the second connection line being disposed in the second display area, being disposed to contact an upper surface of the first connection line, and comprising a first metal, wherein the single metal layer comprises the first transparent metal, and The plurality of metal layers include both the first transparent metal and the first metal.

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