Display device

Abstract

A display device is disclosed. A display device according to the present disclosure includes: a substrate; a light emitting element disposed over the substrate; an encapsulation layer covering the light emitting element; and a protective layer disposed to surround a side surface of the encapsulation layer. According to the present disclosure, a display device having improved moisture and oxygen permeation resistance reliability may be provided.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example but not limited to, a stretchable display device having improved reliability against moisture and oxygen permeation. Background Art

[0002] As society enters the full information age, the field of displays that visually express electrical information signals has developed rapidly. In response to this development, various display devices having excellent properties such as thinness, light weight, and low power consumption are being developed. Examples of such display devices include liquid crystal display (LCD) devices, field emission display (FED) devices, organic light emitting display (OLED) devices, and the like.

[0003] The application range of display devices is becoming increasingly diverse, including not only computer monitors and televisions but also personal portable devices. Currently, display devices having a large display area but small volume and weight are being studied.

[0004] In addition, recently, display devices manufactured by forming display components, lines, etc. on a flexible substrate formed of plastic or the like, which is a flexible material capable of expanding and contracting in a specific direction and changing into various shapes, are attracting much attention as next-generation display devices.

[0005] The descriptions provided in the background art section should not be assumed to be prior art merely because they are mentioned in the background art section or are related to the descriptions in the background art section. The descriptions in the background art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0006] The inventors have recognized that in the related art, light emitting diodes of display devices are vulnerable to damage by moisture and oxygen. Therefore, an object to be achieved by the present disclosure is to provide a display device capable of protecting light emitting diodes from moisture and oxygen.

[0007] Another object to be achieved by the present disclosure is to provide a display device capable of reducing or minimizing damage to connection lines by protecting stretchable connection lines from moisture and oxygen.

[0008] The problems of the present disclosure are not limited to the above problems. That is, other problems not described can be clearly understood by those skilled in the art from the following descriptions.

[0009] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a light emitting element disposed above the substrate; a encapsulation layer covering the light emitting element; and a protective layer disposed to surround a side surface of the encapsulation layer.

[0010] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0011] According to the present disclosure, light-emitting diodes can be protected from being damaged by moisture and oxygen penetrating from the outside.

[0012] According to the present disclosure, the penetration of moisture and oxygen into connection lines and the like can be delayed.

[0013] According to the present disclosure, the reliability of light-emitting diodes or connection lines can be improved.

[0014] The effects according to the present disclosure are not limited to the contents of the above examples, and various other effects are further included in the present disclosure.

[0015] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned above will be clearly understood by those of ordinary skill in the art from the following description.

[0016] The objects to be achieved by the present disclosure, the means for achieving these objects, and the effects of the present disclosure described above do not define the basic features of the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the drawings, in which:

[0018] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2 is an enlarged plan view of a display area of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 3 is a cross-sectional view taken along line III-III' in Figure 2 ;

[0021] Figure 4 is an enlarged plan view of a display area of a display device according to another exemplary embodiment of the present disclosure;

[0022] Figure 5 is a cross-sectional view taken along line V-V' in Figure 4 ;

[0023] Figure 6 is an enlarged plan view of a display area of a display device according to still another exemplary embodiment of the present disclosure;

[0024] Figure 7 is a cross-sectional view taken along line V-V' in Figure 6A cross-sectional view taken along line VII-VII' in;

[0025] Figure 8 is an enlarged plan view of a display area of a display device according to another exemplary embodiment of the present disclosure; and

[0026] Figure 9 is a cross-sectional view taken along Figure 8 line IX-IX' in.

[0027] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Description

[0028] Advantages and features of the present disclosure, and methods of achieving these advantages and features, will become apparent by referring to the exemplary embodiments and the drawings described in detail below. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only, so that those of ordinary skill in the art can fully understand the content disclosed by the present disclosure and the scope of the present disclosure.

[0029] The shapes, sizes, areas, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements used to describe the exemplary embodiments of the present disclosure illustrated in the drawings are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. Further, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted in order to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising," "having," "including," "containing," "constituting," "made of," "formed of," "composed of" used herein generally mean allowing the addition of other components, unless the term "only" is used when the term is used. Any singular reference may include the plural unless otherwise expressly specified.

[0030] For ease of description, dimensions including the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions including the relative size, position, and thickness of the components shown in the respective drawings submitted here are part of the present disclosure.

[0031] Even if not explicitly stated, components are interpreted to include ordinary error ranges.

[0032] When terms such as "on", "above", "over", "below", "under", "beside", "beneath", "near", "by", "adjacent to", "at the side of", "close to" are used to describe the positional relationship between two components, one or more components can be positioned between the two components unless the terms are used with words such as "immediately" or "directly".

[0033] Spatially relative terms, such as "below", "beneath", "under", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of an element during use or operation. For example, if an element in the figure is inverted, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" can include both below and above orientations. Similarly, the exemplary terms "above" or "over" can include both "above" and "below" orientations.

[0034] When describing temporal relationships, terms such as "after", "subsequently", "next", "then", "before", etc. can include cases where any two events are not consecutive, unless terms such as "immediately", "exactly" or "directly" are explicitly used.

[0035] When an element or layer is disposed "on" another element or layer, the other layer or element can be directly disposed on the other element or disposed therebetween.

[0036] Although terms such as "first", "second", "A", "B", "a" and "b" etc. are used to describe various components, these components are not restricted by these terms. These terms are only used to distinguish one component from other components. Thus, the first component mentioned below can be the second component in the technical concept of the present disclosure.

[0037] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used herein. Each of these terms is not used to define the nature, order or sequence of the corresponding component, but only to distinguish the corresponding component from other components. In the case where a structural element or layer is described as "connected", "coupled", "bonded" or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be "connected", "coupled", "bonded" or "joined" to the structural element or layer directly or indirectly.

[0038] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0039] As used herein, the term "device" may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include a light-emitting element and the like. Additionally, examples of the device may include a laptop computer, a television, a computer monitor, a vehicle device, a wearable device, and a vehicle equipment device, and complete product or end-product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including a light-emitting element and the like, such as mobile electronic devices such as smartphones or electronic tablets, but the embodiments of the present disclosure are not limited thereto.

[0040] Similar reference numerals generally denote similar elements throughout the specification.

[0041] For ease of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the components shown.

[0042] The features of the various embodiments of the present disclosure may be adhesively bonded or combined with each other partially or wholly, and may be interlocked and operated in various technical ways, and these embodiments may be executed independently of or in association with each other.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0044] In aspects of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. Furthermore, the source electrode in any aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[0045] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0046] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure.Figure 2 is an enlarged plan view of a display area of a display device according to an exemplary embodiment of the present disclosure. Figure 3 is a cross-sectional view taken along line III-III’ in Figure 2 in the figure.

[0047] First, a display device 100 according to an exemplary embodiment of the present disclosure is a display device capable of displaying an image even when bent or stretched, and may also be referred to as a stretchable display device. Compared with a conventional general display device, the display device 100 may have higher flexibility and stretchability. Therefore, a user can not only bend or stretch the display device 100, but also freely change the shape of the display device 100 according to the user's manipulation. For example, when a user holds and pulls one end of the display device 100, the display device 100 can be stretched in the direction in which the user pulls the display device 100. Or, when the user sets the display device 100 on an uneven outer surface, the display device 100 can be set to bend along the shape of the outer surface. In addition, when the force applied by the user is removed, the display device 100 can return to its original form.

[0048] Referring together to Figure 1 、 Figure 2 and Figure 3 , a substrate SUB1 is a substrate SUB1 for supporting and protecting various components of the display device 100. The substrate SUB1 can support a pattern layer PTL on which pixels PX, a gate driver GD, and a power supply PS are formed. The substrate SUB1 may be a flexible substrate. Here, the flexible characteristic may be interpreted to have the same meaning as the characteristics of being bendable, unbreakable, rollable, and foldable.

[0049] The substrate SUB1 may be formed of a plastic material having flexibility. In some exemplary embodiments, the substrate SUB1 may be made of a flexible polymer film. For example, the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto.

[0050] When the substrate SUB1 is formed of polyimide PI, moisture passes through the substrate SUB1 formed of the polyimide PI layer and penetrates into the plurality of transistors TR1 and TR2 and the plurality of light-emitting diodes LD described later, thereby degrading the performance of the display device 100. Accordingly, the display device 100 according to an exemplary embodiment of the present disclosure may be configured such that the substrate SUB1 includes a double layer of a first substrate SUB1a and a second substrate SUB1b. However, the number of layers of the substrate SUB1 is not limited thereto, and the substrate SUB1 may also include more than two layers.

[0051] In addition, a first buffer layer BUF1 may be disposed between the first substrate SUB1a and the second substrate SUB1b. For example, in the display device 100 according to an exemplary embodiment of the present disclosure, the second substrate SUB1b, the first buffer layer BUF1, and the first substrate SUB1a may be sequentially stacked from the bottom. In this case, the first buffer layer BUF1 may be disposed between the first substrate SUB1a and the second substrate SUB1b to prevent moisture and oxygen that can pass through the second substrate SUB1b disposed on the lower portion from penetrating into the first substrate SUB1a. Accordingly, the reliability of the display device 100 may be improved.

[0052] The first buffer layer BUF1 may be composed of a single layer or multiple layers formed of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). For example, the first buffer layer BUF1 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, and the multiple layers of the inorganic film may be formed by alternately stacking at least two of one or more layers of a silicon oxide (SiOx) film, one or more layers of a silicon nitride (SiNx) film, and one or more layers of a silicon oxynitride (SiON) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. For example, the first buffer layer BUF1 may be formed of a silicon oxide film having excellent ductility, but is not limited thereto.

[0053] The substrate SUB1 may have reversible expansion and contraction capabilities. Accordingly, the substrate SUB1 may also be referred to as a stretchable substrate SUB1, an elastic substrate SUB1, an extensible substrate SUB1, a soft substrate SUB1, a flexible substrate SUB1, etc., but is not limited thereto.

[0054] The substrate SUB1 includes a display area AA and a non-display area NA disposed near, surrounding, or around the display area AA. However, the display area AA and the non-display area NA are not limited to the substrate SUB1, but may be referred to throughout the display device 100.

[0055] The display area AA is an area where an image is displayed in the display device 100, and a plurality of pixels PX are provided in the display area AA. In addition, each pixel PX may include a display element and various driving elements for driving the display element. The various driving elements may refer to at least one thin film transistor (TFT) and a capacitor, but are not limited thereto. For example, the number of transistors TFTs in the pixel circuit of the present disclosure may be two or more, and the number of capacitors may be one or more. For example, the pixel circuit of the present disclosure may be a 3T2C pixel circuit including three TFTs and two capacitors, a 5T1C pixel circuit including five TFTs and one capacitor, a 5T2C pixel circuit including five TFTs and two capacitors, or a 7T2C pixel circuit including seven TFTs and two capacitors, etc.

[0056] The active layer of the transistor TFT may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0057] The oxide semiconductor material may have an excellent effect of preventing leakage current and a relatively low manufacturing cost. The oxide semiconductor may be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0058] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, so it has a high mobility, and has low energy consumption and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0059] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0060] Each of the plurality of pixels PX may be driven by being connected to various lines. For example, each of the plurality of pixels PX may be connected to various lines, such as a gate line, a data line, a high potential voltage line, a low potential voltage line, a reference voltage line, and an initialization voltage line, but is not limited thereto.

[0061] The non-display area NA is an area where an image is not displayed. The non-display area NA may be an area adjacent to the display area AA. In addition, the non-display area NA may be an area adjacent to and surrounding the display area AA. However, the present disclosure is not limited thereto, and the non-display area NA corresponds to an area of the substrate SUB1 that does not include the display area AA and may be modified and separated into various shapes. In the non-display area NA, components for driving a plurality of pixels PX provided in the display area AA, such as a gate driver GD and a power supply PS, may be provided. In addition, a plurality of pads connected to the data driver DD and the printed circuit board PCB may be provided in the non-display area NA, and each pad may be connected to each of the plurality of pixels PX in the display area AA.

[0062] A pattern layer PTL is provided on the substrate SUB1. The pattern layer PTL includes a plurality of first plate patterns PP1 and a plurality of first line patterns LP1 provided in the display area AA and a plurality of second plate patterns PP2 and a plurality of second line patterns LP2 provided in the non-display area NA.

[0063] A plurality of plate patterns PP are provided in the display area AA and the non-display area NA. The plurality of plate patterns PP include a plurality of first plate patterns PP1 and a plurality of second plate patterns PP2. The plurality of first plate patterns PP1 are provided in the display area AA of the substrate SUB1, and the plurality of second plate patterns PP2 are provided in the non-display area NA of the substrate SUB1. A plurality of pixels PX may be formed on the plurality of first plate patterns PP1, and the gate driver GD and the power supply PS may be formed on the plurality of second plate patterns PP2, but are not limited thereto.

[0064] The plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be provided in the form of islands spaced apart from each other. Each of the plurality of first plate patterns PP1 and the plurality of second plate patterns PP1 may be separately separated. Therefore, the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be referred to as first island patterns and second island patterns or first single patterns and second single patterns, etc., but are not limited thereto.

[0065] Refer to Figure 1 , the size of each of the plurality of second plate patterns PP2 may be larger than the size of each of the plurality of first plate patterns PP1. One stage of the gate driver GD may be provided in each of the plurality of second plate patterns PP2. Therefore, since the area occupied by various circuit configurations constituting one stage of the gate driver GD is relatively larger than the area occupied by one pixel PX, the size of each of the plurality of second plate patterns PP2 may be larger than the size of each of the plurality of first plate patterns PP1. However, the present disclosure is not limited thereto, and the size of each of the plurality of second plate patterns PP2 may also not be larger than the size of each of the plurality of first plate patterns PP1.

[0066] In addition, Figure 1 it is shown that in the first direction X of the non-display area NA, a plurality of second plate patterns PP2 are provided on both sides of the display area AA. For example, some portions of the plurality of second plate patterns PP2 are provided in the non-display area NA located below the display area AA in the first direction X, while other portions of the plurality of second plate patterns PP2 are provided in the non-display area NA located above the display area AA in the first direction X. However, the present disclosure is exemplary, and the plurality of second plate patterns PP2 may be provided in any area of the non-display area NA. For example, some portions of the plurality of second plate patterns PP2 are provided in the non-display area NA located to the left of the display area AA in the second direction Y, while other portions of the plurality of second plate patterns PP2 are provided in the non-display area NA located to the right of the display area AA in the second direction Y, but not limited thereto. In addition, the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 are shown in a square shape, but not limited thereto, and the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be modified into various shapes.

[0067] Referring to Figure 1 and Figure 2 , a plurality of line patterns LP are provided in the display area AA and the non-display area NA. The plurality of line patterns LP include a plurality of first line patterns LP1 and a plurality of second line patterns LP2. The plurality of first line patterns LP1 are provided in the display area AA. The plurality of first line patterns LP1 are patterns that connect adjacent first plate patterns PP1 to each other, and may also be referred to as internal connection patterns. That is, the plurality of first line patterns LP1 may be provided between the plurality of first plate patterns PP1.

[0068] The plurality of second line patterns LP2 of the pattern layer PTL are provided in the non-display area NA. The plurality of second line patterns LP2 may be referred to as patterns that connect adjacent first plate patterns PP1 and second plate patterns PP2 to each other or connect adjacent second plate patterns PP2 to each other, and may also be referred to as external connection patterns. The plurality of second line patterns LP2 may be provided between adjacent first plate patterns PP1 and second plate patterns PP2, or between adjacent second plate patterns PP2.

[0069] The plurality of first line patterns LP1 and the plurality of second line patterns LP2 have a curved shape. For example, the plurality of first line patterns LP1 and the plurality of second line patterns LP2 have a sinusoidal shape. However, the shapes of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 are not limited thereto. For example, the plurality of first line patterns LP1 and the plurality of second line patterns LP2 may extend in a zigzag shape. Alternatively, the shapes of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 may have various shapes, such as a shape in which a plurality of rhombic substrates are connected at vertices and extend, or a shape in which a semi-circular substrate and a quarter-circular substrate are connected to each other. In addition, the shapes of the plurality of first line patterns LP1 and the shapes of the plurality of second line patterns LP2 may be the same as or different from each other. For example, each of the plurality of first line patterns LP1 may have a sinusoidal shape, while each of the plurality of second line patterns LP2 may extend in a zigzag shape, but is not limited thereto. In addition, Figure 1 The number and shapes of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 shown are exemplary, and the number and shapes of the plurality of first line patterns LP1 and the number and shapes of the plurality of second line patterns LP2 may vary differently in various ways according to the design.

[0070] In addition, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 are rigid patterns. For example, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 have rigid properties compared to the substrate SUB1.

[0071] The plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2, which are rigid patterns, may be formed of a plastic material having a lower flexibility than the substrate SUB1. For example, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be formed of at least one material selected from polyacrylate and polyacetate, but are not limited thereto. In this case, when the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 are formed of the same material, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be integrated. However, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be formed of different materials, but are not limited thereto. For example, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may all be formed of different materials; alternatively, the plurality of first plate patterns PP1 and the plurality of first line patterns LP1 may be formed of the same material, while the plurality of second plate patterns PP2 and the plurality of second line patterns LP2 may be formed of the same material, but are not limited thereto.

[0072] The elastic modulus of the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be higher than the elastic modulus of the substrate SUB1. The elastic modulus is a parameter representing the rate of deformation with respect to the stress applied to the substrate SUB1. When the elastic modulus is relatively high, the hardness may be relatively high. Therefore, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may each be referred to as the plurality of first rigid patterns, the plurality of second rigid patterns, the plurality of third rigid patterns, and the plurality of fourth rigid patterns. The elastic modulus of the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be 1000 times higher than the elastic modulus of the substrate SUB1. For example, the elastic modulus of the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be 1500 times higher than the elastic modulus of the substrate SUB1, but is not limited thereto.

[0073] In addition, in some exemplary embodiments, the substrate SUB1 may be defined as including a plurality of rigid regions RA and flexible regions SA. The plurality of rigid regions RA may be regions that overlap with the pattern layer PTL in the substrate SUB1. The flexible regions SA may be regions that do not overlap with the pattern layer PTL. Since the pattern layer PTL is disposed in the plurality of rigid regions RA and the pattern layer PTL is not disposed in the flexible regions SA, the plurality of rigid regions RA may have more rigid characteristics than the flexible regions SA. In this case, the flexible regions SA and the plurality of rigid regions RA are not limited to the substrate SUB1 and may be referred to throughout the display device 100.

[0074] The gate driver GD may be mounted on the plurality of second plate patterns PP2. When various components are manufactured on the plurality of second plate patterns PP2, the gate driver GD may be formed on the plurality of second plate patterns PP2 by the gate-in-panel (GIP) method. Accordingly, various circuit components constituting the gate driver GD, such as transistors, capacitors, lines, etc., may be disposed on the plurality of second plate patterns PP2. The gate driver GD is formed above each of the plurality of second plate patterns PP2 and may be provided as one stage of a circuit including transistors, capacitors, etc. However, the gate driver GD may be mounted by the chip-on-film (COF) method, but is not limited thereto.

[0075] The power supply PS is disposed on the plurality of second plate patterns PP2. The power supply PS may be formed on the second plate pattern PP2 adjacent to the gate driver GD. The power supply PS is a plurality of power supply blocks patterned when various components on the second plate pattern PP2 are manufactured and may be formed on the second plate pattern PP2. The power supply PS may be electrically connected to the gate driver GD in the non-display region NA and the plurality of pixels PX in the display region AA to supply a driving voltage. Specifically, the power supply PS may be electrically connected to the gate driver GD formed on the second plate pattern PP2 and the plurality of pixels PX formed on the first plate pattern PP1 through the second line pattern LP2 and the first line pattern LP1. For example, the power supply PS may supply a gate driving voltage and a clock signal to the gate driver GD. The power supply PS may supply a power supply voltage to each of the plurality of pixels PX.

[0076] The printed circuit board PCB is connected to the edge of the substrate SUB1. The printed circuit board PCB is a component that transmits signals and voltages for driving display elements from the control unit to the display elements. Therefore, the printed circuit board PCB can also be referred to as a driving substrate. The printed circuit board PCB can be mounted with a control unit, such as an IC chip and a circuit unit. In addition, a memory, a processor, etc. can be mounted on the printed circuit board PCB. In addition, the printed circuit board PCB provided in the display device 100 may include a stretching area and a non-stretching area to ensure stretchability. In addition, an IC chip, a circuit unit, a memory, a processor, etc. can be mounted within the non-stretching area, and wires electrically connected to the IC chip, the circuit unit, the memory, and the processor can be provided within the stretching area.

[0077] The data driver DD is a component that supplies data voltages to a plurality of pixels PX provided in the display area AA. The data driver DD can be configured in the form of an IC chip, and thus can also be referred to as a data integrated circuit D-IC. In addition, the data driver DD can be mounted on the non-stretching area of the printed circuit board PCB. For example, the data driver DD can be mounted on the printed circuit board PCB in the form of a chip on board (COB). Although Figure 1 it is shown that the data driver DD is mounted by the COB method, the data driver DD can also be mounted by methods such as chip on film (COF), chip on glass (COG), tape carrier package (TCP), etc., but is not limited thereto.

[0078] In addition, Figure 1 it is shown that one data driver DD is provided corresponding to each of a plurality of columns formed by a plurality of first plate patterns PP1 provided in the display area AA, but the present disclosure is not limited thereto. For example, one data driver DD can be provided corresponding to a plurality of columns formed by a plurality of first plate patterns PP1, alternatively, two or more data drivers DD can be provided corresponding to a plurality of columns formed by a plurality of first plate patterns PP1. In addition, two or more data drivers DD can be provided on one side or both sides of the display area AA, but is not limited thereto.

[0079] Referring to Figure 1 and Figure 2 , a plurality of first plate patterns PP1 are spaced apart from each other and provided on the display area AA of the substrate SUB1. For example, as Figure 1As shown, a plurality of first plate patterns PP1 may be arranged on a substrate SUB1 in a matrix form, but is not limited thereto. A plurality of first line patterns LP1 may connect the plurality of first plate patterns PP1 to each other. Some portions of the plurality of first line patterns LP1 connect the plurality of first plate patterns PP1 adjacent to each other in the first direction X, and other portions of the plurality of first line patterns LP1 may connect the plurality of first plate patterns PP1 adjacent to each other in the second direction Y, but is not limited thereto.

[0080] Referring to Figure 2 and Figure 3 , pixels PX are provided in the plurality of first plate patterns PP1, and each pixel PX includes a plurality of sub-pixels SPX as a single unit that emits light. Each of the plurality of sub-pixels SPX may include a light-emitting diode LD as a display element and a pixel circuit (e.g., a driving transistor and a switching transistor) for driving the light-emitting diode LD. The light-emitting diode LD may be composed of an organic light-emitting diode or an inorganic light-emitting diode such as a micro light-emitting diode (LED) or a quantum dot light-emitting diode. In addition, the light-emitting diode LD may be a light-emitting diode LD formed of a composite material of an organic material and an inorganic material. In addition, each of the plurality of pixels PX includes a single light-emitting diode LD, or in another exemplary embodiment, each of the plurality of pixels PX includes a plurality of light-emitting diodes LD, and the plurality of light-emitting diodes LD may be connected to each other in series, parallel, or series-parallel. The display device 100 may display an image by driving the plurality of pixels PX in response to input image data.

[0081] In addition, the plurality of sub-pixels SPX are the smallest units constituting the display area, and n sub-pixels SPX form one pixel. Each of the plurality of sub-pixels SPX may emit light having different wavelengths from each other. The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from each other. For example, the plurality of sub-pixels SPX may include a red sub-pixel SPX, a green sub-pixel SPX, and a blue sub-pixel SPX. According to an exemplary embodiment, at least a portion of the plurality of pixels PX may further include a white sub-pixel SPX. The colors and configurations of the plurality of sub-pixels SPX may be changed in various ways as needed, but are not limited thereto.

[0082] For example, the plurality of sub-pixels SPX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, where the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SPX may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, where the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially arranged along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially arranged along the row direction. However, in the embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited and may be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0083] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, the sub-pixels that emit light of a color different from the color of the blue sub-pixel may have a light-emitting area different from the light-emitting area of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0084] A plurality of connection lines CL are provided on the plurality of line patterns LP. The plurality of connection lines CL may be lines that electrically connect the pads on the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 to each other. The plurality of connection lines CL are provided between the plurality of first plate patterns PP1, between the plurality of second plate patterns PP2, and between the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. The plurality of connection lines CL may electrically connect the pads on the plurality of first plate patterns PP1 to each other, electrically connect the pads on the plurality of second plate patterns PP2 to each other, and electrically connect the pads on the plurality of first plate patterns PP1 to the pads on the plurality of second plate patterns PP1, but is not limited thereto.

[0085] The plurality of connection lines CL include a first connection line CL1 and a second connection line CL2. The first connection line CL1 is a line extending in a first direction X between a plurality of first plate patterns PP1, between a plurality of second plate patterns PP2, and between the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. The second connection line CL2 is a line extending in a second direction Y between a plurality of first plate patterns PP1, between a plurality of second plate patterns PP2, and between the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. The plurality of connection lines CL may have a shape corresponding to the line pattern LP. For example, it may have a curved shape. For example, the plurality of connection lines CL may have a sinusoidal shape, but is not limited thereto. For example, the first connection line CL1 and the second connection line CL2 may have the same shape or different shapes. For example, when any one of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 has a sinusoidal shape, extends in a zigzag shape, has a shape in which a plurality of diamond substrates are connected at vertices and extend, or has a shape in which a semi-circular substrate and a quarter-circular substrate are connected to each other, each of the first connection line CL1 and the second connection line CL2 has a shape corresponding to the plurality of first line patterns LP1 and / or the plurality of second line patterns LP2. For example, each of the first connection line CL1 and the second connection line CL2 has a sinusoidal shape, extends in a zigzag shape, has a shape in which a plurality of diamond substrates are connected at vertices and extend, or has a shape in which a semi-circular substrate and a quarter-circular substrate are connected to each other.

[0086] The plurality of connection lines CL may have a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc. or a laminated structure of metal materials such as copper / molybdenum-titanium (Cu / Moti) and titanium / aluminum / titanium (Ti / Al / Ti), but is not limited thereto.

[0087] In addition, in a general display device, various lines such as a plurality of gate lines and a plurality of data lines are provided to extend linearly between a plurality of sub-pixels, and the plurality of sub-pixels are connected to one signal line. Therefore, in the case of a general display device, various lines such as gate lines, data lines, high-potential voltage lines, and reference voltage lines extend from one side of the display device to the other side without interruption on the substrate.

[0088] In contrast, in the case of the display device 100 according to an exemplary embodiment of the present disclosure, various lines such as straight gate lines, data lines, high-potential voltage lines, reference voltage lines, and initialization voltage lines that can be regarded as being used in a general display device are provided only on the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. That is, in the display device 100 according to an embodiment of the present disclosure, straight lines may be provided only on the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2.

[0089] In the display device 100 according to an exemplary embodiment of the present disclosure, pads on two adjacent first plate patterns PP1 may be connected by a connection line CL. Accordingly, the connection line CL electrically connects the pads on the two adjacent first plate patterns PP1 to each other. Thus, the display device 100 according to an exemplary embodiment of the present disclosure may include a plurality of connection lines CL to electrically connect various lines between the plurality of first plate patterns PP1, such as gate lines, data lines, high potential voltage lines, and reference voltage lines. For example, gate lines may be provided on the plurality of first plate patterns PP1 arranged adjacent to each other in the first direction X, and gate pads GP may be provided at both ends of the gate lines. In this case, each of the plurality of gate pads on the plurality of first plate patterns PP1 arranged adjacent to each other in the first direction X may be connected to each other by a first connection line CL1 serving as a gate line. Accordingly, the gate lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as one gate line. In addition, among all the various lines that may be included in the display device 100, lines extending in the first direction X, such as light emitting signal lines, low potential voltage lines, and high potential voltage lines, may also be electrically connected by the first connection line CL1 as described above. For example, the light emitting signal lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as one light emitting signal line; for example, the low potential voltage lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as one low potential voltage line; for example, the high potential voltage lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as one high potential voltage line, however, the present disclosure is not limited thereto.

[0090] Some portions of the plurality of second connection lines CL2 may connect pads on multiple adjacent first plate patterns PP1 to each other along the second direction Y. The internal lines on the multiple first plate patterns PP1 arranged along the second direction Y may be connected by the plurality of second connection lines CL2 serving as data lines and may transmit a data voltage. For example, the data lines provided on the multiple first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one data line. In addition, the plurality of second connection lines CL2 may serve as high-potential voltage lines, low-potential voltage lines, or reference voltage lines, but are not limited thereto. For example, the high-potential voltage lines provided on the multiple first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one high-potential voltage line; for example, the low-potential voltage lines provided on the multiple first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one low-potential voltage line; for example, the reference voltage lines provided on the multiple first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one reference voltage line, however, the present disclosure is not limited thereto.

[0091] Hereinafter, reference will be made to Figure 3 describe in detail the cross-sectional structure of the display area AA.

[0092] Referring to Figure 3 , a second buffer layer BUF2 is provided on the substrate SUB1 and the first plate pattern PP1. The second buffer layer BUF2 is formed on the multiple first plate patterns PP1 to protect various components of the display device 100 from the penetration of moisture and oxygen from the outside of the substrate SUB1 and the first plate pattern PP1. The second buffer layer BUF2 includes a multi-buffer layer BUF2a and an active buffer layer BUF2b. The second buffer layer BUF2 may be formed of an insulating material. For example, the second buffer layer BUF2 may be composed of a single layer or multiple layers formed of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). For example, the second buffer layer BUF2 may be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films may be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device 100, the second buffer layer BUF2 may be omitted.

[0093] A first transistor TR1 is provided on the second buffer layer BUF2. The first transistor TR1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0094] The first active layer ACT1 is disposed on the second buffer layer BUF2. The first active layer ACT1 may include a source region connected to the first source electrode SE1, a drain region connected to the first drain electrode DE1, and a channel region between the source region and the drain region. The first active layer ACT1 may include a polysilicon semiconductor layer formed by a low temperature polysilicon (LTPS) process, but the present disclosure is not limited thereto.

[0095] The first gate insulating layer GI1 is disposed on the first active layer ACT1. The first gate insulating layer GI1 is an insulating layer for insulating the first active layer ACT1 from the first gate electrode GE1. The first gate insulating layer GI1 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the first gate insulating layer GI1 may be formed by a single layer or multiple layers of inorganic films. For example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layer inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0096] The first gate electrode GE1 is disposed on the first gate insulating layer GI1. The first gate electrode GE1 is disposed to overlap the first active layer ACT1, and the first gate insulating layer GI1 is interposed between the first gate electrode GE1 and the first active layer ACT1. The first gate electrode GE1 may be formed of one of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more thereof, or may be composed of multiple layers thereof, but is not limited thereto.

[0097] The first interlayer insulating layer ILD1 is disposed on the first gate electrode GE1, and the second interlayer insulating layer ILD2 is disposed on the first interlayer insulating layer ILD1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 are disposed to cover the first gate electrode GE1, the first conductive layer GAT1, and the second conductive layer TM1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, each of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be formed by a single layer or multiple layers of inorganic films. For example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layer inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0098] The first conductive layer GAT1 is disposed between the first gate insulating layer GI1 and the first interlayer insulating layer ILD1. The first conductive layer GAT1 may form at least a part of a light emission control line that supplies a light emission control signal to the pixel PX, a scan line that supplies a scan signal, and a power line that supplies various power supply voltages. Here, when the first conductive layer GAT1 forms at least a part of the power line that supplies the power supply voltage, the first conductive layer GAT1 may be formed of a highly conductive material such as metal or conductive oxide. For example, the first conductive layer GAT1 may be composed of a single layer or multiple layers including aluminum (Al), copper (Cu), titanium (Ti), etc. In some exemplary embodiments, the first conductive layer GAT1 may be formed as a three-layer of titanium, aluminum, and titanium (Ti / Al / Ti) sequentially disposed. However, the composition of the first conductive layer GAT1 is not limited thereto, and the first conductive layer GAT1 may be composed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. In addition, the first gate electrode GE1 disposed on the same layer as the first conductive layer GAT1 may be formed as the first conductive layer GAT1 that forms at least a part of the light emission control line or the scan line in the first conductive layer GAT1.

[0099] A second conductive layer TM1 is disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The second conductive layer TM1 includes molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be composed of a single layer or multiple layers. The second conductive layer TM1 is disposed to overlap with the first conductive layer GAT1 and may be used as a kind of capacitor electrode.

[0100] A third buffer layer BUF3 is disposed on the second interlayer insulating layer ILD2. The third buffer layer BUF3 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the third buffer layer BUF3 may be formed of a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films may be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0101] A second transistor TR2 is disposed on the third buffer layer BUF3. The second transistor TR2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0102] First, a second active layer ACT2 is disposed on a third buffer layer BUF3. The second active layer ACT2 may include a source region connected to a second source electrode SE2, a drain region connected to a second drain electrode DE2, and a channel region between the source region and the drain region. The second active layer ACT2 may include an oxide semiconductor layer.

[0103] A second gate insulating layer GI2 is disposed on the second active layer ACT2. The second gate insulating layer GI2 is an insulating layer for insulating the second active layer ACT2 from a second gate electrode GE2. The second gate insulating layer GI2 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the second gate insulating layer GI2 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0104] A second gate electrode GE2 is disposed on the second gate insulating layer GI2. The second gate electrode GE2 is disposed to overlap the second active layer ACT2, and the second gate insulating layer GI2 is interposed between the second gate electrode GE2 and the second active layer ACT2. The second gate electrode GE2 may constitute at least a part of a scan line. The second gate electrode GE2 may be formed of one of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of them, or may be composed of multiple layers thereof, but is not limited thereto.

[0105] A third interlayer insulating layer ILD3 is disposed on the second gate electrode GE2. The third interlayer insulating layer ILD3 is disposed to cover the second gate electrode GE2. The third interlayer insulating layer ILD3 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the third interlayer insulating layer ILD3 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0106] A first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, a second drain electrode DE2, and a third conductive layer SD1 are disposed on the third interlayer insulating layer ILD3.

[0107] The first source electrode SE1 and the first drain electrode DE1 can each be electrically connected to the first active layer ACT1 through contact holes. The contact holes are formed in the third interlayer insulating layer ILD3, the second gate insulating layer GI2, the third buffer layer BUF3, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the first gate insulating layer Gl1. The first source electrode SE1 and the first drain electrode DE1 can be formed of one or an alloy of two or more of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or can be composed of multiple layers thereof, but are not limited thereto.

[0108] Each of the second source electrode SE2 and the second drain electrode DE2 can be electrically connected to the second active layer ACT2 through contact holes formed in the third interlayer insulating layer ILD3 and the second gate insulating layer GI2. The second source electrode SE2 and the second drain electrode DE2 can be formed of one or an alloy of two or more of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or can be composed of multiple layers thereof, but are not limited thereto.

[0109] The third conductive layer SD1 can extend to the side surfaces of a plurality of insulating layers provided below the third conductive layer SD1 and be connected to the connection line CL provided in the flexible region SA. For example, the third conductive layer SD1 can extend from the top surface of the third interlayer insulating layer ILD3 to the side surface of the third interlayer insulating layer ILD3, the side surface of the second gate insulating layer GI2, the side surface of the third buffer layer BUF3, the side surface of the second interlayer insulating layer ILD2, the side surface of the first interlayer insulating layer ILD1, the side surface of the first gate insulating layer GI1, and the side surface of the second buffer layer BUF2. The extended third conductive layer SD1 can be connected to the connection line CL provided on the first line pattern LP1. Therefore, the third conductive layer SD1 can be a conductive layer that electrically connects a plurality of connection lines CL and various lines provided on the first plate pattern PP1. The third conductive layer SD1 can be composed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof.

[0110] The first planarization layer PNL1 is disposed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, and the third conductive layer SD1. The first planarization layer PNL1 is disposed to cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, and the third conductive layer SD1. The first planarization layer PNL1 is an insulating layer for planarizing the upper portion of the first planarization layer PNL1 and protecting other components disposed below the first planarization layer PNL1. For example, the first planarization layer PNL1 may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but is not limited thereto.

[0111] A fourth conductive layer SD2 is disposed on the first planarization layer PNL1. The fourth conductive layer may be formed in a contact hole that penetrates the first planarization layer PNL1 to expose the second drain electrode DE2. The fourth conductive layer SD2 may be a connecting electrode that electrically connects the second transistor TR2 to the anode electrode AND through the contact hole formed by penetrating the first planarization layer PNL1. The fourth conductive layer SD2 may be formed of an alloy of one or two or more of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or may be composed of multiple layers thereof, but is not limited thereto.

[0112] A second planarization layer PNL2 is disposed on the fourth conductive layer SD2. The second planarization layer PNL2 is disposed to cover the fourth conductive layer SD2. The second planarization layer PNL2 is an insulating layer for planarizing the upper portion of the second planarization layer PNL2 and protecting other components disposed below the second planarization layer PNL2. For example, the second planarization layer PNL2 may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but is not limited thereto.

[0113] A light-emitting diode LD is disposed on the second planarization layer PNL2. The light-emitting diode LD includes an anode electrode AND, a light-emitting layer EML, and a cathode electrode CAD.

[0114] The anode electrode AND is disposed on the second planarization layer PNL2. The anode electrode AND may be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), for example, but is not limited thereto.

[0115] In addition, when the display device 100 according to the exemplary embodiment of the present disclosure is a top-emitting type, the anode electrode AND may further include a reflective layer formed of a metal material (such as aluminum (Al) or silver (Ag)) having excellent reflection efficiency, so that the light emitted from the light-emitting layer EML is reflected upward by the anode electrode AND, that is, toward the cathode electrode CAD. On the contrary, when the display device 100 is a bottom-emitting type, the anode may be formed only of a transparent conductive material.

[0116] The bank BNK covering a part of the anode electrode AND is provided on the second planarization layer PNL2. The bank BNK may be provided to cover a part of the edge of the anode electrode, and the part of the anode electrode AND exposed from the bank BNK may correspond to the light-emitting region. The bank BNK may be provided at the boundary between the plurality of sub-pixels SPX to prevent the light from each of the plurality of sub-pixels SPX from being mixed. In addition, the bank BNK may include at least one protrusion disposed adjacent to the outside of the rigid region RA. The bank BNK may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx) or an organic insulating material such as a benzocyclobutene (BCB)-based resin, an acrylic-based resin, or a polyimide. For example, the bank BNK may be formed of a black resin, but is not limited thereto.

[0117] The light-emitting layer EML is provided on the bank BNK and the anode electrode AND. The light-emitting layer EML may be in contact with a part of the anode electrode AND exposed from the bank BNK. In addition, at least a part of the light-emitting layer EML may overlap with the top surface of the protrusion of the bank BNK. The light-emitting layer EML may further include an organic material layer, such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0118] The cathode electrode CAD is provided on the light-emitting layer EML. The cathode electrode CAD supplies electrons to the light-emitting layer EML, and thus may be formed of a conductive material having a low work function. For example, the cathode electrode CAD may be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a ytterbium (Yb) alloy, and may further include a metal doping layer, but is not limited thereto.

[0119] An encapsulation layer is provided on the light-emitting diode LD. The encapsulation layer has a structure in which an inorganic encapsulation layer and an organic encapsulation layer are alternately stacked, and can protect the light-emitting diode LD to prevent moisture or oxygen from penetrating into the light-emitting diode LD. For example, the encapsulation layer may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film can block the penetration of moisture or oxygen. The organic film can planarize the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer EML. For example, the encapsulation layer includes a first inorganic encapsulation layer PAS1, a first organic encapsulation layer PCL1, and a second inorganic encapsulation layer PAS2 that are sequentially stacked.

[0120] The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are made of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (AlOx), etc., but are not limited thereto.

[0121] Each of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can completely cover the upper and side surfaces of the components provided in the rigid region RA. For example, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can cover the upper part of the light-emitting diode LD provided above the first plate pattern PP1. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are provided between the light-emitting diode LD and the first plate pattern PP1, and can cover the exposed side surfaces of the plurality of insulating layers and the third conductive layer SD1 provided on the side surfaces of the plurality of insulating layers. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can extend beyond the rigid region RA to a part of the flexible region SA.

[0122] The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can contact each other within the flexible region SA to seal the first organic encapsulation layer PCL1.

[0123] The first organic encapsulation layer PCL1 is provided between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The first organic encapsulation layer PCL1 can be formed thicker than each of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 to adsorb and block particles that may be generated during the manufacturing process of the display device 100. The first organic encapsulation layer PCL1 can fill the cracks that may appear in the first inorganic encapsulation layer PAS1, and cover the particles on the first inorganic encapsulation layer PAS1 to planarize its upper part. The first organic encapsulation layer PCL1 can be formed of an organic material such as an epoxy-based or acrylic-based polymer, but is not limited thereto.

[0124] In addition, the encapsulation layer is not limited to three layers. For example, it may include n layers in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked (where n is an integer greater than 3).

[0125] Next, a protective layer GET is provided on the side surface of the encapsulation layer to surround the encapsulation layer. The protective layer GET is provided to surround the side surface of the encapsulation layer, thereby protecting the light-emitting diode LD to prevent moisture or oxygen from penetrating into the light-emitting diode LD.

[0126] The protective layer GET may be provided to overlap with the bank portion BNK on a plurality of board patterns PP. In addition, the top surface of the encapsulation layer and the top surface of the protective layer GET may be in the same plane.

[0127] The protective layer GET may be provided to completely cover the ends of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 in the flexible region SA. Therefore, separation of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can be prevented.

[0128] The protective layer GET may be formed of a stretchable organic material. The organic material may include, for example, at least one of isoprene rubber (IR), polyurethane (PUR), chloroprene rubber (CR), acrylic rubber (ACM), epichlorohydrin rubber (ECO), and polydimethylsiloxane (PDMS), but is not limited thereto.

[0129] In addition, the protective layer GET may include a moisture-absorbing material. The moisture-absorbing material may include, for example, at least one of barium oxide (BaO), calcium oxide (CaO), magnesium oxide (MgO), magnesium sulfate (MgSO4), sodium oxide (Na2O), sodium sulfate (Na2SO4), lithium sulfate (LiSO), calcium sulfate (CaSO4), potassium oxide (K2O), lithium oxide (Li2O), gallium sulfate (GaS), calcium chloride (CaCl2), magnesium chloride (MgCl2), calcium bromide (CaBr2), cesium bromide (CsBr), vanadium pentabromide (VBr5), and calcium nitrate (Ca(NO3)2), but is not limited thereto. Therefore, the protective layer GET can absorb moisture that can penetrate from the outside, thereby protecting the light-emitting diode LD from moisture.

[0130] The light-emitting diodes inside the display device are formed of organic materials and are vulnerable to moisture and oxygen, thereby shortening their lifespan and reducing reliability. Specifically, when moisture or oxygen penetrates into the light-emitting diodes, various defects such as black spots, pixel shrinkage, and lifespan reduction may occur due to metal electrode oxidation, organic light-emitting layer deterioration, etc. Pixel shrinkage defect refers to the defect that the interface between the metal electrode and the organic light-emitting layer is oxidized or deteriorated due to moisture penetration, resulting in the edges of the pixels turning black. And when the pixel shrinkage defect persists for a long time, it may deteriorate into a black spot defect where the entire pixel area turns black, thus seriously affecting the reliability of the display device.

[0131] Therefore, the display device 100 according to an exemplary embodiment of the present disclosure includes a protective layer GET surrounding the side surface of the encapsulation layer. In this way, by setting the protective layer GET to surround each side portion of the plurality of plate patterns PP, the penetration of moisture or oxygen from the side direction of the plurality of plate patterns PP can be delayed. Therefore, the path for moisture or oxygen to penetrate into the light-emitting diode LD can be blocked. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, various defects caused by the penetration of moisture and oxygen can be prevented, and the reliability can be improved.

[0132] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, the protective layer GET further includes a moisture-absorbing material, so that the moisture or oxygen that can penetrate from the side surface can be absorbed by the protective layer GET. Therefore, the penetration of moisture or oxygen that may penetrate from the side surface into the light-emitting diode LD can be blocked more effectively.

[0133] In the display device 100 according to an exemplary embodiment of the present disclosure, the protective layer GET can be set to cover the end EPAS1 of the first inorganic encapsulation layer and the end EPAS2 of the second inorganic encapsulation layer. Therefore, the end EPAS1 of the first inorganic encapsulation layer and the end EPAS2 of the second inorganic encapsulation layer can be completely sealed, and the penetration of moisture or oxygen from the side surface can be further delayed.

[0134] In the display device 100 according to an exemplary embodiment of the present disclosure, the protective layer GET can be formed of a stretchable organic material. Therefore, even if the shape of the display device 100 changes freely, the display device 100 can be maintained without being damaged. In addition, even when the shape of the display device 100 is deformed, the penetration of moisture or oxygen into the light-emitting diode LD can be blocked.

[0135] Figure 4 is an enlarged plan view of the display area of a display device according to another exemplary embodiment of the present disclosure. Figure 5 is along Figure 4 the line V-V' in Figure 4 andFigure 5 The display device 500 and Figures 1 to 3 the display device 100 are different in the configuration of the protective layer GET, and other components are substantially the same. Therefore, redundant descriptions thereof will be omitted.

[0136] Referring to Figure 4 and Figure 5 , in the display device 500 according to another exemplary embodiment of the present disclosure, the protective layer GET may be set to overlap a part of the anode electrode AND of each of the plurality of light-emitting diodes LD. For example, the protective layer GET may be disposed on the bank BNK to overlap the bank BNK covering the end of the anode electrode AND. In this case, the top surface of the protective layer GET may be set to be higher than the top surface of the encapsulation layer.

[0137] In addition, the protective layer GET may overlap some of the plurality of transistors TR1 and TR2. Alternatively, the protective layer GET may overlap at least a part of at least one of the plurality of transistors TR1 and TR2. Figure 5 It shows that the protective layer GET overlaps with the second transistor TR2, but this is only an example and is not limited thereto.

[0138] In the display device 500 according to another exemplary embodiment of the present disclosure, the protective layer GET may include openings corresponding to the plurality of light-emitting regions on the bank. Therefore, the protective layer GET may be set not to overlap with the light-emitting regions. For example, in cross-section, the width of the opening may be greater than the width of the light-emitting region, but is not limited thereto. In this case, the light-emitting region may refer to the region between adjacent banks BNK disposed on the first planarization layer PNL1. For example, the light-emitting region may be a region where no bank BNK is provided.

[0139] Therefore, in the display device 500 according to another exemplary embodiment of the present disclosure, the protective layer GET may be set to surround each side of the plurality of plate patterns PP, so that moisture or oxygen permeation from the side surfaces of the plurality of plate patterns PP can be blocked or delayed. In addition, by setting the protective layer GET to overlap a part of the anode electrode AND, not only can moisture or oxygen permeation through the side surfaces of each of the plurality of plate patterns PP be blocked or delayed, but also moisture or oxygen permeation through the top surfaces of each of the plurality of plate patterns PP can be blocked or delayed.

[0140] In a display device 500 according to another exemplary embodiment of the present disclosure, on the encapsulation layer, the protective layer GET may not be provided in the region overlapping with the light-emitting region. Accordingly, when light emitted from the light-emitting region is emitted to the outside, interference caused by the protective layer GET that may be formed of an organic material can be prevented. Accordingly, according to another exemplary embodiment of the present disclosure, the light-emitting efficiency can be improved in the display device 500.

[0141] In addition, in a display device 500 according to another exemplary embodiment of the present disclosure, the end EPAS1 of the first inorganic encapsulation layer and the end EPAS2 of the second inorganic encapsulation layer can be completely sealed, and the penetration of moisture or oxygen can be further delayed.

[0142] In addition, in a display device 500 according to another exemplary embodiment of the present disclosure, even when the shape of the display device 500 is deformed, moisture or oxygen can be blocked from penetrating into the light-emitting diode LD.

[0143] Figure 6 is an enlarged plan view of a display area of a display device according to still another exemplary embodiment of the present disclosure. Figure 7 is along Figure 6 in the cross-sectional view taken along line VII-VII'. Figure 6 and Figure 7 The display device 700 of Figures 1 to 3 differs from the display device 100 of

[0144] in the configuration of the protective layer GET, and the other components are substantially the same, and thus, its redundant description will be omitted. Figure 6 and Figure 7, in a display device 700 according to another exemplary embodiment of the present disclosure, a protective layer GET may be provided to surround the side surface of the encapsulation layer. In addition, the protective layer GET may also be provided on a plurality of connection lines CL. For example, the protective layer GET may be provided to cover the entire top surface of each of the plurality of connection lines CL that connect adjacent board patterns PP among the plurality of board patterns PP. In addition, the protective layer GET surrounding the side surface of the encapsulation layer and the protective layer GET provided on the plurality of connection lines CL may be connected to each other. For example, the protective layer GET surrounding the side surface of the encapsulation layer and the protective layer GET provided on the plurality of connection lines CL may be formed of the same material. In this case, these protective layers GET may be integrated together. Or, the protective layer GET surrounding the side surface of the encapsulation layer and the protective layer GET provided on the plurality of connection lines CL may be formed of different materials. In addition, the top surface of the protective layer GET provided on the plurality of connection lines CL may be positioned in the same plane as the top surface of the encapsulation layer that is not covered by the protective layer GET. For example, the top surface of the protective layer GET provided on the first connection line CL1 may be positioned in the same plane as the top surface of the portion of the second inorganic encapsulation layer PAS2 that overlaps with the first organic encapsulation layer PCL1 and is not covered by the protective layer GET.

[0145] In addition, the protective layer GET and the plurality of connection lines CL may have the same shape and width in a plane. In addition, the protective layer GET may be provided to completely overlap the plurality of connection lines CL.

[0146] Therefore, the display device 700 according to still another exemplary embodiment of the present disclosure can block the paths through which moisture or oxygen penetrate laterally from each of the plurality of board patterns PP into the light-emitting diodes LD.

[0147] In addition, contact between moisture or oxygen and the connection lines CL can be blocked. Therefore, corrosion of the connection lines CL due to moisture or oxygen can be prevented. In addition, various defects that may occur due to corrosion of the connection lines CL can also be prevented or improved. Therefore, the reliability of the connection lines CL can be improved.

[0148] In addition, the display device 700 according to another exemplary embodiment of the present disclosure can completely seal the end EPAS1 of the first inorganic encapsulation layer and the end EPAS2 of the second inorganic encapsulation layer. Therefore, penetration of moisture or oxygen from the side surface can be further delayed.

[0149] In addition, in a display device 700 according to still another exemplary embodiment of the present disclosure, even when the shape of the display device 700 is deformed, moisture or oxygen can be blocked from penetrating into the plurality of light-emitting diodes LD or the plurality of connection lines CL without damaging the display device.

[0150] Figure 8It is an enlarged plan view of a display area of a display device according to still another exemplary embodiment of the present disclosure. Figure 9 is a cross-sectional view taken along line IX-IX’ in Figure 8 . Figure 8 and Figure 9 The display device 900 of Figure 4 and Figure 5 differs from the display device 500 of

[0151] in the configuration of the protective layer GET, and the other components are substantially the same. Therefore, redundant descriptions thereof will be omitted. Figure 8 and Figure 9 Referring to

[0152] In a display device 900 according to still another exemplary embodiment of the present disclosure, the protective layer GET may be disposed on the encapsulation layer to overlap a part of the anode electrode AND of each of the plurality of light-emitting diodes LD. In addition, the protective layer GET may also be disposed on the plurality of connection lines CL. For example, the protective layer GET may be disposed to cover the entire top surface of each of the plurality of connection lines CL that connect adjacent board patterns PP among the plurality of flexible board patterns PP. In this case, the top surface of the protective layer GET disposed on the plurality of connection lines CL may be higher than the top surface of the encapsulation layer on the plurality of board patterns PP. In addition, the top surface of the protective layer disposed on each of the plurality of board patterns PP and the top surface of the protective layer GET disposed on the plurality of connection lines CL may be in the same plane. The protective layer GET on the plurality of board patterns PP and the protective layer GET on the plurality of connection lines CL may be formed of the same material. In this case, these protective layers GET may be integrated together. Alternatively, the protective layer GET on the plurality of board patterns PP and the protective layer GET on the plurality of connection lines CL may be formed of different materials.

[0153] In addition, the protective layer GET and the plurality of connection lines CL may have the same shape and width in a plane. In addition, the protective layer GET may be disposed to completely overlap the plurality of connection lines CL.

[0154] In addition, the display device 900 according to another exemplary embodiment of the present disclosure may delay or block the penetration of moisture or oxygen into each of the plurality of connection lines CL. Accordingly, corrosion that may occur when moisture or oxygen penetrates and contacts each of the plurality of connection lines CL can be prevented. Accordingly, various defects that may occur in the plurality of connection lines CL can be prevented or improved.

[0155] In addition, the display device 900 according to another exemplary embodiment of the present disclosure may completely seal the end EPAS1 of the first inorganic encapsulation layer and the end EPAS2 of the second inorganic encapsulation layer. Accordingly, the penetration of moisture or oxygen from the side surface can be further delayed.

[0156] In addition, in the display device 900 according to another exemplary embodiment of the present disclosure, even when the shape of the display device 900 is deformed, moisture or oxygen can be blocked from penetrating into the plurality of light-emitting diodes LD or the plurality of connection lines CL without damaging the display device.

[0157] The exemplary embodiments of the present disclosure may also be described as follows:

[0158] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a light-emitting element disposed above the substrate; an encapsulation layer covering the light-emitting element; and a protective layer disposed to surround a side surface of the encapsulation layer.

[0159] According to an exemplary embodiment of the present disclosure, the protective layer is disposed to surround the light-emitting element.

[0160] According to an exemplary embodiment of the present disclosure, the display device further includes an insulating layer located between the light-emitting element and the substrate, and the encapsulation layer extends along a side surface of the insulating layer.

[0161] According to an exemplary embodiment of the present disclosure, the protective layer includes a moisture-absorbing material.

[0162] According to an exemplary embodiment of the present disclosure, the protective layer is formed of a stretchable organic material.

[0163] According to an exemplary embodiment of the present disclosure, the display device further includes: a pattern layer disposed on the substrate, the pattern layer including a plurality of plate patterns disposed in a rigid region and a plurality of line patterns disposed in a flexible region, wherein the plurality of line patterns connect the adjacent plate patterns to each other, and wherein the light-emitting element is disposed above the plurality of plate patterns.

[0164] According to an exemplary embodiment of the present disclosure, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are stacked in sequence, and each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends from the rigid region to the flexible region.

[0165] According to an exemplary embodiment of the present disclosure, the display device further includes an insulating layer that is located between the light-emitting element and the plurality of plate patterns, and the first inorganic encapsulation layer and the second inorganic encapsulation layer extend along the side surface of the insulating layer and are in contact with each other.

[0166] According to an exemplary embodiment of the present disclosure, the display device further includes: a plurality of connection lines that are disposed on a plurality of line patterns, wherein the plurality of connection lines electrically connect the pads on the plurality of plate patterns to each other, and the ends of the first inorganic encapsulation layer and the ends of the second inorganic encapsulation layer are disposed on the plurality of connection lines.

[0167] According to an exemplary embodiment of the present disclosure, the protective layer includes a first protective layer that is disposed in the rigid region and surrounds the side surface of the encapsulation layer, and a second protective layer that covers the plurality of connection lines and the ends of the first inorganic encapsulation layer and the ends of the second inorganic encapsulation layer.

[0168] According to an exemplary embodiment of the present disclosure, the first protective layer and the second protective layer are formed of the same material.

[0169] According to an exemplary embodiment of the present disclosure, the first protective layer and the second protective layer are formed of different materials.

[0170] According to an exemplary embodiment of the present disclosure, the top surface of the first protective layer and the top surface of the second protective layer are in the same plane.

[0171] According to an exemplary embodiment of the present disclosure, the top surface of the protective layer and the top surface of the encapsulation layer are in the same plane.

[0172] According to an exemplary embodiment of the present disclosure, the first protective layer is disposed to overlap a part of the anode electrode of the light-emitting element.

[0173] According to an exemplary embodiment of the present disclosure, the top surface of the protective layer is disposed higher than the top surface of the encapsulation layer.

[0174] According to an exemplary embodiment of the present disclosure, the second protective layer and the plurality of connection lines have the same shape and width in a plane.

[0175] According to an exemplary embodiment of the present disclosure, the plurality of plate patterns are disposed in the form of islands spaced apart from each other.

[0176] According to an exemplary embodiment of the present disclosure, the plurality of line patterns have a curved shape.

[0177] According to an exemplary embodiment of the present disclosure, the display device further includes: a bank portion that covers a part of the anode electrode of the light-emitting element, and the protective layer includes an opening corresponding to the other part of the anode electrode exposed from the bank portion.

[0178] According to an exemplary embodiment of the present disclosure, the bank portion is configured to have a stepped structure.

[0179] According to an exemplary embodiment of the present disclosure, the encapsulation layer extends along a side surface of the bank portion having the stepped structure.

[0180] According to an exemplary embodiment of the present disclosure, a width of the opening is greater than a width of the other part of the anode electrode exposed from the bank portion.

[0181] According to an exemplary embodiment of the present disclosure, the substrate includes a first substrate and a second substrate, and a first buffer layer is disposed between the first substrate and the second substrate.

[0182] According to an exemplary embodiment of the present disclosure, the display device further includes: a second buffer layer disposed on the plurality of plate patterns, and the plurality of plate patterns are disposed on the second substrate.

[0183] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

[0184] Cross-reference to Related Applications

[0185] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0196690, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is hereby expressly incorporated herein for all purposes.

Claims

1. A display device, comprising: substrate; A light emitting element, wherein the light emitting element is disposed above the substrate; An encapsulation layer, wherein the encapsulation layer covers the light-emitting element; as well as A protection layer is provided to surround a side surface of the encapsulation layer.

2. The display device according to claim 1, wherein: The protection layer is disposed to surround the light emitting element. 3 . The display device according to claim 1 , further comprising an insulating layer, wherein the insulating layer is located between the light emitting element and the substrate, and the encapsulation layer extends along a side surface of the insulating layer.

4. The display device according to claim 1, wherein: The protective layer includes a hygroscopic material.

5. The display device according to claim 1, wherein: The protective layer is formed of a stretchable organic material.

6. The display device according to claim 1, further comprising: a pattern layer, the pattern layer being disposed on the substrate, the pattern layer comprising a plurality of plate patterns disposed in a rigid region and a plurality of line patterns disposed in a flexible region, wherein the plurality of line patterns connect the plate patterns adjacent to each other, and Wherein, the light emitting element is arranged above the plurality of plate patterns.

7. The display device according to claim 6, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence, and Wherein, each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends from the rigid region to the flexible region. 8 . The display device of claim 7 , further comprising an insulating layer between the light emitting element and the plurality of plate patterns, the first inorganic encapsulation layer and the second inorganic encapsulation layer extending along a side surface of the insulating layer and contacting each other.

9. The display device according to claim 7, further comprising: a plurality of connection lines, the plurality of connection lines being arranged on a plurality of line patterns, wherein the plurality of connection lines electrically connect the pads on the plurality of board patterns to each other, and Wherein, an end portion of the first inorganic encapsulation layer and an end portion of the second inorganic encapsulation layer are arranged on the plurality of connection lines.

10. The display device according to claim 9, wherein: The protective layer includes a first protective layer disposed in the rigid region and surrounding a side surface of the encapsulation layer, and a second protective layer covering the plurality of connection lines and ends of the first inorganic encapsulation layer and ends of the second inorganic encapsulation layer.

11. The display device according to claim 10, wherein: The first protection layer and the second protection layer are formed of the same material.

12. The display device according to claim 10, wherein: The first protection layer and the second protection layer are formed of different materials.

13. The display device according to claim 10, wherein: A top surface of the first protection layer and a top surface of the second protection layer are located on the same plane.

14. The display device according to claim 10, wherein: A top surface of the protection layer and a top surface of the encapsulation layer are located on the same plane.

15. The display device according to claim 10, wherein: The first protective layer is disposed to overlap a portion of the anode electrode of the light emitting element.

16. The display device according to claim 15, wherein: A top surface of the protection layer is disposed to be higher than a top surface of the encapsulation layer.

17. The display device according to claim 10, wherein: The second protection layer and the plurality of connection lines have the same shape and width on a plane.

18. The display device according to claim 6, wherein: The plurality of plate patterns are arranged in the form of islands spaced apart from each other.

19. The display device according to claim 6, wherein: The plurality of line patterns have a bent shape.

20. The display device according to claim 1, further comprising: a bank portion covering a portion of an anode electrode of the light emitting element, The protection layer includes an opening corresponding to another portion of the anode electrode exposed from the bank.

21. The display device according to claim 20, wherein: The bank is configured to have a stepped structure.

22. The display device according to claim 21, wherein: The encapsulation layer extends along a side surface of the bank having the stepped structure.

23. The display device according to claim 20, wherein: The opening has a width greater than a width of the other portion of the anode electrode exposed from the bank.

24. The display device according to claim 6, wherein: The substrate includes a first substrate and a second substrate, and Wherein, the first buffer layer is arranged between the first substrate and the second substrate.

25. The display device according to claim 24, further comprising: a second buffer layer disposed on the plurality of plate patterns, and Wherein, the plurality of plate patterns are arranged on the second substrate.

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