Display device

Abstract

The present disclosure provides a display device including a first light-emitting layer including a first host in an optical region provided with low-resolution pixels, and a second light-emitting layer including a second host different from the first host, the display device is capable of reducing a brightness difference between a region in which low-resolution pixels are provided and a region in which high-resolution pixels are provided.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of Korean Patent Application No. 10 - 2023 - 0195629, filed with the Korean Intellectual Property Office on December 28, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to an electronic device having a display, and more particularly, to a display device. Background art

[0004] As display technology has evolved to provide increased functionality, display devices can provide an image capture function, a sensing function, etc., as well as an image display function.

[0005] To provide such functions, a display device may need to include optoelectronic devices such as a light - receiving device, a camera, a sensor for detecting an image, etc.

[0006] To receive light passing through the front surface of the display device, it may be desirable for such optoelectronic devices to be located in an area where incident light from the front of the display device can be more received and detected.

[0007] To achieve the foregoing purpose, in a display device, optoelectronic devices have been designed to be located at the front of the display device so that cameras, sensors, etc., which are optoelectronic devices, can be more exposed to incident light.

[0008] To install optoelectronic devices in the display device in this way, the bezel area of the display device may increase, or it may be necessary to form a notch or a hole in the display area of the associated display panel.

[0009] Therefore, even when optoelectronic devices (e.g., cameras, sensors, etc.) that receive or detect incident light and perform a predetermined function are attached to the display device, it may be desirable for the display device to have a higher transmittance to perform the intended function. Summary of the invention

[0010] To achieve a full - screen in a display device, the following solution may be provided: allocate an area for low - resolution pixels in the screen area of the display panel, and set a camera and / or various sensors in an area of the display device that is located below the display panel and opposite to the area where the low - resolution pixels are set.

[0011] However, since pixels still exist in the area where low - resolution pixels are set and the corresponding light - emitting area becomes smaller, it may be necessary to drive a current more than 1.5 times that required for driving low - resolution pixels to maintain the same brightness.

[0012] As the required current amount increases, the lifespan of the pixels may decrease. Accordingly, as time passes, the brightness difference between the region where low-resolution pixels are provided and the region where high-resolution pixels are provided may become large, and thus the boundary of the region where low-resolution pixels are provided may be clearly recognized.

[0013] To solve these problems, the inventors of the present disclosure invented a display device that can reduce the brightness difference between the region where low-resolution pixels are provided and the region where high-resolution pixels are provided even when the low-resolution pixels are used for a long time by increasing the lifespan of the low-resolution pixels.

[0014] One or more aspects of the present disclosure may provide a display device that can reduce the brightness difference between the region where low-resolution pixels are provided and the region where high-resolution pixels are provided.

[0015] According to one or more example embodiments of the present disclosure, a display device may include: a substrate including a normal region and an optical region, the normal region being configured to have a plurality of first pixels provided therein and being configured to have a first resolution, the optical region being configured to have a plurality of second pixels provided therein and being configured to have a second resolution lower than the first resolution; a first electrode layer located on the substrate; a first light-emitting layer located on the first electrode layer and including a first host in the normal region and the optical region; a second light-emitting layer located on the first light-emitting layer, including the first host in the normal region, and including a second host different from the first host in the optical region; and a second electrode layer located on the second light-emitting layer.

[0016] According to one or more example embodiments of the present disclosure, a display device may include: a normal region in which a plurality of first sub-pixels are provided; and an optical region in which a plurality of second sub-pixels are provided, wherein the number of the plurality of second sub-pixels per unit area in the optical region is less than the number of the plurality of first sub-pixels per unit area in the normal region, wherein each of the plurality of first sub-pixels in the normal region and the plurality of second sub-pixels in the optical region includes a light-emitting element, wherein the light-emitting element includes: a first electrode layer located on a substrate; one or more stacked layers; and a second electrode layer located on the one or more stacked layers, wherein each of the one or more stacked layers includes: a first light-emitting layer located on the first electrode layer and including a first host in the normal region and the optical region; and a second light-emitting layer located on the first light-emitting layer, including the first host in the normal region, and including a second host different from the first host in the optical region.

[0017] According to one or more aspects of the present disclosure, a display device can be provided that can reduce the luminance difference between an area provided with low-resolution pixels and an area provided with high-resolution pixels, thereby enabling low-power operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present disclosure includes drawings to provide a further understanding of the present disclosure. The drawings are incorporated into and constitute a part of the present disclosure. The drawings illustrate various aspects of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0019] Figure 1 is a plan view of an exemplary display device according to an aspect of the present disclosure;

[0020] Figure 2 illustrates an exemplary system configuration of a display device according to an aspect of the present disclosure;

[0021] Figure 3 illustrates an exemplary equivalent circuit of sub-pixels in a display panel according to an aspect of the present disclosure;

[0022] Figure 4 illustrates the arrangement of sub-pixels in three exemplary regions included in a display area of a display device according to an aspect of the present disclosure;

[0023] Figure 5 and Figure 6 is a cross-sectional view of an exemplary light-emitting element included in a display device according to an aspect of the present disclosure;

[0024] Figure 7A and Figure 7B are cross-sectional views of exemplary light-emitting elements provided in a normal region and an optical region of a display device according to an aspect of the present disclosure;

[0025] Figures 8A to 8C illustrates the triplet energy levels of an exemplary light-emitting element included in a display device according to an aspect of the present disclosure;

[0026] Figures 9A to 9D is a graph showing the evaluation results of an exemplary light-emitting element manufactured according to an exemplary embodiment of the present disclosure; and

[0027] Figures 10A to 10D is a graph showing the evaluation results of another light-emitting element manufactured according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

[0029] In the following description, the structures, embodiments, implementations, methods, and operations described herein are not limited to the specific examples or embodiments set forth herein and may be varied as known in the art, unless otherwise specified. The same reference numerals denote the same elements throughout the text, unless otherwise indicated. The names of the respective elements used in the following description are chosen only for convenience in writing the specification and may thus be different from the names used in actual products. The advantages and features of the present disclosure and methods of achieving the same will be elucidated by example embodiments described below with reference to the drawings. However, the present disclosure may be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure may be sufficiently thorough and complete to enable those of ordinary skill in the art to fully understand the scope of the present disclosure. Additionally, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of related known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of the present disclosure. The shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings are given by way of example only. Accordingly, the present disclosure is not limited to the illustrations in the drawings. When using terms such as "comprising," "having," "including," "containing," "constituting," "composing," "forming," etc., one or more other elements may be added, unless a term such as "only" is used. An element described in the singular is intended to include a plurality of elements, and vice versa, unless the context clearly indicates otherwise

[0030] Although terms such as "first," "second," "A," "B," "(a)," "(b)," etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms, since these terms are not used to define a specific order or priority. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] When referring to a first element being "connected or coupled to" a second element, "contacting or overlapping" the second element, etc., it should be construed that not only can the first element be "directly connected or coupled to" the second element or "directly contacting or overlapping" the second element, but also a third element may be "interposed" between the first element and the second element, or the first element and the second element may be "connected or coupled," "contacting or overlapping," etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled," "contacting or overlapping," etc. with each other.

[0032] In the case of describing positional relationships, for example, in the case of using terms such as "on", "above", "under", "upper part", "next to", "adjacent to", etc. to describe the positional relationship between two parts, one or more other parts may be located between these two parts, unless more restrictive terms such as "immediately", "directly", or "closely" are used. For example, in the case where one element or layer is disposed "on" another element or layer, a third element or layer may be interposed therebetween. In addition, terms such as "left", "right", "top", "bottom", "downward", "upward", "on", "under", etc. refer to any reference system.

[0033] In addition, when referring to any dimensions, relative sizes, etc., it should be considered that even if the relevant description is not specified, the numerical values or corresponding information of the elements or features (e.g., horizontal, range, etc.) also include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Additionally, the term "may" fully includes all meanings of the term "can".

[0034] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a plan view of an exemplary display device 100 according to an aspect of the present disclosure.

[0036] Referring to Figure 1 , in one or more exemplary embodiments, the display device 100 may include a display panel 110 for displaying an image and one or more optoelectronic devices 11 and / or 12. Here, the optoelectronic device may be referred to as a photodetector, a photoreceiver, or a photosensing device. The optoelectronic device may include one or more of a camera, a camera lens, a sensor, a sensor for detecting an image, etc.

[0037] The display panel 110 may include a display area DA configured to be able to display one or more images and a non-display area NDA where no image is displayed.

[0038] A plurality of sub-pixels may be provided in the display area DA, and several types of signal lines for driving the plurality of sub-pixels may be provided in the display area DA.

[0039] The non-display area NDA may refer to the area outside the display area DA.

[0040] Several types of signal lines may be provided in the non-display area NDA, and several types of driving circuits may be connected to the non-display area NDA.

[0041] At least a part of the non-display area NDA may be bent so as to be invisible from the front of the display device 100 or may be covered by a housing or enclosure (not shown) of the display device 100.

[0042] The non-display area NDA may also be referred to as a border or a border area.

[0043] Referring Figure 1 to, in one or more aspects, one or more optoelectronic devices 11 and / or 12 included in the display device 100 may be located below or at the lower part (the opposite side of the viewing surface) of the display panel 110.

[0044] Light may enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optoelectronic devices 11 and / or 12 located below or at the lower part (the opposite side of the viewing surface) of the display panel 110.

[0045] One or more optoelectronic devices 11 and / or 12 may be devices capable of receiving or detecting the light passing through the display panel 110 and performing a predetermined function based on the received light.

[0046] For example, one or more optoelectronic devices 11 and / or 12 may include one or more of the following: an image capture device such as a camera (image sensor); or a sensor such as a proximity sensor, an illuminance sensor, etc.

[0047] For example, the illuminance sensor may be an ambient light sensor, but the exemplary embodiments of the present disclosure are not limited thereto.

[0048] In a state where the display device 100 is turned off, the display device 100 may use the illuminance sensor to detect the ambient light and adjust the brightness of the image on the screen displayed through the display panel 110 based on the brightness of the ambient light.

[0049] Referring Figure 1 to, in one or more aspects, the display area DA defined in the display panel 100 may include a normal area NA and one or more optical areas OA1 and / or OA2. Here, the term "normal area" NA may be an area that exists in the display area DA but does not overlap with one or more optoelectronic devices 11 and / or 12. The normal area NA may also be referred to as a non-optical area.

[0050] Referring Figure 1 to, one or more optical areas OA1 and / or OA2 may be one or more areas that respectively overlap with one or more optoelectronic devices 11 and / or 12.

[0051] According to Figure 1 an example of, the display area DA may include a normal area NA, a first optical area OA1, and a second optical area OA2.

[0052] In Figure 1In the example, a part of the normal area NA can be present between the first optical area OA1 and the second optical area OA2.

[0053] Although Figure 1 The structure is shown in which each of the first optical area OA1 and the second optical area OA2 has a circular shape, but the respective shapes of the first optical area OA1 and the second optical area OA2 according to the exemplary embodiments of the present disclosure are not limited thereto.

[0054] In one or more aspects, the first optical area OA1 can have various shapes, such as circular, oval, quadrilateral, hexagonal, octagonal, etc.

[0055] In one or more aspects, the second optical area OA2 can have various shapes, such as circular, oval, quadrilateral, hexagonal, octagonal, etc.

[0056] The first optical area OA1 and the second optical area OA2 can have the same or substantially the same or nearly the same shape, or different shapes.

[0057] Hereinafter, for convenience of description, discussion is made based on the example in which each of the first optical area OA1 and the second optical area OA2 has a circular shape. However, it should be understood that the scope of the present disclosure includes examples in which at least one of the first optical area OA1 and the second optical area OA2 has a shape other than a circular shape.

[0058] In this example, at least a part of the first optical area OA1 can overlap with the first optoelectronic device 11, and at least a part of the second optical area OA2 can overlap with the second optoelectronic device 12.

[0059] In one or more aspects, one or more optical areas OA1 and / or OA2 included in the display panel 110 or the display device 100 need to be configured with both an image display structure and a light transmission structure.

[0060] For example, since one or more optical areas OA1 and / or OA2 are respective parts of the display area DA, sub-pixels for displaying an image are desirably provided in one or more optical areas OA1 and / or OA2.

[0061] In addition, in order for the light entering the display panel 110 or the display device 100 to reach one or more optoelectronic devices 11 and / or 12, it is also desirable that each of one or more optical areas OA1 and / or OA2 be configured with a light transmission structure.

[0062] It should be noted that even if one or more optoelectronic devices 11 and / or 12 are devices that need to receive light, one or more optoelectronic devices 11 and / or 12 can be located on the back surface of the display panel 110 (e.g., on the opposite side of its viewing surface). Therefore, one or more optoelectronic devices 11 and / or 12 can receive the light that has passed through the display panel 110.

[0063] For example, one or more optoelectronic devices 11 and / or 12 may not be exposed on the front surface (viewing surface) of the display panel 110 or the display device 100.

[0064] Therefore, when a user observes the front surface of the display device 110, one or more optoelectronic devices 11 and / or 12 are arranged such that they are invisible to the user.

[0065] The first optoelectronic device 11 can be, for example, a camera, and the second optoelectronic device 12 can be, for example, a sensor. The sensor can be a proximity sensor, an illuminance sensor, an infrared sensor, etc.

[0066] In one or more aspects, the camera can be a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor, and the sensor can be an infrared sensor capable of detecting infrared light.

[0067] In one or more aspects, the first optoelectronic device 11 can be a sensor, and the second optoelectronic device 12 can be a camera.

[0068] Hereinafter, for ease of description, discussion will be based on an example where the first optoelectronic device 11 is a camera and the second optoelectronic device 12 is a sensor. However, it should be understood that the scope of the present disclosure includes examples where the first optoelectronic device 11 is a sensor and the second optoelectronic device 12 is a camera.

[0069] The camera can be, for example, a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor.

[0070] In an example where the first optoelectronic device 11 is a camera, the camera can be located on the back surface (e.g., below or at the lower part) of the display panel 110, and can be a front camera capable of photographing an object or an image in the front direction of the display panel 110.

[0071] Therefore, the user can photograph an image or an object that is invisible on the viewing surface through the camera while observing the viewing surface of the display panel 110.

[0072] Although the normal area NA and one or more optical areas OA1 and / or OA2 included in the display area DA are areas configured to be capable of displaying images, the normal area NA may be an area where it is not necessary to implement a light transmission structure, while one or more optical areas OA1 and / or OA2 may be areas where it is necessary to implement a light transmission structure. Thus, in one or more aspects, the normal area NA may be an area where a light transmission structure is not implemented or not included, and one or more optical areas OA1 and / or OA2 may be areas where a light transmission structure is implemented or included.

[0073] Therefore, one or more optical areas OA1 and / or OA2 may have a transmittance greater than or equal to a predetermined level, that is, a relatively high transmittance, while the normal area NA may have a transmittance less than the predetermined level or no light transmittance.

[0074] For example, one or more optical areas OA1 and / or OA2 may have a different resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, line arrangement structure, etc. from the normal area NA.

[0075] For example, the number of sub-pixels per unit area in one or more optical areas OA1 and / or OA2 may be less than the number of sub-pixels per unit area in the normal area NA.

[0076] For example, the resolution of one or more optical areas OA1 and / or OA2 may be lower than the resolution of the normal area NA.

[0077] Here, the number of sub-pixels per unit area may be a unit for measuring resolution. For example, it is called pixels (or sub-pixels) per inch (PPI), which represents the number of pixels (or sub-pixels) within 1 inch.

[0078] For example, the number of sub-pixels per unit area in the first optical area OA1 may be less than the number of sub-pixels per unit area in the normal area NA.

[0079] For example, the number of sub-pixels per unit area in the second optical area OA2 may be greater than or equal to the number of sub-pixels per unit area in the first optical area OA1.

[0080] Here, in an example where the display device 100 has a structure in which a first optoelectronic device 11 such as a camera is located below or at the lower part of the display panel 100 and is not exposed to the outside, such a display device 100 may be referred to as a display applying under-display camera (UDC) technology.

[0081] According to these examples, since there is no need to form a notch or a camera hole for exposing the camera in the display panel 110, the display device 100 can have the advantage of avoiding a reduction in the size of the display area DA.

[0082] In fact, since there is no need to form a notch or a camera hole for exposing the camera in the display panel 110, the display device 100 can further have the advantages of reducing the size of the bezel area and increasing the design freedom due to the elimination of this limitation on the design.

[0083] Although one or more optoelectronic devices 11 and / or 12 are located on the back surface of the display panel 110 of the display device 100 (e.g., below it, or at its lower part) (e.g., hidden or not exposed to the outside), one or more optoelectronic devices 11 and / or 12 are required to perform a predetermined function by normally receiving or detecting light.

[0084] In addition, in the display device 100, although one or more optoelectronic devices 11 and / or 12 are located on the back surface of the display panel 110 (e.g., below it, or at its lower part) to be hidden and located at a position overlapping with the display area DA, it is necessary to normally perform image display in one or more optical areas OA1 and / or OA2 overlapping with one or more optoelectronic devices 11 and / or 12 in the display area DA. Therefore, in one or more examples, even if one or more optoelectronic devices 11 and / or 12 are located on the back surface of the display panel, images can be displayed in a normal manner (e.g., without degrading the image quality) in one or more optical areas OA1 and / or OA2 overlapping with one or more optoelectronic devices 11 and / or 12 in the display area DA.

[0085] Figure 2 An example system configuration of the display device 100 according to an aspect of the present disclosure is shown.

[0086] Referring to Figure 2 , the display device 100 may include a display panel 110 and a display driving circuit as components for displaying one or more images.

[0087] The display driving circuit may be a circuit for driving the display panel 110, and includes a data driving circuit 220, a gate driving circuit 230, a display controller 240, and other circuit components.

[0088] The display panel 110 may include a display area DA configured to be able to display one or more images and a non-display area NDA where no image is displayed.

[0089] The non-display area NDA may be an area outside the display area DA, and may also be referred to as an edge area or a bezel area.

[0090] All or a part of the non-display area NDA may be an area visible from the front of the display device 100, or may be a curved area and not visible from the front of the display device 100.

[0091] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP provided on the substrate SUB.

[0092] The display panel 110 may further include various types of signal lines for driving the plurality of sub-pixels SP.

[0093] In one or more aspects, the display device 100 may be a liquid crystal display device or the like, or a self-luminous display device in which light is emitted from the display panel 210 itself.

[0094] In an example where the display device 100 is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0095] For example, the display device 100 according to an aspect of the present disclosure may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to implement the light-emitting element ED.

[0096] In another example, the display device 100 according to an aspect of the present disclosure may be an inorganic light-emitting display device that uses a light-emitting diode based on an inorganic material to implement the light-emitting element.

[0097] In still another example, the display device 100 according to an aspect of the present disclosure may be a quantum dot display device that uses quantum dots (which are self-luminous semiconductor crystals) as light-emitting elements.

[0098] The structure of each of the plurality of sub-pixels SP may be configured or designed differently according to the type of the display device 100.

[0099] In an example where the display device 100 is a self-luminous display device including self-luminous sub-pixels SP, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, and one or more capacitors.

[0100] Various types of signal lines may include, for example, a plurality of data lines DL for carrying data signals (which may be referred to as data signals or image signals), a plurality of gate lines GL for carrying gate signals (which may be referred to as scan signals), and the like.

[0101] The plurality of data lines DL and the plurality of gate lines GL may cross each other.

[0102] Each of the plurality of data lines DL may be configured to extend in a first direction.

[0103] Each of the plurality of gate lines GL may be configured to extend in a second direction.

[0104] For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction.

[0105] For another example, the first direction may be a row direction or a horizontal direction, and the second direction may be a column direction or a vertical direction.

[0106] The data driving circuit 220 may be a circuit for driving the plurality of data lines DL, and may supply data signals to the plurality of data lines DL.

[0107] The gate driving circuit 230 may be a circuit for driving the plurality of gate lines GL, and may supply gate signals to the plurality of gate lines GL.

[0108] The display controller 240 may be a device for controlling the data driving circuit 220 and the gate driving circuit 230, and may control the driving times of the plurality of data lines DL and the driving times of the plurality of gate lines GL.

[0109] The display controller 240 may supply a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220, and supply a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230.

[0110] The display controller 240 may receive input image data from the host system 250 and supply image data Data based on the input image data to the data driving circuit 220.

[0111] The data driving circuit 220 may control the supply of data signals to the plurality of data lines DL according to the driving timing of the display controller 240.

[0112] The data driving circuit 220 may receive digital image data Data from the display controller 240, convert the received image data Data into an analog data signal, and output the obtained analog data signal to the plurality of data lines DL.

[0113] The gate driving circuit 230 may supply gate signals to the plurality of gate lines GL according to the timing control of the display controller 240.

[0114] The gate driving circuit 230 may receive a first gate voltage corresponding to a conduction level voltage and a second gate voltage corresponding to a cut-off level voltage, as well as various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0115] In one or more aspects, the data driving circuit 220 can be connected to the display panel 210 through tape automated bonding (TAB) technology, or to a conductive pad (e.g., a bonding pad) of the display panel 210 through chip on glass (COG) technology or chip on panel (COP) technology, or to the display panel 210 through chip on film (COF) technology.

[0116] In one or more aspects, the gate driving circuit 230 can be connected to the display panel 110 through tape automated bonding (TAB) technology, or to a conductive pad (e.g., a bonding pad) of the display panel 110 through chip on glass (COG) technology or chip on panel (COP) technology, or to the display panel 110 through chip on film (COF) technology.

[0117] In one or more aspects, the gate driving circuit 230 can be disposed in the non-display area NDA of the display panel 110 through gate in panel (GIP) technology.

[0118] The gate driving circuit 230 can be disposed on a substrate or connected to a substrate.

[0119] In an example where the gate driving circuit 230 is implemented by GIP technology, the gate driving circuit 230 can be disposed in the non-display area NDA of the substrate SUB.

[0120] In an example where the gate driving circuit 230 is implemented by chip on glass (COG) technology, chip on film (COF) technology, etc., the gate driving circuit 230 can be connected to the substrate SUB.

[0121] In one or more aspects, at least one of the data driving circuit 220 and the gate driving circuit 230 can be disposed in the display area DA of the display panel 110.

[0122] For example, at least one of the data driving circuit 220 and the gate driving circuit 230 can be configured not to overlap with the sub-pixel SP, or to overlap with one or more or all of the sub-pixels SP, or to overlap with at least one or more parts of at least one or more sub-pixels.

[0123] The data driving circuit 220 can be disposed on and / or electrically connected to one side or part (e.g., the upper edge or the lower edge) of the display panel 110, but is not limited thereto.

[0124] In one or more aspects, the data driving circuit 220 can be located on and / or electrically connected to at least two sides (e.g., the upper edge and the lower edge) of the display panel 110 or two sides of four sides (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110 according to a driving scheme, a panel design scheme, etc., but is not limited thereto.

[0125] The gate driving circuit 230 may be located at and / or electrically connected to one side or part (e.g., the left edge or the right edge) of the display panel 110, but is not limited thereto.

[0126] In one or more aspects, the gate driving circuit 230 may be located at and / or electrically connected to two sides or parts (e.g., the left edge and the right edge) of the panel 110 or at least two of the four sides or parts (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110 according to a driving scheme, a panel design scheme, etc., but is not limited thereto.

[0127] The display controller 240 may be implemented as a component separate from the data driving circuit 220, or incorporated in the data driving circuit 220 and thus implemented as an integrated circuit.

[0128] The display controller 240 may be a timing controller used in conventional display technologies, or a controller or control device capable of performing other control functions in addition to the functions of a conventional timing controller. In one or more embodiments, the display controller 140 may be a controller or control device different from a timing controller, or may be a circuit or component included in a controller or control device.

[0129] The display controller 240 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, etc.

[0130] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, etc. and electrically connected to the gate driving circuit 230 and the data driving circuit 220 through a printed circuit board, a flexible printed circuit, etc.

[0131] The display controller 240 may send signals to the data driving circuit 220 via one or more predefined interfaces, and receive signals from the data driving circuit 220 via one or more predefined interfaces.

[0132] For example, such an interface may include a low voltage differential signal (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc.

[0133] In one or more aspects, in order to further provide a touch sensing function and an image display function, the display device 100 may include at least one touch sensor, and a touch sensing circuit capable of detecting the occurrence of a touch event of a touch object such as a finger, a pen, etc. or detecting a corresponding touch position (or touch coordinate) by sensing the touch sensor.

[0134] The touch sensing circuit may include a touch driving circuit 260 capable of generating and providing touch sensing data by driving and sensing a touch sensor, a touch controller 270 capable of detecting the occurrence of a touch event or detecting a touch position (or touch coordinates) using the touch sensing data, and one or more other components.

[0135] The touch sensor may include a plurality of touch electrodes.

[0136] The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit 260.

[0137] The touch sensor may be implemented in the form of a touch panel located outside the display panel 110 or integrated inside the display panel 110.

[0138] In an example where the touch sensor is implemented in the form of a touch panel located outside the display panel 110, such a touch sensor may be referred to as an external type.

[0139] In an example where an external type touch sensor is provided in the display device 100, the touch panel and the display panel 110 may be separately manufactured and combined in an assembly process.

[0140] The external type touch panel may include a touch panel substrate and a plurality of touch electrodes provided on the touch panel substrate.

[0141] In an example where the touch sensor is integrated inside the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0142] The touch driving circuit 260 may supply a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0143] The touch sensing circuit may perform touch sensing through self - capacitance sensing technology or mutual - capacitance sensing technology.

[0144] In an example where the touch sensing circuit performs touch sensing through self - capacitance sensing technology, the touch sensing circuit may perform touch sensing based on the capacitance between one or more touch electrodes and an object such as a finger or a pen.

[0145] According to the self - capacitance sensing technology, each of the plurality of touch electrodes may be used as a driving touch electrode and a sensing touch electrode simultaneously.

[0146] The touch driving circuit 260 may drive all or one or more of the plurality of touch electrodes and sense all or one or more of the plurality of touch electrodes.

[0147] In an example where a touch sensing circuit performs touch sensing through mutual capacitance sensing technology, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes.

[0148] According to the mutual capacitance sensing technology, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes.

[0149] The touch driving circuit 260 may drive the driving touch electrodes and sense the sensing touch electrodes.

[0150] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or a single device.

[0151] In addition, the touch driving circuit 260 and the data driving circuit 220 may be implemented as separate devices or a single device.

[0152] The display device 100 may further include a power supply circuit for supplying various types of power to the display driving circuit and / or the touch sensing circuit.

[0153] In some aspects, the display device 100 may be a mobile terminal such as a smart phone, a tablet computer, etc., or a display, a television (TV), etc. Such devices may be configured in various types, sizes, and shapes. The display device 100 according to the aspects of the present disclosure is not limited thereto, and may include various types, sizes, and shapes configured to display information or images.

[0154] As described above, as Figure 1 shown, the display area DA of the display panel 110 may include a normal area NA and one or more optical areas OA1 and / or OA2.

[0155] The normal area NA and the one or more optical areas OA1 and / or OA2 may be areas configured to be able to display images.

[0156] It should be noted that the normal area NA may be an area where it is not necessary to implement a light transmission structure, and the one or more optical areas OA1 and / or OA2 may be areas where it is necessary to implement a light transmission structure.

[0157] As discussed above, although the display area DA of the display panel 110 may include one or more optical areas OA1 and / or OA2 and the normal area NA, for the sake of convenience of description, the following discussion is provided based on an example where the display area DA includes both the first optical area OA1 and the second optical area OA2.

[0158] Figure 3 An example equivalent circuit of a sub-pixel SP in the display panel 110 according to an aspect of the present disclosure is shown.

[0159] Each sub-pixel SP provided in the normal area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA of the display panel 110 may include a light-emitting element ED, a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT for transferring a data voltage Vdata to a first node N1 of the driving transistor DRT, a storage capacitor Cst for maintaining a voltage at an approximately constant level during one frame, and the like.

[0160] The driving transistor DRT may include a first node N1 to which a data voltage is applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which a driving voltage ELVDD transmitted through a driving voltage line DVL is applied.

[0161] In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0162] The light-emitting element ED may include a first electrode layer AE, a light-emitting layer EL, and a second electrode layer CE.

[0163] The first electrode layer AE may be a pixel electrode provided in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP.

[0164] The second electrode layer CE may be a common electrode provided in all or part of a plurality of sub-pixels SP. For example, a base voltage ELVSS may be applied to the second electrode layer CE.

[0165] For example, the first electrode layer AE may be a pixel electrode, and the second electrode layer CE may be a common electrode.

[0166] For another example, the first electrode layer AE may be a common electrode, and the second electrode layer CE may be a pixel electrode.

[0167] Hereinafter, for the sake of convenience of explanation, a discussion will be made based on an example in which the first electrode layer AE is a pixel electrode and the second electrode layer CE is a common electrode.

[0168] In one or more aspects, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot (QD) light-emitting element.

[0169] In an example where the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL of the light-emitting element ED may include an organic light-emitting layer containing an organic material.

[0170] The scan transistor SCT can be turned on and off by a scan signal SCAN (which is a gate signal applied through the gate line GL), and is electrically connected between the first node N1 of the driving transistor DRT and the data line DL.

[0171] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0172] As Figure 3 shown, each sub-pixel SP can include two transistors (2T: DRT and SCT) and one capacitor (1C: Cst) (which can be referred to as a "2T1C structure"), and in some cases, can also include one or more transistors, or can also include one or more capacitors.

[0173] The storage capacitor Cst can be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor such as a parasitic capacitor (e.g., Cgs or Cgd) that can be formed between the first node N1 and the second node N2 of the driving transistor DRT.

[0174] In one or more aspects, each of the driving transistor DRT and the scan transistor SCT can be an n-type transistor or a p-type transistor.

[0175] In one or more aspects, each of the driving transistor DRT and the scan transistor SCT can be a low-temperature polycrystalline silicon transistor.

[0176] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, at least one of the driving transistor DRT and the scan transistor SCT can be an oxide thin-film transistor.

[0177] Since the circuit elements included in each sub-pixel SP (in particular, the light-emitting element ED implemented with an organic light-emitting diode containing an organic material) are vulnerable to external moisture or oxygen, the encapsulation layer ENCAP can be configured to cover the circuit elements (e.g., the light-emitting element ED) to prevent external moisture or oxygen from penetrating into such circuit elements.

[0178] Figure 4 Shows the arrangement of sub-pixels SP in three regions NA, OA1, and OA2, which are examples included in the display area of the display device 100 according to an aspect of the present disclosure.

[0179] Referring to Figure 4 , in one or more exemplary embodiments, a plurality of sub-pixels SP can be provided in each of the normal region NA, the first optical region OA1, and the second optical region OA2 included in the display area DA.

[0180] For example, a plurality of sub-pixels SP may include a red sub-pixel (Red SP) that emits red light, a green sub-pixel (Green SP) that emits green light, and a blue sub-pixel (Blue SP) that emits blue light.

[0181] Accordingly, each of the normal region NA, the first optical region OA1, and the second optical region OA2 may include one or more light-emitting regions EA of one or more red sub-pixels (Red SP), one or more light-emitting regions EA of one or more green sub-pixels (Green SP), and one or more light-emitting regions EA of one or more blue sub-pixels (Blue SP).

[0182] Referring to Figure 4 , the normal region NA may not include a light-transmitting structure, but may include a light-emitting region EA.

[0183] In one or more aspects, each of the first optical region OA1 and the second optical region OA2 may need to include a light-transmitting structure and a light-emitting region EA.

[0184] Accordingly, in one or more aspects, the first optical region OA1 may include one or more light-emitting regions EA and one or more first transmission regions TA1, and the second optical region OA2 may include one or more light-emitting regions EA and one or more second transmission regions TA2.

[0185] The light-emitting region EA and the transmission regions TA1 and / or TA2 may be distinguishable from each other by whether light can be transmitted.

[0186] For example, the light-emitting region EA may be a region where light cannot be transmitted (e.g., where light cannot be transmitted to the back surface of the display panel), and the transmission regions TA1 and / or TA2 may be regions where light can be transmitted (e.g., where light can be transmitted to the back surface of the display panel).

[0187] The light-emitting region EA and the transmission regions TA1 and / or TA2 may also be distinguishable from each other by whether a second electrode layer (e.g., Figure 3 the second electrode CE) is provided.

[0188] For example, although the second electrode CE may be provided in the light-emitting region EA, the second electrode CE may not be provided in the transmission regions TA1 and / or TA2.

[0189] In one or more aspects, a light-shielding layer may be provided in the light-emitting region EA, and the light-shielding layer may not be provided in the transmission regions TA1 and / or TA2.

[0190] Since the first optical region OA1 includes the first transmissive region TA1 and the second optical region OA2 includes the second transmissive region TA2, both the first optical region OA1 and the second optical region OA2 can be regions configured such that light can be transmitted therethrough.

[0191] The transmittance (degree of transmission) of the first optical region OA1 and the transmittance (degree of transmission) of the second optical region OA2 can be substantially the same.

[0192] Here, substantially the same can mean being considered equivalent to each other considering the minute differences due to errors in the manufacturing process of the display panel 110 or the display device 100.

[0193] According to this definition, the first transmissive region TA1 of the first optical region OA1 and the second transmissive region TA2 of the second optical region OA2 can have substantially the same shape or size.

[0194] In one or more aspects, even when the first transmissive region TA1 of the first optical region OA1 and the second transmissive region TA2 of the second optical region OA2 have different shapes or sizes, the ratio of the first transmissive region TA1 to the first optical region OA1 and the ratio of the second transmissive region TA2 to the second optical region OA2 can also be substantially the same.

[0195] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, the transmittance (degree of transmission) of the first optical region OA1 and the transmittance (degree of transmission) of the second optical region OA2 can be different from each other.

[0196] In this embodiment, the first transmissive region TA1 of the first optical region OA1 and the second transmissive region TA2 of the second optical region OA2 can have different shapes or sizes.

[0197] In one or more aspects, even when the first transmissive region TA1 of the first optical region OA1 and the second transmissive region TA2 of the second optical region OA2 have substantially the same shape or size, the ratio of the first transmissive region TA1 to the first optical region OA1 and the ratio of the second transmissive region TA2 to the second optical region OA2 can also be different from each other.

[0198] For example, in an example where the first optoelectronic device 11 overlapping the first optical region OA1 is a camera and the second optoelectronic device 12 overlapping the second optical region OA2 is a sensor for detecting an image, the camera may require a larger amount of light than the sensor.

[0199] In this example, the transmittance (degree of transmission) of the first optical region OA1 can be greater than the transmittance (degree of transmission) of the second optical region OA2.

[0200] In this embodiment, the area of all or each first transmission region TA1 of the first optical region OA1 may be larger than the area of all or each second transmission region TA2 of the second optical region OA2.

[0201] In one or more aspects, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have substantially the same size, the ratio of the first transmission region TA1 to the first optical region OA1 may be larger than the ratio of the second transmission region TA2 to the second optical region OA2.

[0202] In one or more aspects, as Figure 4 shown, the first transmission region TA1 of the first optical region OA1 may have a circular shape in a cross-sectional view, but the exemplary embodiments of the present disclosure are not limited to this shape for the first transmission region TA1.

[0203] For example, the first transmission region TA1 of the first optical region OA1 may have an octagonal shape in a plan view, or may have an elliptical or polygonal shape.

[0204] As discussed above, by changing the shape of the first transmission region TA1, the transmittance of the first transmission region TA1 can be adjusted and the area or size of the light-emitting region of the first optical region OA1 can be adjusted.

[0205] Hereinafter, for the sake of convenience of explanation, an example in which the transmittance (transmission degree) of the first optical region OA1 is greater than the transmittance (transmission degree) of the second optical region OA2 will be discussed.

[0206] In addition, as Figure 4 shown, the transmission regions TA1 and TA2 may be referred to as transparent regions, and transmission may also be referred to as transparency.

[0207] In the following discussion, as Figure 4 shown, it is assumed that the first optical region OA1 and the second optical region OA2 are located above the display region DA of the display panel 110 and are arranged side by side left and right.

[0208] Referring to Figure 4 , the horizontal display region provided with the first optical region OA1 and the second optical region OA2 may be referred to as a first horizontal display region HA1, and the horizontal display region not provided with the first optical region OA1 and the second optical region OA2 may be referred to as a second horizontal display region HA2.

[0209] Referring to Figure 4 , the first horizontal display region HA1 may include a normal region NA, the first optical region OA1, and the second optical region OA2.

[0210] The second horizontal display area HA2 may include only the normal area NA.

[0211] Figure 5 and Figure 6 is a cross-sectional view of an exemplary light-emitting element ED included in the display device 100 according to an aspect of the present disclosure.

[0212] Referring to Figure 5 , in one or more exemplary embodiments, the stack of the light-emitting elements ED included in the display device 100 may include respective portions of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B that are disposed on the substrate 10 and configured to emit different colors.

[0213] The stack of the light-emitting element ED may include a first electrode layer 51 disposed on the substrate 10, a second electrode layer 58 disposed opposite to the first electrode layer 51, and a light-emitting layer 55 disposed between the first electrode layer 51 and the second electrode layer 58.

[0214] The first electrode layer 51 may be an anode, and the second electrode layer 58 may be a cathode, but the exemplary embodiments of the present disclosure are not limited thereto.

[0215] For example, in the case of an inverted type, the first electrode layer 51 may be a cathode and the second electrode layer 58 may be an anode.

[0216] It should be noted that the following discussion is based on an example in which the first electrode layer 51 and the second electrode layer 58 of each light-emitting element ED are an anode and a cathode, respectively.

[0217] At least one transistor (not shown in Figure 5 ) disposed above the substrate 10 may include a source, a drain, a gate, and an active layer, and the first electrode layer 51 may be electrically connected to either the source or the drain of the transistor through a contact hole formed in an insulating layer disposed on the substrate 10.

[0218] The first electrode layer 51 may include a material having a relatively high work function.

[0219] For example, the first electrode layer 51 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), indium oxide (In2O3), tin oxide (SnO2), etc., but the exemplary embodiments of the present disclosure are not limited thereto.

[0220] The second electrode layer 58 may include a material having a relatively low work function, and for example, includes a metal, an alloy, a conductive compound, or a mixture of two or more of them.

[0221] For example, a transmissive electrode as the second electrode layer 58 can be obtained by forming lithium (Li), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), etc. in the form of a thin film.

[0222] In this regard, in one or more aspects, various modifications can be made, such as forming a transmissive electrode using ITO or IZO to obtain a top-emitting element.

[0223] A cover layer (not shown in Figure 5 ) can be provided on the second electrode layer 58 to improve optical capabilities and maximize luminous efficiency.

[0224] For example, the cover layer can include a metal oxide layer, a metal nitride layer, or a metal oxynitride layer.

[0225] For example, the cover layer can contain MoO x (x = 2 - 4), Al2O3, Sb2O3, BaO, CdO, CaO, Ce2O3, CoO, Cu2O, DyO, GdO, HfO2, La2O3, Li2O, MgO, NbO, NiO, Nd2O3, PdO, Sm2O3, ScO, SiO2, SrO, Ta2O3, TiO, WO3, VO2, YbO, Y2O3, ZnO, ZrO, AlN, BN, NbN, SiN, TaN, TiN, VN, YbN, ZrN, SiON, AlON, or a mixture thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0226] Referring to Figure 5 , the light-emitting layer 55 of the stack of the light-emitting element ED can include a red light-emitting layer 55R of the red sub-pixel R, a green light-emitting layer 55G of the green sub-pixel G, and a blue light-emitting layer 55B of the blue sub-pixel B.

[0227] For example, the wavelengths of the light emitted from the red light-emitting layer 55R, the green light-emitting layer 55G, and the blue light-emitting layer 55B become shorter in the order from the red light-emitting layer 55R to the blue light-emitting layer 55B.

[0228] The red light-emitting layer 55R can include a red host and a red dopant.

[0229] The red host can use Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0230] The red dopant can be PtOEP, Ir(piq)3, Btp2Ir(acac), Ir(2-phq)2(acac), Ir(2-phq)3, Ir(flq)2(acac), Ir(fliq)2(acac), or a compound containing DCM or DCJTB, but the exemplary embodiments of the present disclosure are not limited thereto.

[0231] The green light-emitting layer 55G can include a green host and a green dopant.

[0232] The green host can be Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0233] The green dopant can be Ir(ppy)3 tris(2-phenylpyridine) iridium, Ir(ppy)2(acac) (Bis(2-phenylpyridine)(Acetylacetonato)iridium(III)), Ir(mppy)3 (tris(2-(4-tolyl)phenylpiridine) iridium), C545T 10-(2-benzothiazolyl)-1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-[1]benzopyrano[6,7,8-ij]-quinolizin11-one, etc., but the exemplary embodiments of the present disclosure are not limited thereto.

[0234] The blue light-emitting layer 55B can include a blue host and a blue dopant.

[0235] The blue matrix can use Alq3, CBP (4,4'-N,N'-dicabazole-biphenyl), PVK (poly(n-vinylcabazole)), ADN (9,10-di(naphthalene-2-yl)anthracene), TCTA, TPBI (1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene), TBADN (3-tert-butyl-9,10-di(naphth-2-yl)anthracene), E3, DSA (distyrylarylene), or a mixture of two or more of them, but the exemplary embodiments of the present disclosure are not limited thereto.

[0236] The blue dopant can use compounds containing F2Irpic, (F2ppy)2Ir(tmd), Ir(dfppz)3, trifuorene, DPAVBi (4,4'-bis(4diphenylaminostyryl)biphenyl), TBPe, etc., but the exemplary embodiments of the present disclosure are not limited thereto.

[0237] Referring to Figure 5 , the stack of the light-emitting element ED may include a hole transport layer 53 disposed between the first electrode layer 51 and the light-emitting layer 55.

[0238] The hole transport layer 53 may include a common hole transport layer 53C disposed on the hole injection layer 52.

[0239] The hole transport layer 53 may include a light-emission assisting layer disposed between the hole transport layer 53 and the common hole transport layer 53C.

[0240] The light-emission assisting layer may include a red light-emission assisting layer 53R, a green light-emission assisting layer 53G, and a blue light-emission assisting layer (not shown) disposed on the common hole transport layer 53C.

[0241] For example, the light-emission assisting layer can be used to transport holes and may include hole transport materials. The light-emission assisting layer may include the same materials or compounds, or may include different materials or compounds.

[0242] For example, the hole transport layer 53, the common hole transport layer 53C, the red light emission assisting layer 53R, the green light emission assisting layer 53G, and the blue light emission assisting layer (not shown) may include a material containing a tertiary amine or a fluorene-containing tertiary amine, but the exemplary embodiments of the present disclosure are not limited thereto.

[0243] Referring to Figure 5 , the stack of the light-emitting element ED may include a hole injection layer 52 disposed on the first electrode layer 51, a hole transport layer 53 disposed on the hole injection layer 52, a light-emitting layer 55 disposed on the hole transport layer 53, and an electron transport layer 57 disposed on the light-emitting layer 55, but the exemplary embodiments of the present disclosure are not limited thereto.

[0244] When a voltage is applied between the first electrode layer 51 and the second electrode layer 58 of the stack of the light-emitting element ED, holes passing through the hole transport layer 53 and electrons passing through the electron transport layer 57 may move to the light-emitting layer 55 and form excitons, which enables the light-emitting layer 55 to emit visible light.

[0245] Referring to Figure 5 , the stack of the light-emitting element ED may include an electron blocking layer 54 between the hole transport layer 53 and the light-emitting layer 55.

[0246] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, the stack of the light-emitting element ED may not include the electron blocking layer 54.

[0247] The electron blocking layer 54 may include at least one of tris(phenylpyrazole)iridium, BPAPF (9,9-bis[4-(N,N-bis-biphenyl-4-ylamino)phenyl]-9H-fluorene), bis[4-(p,p-ditolylamino)phenyl]diphenylsilane, NPD (4,4'-bis[N-(1-napthyl)-N-phenyl-amino]biphenyl), mCP (N,N'-dicarbazolyl-3,5-benzene), and MPMP (bis[4-(N,N-diethylamino)-2-methylphenyl](4-methylphenyl)methane), or a combination thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0248] In one or more aspects, the electron blocking layer 54 may comprise an inorganic compound. For example, the electron blocking layer 144 may comprise at least one of halides such as LiF, NaF, KF, RbF, CsF, FrF, MgF2, CaF2, SrF2, BaF2, LiCl, NaCl, KCl, RbCl, CsCl, FrCl, oxides such as Li2O, Li2O2, Na2O, K2O, Rb2O, Rb2O2, Cs2O, Cs2O2, LiAlO2, LiBO2, LiTaO3, LiNbO3, LiWO4, Li2CO, NaWO4, KAlO2, K2SiO3, B2O5, Al2O3, SiO2, or a combination of a halide and an oxide. However, the exemplary embodiments of the present disclosure are not limited thereto.

[0249] The electron blocking layer 54 can be used as a buffer layer to block direct contact between the hole transport layer 53 and the light emitting layer 55 and to prevent electrons from easily flowing into the hole transport layer 53.

[0250] For example, the electron blocking layer 54 can improve the efficiency and lifetime of the light emitting device ED by controlling the injection and movement of electrons and the combination of electrons and holes.

[0251] The electron transport layer 57 can be disposed on the light-emitting layer 55.

[0252] The electron transport layer 57 can control the moving speed of electrons, so that electrons and holes can meet in the light-emitting layer 55 and enable the light-emitting layer 55 to emit light.

[0253] The electron transport layer 57 can include materials that enable electrons to move at a speed several times higher than the speed at which electrons can move in other materials.

[0254] For example, the electron transport layer 57 can include at least one of or a combination of Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, and SAlq, but the exemplary embodiments of the present disclosure are not limited thereto.

[0255] An electron injection layer (not shown) can be disposed on the electron transport layer 57.

[0256] The electron injection layer (not shown) can transfer the electrons flowing in from the second electrode layer 58 to the electron transport layer 57.

[0257] Referring to Figure 5 , the stack of the light-emitting element ED can include a hole blocking layer 56 between the light-emitting layer 55 and the electron transport layer 57.

[0258] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, the stack of the light-emitting element ED may not include the hole blocking layer 56.

[0259] The hole blocking layer 56 can act as a buffer layer for preventing direct contact between the electron transport layer 57 and the light-emitting layer 55, and for preventing holes from easily flowing into the electron transport layer 57.

[0260] For example, the hole blocking layer 56 can improve the efficiency and lifespan of the light-emitting element ED by controlling the injection and movement of holes and the combination of holes and electrons.

[0261] As described above, an example in which each light-emitting element has a single stack structure has been described with reference to Figure 5 Another example in which each light-emitting element ED has a multi-stack structure will be described below with reference to

[0262] Hereinafter, another example in which each light-emitting element ED has a multi-stack structure will be described with reference to Figure 6 Referring to

[0263] Referring to Figure 6, in one or more example embodiments, each light-emitting element ED has a multi-stack structure including a first stacked light-emitting layer 651 and a second stacked light-emitting layer 652. Each light-emitting element ED may further include a first electrode layer 61 disposed on a substrate 10, a hole injection layer 62 on the first electrode layer 61, and a second electrode layer 68 disposed opposite to the first electrode layer 61.

[0264] For example, the first stacked light-emitting layer 651 and the second stacked light-emitting layer 652 may include light-emitting materials capable of emitting light of the same color.

[0265] Referring to Figure 6 , each light-emitting element ED may be configured with a first stack structure including the first stacked light-emitting layer 651 and a second stack structure including the second stacked light-emitting layer 652.

[0266] The first hole transport layer 631 (including 631C, 631G, and 631R), the first electron blocking layer 641, the first stacked light-emitting layer 651 (including 651R, 651G, and 651B), the first hole blocking layer 661, and the first electron transport layer 671 included in the first stack structure may be the same as or substantially the same as Figure 5 the hole transport layer 53, the electron blocking layer 54, the light-emitting layer 55, the hole blocking layer 56, and the electron transport layer 57. Therefore, for simplicity, the discussion of these elements is omitted.

[0267] In one or more aspects, in the second stack structure, a charge generation layer 69, a second hole transport layer 632 (including 632R, 632G, and 632B), a second electron blocking layer 642, a second stacked light-emitting layer 652 (including 652R, 652G, and 652B), a second hole blocking layer 662, and a second electron transport layer 672 may be disposed between the second electrode layer 68 and the first electron transport layer 671.

[0268] In one or more aspects, the charge generation layer 69 may be located on the first electron transport layer 671, the second hole transport layer 632 may be located on the charge generation layer 69, the second electron blocking layer 642 may be located on the second hole transport layer 632, the second stacked light-emitting layer 652 may be located on the second electron blocking layer 642, the second hole blocking layer 662 may be located on the first stacked light-emitting layer 651, and the second electron transport layer 672 may be disposed on the second hole blocking layer 662.

[0269] The second electron transport layer 672 may be disposed adjacent to the second stacked light-emitting layer 652 and may transfer electrons to the second stacked light-emitting layer 652.

[0270] The charge generation layer 69 can be disposed between the first electron transport layer 671 and the second hole transport layer 632 and can transfer electrons to the first electron transport layer 671.

[0271] The first hole transport layer 671 can be disposed adjacent to the first stacked light-emitting layer 651 and can transfer holes to the first stacked light-emitting layer 651.

[0272] Although Figure 6 each light-emitting element is shown to include a two-stack structure, the exemplary embodiments of the present disclosure are not limited thereto. For example, each light-emitting element can have other multi-stack structures such as a three-stack structure, a four-stack structure, and the like.

[0273] Figure 7A and Figure 7B are cross-sectional views of an exemplary light-emitting element ED disposed in the normal area NA and the optical area OA of the display device 100 according to an aspect of the present disclosure.

[0274] Although for ease of illustration, Figure 7A and Figure 7B show an exemplary light-emitting element configured with a single-stack structure, however, the exemplary embodiments of the present disclosure are not limited thereto. Figure 7A and Figure 7B The configurations and related discussions can be equally applied to multi-stack structures.

[0275] It should be noted that for ease of illustration, in Figure 7A and Figure 7B , portions of the materials included in the light-emitting layer 75 are shown in the form of particles. For example, the first matrix H1 and the second matrix H2, which are portions of the materials included in the light-emitting layer 75, can be shown in the form of particles.

[0276] Referring to Figure 7A , the first electrode layer 71, the hole injection layer 72, the common hole transport layer 73C, the hole transport layer 73, the electron blocking layer 74, the light-emitting layer 75, the hole blocking layer 76, the electron transport layer 77, and the second electrode layer 78 included in the normal area NA and the optical area OA can be the same as or substantially the same as the first electrode layer 51, the hole injection layer 52, the common hole transport layer 53C, the hole transport layer 53, the electron blocking layer 54, the light-emitting layer 55, the hole blocking layer 56, the electron transport layer 57, and the second electrode layer 58 in Figure 5 . Therefore, for simplicity, the discussion of these elements is omitted.

[0277] Referring to Figure 7A , each of the light-emitting layers 75 in the normal area NA and the optical area OA can include a first light-emitting layer 751 and a second light-emitting layer 752.

[0278] The first light-emitting layer 751 may be located on the electron blocking layer 74, and the second light-emitting layer 752 may be located on the first light-emitting layer 751.

[0279] In one or more aspects, the first light-emitting layer 751 and the second light-emitting layer 752 in the normal region NA may include a first host H1.

[0280] Although Figure 7A it is shown that the first light-emitting layer 751 and the second light-emitting layer 752 in the normal region NA are located in different layers, however, the exemplary embodiments of the present disclosure are not limited thereto. In an example where the first light-emitting layer 751 and the second light-emitting layer 752 in the normal region NA include the same material by including the first host H1, the first light-emitting layer 751 and the second light-emitting layer 752 may be regarded as a single layer.

[0281] In one or more aspects, the first light-emitting layer 751 and the second light-emitting layer 752 in the optical region OA may include the first host H1 and the second host H2, respectively.

[0282] For example, the second host H2 may be different from the first host H1.

[0283] It should be noted that the number of particles of the first host H1 and the second host H2 shown in the normal region NA and the optical region OA of Figure 7A is only for convenience of explanation, and thus, the exemplary embodiments of the present disclosure are not limited thereto. The amount of particles of each of the first host H1 and the second host H2 may vary due to errors in the manufacturing process.

[0284] In one or more aspects, the first light-emitting layer 751 and the second light-emitting layer 752 in the normal region NA may include the same type of dopant.

[0285] In one or more aspects, the first light-emitting layer 751 and the second light-emitting layer 752 in the optical region OA may include a first dopant (not shown) and a second dopant (not shown), respectively. In one or more aspects, referring to Figure 7A , the thickness of the first light-emitting layer 751 in the optical region OA is greater than the thickness of the first light-emitting layer 751 in the normal region NA, and the thickness of the second light-emitting layer 752 in the optical region OA is greater than the thickness of the second light-emitting layer 752 in the normal region NA. Therefore, the area for light emission is increased and the efficiency is improved.

[0286] For example, the second dopant and the first dopant may be different from each other.

[0287] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, the first light-emitting layer 751 and the second light-emitting layer 752 in the optical region OA may include the same type of dopant.

[0288] The lifetime of the light-emitting element ED provided in the optical region OA can be increased by adjusting the types and amounts of one or more matrices and one or more dopants included in the first light-emitting layer 751 and the second light-emitting layer 752, which are different from the normal region NA.

[0289] Referring to Figure 7A , as the number of the light-emitting layers 75 increases (i.e., the first light-emitting layer 751 and the second light-emitting layer 752), the thicknesses (B1 and B2) of the entire light-emitting layer 75 can increase.

[0290] For example, the thicknesses (A1 or A2) of the hole transport layer 73 or the common hole transport layer 73C can be adjusted to compensate for the increased thicknesses (B1 and B2) of the entire light-emitting layer 75. The combination of the hole transport layer 73 and the common hole transport layer 73C can also be referred to as the hole transport layer 73. In addition, the common hole transport layer 73C can be omitted.

[0291] Referring to Figure 7A , as the thickness B2 of the light-emitting layer 75 in the optical region OA increases compared to the thickness B1 of the light-emitting layer 75 in the normal region NA, the increased thickness B2 of the light-emitting layer in the optical region OA can be compensated by reducing the thickness A2 of the hole transport layer 73 and the common hole transport layer 73C in the optical region OA rather than the thickness A1 of the hole transport layer 73 and the common hole transport layer 73C in the normal region NA.

[0292] For example, the sum of the respective thicknesses of the hole transport layer 73, the common hole transport layer 73C, the first light-emitting layer 751, and the second light-emitting layer 752 in the normal region NA can be the same as the sum of the respective thicknesses of the hole transport layer 73, the common hole transport layer 73C, the first light-emitting layer 751, and the second light-emitting layer 752 in the optical region OA.

[0293] In one or more aspects, according to the design requirements, the first light-emitting layer 751 and the second light-emitting layer 752 of the light-emitting element ED can include a phosphorescent matrix and a phosphorescent dopant, or a fluorescent matrix and a fluorescent dopant.

[0294] As described above, reference has been made to Figure 7A an example in which the light-emitting layer 75 has two layers.

[0295] Hereinafter, reference is made to Figure 7B an example in which the light-emitting layer 75 has three layers.

[0296] Referring to Figure 7B , the first electrode layer 71, the hole injection layer 72, the common hole transport layer 73C, the hole transport layer 73, the electron blocking layer 74, the light-emitting layer 75, the hole blocking layer 76, the electron transport layer 77, and the second electrode layer 78 included in the normal region NA and the optical region OA can be the same as those described aboveFigure 5 The first electrode layer 51, hole injection layer 52, common hole transport layer 53C, hole transport layer 53, electron blocking layer 54, light-emitting layer 55, hole blocking layer 56, electron transport layer 57, and second electrode layer 58 in

[0297] Referring to Figure 7B , each of the light-emitting layers 75 in the normal area NA and the optical area OA may include a first light-emitting layer 751, a second light-emitting layer 752, and a third light-emitting layer 753.

[0298] The first light-emitting layer 751 may be located on the electron blocking layer 74, the second light-emitting layer 752 may be located on the first light-emitting layer 751, and the third light-emitting layer 753 may be located on the second light-emitting layer 752.

[0299] In one or more aspects, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the normal area NA may include a first matrix H1.

[0300] Although Figure 7B it is shown that the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the normal area NA are located in different layers, however, the exemplary embodiments of the present disclosure are not limited thereto. In an example where the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the normal area NA include the same material by including the first matrix H1, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 may be regarded as a single layer.

[0301] In one or more aspects, the first light-emitting layer 751 and the third light-emitting layer 753 in the optical area OA may include a first matrix H1, and the second light-emitting layer 752 in the optical area OA may include a second matrix H2.

[0302] For example, the second matrix H2 may be different from the first matrix H1.

[0303] It should be noted that the number of particles of the first matrix H1 and the second matrix H2 shown in Figure 7B the normal area NA and the optical area OA of

[0304] is only for the convenience of description, and thus, the exemplary embodiments of the present disclosure are not limited thereto. The amount of particles of each of the first matrix H1 and the second matrix H2 may vary due to errors in the manufacturing process.

[0305] In one or more aspects, the first light-emitting layer 751 and the third light-emitting layer 753 of the optical region OA may include a first dopant, and the second light-emitting layer 752 of the optical region OA may include a second dopant.

[0306] For example, the second dopant and the first dopant may be different from each other.

[0307] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 of the optical region OA may include the same type of dopant.

[0308] The lifetime of the light-emitting element ED provided in the optical region OA can be increased by adjusting the types and amounts of one or more host materials and one or more dopants included in the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753, which are different from those in the normal region NA.

[0309] Refer to Figure 7B , as the number of the light-emitting layers 75 increases (i.e., the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753), the thicknesses (B1 and B2) of the entire light-emitting layer 75 can increase.

[0310] For example, the thicknesses (A1 or A2) of the hole transport layer 73 or the common hole transport layer 73C can be adjusted to compensate for the increased thicknesses (B1 and B2) of the entire light-emitting layer 75.

[0311] Refer to Figure 7B , as the thickness B2 of the light-emitting layer 75 in the optical region OA increases compared to the thickness B1 of the light-emitting layer 75 in the normal region NA, the increased thickness B2 of the light-emitting layer in the optical region OA can be compensated by reducing the thickness A2 of the hole transport layer 73 and the common hole transport layer 73C in the optical region OA rather than the thickness A1 of the hole transport layer 73 and the common hole transport layer 73C in the normal region NA.

[0312] For example, the sum of the respective thicknesses of the hole transport layer 73, the common hole transport layer 73C, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the normal region NA may be the same as or substantially the same as the sum of the respective thicknesses of the hole transport layer 73, the common hole transport layer 73C, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the optical region OA.

[0313] In one or more aspects, according to design requirements, the first light-emitting layer 751 and the second light-emitting layer 752 of the light-emitting element ED may include a phosphorescent host material and a phosphorescent dopant, or a fluorescent host material and a fluorescent dopant.

[0314] Figures 8A to 8C Shows the triplet energy levels of an exemplary light-emitting element ED included in a display device 100 according to aspects of the present disclosure.

[0315] In one or more aspects, Figure 8A and Figure 8B Shows that the light-emitting layer 85 of the light-emitting element ED includes a first light-emitting layer 851 and a second light-emitting layer 852, and the light-emitting layer 85 disposed between the electron blocking layer 84 and the hole blocking layer 86 has two layers.

[0316] In one or more aspects, Figure 8C Shows that the light-emitting layer 85 of the light-emitting element ED includes a first light-emitting layer 851, a second light-emitting layer 852, and a third light-emitting layer 853, and the light-emitting layer 85 disposed between the electron blocking layer 84 and the hole blocking layer 86 has three layers.

[0317] Referring to Figure 8A , the second light-emitting layer 852 may be disposed between the hole blocking layer 86 and the first light-emitting layer 851 to prevent triplet exciton quenching (TPQ).

[0318] For example, the thickness of the second light-emitting layer 852 may preferably be 2 nm or more and 5 nm or less.

[0319] In this example, the first light-emitting layer 851 may be a main light-emitting layer, and the second light-emitting layer 852 may be an auxiliary light-emitting layer.

[0320] According to this example, the second light-emitting layer 852 may transfer the energy generated by combining the holes accumulated at the interface of the hole blocking layer 86 and the electrons transferred through the hole blocking layer 86 to the first light-emitting layer 851.

[0321] Here, in order to stably transfer electrons and block holes, Equation 1 may be satisfied in the optical region OA, or at least one of Equation 2 or Equation 3 may be satisfied.

[0322] [Equation 1]

[0323] T1 < T2 < T HB

[0324] In Equation 1, T HB is the triplet energy level of the hole blocking layer, T1 is the triplet energy level of the first light-emitting layer, and T2 is the triplet energy level of the second light-emitting layer.

[0325] [Equation 2]

[0326] L HB < L2 < L1

[0327] In Equation 2, L HBis the lowest unoccupied molecular orbital (LUMO) energy level of the hole blocking layer, L1 is the LUMO energy level of the first light-emitting layer, and L2 is the LUMO energy level of the second light-emitting layer.

[0328] [Equation 3]

[0329] |H2 - H1| ≤ 0.1 eV

[0330] In Equation 3, H1 is the highest occupied molecular orbital (HOMO) energy level of the first light-emitting layer, and H2 is the HOMO energy level of the second light-emitting layer.

[0331] When the light-emitting element ED satisfies Equation 1 and at least one of Equation 2 or Equation 3, the phosphorescence efficiency can be increased.

[0332] Refer to Figure 8B , the second light-emitting layer 852 can be disposed between the hole blocking layer 86 and the first light-emitting layer 851 to prevent triplet-triplet annihilation (TTA).

[0333] For example, the thickness of the first light-emitting layer 851 can preferably be 2 nm or more and 5 nm or less.

[0334] In this example, the second light-emitting layer 852 can be the main light-emitting layer, and the first light-emitting layer 851 can be the auxiliary light-emitting layer.

[0335] According to this example, the first light-emitting layer 851 can transfer the energy generated by combining the electrons accumulated at the interface of the electron blocking layer 84 and the holes transferred through the electron blocking layer 84 to the second light-emitting layer 852.

[0336] Here, in order to stably transfer holes and block electrons, Equation 4 can be satisfied in the optical region OA, or at least one of Equation 5 or Equation 6 can be satisfied.

[0337] [Equation 4]

[0338] T2 < T1 < T EB

[0339] In Equation 4, T EB is the triplet energy level of the electron blocking layer, T1 is the triplet energy level of the first light-emitting layer, and T2 is the triplet energy level of the second light-emitting layer.

[0340] [Equation 5]

[0341] L2 < L1 < L EB

[0342] In Equation 5, L EB is the lowest unoccupied molecular orbital (LUMO) energy level of the electron blocking layer, L1 is the LUMO energy level of the first light-emitting layer, and L2 is the LUMO energy level of the second light-emitting layer.

[0343] [Formula 6]

[0344] H2 < H1 < H EB

[0345] In Formula 6, H EB is the highest occupied molecular orbital (HOMO) energy level of the electron blocking layer, H1 is the HOMO energy level of the first light-emitting layer, and H2 is the HOMO energy level of the second light-emitting layer.

[0346] When the light-emitting element ED satisfies Formula 4 and at least one of Formula 5 or Formula 6, the fluorescence efficiency can be increased.

[0347] Referring to Figure 8C , the third light-emitting layer 853 can be disposed between the hole blocking layer 86 and the second light-emitting layer 852 to prevent triplet exciton quenching (TPQ) in the light-emitting layer 85 and the hole blocking layer 86.

[0348] For example, the thicknesses of the first light-emitting layer 851 and the third light-emitting layer 853 can preferably be 2 nm or more and 5 nm or less.

[0349] In this example, the second light-emitting layer 852 can be the main light-emitting layer, and the first light-emitting layer 851 and the third light-emitting layer 853 can be auxiliary light-emitting layers.

[0350] According to this example, the first light-emitting layer 851 can have a lower electron transport ability but a greater hole transport ability than the second light-emitting layer 852 and the third light-emitting layer 853.

[0351] Here, in order to stably transfer energy and emit light, Formulas 7 and 8 can be satisfied in the optical region OA.

[0352] [Formula 7]

[0353] T1 > T2

[0354] [Formula 8]

[0355] T3 > T2

[0356] In Formulas 7 and 8, T1 is the triplet energy level of the first light-emitting layer, T2 is the triplet energy level of the second light-emitting layer, and T3 is the triplet energy level of the third light-emitting layer.

[0357] When the light-emitting element ED satisfies Formulas 7 and 8, since the triplet energy level T2 of the second light-emitting layer 852 is lower than the triplet energy levels T1 of the first light-emitting layer 851 and T3 of the third light-emitting layer 853, energy can be transferred from the auxiliary light-emitting layers 851 and 853 to the main light-emitting layer 852.

[0358] Here, in order to stably transfer energy and emit light, it is preferable to satisfy at least one of Formula 9, Formula 10, Formula 11, and Formula 12.

[0359] [Formula 9]

[0360] T EB >T1>T2

[0361] In Formula 9, T1 is the triplet energy level of the first light-emitting layer, T2 is the triplet energy level of the second light-emitting layer, and T EB is the triplet energy level of the electron blocking layer.

[0362] [Formula 10]

[0363] T HB >T3>T2

[0364] In Formula 10, T2 is the triplet energy level of the second light-emitting layer, T3 is the triplet energy level of the third light-emitting layer, and T HB is the triplet energy level of the hole blocking layer.

[0365] [Formula 11]

[0366] L1>L2

[0367] In Formula 11, L1 is the lowest unoccupied molecular orbital (LUMO) energy level of the first light-emitting layer, and L2 is the LUMO energy level of the second light-emitting layer.

[0368] [Formula 12]

[0369] H1>H2

[0370] In Formula 12, H1 is the highest occupied molecular orbital (HOMO) energy level of the first light-emitting layer, and H2 is the HOMO energy level of the second light-emitting layer.

[0371] Figures 8A to 8C The values of HOMO, LUMO, and T described in can be values measured by cyclic voltammetry.

[0372] Manufacture of light-emitting elements according to exemplary embodiments of the present disclosure, and evaluation of these light-emitting elements

[0373] [Example 1]

[0374] A light-emitting element was manufactured as follows. A hole injection layer was formed by depositing a 2-TNATA film on an indium tin oxide (ITO) layer (serving as an anode) formed on a glass substrate by using a vacuum deposition technique. Thereafter, a hole transport layer was formed by depositing NPD on the hole injection layer by using a vacuum deposition technique.

[0375] Next, a first light-emitting layer with a thickness of 5 nm including a first matrix material and a dopant material was deposited on the hole transport layer. Thereafter, a second light-emitting layer with a thickness of 17.5 nm including a second matrix material and a dopant material was deposited on the first light-emitting layer.

[0376] Next, a hole blocking layer was formed by depositing BAlq on the second light-emitting layer using a vacuum deposition technique, and an electron transport layer was formed by depositing Alq3 on the hole blocking layer.

[0377] Thereafter, an electron injection layer was formed by depositing LiF on the electron transport layer, and then a cathode was formed by depositing Al on the electron injection layer.

[0378] [Example 2]

[0379] The light-emitting element of Example 2 was fabricated by the same process as in Example 1, except that a second light-emitting layer with a thickness of 17.5 nm including a second matrix material and a dopant material was deposited on the hole transport layer, and thereafter, a first light-emitting layer with a thickness of 5 nm including a first matrix material and a dopant material was deposited on the second light-emitting layer.

[0380] [Comparative Example]

[0381] The light-emitting element of the comparative example was fabricated by the same process as in Example 1, except that a light-emitting layer with a thickness of 22.5 nm including a second matrix material and a dopant material was deposited on the hole transport layer.

[0382] To evaluate the light-emitting elements fabricated according to Example 1 and 2 and the comparative example, the electroluminescence (EL) characteristics were measured by applying a forward bias DC voltage to the light-emitting elements, and the measurement results of the T95 lifetime measured by a lifetime measurement device are shown in Table 1 below.

[0383]

Table 1

[0384]

[0385] Figures 9A to 9D It is a graph showing the result of comparing Example 1 with the comparative example.

[0386] Figures 10A to 10D It is a graph showing the result of comparing Example 2 with the comparative example.

[0387] From the results in Table 1, it can be seen that Example 1, in which the first light-emitting layer is introduced between the electron blocking layer and the second light-emitting layer, shows improved efficiency and lifetime (T95) compared to the comparative example.

[0388] In addition, Example 2, in which the first light-emitting layer was introduced between the hole blocking layer and the second light-emitting layer, showed an increased lifetime (T95) compared to the comparative example.

[0389] The exemplary embodiments described above will be briefly described as follows.

[0390] According to an example embodiment of the present disclosure, a display device may be provided, including: a substrate including a normal region and an optical region, the normal region being configured to have a plurality of first pixels disposed therein and to have a first resolution, the optical region being configured to have a plurality of second pixels disposed therein and to have a second resolution lower than the first resolution; a first electrode layer located on the substrate; a first light-emitting layer located on the first electrode layer and including a first matrix; a second light-emitting layer located on the first light-emitting layer, including the first matrix in the normal region and including a second matrix different from the first matrix in the optical region; and a second electrode layer located on the second light-emitting layer.

[0391] According to one or more example embodiments of the present disclosure, a display device may include: a normal area, in which a plurality of first sub-pixels are arranged; and an optical area, in which a plurality of second sub-pixels are arranged, wherein the number of the plurality of second sub-pixels per unit area in the optical area is less than the number of the plurality of first sub-pixels per unit area in the normal area, wherein each of the plurality of first sub-pixels in the normal area and the plurality of second sub-pixels in the optical area includes a light-emitting element, wherein the light-emitting element includes: a first electrode layer, located on a substrate; one or more stacks; and a second electrode layer, the second electrode layer is located on the one or more stacks, wherein each of the one or more stacks includes: a first light-emitting layer, the first light-emitting layer is located on the first electrode layer and includes a first matrix in the normal area and the optical area; and a second light-emitting layer, the second light-emitting layer is located on the first light-emitting layer, includes a first matrix in the normal area, and includes a second matrix different from the first matrix in the optical area.

[0392] The above description has been presented to enable one of ordinary skill in the art to make, use, and practice the technical features of the present invention, and the above description has been provided as an example in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to one of ordinary skill in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present invention. The above description and accompanying drawings provide examples of the technical features of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present invention.

Claims

1. A display device, comprising: a substrate including a general area configured to have a plurality of first pixels disposed therein and to have a first resolution and an optical area configured to have a plurality of second pixels disposed therein and to have a second resolution lower than the first resolution; a first electrode layer, wherein the first electrode layer is located on the substrate; a first light emitting layer, the first light emitting layer being located on the first electrode layer and comprising a first matrix in the general region and the optical region; a second light-emitting layer, the second light-emitting layer being located on the first light-emitting layer, including the first host in the general region, and including a second host different from the first host in the optical region; as well as A second electrode layer is located on the second light-emitting layer.

2. The display device according to claim 1, wherein: The first light emitting layer and the second light emitting layer in the optical region include a first dopant and a second dopant, respectively, and the second dopant and the first dopant are the same as or different from each other.

3. The display device according to claim 2, wherein: The first host and the second host are phosphorescent hosts or fluorescent hosts, and the first dopant and the second dopant are phosphorescent dopants or fluorescent dopants.

4. The display device according to claim 1, wherein: A sum of thicknesses of the first light-emitting layer and the second light-emitting layer in the optical region is greater than a sum of thicknesses of the first light-emitting layer and the second light-emitting layer in the general region.

5. The display device according to claim 1, further comprising: The hole transport layer is located between the first electrode layer and the first light-emitting layer.

6. The display device according to claim 5, wherein: The sum of the thicknesses of the hole transport layer, the first light emitting layer, and the second light emitting layer in the general region is the same as the sum of the thicknesses of the hole transport layer, the first light emitting layer, and the second light emitting layer in the optical region.

7. The display device according to claim 1, further comprising: A third light-emitting layer is located on the second light-emitting layer, and the third light-emitting layer in the general area and the optical area includes the first matrix.

8. The display device according to claim 7, wherein: The third light emitting layer in the optical region includes a third dopant that is the same as or different from the second dopant and the first dopant.

9. The display device according to claim 7, wherein: The sum of thicknesses of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region is greater than the sum of thicknesses of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region.

10. The display device according to claim 9, further comprising: The hole transport layer is located between the first electrode layer and the first light-emitting layer.

11. The display device according to claim 10, wherein: The sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer and the third light-emitting layer in the general region is the same as the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer and the third light-emitting layer in the optical region.

12. The display device according to claim 5, further comprising: An electron blocking layer, the electron blocking layer being arranged between the hole transport layer and the first light-emitting layer; as well as A hole blocking layer is disposed on the second light emitting layer.

13. The display device according to claim 10, further comprising: An electron blocking layer, the electron blocking layer being arranged between the hole transport layer and the first light-emitting layer; as well as A hole blocking layer is disposed on the third light emitting layer.

14. The display device according to claim 12, wherein: In the optical region, Formula 1 is satisfied, or at least one of Formula 2 or Formula 3 is satisfied: [Formula 1] T1 <T2<T HB In the formula 1, T HB is the triplet energy level of the hole blocking layer, T1 is the triplet energy level of the first light-emitting layer, and T2 is the triplet energy level of the second light-emitting layer, [Formula 2] L HB <L2 <L1 In Formula 2, L HB is the lowest unoccupied molecular orbital energy level of the hole blocking layer, i.e., the LUMO energy level, L1 is the LUMO energy level of the first light-emitting layer, and L2 is the LUMO energy level of the second light-emitting layer, [Formula 3] |H2-H1|≤0.1eV In Formula 3, H1 is the highest occupied molecular orbital energy level, ie, the HOMO energy level, of the first light-emitting layer, and H2 is the HOMO energy level of the second light-emitting layer.

15. The display device according to claim 14, wherein: The second light-emitting layer has a thickness of 2 nm to 5 nm.

16. The display device according to claim 12, wherein: In the optical region, Formula 4 is satisfied, or at least one of Formula 5 or Formula 6 is satisfied: [Formula 4] T2 <T1<T EB In the formula 4, T EB is the triplet energy level of the electron blocking layer, T1 is the triplet energy level of the first light-emitting layer, and T2 is the triplet energy level of the second light-emitting layer, [Formula 5] <h2 style=";text-align:left;direction:ltr">L2 <L1<L <h2 style=";text-align:left;direction:ltr"> EB In the above formula 5, L EB is the lowest unoccupied molecular orbital energy level of the electron blocking layer, i.e., the LUMO energy level, L1 is the LUMO energy level of the first light-emitting layer, and L2 is the LUMO energy level of the second light-emitting layer, [Formula 6] H2 EB ​ In formula 6, H EB is the highest occupied molecular orbital energy level, ie, the HOMO energy level, of the electron blocking layer, H1 is the HOMO energy level of the first light-emitting layer, and H2 is the HOMO energy level of the second light-emitting layer.

17. The display device according to claim 16, wherein: The thickness of the first light-emitting layer is greater than or equal to 2 nm and less than or equal to 5 nm.

18. The display device according to claim 13, wherein: In the optical region, equations 7 and 8 are satisfied, or at least one of equations 9, 10, 11, and 12 is satisfied: [Formula 7] T1>T2 [Formula 8] T3>T2 In Formula 7 and Formula 8, T1 is the triplet energy level of the first light-emitting layer, T2 is the triplet energy level of the second light-emitting layer, and T3 is the triplet energy level of the third light-emitting layer, [Formula 9] T EB >T1>T2 In Formula 9, T1 is the triplet energy level of the first light-emitting layer, T2 is the triplet energy level of the second light-emitting layer, and T EB is the triplet energy level of the electron blocking layer, [Formula 10] <h2 style=";text-align:left;direction:ltr">T<h2 style=";text-align:left;direction:ltr"> HB <h2 style=";text-align:left;direction:ltr"> >T3>T2 In Formula 10, T2 is the triplet energy level of the second light-emitting layer, T3 is the triplet energy level of the third light-emitting layer, and T HB is the triplet energy level of the hole blocking layer, [Formula 11] L1>L2 In Formula 11, L1 is the lowest unoccupied molecular orbital energy level of the first light-emitting layer, that is, the LUMO energy level, and L2 is the LUMO energy level of the second light-emitting layer, [Formula 12] H1>H2 In Formula 12, H1 is the highest occupied molecular orbital energy level, ie, the HOMO energy level, of the first light-emitting layer, and H2 is the HOMO energy level of the second light-emitting layer.

19. The display device according to claim 18, wherein: The first light-emitting layer and the third light-emitting layer each have a thickness of 2 nm or more and 5 nm or less.

20. A display device, comprising: A common area, wherein a plurality of first sub-pixels are arranged in the common area; as well as an optical region, wherein a plurality of second sub-pixels are arranged in the optical region, wherein the number of the plurality of second sub-pixels per unit area in the optical region is smaller than the number of the plurality of first sub-pixels per unit area in the general region, wherein each of the plurality of first sub-pixels in the general area and the plurality of second sub-pixels in the optical area comprises a light emitting element, Wherein, the light emitting element comprises: A first electrode layer, located on the substrate; one or more stacks; and a second electrode layer, the second electrode layer being located on the one or more stacked layers, Wherein each of the one or more stacks comprises: a first light emitting layer, the first light emitting layer being located on the first electrode layer and comprising a first host in the general region and the optical region; and A second light emitting layer is located on the first light emitting layer, includes the first host in the general region, and includes a second host different from the first host in the optical region.

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