Display device and method of manufacturing display device

Abstract

The present disclosure may provide a display apparatus and a method of manufacturing the same. The display device includes: a substrate; a pixel electrode and a common electrode over the substrate and spaced apart from each other; and a light emitting element including: a first contact electrode over the pixel electrode; a second contact electrode over the common electrode; a semiconductor layer stack; a first protective layer stacked around the semiconductor layer in a plan view; a reflective layer on the first protective layer, stacked around the semiconductor layer in plan view, and not contacting the first contact electrode or the second contact electrode; and a second protective layer on the reflective layer and the first protective layer, and stacked around the semiconductor layer in a plan view.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0197248, filed with the Korean Intellectual Property Office on December 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background art

[0004] With the development of multimedia, the importance of display devices has been increasing day by day. In response to this, various types of display devices are being used, such as organic light - emitting displays (OLEDs) and liquid - crystal displays (LCDs).

[0005] A display device for displaying an image includes a display panel, such as an organic light - emitting display panel or a liquid - crystal display panel. Among them, a light - emitting display panel may include light - emitting elements, for example, light - emitting diodes (LEDs), organic light - emitting diodes (OLEDs) using an organic material as a light - emitting material, inorganic light - emitting diodes using an inorganic material as a light - emitting material, etc. Summary of the invention

[0006] Aspects of embodiments of the present disclosure provide a reflective layer on a side surface of a light - emitting element, which can improve the light - emitting efficiency of the light - emitting element on a base substrate, and aspects of embodiments of the present disclosure provide a method of manufacturing a display device and a display device formed thereby, in which the base substrate and the light - emitting element can be easily separated.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. Through reference to the following detailed description of the present disclosure, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0008] According to one or more embodiments, a display device includes: a substrate; a pixel electrode and a common electrode, which are above the substrate and spaced apart from each other; and a light - emitting element, including: a first contact electrode above the pixel electrode; a second contact electrode above the common electrode; a semiconductor layer stack; a first protective layer surrounding the semiconductor layer stack in a plan view; a reflective layer on the first protective layer, surrounding the semiconductor layer stack in a plan view, and not contacting the first contact electrode or the second contact electrode; and a second protective layer on the reflective layer and the first protective layer, and surrounding the semiconductor layer stack in a plan view.

[0009] The reflective layer may define an opening overlapping with the first contact electrode or the second contact electrode.

[0010] One end of the reflective layer may be adjacent to a side surface of the semiconductor layer stack and may have a height lower than the height of the semiconductor layer stack.

[0011] The semiconductor layer stack may include an undoped semiconductor layer, a second semiconductor layer, an active layer, a first semiconductor layer, and a current diffusion layer.

[0012] The reflective layer may be adjacent to side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer, and may be adjacent to a part of a side surface of the undoped semiconductor layer.

[0013] The second protective layer may cover one end of the reflective layer and may be in direct contact with the first protective layer.

[0014] The semiconductor layer stack may define an upwardly concave groove that passes through the current diffusion layer, the first semiconductor layer, the active layer, and a part of the second semiconductor layer, wherein a second contact electrode is in the groove and is electrically connected to the second semiconductor layer.

[0015] The first protective layer may be in direct contact with one surface of the semiconductor layer stack, may define a first opening and a second opening adjacent to another surface of the semiconductor layer stack, and may be adjacent to one side of the groove, wherein the second opening is adjacent to a bottom surface of the groove.

[0016] The reflective layer may not overlap with the first opening or the second opening, wherein the first contact electrode is electrically connected to the current diffusion layer through the first opening, and wherein the second contact electrode is electrically connected to the second semiconductor layer through the second opening.

[0017] The reflective layer may define an opening that overlaps with the first opening or the second opening.

[0018] The reflective layer may extend along a side surface of the groove.

[0019] According to one or more embodiments, a method of manufacturing a display device includes: forming a semiconductor layer stack by stacking semiconductor material layers on a base substrate and performing mesa patterning; forming a first protective material layer over the base substrate to cover the semiconductor layer stack; forming a photoresist over the base substrate; forming a reflective material layer that covers the photoresist and the semiconductor layer stack; removing the photoresist to form a reflective layer; forming a second protective material layer over the base substrate to cover the semiconductor layer stack and the reflective layer; and forming a light-emitting element by forming a first contact electrode electrically connected to the first semiconductor layer of the semiconductor layer stack and a second contact electrode electrically connected to the second semiconductor layer of the semiconductor layer stack over a top surface of the semiconductor layer stack.

[0020] The method may further include forming, by etching portions of a first protective material layer and a second protective material layer extending from the semiconductor layer stack to the underlying substrate, a first protective layer and a second protective layer surrounding the semiconductor layer stack in a plan view.

[0021] The method may further include forming an upwardly concave groove in the semiconductor layer stack by a local etching process.

[0022] The semiconductor layer stack may include an undoped semiconductor layer, a second semiconductor layer, an active layer, a first semiconductor layer, and a current diffusion layer, wherein the groove passes through the current diffusion layer, the first semiconductor layer, the active layer, and a portion of the second semiconductor layer.

[0023] The height of the photoresist may be lower than the height of the undoped semiconductor layer.

[0024] The reflective layer may not contact the first contact electrode or the second contact electrode.

[0025] Forming the photoresist over the underlying substrate may include forming the photoresist on the top surface of the semiconductor layer stack in a region overlapping the first contact electrode or a region overlapping the second contact electrode using a mask, wherein removing the photoresist includes forming an opening in the reflective material layer.

[0026] The reflective layer may extend along the inner side of the groove in the semiconductor layer stack.

[0027] When forming the second protective material layer, the second protective material layer may cover one end of the reflective layer and may directly contact the first protective material layer.

[0028] According to one or more embodiments, a reflective layer formed on a side surface of the light-emitting element may improve the emission efficiency of the light-emitting element on the underlying substrate and may facilitate separation of the underlying substrate and the light-emitting element, thereby reducing or preventing the possibility of non-separation or abnormal separation of the light-emitting element and the underlying substrate when the light-emitting element is transferred to a target substrate.

[0029] However, aspects of the present disclosure are not limited to the above effects, and various other aspects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0031] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0032] Figure 2 is a plan view showing a display panel according to one or more embodiments.

[0033] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0034] Figure 4 is an equivalent circuit diagram showing sub-pixels according to one or more embodiments.

[0035] Figure 5 is an equivalent circuit diagram showing sub-pixels according to one or more other embodiments.

[0036] Figure 6 is a plan view showing sub-pixels according to one or more embodiments.

[0037] Figure 7 is showing along Figure 6 a cross-sectional view of an example of a display panel taken along line X1-X1' in

[0038] Figure 8 is a cross-sectional view showing in detail Figure 7 example of region A of

[0039] Figures 9 to 13 is a cross-sectional view showing in detail examples of Figure 7 region A according to various embodiments of

[0040] Figure 14 is a flowchart showing a method of manufacturing a display device according to one or more embodiments.

[0041] Figures 15 to 29 is a diagram showing a method of manufacturing a display device according to one or more embodiments.

[0042] Figure 30 is a diagram showing a method for separating a light-emitting element from a base substrate according to one or more embodiments.

[0043] Figures 31 to 34 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0044] Figures 35 to 38 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0045] Figures 39 to 42 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0046] Figures 43 to 46 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0047] Figure 47FIG. is a diagram schematically showing a virtual reality device including a display device according to one or more embodiments.

[0048] Figure 48 FIG. is a diagram schematically showing a smart device including a display device according to one or more embodiments.

[0049] Figure 49 FIG. is a diagram schematically showing a vehicle including a display device according to one or more embodiments.

[0050] Figure 50 FIG. is a diagram schematically showing a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0051] Aspects of some embodiments of the present disclosure and methods of implementing them can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand aspects of the present disclosure may be omitted. Unless otherwise noted, in all the drawings and the written description, the same reference numerals, marks, or combinations thereof represent the same elements, and thus, their repeated description may be omitted.

[0052] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments illustrated herein. The use of "may", "can", or "may not" in the description of the embodiments corresponds to one or more embodiments of the present disclosure.

[0053] Considering the overall content of the present disclosure, those of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents, and substitutions within the spirit and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure may be partially or wholly combined with each other, and various interconnections and operations are possible technically, and each embodiment may be implemented independently of each other or may be implemented in association with each other, unless otherwise stated or implied.

[0054] In the drawings, for clarity and / or for the purpose of description, the relative dimensions of elements, layers, and regions may be exaggerated. Further, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a particular material, material property, dimension, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0055] In this document, various embodiments are described with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments in accordance with the concepts of the present disclosure. Thus, the embodiments disclosed herein should not be construed as being limited to the shapes shown of elements, layers, or regions, but should include, for example, deviations in shapes resulting from manufacturing.

[0056] For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0057] For ease of explanation, spatial relative terms such as "below", "beneath", "under", "underside", "underneath", "above", "on", "upper side", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element(s) or feature(s). It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath", or "underneath" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "underneath" can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this means that the first part is disposed at the upper side or the lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0058] In addition, the phrase "in a plan view" means when the object part is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object part is observed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" can include stacking, facing or facing each other, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The expression "not overlap" can include meanings such as "spaced apart from each other" or "offset from each other" or "separated from each other" and any other suitable equivalents as would be appreciated and understood by those of ordinary skill in the art. The terms "face" and "facing" can mean that the first object can be directly or indirectly opposite the second object. In the case where a third object is inserted between the first object and the second object, the first object and the second object can be understood to be indirectly opposite each other, although still facing each other.

[0059] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to", or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region or component, such that there can be one or more intervening elements, layers, regions or components. Further, this can collectively mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component, or directly on another component, without an intervening component.

[0060] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between", "directly between", or "adjacent to" and "directly adjacent to") can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intermediate elements or layers.

[0061] For the purposes of this disclosure, when located after a list of elements, expressions such as "at least one of...", "any one of...", or "one or more of..." modify the elements of the entire list rather than individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when located after a list of elements, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases modify the elements of the entire list rather than individual elements in the list.

[0062] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are only used to distinguish one element, member, component, region, zone, layer, section, or part from another element, member, component, region, zone, layer, section, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer, or first section described below may be referred to as a second element, second component, second region, second layer, or second section. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc. may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc. may respectively denote “first category (or first group),” “second category (or second group),” etc.

[0063] In an example, the DR1 axis, DR2 axis, and / or DR3 axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0064] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including” specify the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0065] When one or more embodiments can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the described order.

[0066] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of +5% / -5% of the corresponding value. Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0067] In some embodiments, in relation to one or more functional blocks (e.g., block diagrams), units, and / or modules, well-known structures and devices may be shown in the figures to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connectors, and other electronic circuits. This may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed with software and controlled to perform the various functions discussed herein, and may be selectively driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented by a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing functions different from those of the dedicated hardware. Further, in some embodiments, without departing from the scope of the present disclosure, the blocks, units, and / or modules may be physically separated into two or more interacting separate blocks, units, and / or modules. Additionally, in some embodiments, without departing from the scope of the present disclosure, the blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0069] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0070] Reference Figure 1 , the display device 10 is a device for displaying video or still images, such as mobile phones, smart phones, tablet personal computers, and portable electronic devices such as smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs), and display screens for various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0071] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using micro or nano light-emitting diodes (micro-LED or nano-LED). Hereinafter, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the embodiments are not limited thereto. At the same time, for ease of description, hereinafter, ultra-small light-emitting diodes are described as light-emitting elements. However, the type of light-emitting element that can be applied to the embodiments is not limited to ultra-small light-emitting diodes.

[0072] The display device 10 includes a display panel 100, a display driver 250, a circuit board 300, and a power supply circuit 500.

[0073] The display panel 100 may have a rectangular or square planar shape having sides extending in a first direction DR1 and sides extending in a second direction DR2 intersecting the first direction DR1. The corners where the sides in the first direction DR1 and the sides in the second direction DR2 intersect may be rounded to have a curvature (e.g., a predetermined curvature), or may be formed as right angles. The planar shape of the display panel 100 is not limited to a square shape. For example, the display panel 100 may have another polygon, circular, or elliptical planar shape. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having a constant or varying curvature. In one or more embodiments, the display panel 100 may be flexibly formed to be capable of bending, curving, folding, or curling.

[0074] The display panel 100 may include a main area MA and a sub-area SBA.

[0075] The main region MA may include a display region DA for displaying an image and a non-display region NDA that is a peripheral region of the display region DA. The display region DA may include a plurality of pixels for displaying an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0076] The sub-region SBA may protrude from one side in the second direction DR2 of the main region MA. Although Figure 1 the unfolded sub-region SBA is shown, the sub-region SBA may be bent, and in this case, the sub-region SBA may be located below the bottom surface of the display panel 100. When the sub-region SBA is bent, it may overlap with the main region MA in the third direction DR3 that is the thickness direction of the display panel 100. The display driver 250 may be located in the sub-region SBA.

[0077] The display driver 250 may generate signals and voltages for driving the display panel 100. The display driver 250 may be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. In one or more embodiments, the display driver 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0078] The circuit board 300 may be attached to the sub-region SBA of the display panel 100. In one or more embodiments, the circuit board 300 may be attached to a pad located at one end of the sub-region SBA of the display panel 100. Thus, the circuit board 300 may be electrically connected to the display panel 100 and the display driver 250. The display panel 100 and the display driver 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0079] The power supply circuit 500 may generate a panel driving voltage according to a power voltage provided from the outside. The power supply circuit 500 may be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0080] Figure 2 is a plan view showing a display panel according to one or more embodiments. Figure 2 The unfolded sub-region SBA without being bent is shown.

[0081] Reference Figure 1 and Figure 2 , the display panel 100 may include a main region MA and a sub-region SBA.

[0082] The main area MA may include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be located at the center of the main area MA.

[0083] The display area DA may include unit pixels PX for displaying an image, and each unit pixel PX may include a plurality of sub-pixels SPX (or pixels). The unit pixel PX may be defined as the smallest group of sub-pixels capable of representing a white gray level.

[0084] The non-display area NDA may be placed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged (e.g., in a plan view) to surround the display area DA. The non-display area NDA may be an edge area of the display panel 100.

[0085] The first scan driver SDC1 and the second scan driver SDC2 may be located in the non-display area NDA. The first scan driver SDC1 is located at one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 is located at the other side (e.g., the right side) of the display panel 100. However, it is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driver 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal from the display driver 250, may generate a scan signal according to the scan control signal, and may output the scan signal to the scan line.

[0086] The sub-area SBA may protrude from one side in the second direction DR2 of the main area MA. The length of the sub-area SBA in the second direction DR2 may be less than the length of the main area MA in the second direction DR2. The length of the first direction DR1 of the sub-area SBA is less than or substantially equal to the length of the first direction DR1 of the main area MA. The sub-area SBA may be curved, and thus a part of the sub-area SBA may be located below the main area MA. For example, the sub-area SBA may overlap the main area MA in the third direction DR3.

[0087] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0088] The connection area CA is an area that protrudes from one side in the second direction DR2 of the main area MA. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0089] The pad region PA is the region where the pad PD and the display driver 250 are located. The display driver 250 can be attached to the driving pads of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pad PD of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad region PA can be in contact with the bending region BA.

[0090] The bending region BA is a bent region. When the bending region BA is bent, the pad region PA can be located below the connection region CA and the main region MA. The bending region BA can be located between the connection region CA and the pad region PA. One side of the bending region BA can be in contact with the connection region CA, and the other side of the bending region BA can be in contact with the pad region PA.

[0091] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0092] Reference Figures 1 to 3 , the display area DA can be positioned to include unit pixels PX each including a sub-pixel SPX, scan lines SL connected to the sub-pixels SPX, emission control lines EL, and data lines DL.

[0093] The sub-pixels SPX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. The scan lines SL and the emission control lines EL can extend in the first direction DR1 and can be arranged in the second direction DR2. The data lines DL can extend in the second direction DR2 and can be arranged in the first direction DR1. The scan lines SL can include write scan lines GWL, control scan lines GCL, initialization scan lines GIL, and bias scan lines GBL located in each pixel row.

[0094] Each of the sub-pixels SPX can be connected to one or more of the write scan lines GWL, one or more of the control scan lines GCL, one or more of the initialization scan lines GIL, one or more of the bias scan lines GBL, one or more of the emission control lines EL, and one or more of the data lines DL. For example, each sub-pixel SPX can be respectively connected to the write scan line GWL, the control scan line GCL, the initialization scan line GIL, the bias scan line GBL, and the emission control line EL located in each pixel row and the data line DL located in each pixel column.

[0095] Each of the sub-pixels SPX can be provided with a data signal (e.g., a data voltage) of the data line DL according to a write scan signal provided through the write scan line GWL, and can operate a light-emitting element according to the data signal.

[0096] The non-display area NDA includes a first scan driver SDC1, a second scan driver SDC2, and a display driver 250.

[0097] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a light emission signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the light emission signal output unit 615 may receive a scan timing control signal SCS from the timing controller 251. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS of the timing controller 251, and may sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals according to the scan timing control signal SCS, and may sequentially output them to the control scan lines GCL. The initialization scan signal output unit 613 may generate initialization scan signals according to the scan timing control signal SCS, and may sequentially output them to the initialization scan lines GIL. The bias scan signal output unit 614 may generate bias scan signals according to the scan timing control signal SCS, and may sequentially output them to the bias scan lines GBL. The light emission signal output unit 615 may generate light emission control signals according to the scan timing control signal SCS, and may sequentially output them to the light emission control lines EL.

[0098] The display driver 250 may include a timing controller 251 and a data driver 252.

[0099] The timing controller 251 may receive video data DATA (e.g., digital video data) and a timing signal from an external source. The timing controller 251 may generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing controller 251 may output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing controller 251 may output the video data DATA and the data timing control signal DCS to the data driver 252.

[0100] The data driver 252 may receive video data DATA and a data timing control signal DCS from the timing controller 251. The data driver 252 may provide corresponding data signals (e.g., analog data voltages) to the sub-pixels SPX. For example, the data driver 252 may convert the video data DATA into analog data voltages according to the data timing control signal DCS and may output them to the data lines DL. The sub-pixels SPX may be selected by the write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data signals may be provided to the selected sub-pixels SPX.

[0101] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT and may provide them to the display panel 100.

[0102] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments.

[0103] Reference Figure 4 , according to one or more embodiments, the sub-pixel SPX may be connected to scan lines GWL, GIL, GCL, and GBL, an emission control line EL, and a data line DL. For example, the sub-pixel SPX may be connected to a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, an emission control line EL, and a data line DL.

[0104] According to one or more embodiments, the sub-pixel SPX includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6. The driving transistor DT, the switching element, and the capacitor C1 may be referred to as a pixel circuit PXC. The pixel circuit PXC may include a driving transistor DT, at least one switching element, and a capacitor C1. In one or more embodiments, the pixel circuit PXC may include the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 as the switching element. The configuration of the pixel circuit PXC is not limited to Figure 4 and Figure 5 the embodiments of, but may vary.

[0105] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current (hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0106] The light-emitting element LE can be a micro light-emitting diode. The light-emitting element LE emits light according to a driving current. The amount of light emitted from the light-emitting element LE can be proportional to the driving current. The anode electrode of the light-emitting element LE is connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode can be connected to the second power supply line VSL to which a second power supply voltage is applied. A parasitic capacitor Cel can be formed between the anode electrode and the cathode electrode of the light-emitting element LE.

[0107] A capacitor C1 is formed between the second electrode of the driving transistor DT and the first power supply line VDL to which a first power supply voltage is applied. The level of the first power supply voltage can be higher than the level of the second power supply voltage. One electrode of the capacitor C1 can be connected to the second electrode of the driving transistor DT, and the other electrode can be connected to the first power supply line VDL.

[0108] As Figure 4 shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, and the driving transistor DT can all be formed as p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can be formed of polysilicon.

[0109] The gate electrode of the second transistor ST2 can be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 can be connected to the control scan line GCL. The gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on when a scan signal and an emission signal of a low gate voltage are respectively applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the light emission control line EL. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 can be connected to the initialization voltage line VIL.

[0110] Figure 5 is an equivalent circuit diagram showing a sub-pixel according to one or more other embodiments.

[0111] Reference Figure 5, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of an oxide semiconductor may be disposed in different layers.

[0112] Since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal having a high gate voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal having a high gate voltage is applied to the initialization scan line GIL. In comparison, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, and thus they can be turned on when scan signals and emission signals having low gate voltages are applied to the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively.

[0113] Alternatively, Figure 4 the fourth transistor ST4 in [[ ]] may be formed of an n-type MOSFET. In this case, the active layer of each fourth transistor ST4 may be formed of an oxide semiconductor. When the fourth transistor ST4 is formed of an n-type MOSFET, it can be turned on when a bias scan signal having a high gate voltage is applied to the bias scan line GBL.

[0114] Alternatively, in one or more embodiments, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may all be formed as n-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may be formed of an oxide semiconductor.

[0115] Figure 6 is a plan view showing a sub-pixel according to one or more embodiments. For example, Figure 6 schematically shows a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 located in the display area DA.

[0116] Reference Figures 1 to 6 , each of the unit pixels PX located in the display area DA includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In one or more embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 constituting one unit pixel PX may be arranged in a first direction DR1, but is not limited thereto. For example, the arrangement of the sub-pixels SPX may vary according to the embodiment.

[0117] Figure 6 One or more embodiments are shown in which the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 constitute one unit pixel PX, but the embodiments are not limited thereto. For example, the type, number, or ratio of the sub-pixels SPX constituting each unit pixel PX may vary according to the embodiment.

[0118] In addition, in Figure 6 , the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 (or the light-emitting regions of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3) have substantially the same size and shape, but the embodiments are not limited thereto. For example, the size or shape of the sub-pixel SPX may vary according to the embodiment. For example, the size of the sub-pixel SPX may be appropriately adjusted according to the light efficiency of the sub-pixel SPX.

[0119] The first sub-pixel SPX1 may emit first light, the second sub-pixel SPX2 may emit second light, and the third sub-pixel SPX3 may emit third light. In one or more embodiments, the first light may be light in the blue wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the red wavelength band. In one example, the first light, the second light, and the third light may each be blue light having a peak wavelength in the range of about 440 nm to about 480 nm, green light having a peak wavelength in the range of about 510 nm to about 550 nm, and red light having a peak wavelength in the range of about 610 nm to about 650 nm. The color or wavelength band of the light emitted from each sub-pixel SPX may vary according to the embodiment.

[0120] The sub-pixels SPX may each include a pixel electrode PXE, a common electrode CE, and a light-emitting element LE. For example, the first sub-pixel SPX1 may include a first pixel electrode PXE1, a first common electrode CE1, and a first light-emitting element LE1. The second sub-pixel SPX2 may include a second pixel electrode PXE2, a second common electrode CE2, and a second light-emitting element LE2. The third sub-pixel SPX3 may include a third pixel electrode PXE3, a third common electrode CE3, and a third light-emitting element LE3.

[0121] The pixel electrode PXE and the common electrode CE of each sub-pixel SPX may be spaced apart from each other in each sub-pixel region. For example, the first pixel electrode PXE1 and the first common electrode CE1 may be spaced apart from each other in the light-emitting region of the first sub-pixel SPX1. The second pixel electrode PXE2 and the second common electrode CE2 may be spaced apart from each other in the light-emitting region of the second sub-pixel SPX2. The third pixel electrode PXE3 and the third common electrode CE3 may be spaced apart from each other in the light-emitting region of the third sub-pixel SPX3.

[0122] Each light-emitting element LE may be located on or bonded to the pixel electrode PXE and the common electrode CE. For example, the pixel electrode PXE and the common electrode CE may be bonding pads bonded to the corresponding light-emitting element LE. In one or more embodiments, the pixel electrode PXE and the common electrode CE may be metal electrodes including a metal suitable for bonding, but are not limited thereto.

[0123] Figure 6 One or more embodiments are shown in which each pixel electrode PXE and common electrode CE has a rectangular planar shape, but the embodiments are not limited thereto. In addition, although Figure 6 One or more embodiments are shown in which each pixel electrode PXE, light-emitting element LE, and common electrode CE are formed to have substantially the same size, but the embodiments are not limited thereto. For example, in different embodiments, the shapes and sizes of the pixel electrode PXE, light-emitting element LE, and common electrode CE located in each sub-pixel SPX may vary. The sub-pixels SPX may have pixel electrodes PXE and / or common electrodes CE of substantially the same size, or the sizes of the pixel electrodes PXE and / or common electrodes CE may vary for each sub-pixel SPX.

[0124] Each pixel electrode PXE may be connected to the pixel circuit PXC of the corresponding sub-pixel SPX through a corresponding first connection hole CT1. For example, the first pixel electrode PXE1 may be connected to the pixel circuit PXC of the first sub-pixel SPX1, the second pixel electrode PXE2 may be connected to the pixel circuit PXC of the second sub-pixel SPX2, and the third pixel electrode PXE3 may be connected to the pixel circuit PXC of the third sub-pixel SPX3.

[0125] Each common electrode CE can be connected to a second power line VSL to which a second driving voltage VSS is applied through a corresponding second connection hole CT2. For example, each of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 can be connected to the second power line VSL through a corresponding second connection hole CT2. Accordingly, the second driving voltage VSS can be applied to the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3.

[0126] Figure 6 One or more embodiments are shown in which the common electrodes CE of the sub-pixels SPX are separately separated, but the embodiments are not limited thereto. For example, the common electrodes CE among the plurality of sub-pixels SPX located in the display area DA can be formed as a unit to form a single common electrode CE.

[0127] In one or more embodiments, each light-emitting element LE may include a first contact electrode CTE1 connected to each pixel electrode PXE. In one or more embodiments, each light-emitting element LE may further include a second contact electrode CTE2 connected to each common electrode CE.

[0128] In an embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit light of different wavelengths. For example, the first light-emitting element LE1 may mainly emit first light, the second light-emitting element LE2 may mainly emit second light, and the third light-emitting element LE3 may mainly emit third light. In one or more embodiments, the first light may be light in a blue wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a red wavelength band.

[0129] Figure 7 is a cross-sectional view showing an example of a cross-section of a display panel taken along the line X1-X1' in Figure 6 is a cross-sectional view showing an example of the region A in Figure 8 is a cross-sectional view showing in detail an example of Figure 7 is a cross-sectional view showing an example of the region A in

[0130] Referring to Figure 7 and Figure 8 , the substrate SUB may be made of an insulating material such as glass, polymer resin, etc. If the substrate SUB is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0131] The barrier film BR may be located on the substrate SUB (as used herein, "located on" may mean "above"). The barrier film BR is a diaphragm for protecting the transistors of the thin film transistor layer TFTL from moisture that penetrates through the substrate SUB (which may be easily permeated by moisture). The barrier film BR may be composed of a plurality of inorganic films stacked alternately. For example, the barrier film BR may be formed as a multilayer of alternating inorganic films of one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0132] The first thin film transistor TFT1 may be located on the barrier film BR. The first thin film transistor TFT1 may be, for example, Figure 5 the fourth transistor ST4 or the sixth transistor ST6 shown in. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0133] The first active layer ACT1 of the first thin film transistor TFT1 may be located on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polysilicon, single crystal silicon, low temperature polysilicon, or amorphous silicon.

[0134] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region that overlaps with the first gate electrode G1 in a third direction DR3 that is the thickness direction of the substrate SUB. The first source region S1 may be located on one side of the first channel region CHA1, and the first drain region D1 may be located on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions in which the silicon semiconductor is doped with ions to make it conductive.

[0135] The first gate insulating film 131 may be located on / above the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1. The first gate insulating film 131 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0136] The first gate metal layer GTL1 may be located on the first gate insulating film 131. The first gate metal layer GTL1 may include the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 in the third direction DR3. In Figure 7In [the figure], the first gate electrode G1 and the first capacitor electrode CAE1 are shown as being positioned apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 can be connected to each other. The first gate metal layer GTL1 can be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0137] The second gate insulating film 132 can be located on the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The second gate insulating film 132 can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0138] The second gate metal layer GTL2 can be located on the second gate insulating film 132. The second gate metal layer GTL2 can include the second capacitor electrode CAE2. The second capacitor electrode CAE2 can overlap with the first capacitor electrode CAE1 in the third direction DR3. Because the second gate insulating film 132 has a dielectric constant (e.g., a predetermined dielectric constant), the capacitor ( Figure 5 C1 in [the figure]) can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating film 132 located therebetween. The second gate metal layer GTL2 can be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0139] The first interlayer insulating film 141 can be located on the second capacitor electrode CAE2. The first interlayer insulating film 141 can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0140] The second thin film transistor TFT2 can be located on the first interlayer insulating film 141. The second thin film transistor TFT2 can be, for example, Figure 5 the first transistor ST1 or the third transistor ST3 shown in [the figure]. The second thin film transistor TFT2 can include a second active layer ACT2 and a second gate electrode G2.

[0141] The second active layer ACT2 of the second thin film transistor TFT2 can be located on the first interlayer insulating film 141. The second active layer ACT2 can include an oxide semiconductor. For example, the second active layer ACT2 can include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0142] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in a third direction DR3. The second source region S2 may be located on one side of the second channel region CHA2, and the second drain region D2 may be located on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions in which an oxide semiconductor is doped with ions to make it conductive.

[0143] The third gate insulating film 133 may be located on the second active layer ACT2 of the second thin film transistor TFT2. The third gate insulating film 133 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0144] The third gate metal layer GTL3 may be located on the third gate insulating film 133. The third gate metal layer GTL3 may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap with the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0145] The second interlayer insulating film 142 may be located on the second gate electrode G2 of the second thin film transistor TFT2. The second interlayer insulating film 142 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0146] The first data metal layer DTL1 may be located on the second interlayer insulating film 142. The first data metal layer DTL1 may include a first connection electrode PCE1, a second connection electrode BE1, and a third connection electrode BE2. The first connection electrode PCE1 may be connected to a first drain region D1 of the first active layer ACT1 through a first contact hole PCT1 that passes through the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142. The second connection electrode BE1 may be connected to a second source region S2 of the second active layer ACT2 through a second contact hole BCT1 that passes through the third gate insulating film 133 and the second interlayer insulating film 142. The third connection electrode BE2 may be connected to a second drain region D2 of the second active layer ACT2 through a third contact hole BCT2 that passes through the third gate insulating film 133 and the second interlayer insulating film 142. The first data metal layer DTL1 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the first data metal layer DTL1 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0147] On the first connection electrode PCE1, on the second connection electrode BE1, and on the third connection electrode BE2, a first organic film 160 may be positioned to planarize the step difference caused by the first thin film transistor TFT1 and the second thin film transistor TFT2. The first organic film 160 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0148] The second data metal layer DTL2 (also referred to as the "second source-drain conductive layer") may be located on the first organic film 160. The second data metal layer DTL2 may include a fourth connection electrode PCE2. The fourth connection electrode PCE2 may be connected to the first connection electrode PCE1 through a fourth contact hole PCT2 that passes through the first organic film 160. The second data metal layer DTL2 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the second data metal layer DTL2 may include a first layer of titanium (Ti), a second layer of aluminum (Al), and a third layer of titanium (Ti).

[0149] The second organic film 180 may be located on the fourth connection electrode PCE2. The second organic film 180 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0150] The light-emitting element layer LEL may be located on the second organic film 180. The light-emitting element layer LEL may include a pixel electrode PXE, a common electrode CE, a light-emitting element LE, a bank 190, a third organic layer 191, and a first capping layer CAP1.

[0151] The pixel electrode PXE and the common electrode CE may be located on the second organic film 180. The pixel electrode PXE of each sub-pixel SPX may be connected to the fourth connection electrode PCE2 of the corresponding sub-pixel SPX through a first connection hole (e.g., CT1 in Figure 6 that penetrates the second organic film 180. The common electrode CE of each sub-pixel SPX may be connected to a second power line (e.g., VSL in Figure 6 through a second connection hole (e.g., CT2 in Figure 5 ).

[0152] In one or more embodiments, the pixel electrode PXE and the common electrode CE of each sub-pixel SPX may not overlap each other in the thickness direction (e.g., the third direction DR3) of the light-emitting element LE, and may overlap different parts of the light-emitting element LE. For example, the first pixel electrode PXE1 and the first common electrode CE1 may not overlap each other in the thickness direction of the first light-emitting element LE1 in the first sub-pixel SPX1. In addition, a part of the first light-emitting element LE1 may be located on the first pixel electrode PXE1, and another part of the first light-emitting element LE1 may be located on the first common electrode CE1.

[0153] The pixel electrode PXE and the common electrode CE may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the pixel electrode PXE and the common electrode CE may be formed as multiple layers of copper (Cu) or an alloy of titanium (Ti) and copper (Cu), which have a low surface resistance to reduce the resistance of each of the pixel electrode PXE and the common electrode CE.

[0154] The bank 190 may cover a part of each of the pixel electrode PXE and the common electrode CE. For example, the bank 190 may cover at least one edge of the pixel electrode PXE and the common electrode CE. The bank 190 may not be located on the remaining parts of the pixel electrode PXE and the common electrode CE. For example, the bank 190 may not be located on the central part of each of the pixel electrode PXE and the common electrode CE, and may be located on the edge where the pixel electrode PXE and the common electrode CE face each other.

[0155] The bank 190 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The bank 190 may include a light-blocking material to reduce or prevent light from the light-emitting element LE of one sub-pixel SPX from advancing to an adjacent sub-pixel SPX. For example, the bank 190 may include an inorganic black pigment such as carbon black or an organic black pigment.

[0156] Each light-emitting element LE may be located on the pixel electrode PXE and the common electrode CE. For example, a part of the light-emitting element LE disposed in the corresponding sub-pixel SPX may be located on the pixel electrode PXE of each sub-pixel SPX, and a different part of the light-emitting element LE disposed in the corresponding sub-pixel SPX may be located on the common electrode CE of each sub-pixel SPX. In one example, the first contact electrode CTE1 of each light-emitting element LE disposed in the sub-pixel SPX may be located on the pixel electrode PXE of each sub-pixel SPX, and the second contact electrode CTE2 of each of the light-emitting elements LE disposed in the corresponding sub-pixel SPX may be located on the common electrode CE of each sub-pixel SPX.

[0157] In Figure 7 and Figure 8 embodiments, each light-emitting element LE may be a flip-type micro-LED. A flip-type micro-LED may refer to an LED in which the first contact electrode CTE1 and the second contact electrode CTE2 are formed on one surface (e.g., the bottom surface) of the light-emitting element LE.

[0158] In one or more embodiments, each of the light-emitting elements LE may be formed of gallium nitride (GaN) or another inorganic material. In one or more embodiments, each of the light-emitting elements LE may be a micro-light-emitting diode having lengths in a first direction DR1, a second direction DR2, and a third direction DR3 that are each from several micrometers to several hundred micrometers. For example, the lengths of each of the light-emitting elements LE in the first direction DR1, the second direction DR2, and the third direction DR3 may each be about 100 μm or less.

[0159] Each of the light-emitting elements LE may be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The light-emitting element LE may be directly transferred from the semiconductor substrate onto the pixel electrode PXE and the common electrode CE of the display panel 100. Alternatively, the light-emitting element LE may be transferred onto the pixel electrode PXE and the common electrode CE of the display panel 100 by an electrostatic method using an electrostatic head or by a stamping method using an elastic polymeric material (such as PDMS or silicone) as a transfer substrate.

[0160] Each of the light-emitting elements LE may include a current spreading layer CSL, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, an undoped semiconductor layer USE, and a shell layer OSL. In one or more embodiments, the current spreading layer CSL may be omitted. In one or more embodiments, each of the light-emitting elements LE may further include at least one contact electrode CTE1 and CTE2. For example, each of the light-emitting elements LE may further include a first contact electrode CTE1 electrically connected to the current spreading layer CSL and a second contact electrode CTE2 in contact with the second semiconductor layer SEM2. In one or more embodiments, when the current spreading layer CSL is omitted, the first contact electrode CTE1 may be electrically connected to the first semiconductor layer SEM1.

[0161] The first contact electrode CTE1 may be located on the pixel electrode PXE of the sub-pixel SPX. For example, the first contact electrode CTE1 may be located between the pixel electrode PXE of the sub-pixel SPX and the first semiconductor layer SEM1 of the light-emitting element LE. The first contact electrode CTE1 may connect the first semiconductor layer SEM1 of the light-emitting element LE to the pixel electrode PXE of the sub-pixel SPX.

[0162] The second contact electrode CTE2 may be located on the common electrode CE of the sub-pixel SPX. For example, the second contact electrode CTE2 may be located between the common electrode CE of the sub-pixel SPX and the second semiconductor layer SEM2 of the light-emitting element LE. The second contact electrode CTE2 may connect the second semiconductor layer SEM2 of the light-emitting element LE to the common electrode CE of the sub-pixel SPX.

[0163] The first contact electrode CTE1 and the second contact electrode CTE2 may include a metal, a metal oxide, or other conductive material. In one example, the first contact electrode CTE1 and the second contact electrode CTE2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0164] The current spreading layer CSL is a layer that improves the light extraction efficiency and may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) to allow light to pass through.

[0165] The first semiconductor layer SEM1 may be located on the first contact electrode CTE1. In one or more embodiments, the first semiconductor layer SEM1 may be made of GaN doped with a first conductive type dopant (e.g., p-type dopant) (such as Mg, Zn, Ca, Ba, etc.).

[0166] The first semiconductor layer SEM1 can be electrically connected to the pixel electrode PXE of each sub-pixel SPX. For example, the first semiconductor layer SEM1 can be electrically connected to the pixel electrode PXE of each sub-pixel SPX through the first contact electrode CTE1.

[0167] The active layer MQW can be located on the first semiconductor layer SEM1. For example, the active layer MQW can be located between the first semiconductor layer SEM1 and the second semiconductor layer SEM2. According to the electrical signals applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2, the active layer MQW can emit light through the recombination of electron-hole pairs.

[0168] The active layer MQW can include materials having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes materials having a multi-quantum well structure, it can have a structure in which a plurality of well layers and barrier layers are alternately stacked. In one or more embodiments, the well layer can be formed of InGaN, and the barrier layer can be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer MQW can have a structure in which a semiconductor material having a high bandgap and a semiconductor material having a low bandgap are alternately stacked with each other, and can include other group III-V semiconductor materials according to the wavelength range of the emitted light.

[0169] When the active layer MQW includes InGaN, the color of the emitted light can vary according to the content of indium (In). For example, as the indium (In) content increases, the wavelength band of the light emitted by the active layer MQW can move to the red wavelength band, and as the indium (In) content decreases, the wavelength band of the light emitted by the active layer MQW can move to the blue wavelength band. For example, the indium (In) content in the active layer MQW of the light-emitting element LE that emits the third light (light in the blue wavelength band) can be about 10 wt% to about 20 wt%.

[0170] The second semiconductor layer SEM2 can be located on the active layer MQW. In one or more embodiments, the second semiconductor layer SEM2 can be n-GaN doped with a second conductive dopant (e.g., an n-type dopant) (such as Si, Ge, Se, Sn, etc.).

[0171] The second semiconductor layer SEM2 can be electrically connected to the common electrode CE of each sub-pixel SPX. For example, the second semiconductor layer SEM2 can be electrically connected to the common electrode CE of each sub-pixel SPX through the second contact electrode CTE2.

[0172] The undoped semiconductor layer USE can be located on the second semiconductor layer SEM2. The undoped semiconductor layer USE can be formed as a semiconductor layer undoped with an n-type dopant or a p-type dopant (e.g., an undoped semiconductor layer). For example, the undoped semiconductor layer USE can be any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN that is undoped with a dopant. For example, the undoped semiconductor layer USE can be GaN that is undoped with a dopant.

[0173] The electron blocking layer can be located between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer that inhibits or prevents too many electrons from flowing into the active layer MQW. For example, the electron blocking layer can be p-AlGaN doped with a p-type Mg. The thickness of the electron blocking layer can be from about 10 nm to about 50 nm. The electron blocking layer can be omitted.

[0174] The superlattice layer can be located between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be a layer for relieving the stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be formed of InGaN or GaN. The thickness of the superlattice layer can be from about 50 nm to about 200 nm. The superlattice layer can be omitted.

[0175] The light-emitting element LE has a groove HCTE on a surface that passes through the current diffusion layer CSL, the first semiconductor layer SEM1, and the active layer MQW and exposes one surface of the second semiconductor layer SEM2. The width or diameter of the groove HCTE can gradually increase from the second semiconductor layer SEM2 toward the current diffusion layer CSL. The second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 through the groove HCTE located in the current diffusion layer CSL, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2.

[0176] The encapsulation layer OSL can include a first protective layer INS1, a first reflective layer RF1, and a second protective layer INS2.

[0177] The first protective layer INS1 can cover the outer surface of the light-emitting element LE except for one surface (e.g., the top surface of the light-emitting element LE). For example, it can surround the side surfaces of the current diffusion layer CSL and the plurality of semiconductor layers and can be located on one side of the current diffusion layer CSL. In one or more embodiments, the first protective layer INS1 can be located on one side of the groove HCTE (e.g., on the inner side of or adjacent to the semiconductor layer).

[0178] The first protective layer INS1 may have two openings OP1 and OP2. The two openings OP1 and OP2 may be spaced apart from each other. The second opening OP2 may be arranged to overlap with the bottom of the groove HCTE. That is, the second semiconductor layer SEM2 may be exposed through the second opening OP2 and the groove HCTE of the first protective layer INS1.

[0179] The first protective layer INS1 may include a material having insulating properties, for example, an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), etc.

[0180] In one or more embodiments, the first protective layer INS1 may be made of a single layer or multiple layers of a material having insulating properties. The first protective layer INS1 may reduce or prevent the possibility of an electrical short circuit that may occur when the active layer MQW directly contacts the electrode (through which an electrical signal is transmitted to the light-emitting element LE). In addition, since the first protective layer INS1 protects the outer surface of the light-emitting element LE including the active layer MQW, a reduction in luminous efficiency can be reduced or prevented.

[0181] The first reflective layer RF1 is located on the first protective layer INS1, surrounds a part of the side surfaces of the current spreading layer CSL and the plurality of semiconductor layers, and may be located on one side of the current spreading layer CSL. For example, the first reflective layer RF1 may be formed to surround the side surfaces of the current spreading layer CSL and the plurality of semiconductor layers along the first protective layer INS1, but the first protective layer INS1 at both ends of the longitudinal side surfaces of the current spreading layer CSL and the plurality of semiconductor layers may be formed such that at least a part of the first protective layer INS1 is exposed.

[0182] The first reflective layer RF1 may be lower than the height of the first protective layer INS1. There is a step difference between one end of the first reflective layer RF1 and one end of the first protective layer INS1. For example, the first reflective layer RF1 may not be located on at least a part of the undoped semiconductor layer USE, or may not extend to at least a part of the undoped semiconductor layer USE.

[0183] The first reflective layer RF1 may not be electrically connected to at least one of the first contact electrode CTE1 and the second contact electrode CTE2. In one or more embodiments, the first reflective layer RF1 may have a third opening OP3, may cover the first opening OP1 of the first protective layer INS1, may extend to the side surface of the groove HCTE, and may overlap with the second opening OP2 of the first protective layer INS1. Refer to Figure 8, the first reflective layer RF1 can be electrically connected to the first contact electrode CTE1 and can be not electrically connected to the second contact electrode CTE2.

[0184] In one or more embodiments, the first reflective layer RF1 can include a metal material that is conductive and has a high light reflectivity. The first reflective layer RF1 can include, for example, aluminum (Al) or silver (Ag) and their alloys, and can include a single layer or multiple layers thereof. The multiple layers can be, for example, two layers of titanium / copper, two layers of titanium / aluminum, two layers of nickel / aluminum, two layers of silver / aluminum-silicon alloy, etc.

[0185] Alternatively, the first reflective layer RF1 can include M pairs of first and second layers having different refractive indices, where M is an integer greater than or equal to 2, to be used as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers can be alternately arranged. The first layer and the second layer can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0186] Meanwhile, an adhesive layer can be further located between the first reflective layer RF1 and the first protective layer INS1. The adhesive layer can be made of Cr, Ti, etc.

[0187] The second protective layer INS2 can be located on the first reflective layer RF1 and can be located on one side of the current spreading layer CSL and the multiple semiconductor layers. The second protective layer INS2 can directly contact the first protective layer INS1 on the first protective layer INS1 where the first reflective layer RF1 is not located. For example, the second protective layer INS2 can directly contact the first protective layer INS1 on one side of the undoped semiconductor layer USE. Thus, one end of the first reflective layer RF1 can be surrounded by the second protective layer INS2.

[0188] The second protective layer INS2 can include a fourth opening OP4 overlapping with the first opening OP1 of the first protective layer INS1 and a fifth opening OP5 overlapping with the second opening OP2 of the first protective layer INS1.

[0189] The second protective layer INS2 can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0190] The first contact electrode CTE1 and the second contact electrode CTE2 can contact the underlying layer through corresponding openings or grooves HCTE in the openings OP1, OP2, OP3, OP4, and OP5 of the outer shell layer OSL. In one or more embodiments, the first contact electrode CTE1 contacts the first reflective layer RF1 through the fourth opening OP4 of the second protective layer INS2, which will be described later, and the first reflective layer RF1 can contact the current spreading layer CSL through the first opening OP1 of the first protective layer INS1. The second semiconductor layer SEM2 can be exposed through the fifth opening OP5 of the second protective layer INS2, the third opening OP3 of the first reflective layer RF1, and the second opening OP2 of the first protective layer INS1. The second contact electrode CTE2 can be located in the opening exposing the second semiconductor layer SEM2 and can contact the second semiconductor layer SEM2.

[0191] The third organic layer 191 can cover the bank 190 and a part of the side surfaces of the plurality of light-emitting elements LE. The third organic layer 191 is a layer for planarizing the steps caused by the plurality of light-emitting elements LE. The third organic layer 191 can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0192] The first capping layer CAP1 can be located on the third organic layer 191 and the light-emitting elements LE. The first capping layer CAP1 can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0193] As Figure 7 shown, the light blocking layer BM, the light transmissive layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2 can be located on the first capping layer CAP1. However, the embodiments are not limited thereto, and a third light conversion layer can be positioned instead of the light transmissive layer TPL. In this case, the third light conversion layer can include a material different from the first light conversion layer QDL1 and the second light conversion layer QDL2. For example, the first light conversion layer QDL1 can include quantum dots that convert light in the blue wavelength band into light in the green wavelength band, the second light conversion layer QDL2 can include quantum dots that convert light in the blue wavelength band into light in the red wavelength band, and when the third light conversion layer is included, the third light conversion layer can include blue phosphors. In addition, each of the first light conversion layer QDL1, the second light conversion layer QDL2, and the third light conversion layer can include quantum dots and a light scattering agent such as titanium dioxide (TiO2). In this case, the number of titanium dioxide (TiO2) particles in the third light conversion layer can be greater than the number of titanium dioxide (TiO2) particles in the first light conversion layer QDL1 or the number of titanium dioxide (TiO2) particles in the second light conversion layer QDL2.

[0194] The light-transmitting layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2 may be formed in corresponding light-emitting regions separated by the light-blocking layer BM. For example, the light-transmitting layer TPL is located on the first capping layer CAP1 in the first sub-pixel SPX1, and the first light conversion layer QDL1 is located on the first capping layer CAP1 in the second sub-pixel SPX2, and the second light conversion layer QDL2 may be located on the first capping layer CAP1 in the third sub-pixel SPX3. The light-blocking layer BM may overlap with the bank 190 in the third direction DR3 and may not overlap with the light-emitting element LE.

[0195] The light-transmitting layer TPL may include a light-transmitting organic material. For example, the light-transmitting layer TPL may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0196] The first light conversion layer QDL1 may convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the second light (light in the green wavelength band). The first light conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The first wavelength conversion particles WCP1 may convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the second light (light in the green wavelength band). The first wavelength conversion particles WCP1 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The first light conversion layer QDL1 may further include a light-scattering agent such as titanium dioxide (TiO2).

[0197] The second light conversion layer QDL2 may convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the third light (light in the red wavelength band). The second light conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a light-transmitting organic material. For example, the second base resin BRS2 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The second wavelength conversion particles WCP2 may convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the third light (light in the red wavelength band). The second wavelength conversion particles WCP2 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The second light conversion layer QDL2 may further include a light-scattering agent such as titanium dioxide (TiO2).

[0198] The light blocking layer BM may include a first light blocking layer BM1 and a second light blocking layer BM2 stacked in sequence. The length of the first light blocking layer BM1 in the first direction DR1 or the second direction DR2 may be greater than the length of the second light blocking layer BM2 in the first direction DR1 or the second direction DR2. The first light blocking layer BM1 and the second light blocking layer BM2 may include an organic film formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. For example, the first light blocking layer BM1 and the second light blocking layer BM2 may include an inorganic black pigment or an organic black pigment such as carbon black.

[0199] The second capping layer CAP2 may be located on the first capping layer CAP1 and the light blocking layer BM. The second capping layer CAP2 may be located on the side surface and the top surface of the light blocking layer BM. That is, the second capping layer CAP2 may be located on the side surfaces of the first light blocking layer BM1 and the second light blocking layer BM2 and the top surface. The second capping layer CAP2 protects the first wavelength conversion particles WCP1 of the first light conversion layer QDL1 and the second wavelength conversion particles WCP2 of the second light conversion layer QDL2 from moisture penetration, and thus may surround the bottoms and side surfaces of the first light conversion layer QDL1 and the second light conversion layer QDL2.

[0200] The second reflective layer RF2 may be located between the light blocking layer BM and the light transmissive layer TPL, between the light blocking layer BM and the first light conversion layer QDL1, and between the light blocking layer BM and the second light conversion layer QDL2. The second reflective layer RF2 may be located on the second capping layer CAP2 positioned on one side of the first light blocking layer BM1 and one side of the second light blocking layer BM2. The second reflective layer RF2 is used to reflect the light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmissive layer TPL.

[0201] The second reflective layer RF2 may include a highly reflective metal material such as aluminum (Al). The thickness of the second reflective layer RF2 may be about 0.1 μm.

[0202] Alternatively, the second reflective layer RF2 may include M pairs of a first layer and a second layer having different refractive indexes, where M is an integer greater than or equal to 2, to be used as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be alternately arranged. The first layer and the second layer may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0203] The third capping layer CAP3 can be located on the second capping layer CAP2, the light-transmitting layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2. The third capping layer CAP3 can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The light-transmitting layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2 can be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3. The refractive index of the third capping layer CAP3 can be lower than the refractive index of the second capping layer CAP2. In addition, the refractive index of the third capping layer CAP3 can be lower than the refractive index of the fourth organic layer 192.

[0204] The fourth organic layer 192 can be located on the third capping layer CAP3. The fourth organic layer 192 can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0205] The color filter can be located on the fourth organic layer 192. The color filter can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. However, the embodiments are not limited thereto. For example, when the light-emitting element LE of the first sub-pixel SPX1 emits light of a first color, the light-emitting element LE of the second sub-pixel SPX2 emits light of a second color, and the light-emitting element LE of the third sub-pixel SPX3 emits light of a third color, the light-transmitting layer TPL, the first light conversion layer QDL1, the second light conversion layer QDL2, and / or the light-blocking layer BM can be omitted. In addition, in this case, the fourth organic layer 192 can be located on the first capping layer CAP1, and the color filter can be located on the fourth organic layer 192, or the color filter can be omitted.

[0206] The first color filter CF1 can be located in the first sub-pixel SPX1. The first color filter CF1 can transmit first light (e.g., light in a blue wavelength band). For example, the first color filter CF1 can transmit the first light emitted from the light-emitting element LE and passing through the light-transmitting layer TPL. Thus, the first sub-pixel SPX1 can emit the first light.

[0207] The second color filter CF2 can be located in the second sub-pixel SPX2. The second color filter CF2 can transmit second light (e.g., light in a green wavelength band) and can absorb or block the first light. For example, the second color filter CF2 can transmit the second light converted by the first light conversion layer QDL1 in the first light emitted from the light-emitting element LE and can absorb or block the first light not converted by the first light conversion layer QDL1.

[0208] The third color filter CF3 may be located in the third sub-pixel SPX3. The third color filter CF3 may transmit third light (e.g., light in a red wavelength band) and may absorb or block the first light. For example, the third color filter CF3 may transmit the third light converted from the first light emitted by the light-emitting element LE by the second light conversion layer QDL2 and may absorb or block the first light not converted by the second light conversion layer QDL2. Accordingly, the third sub-pixel SPX3 may emit the third light.

[0209] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may block external light incident from the outside. For example, the third color filter CF3 may improve the color purity (color chroma) of the third light corresponding to the red wavelength band by blocking the first light and the second light incident from the outside, where the first light is light in a blue wavelength band and the second light is light in a green wavelength band.

[0210] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may overlap the bank 190 and the light blocking layer BM in the third direction DR3.

[0211] A fifth organic layer 193 for planarization may be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The fifth organic layer 193 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0212] Figures 9 to 13 is a cross-sectional view showing an example of region A according to various embodiments in detail Figure 7 of.

[0213] In Figures 9 to 13 , the arrangement, number, and position of the openings of the first reflective layer RF1 are different from the arrangement, number, and position of the openings of the first reflective layer RF1 of Figure 8 , and a repetitive description redundant with one or more embodiments corresponding to Figure 8 is omitted.

[0214] Refer to Figure 9 and Figure 10, the first reflective layer RF1 can be located on top of the first protective layer INS1 and can be located on one side of the current spreading layer CSL while surrounding a part of the sides of the current spreading layer CSL and the plurality of semiconductor layers. The first reflective layer RF1 can be lower than the height of the first protective layer INS1. One end of the first reflective layer RF1 and one end of the first protective layer INS1 have a step difference. For example, the first reflective layer RF1 may not be located on at least a part of the undoped semiconductor layer USE. The third opening OP3-1 of the first reflective layer RF1 can be located at a position overlapping with the first opening OP1 of the first protective layer INS1. The diameter of the third opening OP3-1 of the first reflective layer RF1 can be wider than the diameter of the first opening OP1 of the first protective layer INS1. The third opening OP3-1 of the first reflective layer RF1 can have a step difference with the first opening OP1 of the first protective layer INS1.

[0215] The second protective layer INS2 can have a fourth opening OP4-1 overlapping with the third opening OP3-1.

[0216] As Figure 9 and Figure 10 shown in, the first reflective layer RF1 can be surrounded by the first protective layer INS1 and the second protective layer INS2. Therefore, the first contact electrode CTE1 may not be electrically connected to the first reflective layer RF1. As Figure 9 shown in, the second protective layer INS2 can be disposed along the third opening OP3-1 of the first reflective layer RF1. Alternatively, as Figure 10 shown in, the second protective layer INS2 can be positioned along the side of the third opening OP3-1 of the first reflective layer RF1 and the side of the first opening OP1 of the first protective layer INS1, but not at the bottom of the first opening OP1 to expose the current spreading layer CSL. Therefore, the first contact electrode CTE1 can be electrically connected to the first semiconductor layer SEM1 by directly contacting the current spreading layer CSL via the first opening OP1, the third opening OP3-1, and the fourth opening OP4-1.

[0217] In addition, the first reflective layer RF1 can extend along the side of the trench HCTE and can cover the second opening OP2 of the first protective layer INS1. Therefore, the first reflective layer RF1 can directly contact the exposed second semiconductor layer SEM2 through the second opening OP2. The first reflective layer RF1 can be electrically connected to the second contact electrode CTE2 at a position overlapping with the second opening OP2 of the first protective layer INS1.

[0218] As Figure 11 and Figure 12As shown, the first reflective layer RF1 may have two openings that respectively overlap with the first opening OP1 and the second opening OP2 of the first protective layer INS1. In addition, the first reflective layer RF1 may be completely surrounded by the first protective layer INS1 and the second protective layer INS2.

[0219] As Figure 11 shown, the first reflective layer RF1 may define a third opening OP3-1 and a sixth opening OP6.

[0220] The sixth opening OP6 of the first reflective layer RF1 may overlap with the second opening OP2 of the first protective layer INS1.

[0221] The second protective layer INS2 is positioned along the sides of the third opening OP3-1 of the first reflective layer RF1 and the sides of the first opening OP1 of the first protective layer INS1, but not at the bottom of the first opening OP1 (e.g., the bottom of the current spreading layer CSL) to expose the current spreading layer CSL. Thus, the first contact electrode CTE1 can be electrically connected to the first semiconductor layer SEM1 that is in direct contact with the current spreading layer CSL through the first opening OP1, the third opening OP3-1, and the fourth opening OP4-1.

[0222] The second protective layer INS2 is positioned along the sides of the sixth opening OP6 of the first reflective layer RF1, but not at the bottom of the sixth opening OP6 to expose the second semiconductor layer SEM2. Thus, the second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 through the second opening OP2, the sixth opening OP6, and the fifth opening OP5.

[0223] Referring Figure 12 , the first reflective layer RF1 may be different from Figure 11 in that it is not located on the side of the trench HCTE. Thus, the sides of the trench HCTE can be in direct contact with the first protective layer INS1 and the second protective layer INS2.

[0224] Referring Figure 13 , the first reflective layer RF1 may be different from Figure 8 in that it does not overlap with the second contact electrode CTE2. Thus, the sides of the trench HCTE can be in direct contact with the first protective layer INS1 and the second protective layer INS2.

[0225] Referring Figures 7 to 13, the first reflective layer RF1 has a step in the longitudinal direction of the first protective layer INS1, the second protective layer INS2, and the light-emitting element LE. The first reflective layer RF1 may be spaced apart from a member (e.g., the first capping layer CAP1) located on the upper surface of the light-emitting element LE in the thickness direction. Accordingly, the first reflective layer RF1 does not directly contact a member such as the first capping layer CAP1 located on the upper surface of the light-emitting element LE.

[0226] Hereinafter, a manufacturing process of the display device 10 according to one or more embodiments will be described with reference to other drawings.

[0227] Figure 14 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments. Figures 15 to 29 is a diagram illustrating a method of manufacturing a display device according to one or more embodiments. Figure 30 is a diagram illustrating a method of separating a light-emitting element from a base substrate according to one or more embodiments.

[0228] Figures 15 to 29 A cross-sectional view of a structure showing the formation order of each layer of the display device 10 is shown. Figures 15 to 29 illustrates a manufacturing process of the light-emitting element layer LEL of the display device 10, which may respectively roughly correspond to Figure 8 the cross-sectional view. In addition, the following will focus on the first sub-pixel SPX1 of the display device 10. Hereinafter, in combination with Figure 14 description Figures 15 to 29 the method of manufacturing a display device shown in

[0229] Reference Figure 14 , a manufacturing method of the display device 10 according to one or more embodiments may include: stacking a plurality of semiconductor material layers on a base substrate and forming a plurality of semiconductor layer stacks by mesa patterning (S100); forming a first protective material layer on the base substrate to cover the plurality of semiconductor layer stacks (S110); forming a first reflective layer on the base substrate using a photoresist (S120); forming a second protective material layer on the base substrate to cover the plurality of semiconductor layer stacks and the first reflective layer (S130); forming a first contact electrode electrically connected to the first semiconductor layer and a second contact electrode electrically connected to the second semiconductor layer on the top surface of the plurality of semiconductor layer stacks (S140); and transferring the light-emitting element onto the pixel electrode and the common electrode of the circuit board (S150).

[0230] First, referring to Figures 15 to 17 , a plurality of semiconductor material layers are stacked on a base substrate BSUB and the plurality of semiconductor material layers are mesa-patterned to form a plurality of semiconductor layer stacks ( Figure 14in S100).

[0231] Reference Figure 15 , a base substrate BSUB is prepared. The base substrate BSUB can be a sapphire substrate (Al2O3) or a silicon wafer including silicon. However, it is not limited thereto, and in one or more embodiments, the case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0232] A plurality of semiconductor material layers are formed on the base substrate BSUB. The plurality of semiconductor material layers grown by an epitaxial method can be formed by a growth seed crystal. The methods for forming the semiconductor material layers include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metalorganic chemical vapor deposition (MOCVD), etc., and the plurality of semiconductor material layers can be formed by metalorganic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0233] Within the range that can be conventionally selected for forming the subject material, the precursor material for forming the plurality of semiconductor material layers is not particularly limited. In one example, the precursor material can be a metal precursor including an alkyl group (such as a methyl or ethyl group). For example, it can be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), or triethyl phosphate ((C2H5)3PO4), but it is not limited thereto.

[0234] For example, a third semiconductor material layer USEL is formed on the base substrate BSUB. Although the drawings show a single layer of the third semiconductor material layer USEL, it is not limited thereto, and multiple layers can be formed. The third semiconductor material layer USEL can reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer USEL can include an undoped semiconductor, which can be an n-type or p-type undoped material. In one or more embodiments, the third semiconductor material layer USEL can be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but it is not limited thereto.

[0235] The second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer USEL by using the above method. Next, a current spreading material layer CSLL is formed on the first semiconductor material layer SEM1L.

[0236] Next, reference Figure 16 , a downwardly concave groove HCTE is formed in the plurality of semiconductor material layers by an etching process.

[0237] The concave groove HCTE penetrates through the current spreading material layer CSLL, the first semiconductor material layer SEM1L, and the active material layer MQWL, and is formed on the second semiconductor material layer SEM2L to be concave in the downward direction. To this end, a plurality of first mask patterns are formed on the current spreading material layer CSLL. The first mask pattern may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern reduces or prevents the possibility of the semiconductor material layer being etched. Next, the groove HCTE can be formed by etching (first etching) a part of the plurality of semiconductor material layers using the plurality of first mask patterns as masks.

[0238] The semiconductor material layer can be etched by a conventional method. For example, the process of etching the semiconductor material layer can be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of the dry etching method, anisotropic etching is possible and can be suitable for vertical etching. When using the above etching methods, the etchant for etching can be Cl2 or O2. However, it is not limited thereto.

[0239] Next, referring to Figure 17 , the plurality of semiconductor material layers are etched into a mesa shape to form a plurality of semiconductor layer stacks. The plurality of semiconductor layer stacks may include an undoped semiconductor layer USE, a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, and a current spreading layer CSL stacked in sequence.

[0240] To this end, a plurality of second mask patterns are formed on the current spreading material layer CSLL. The second mask pattern may be a hard mask including an inorganic material or a photoresist mask including an organic material. The second mask pattern reduces or prevents the possibility of the semiconductor material layer being etched. Then, a part of the plurality of semiconductor material layers is etched (second etching) using the plurality of second mask patterns as masks to form a semiconductor layer stack.

[0241] On the base substrate BSUB, the parts of the semiconductor material layer and the current spreading material layer CSLL that do not overlap with the second mask pattern are etched and removed, and the parts that are not etched due to overlapping with the second mask pattern can be formed into a plurality of semiconductor layer stacks.

[0242] Next, referring to Figure 18 and Figure 19 , a first protective material layer INS1L ([S110 in Figure 14 ) having a first opening OP1 and a second opening OP2 is formed on the base substrate BSUB on which the semiconductor layer stack including the groove HCTE is formed.

[0243] For example, a protective material layer is formed on the outer surface of the semiconductor layer stack. The protective material layer can be formed on the entire surface of the base substrate BSUB, and can be formed not only on the semiconductor layer stack, but also on the top surface of the base substrate BSUB exposed by the semiconductor layer stack.

[0244] Next, etching is performed to partially remove the protective material layer to form a first protective material layer INS1L having a first opening OP1 and a second opening OP2 on the top surface of the semiconductor layer stack. The second opening OP2 can be located in the center of the trench HCTE. In this process, a part of the first protective material layer INS1L can be removed to expose the top surfaces of the current diffusion layer CSL and the second semiconductor layer SEM2. The part of the first protective material layer INS1L at the center of the trench HCTE can be removed to expose the second semiconductor layer SEM2. The process of partially removing the protective material layer can be performed by anisotropic dry etching followed by an etch-back process, but is not limited thereto.

[0245] Next, referring to Figures 20 to 23 , a first reflective layer RF1 having a desired height is formed on the first protective material layer INS1L using a first photoresist PR1.

[0246] For example, referring to Figure 20 , a first photoresist PR1 is applied to cover the top surfaces of the plurality of semiconductor layers USE, SEM2, MQW, and SEM1 and the current diffusion layer CSL to planarize them. Then, the first photoresist PR1 is partially exposed to expose a part of the top surfaces and side surfaces of the plurality of semiconductor layers USE, SEM2, MQW, and SEM1 and the current diffusion layer CSL. For example, according to this, the first photoresist PR1 can be partially removed to at least expose the side surface and the top surface of the light-emitting element LE. The first photoresist PR1 remaining from this process can partially have a thickness of about 3 μm on the base substrate BSUB, but is not limited thereto.

[0247] Next, referring to Figure 21 and Figure 23 , a first reflective layer RF1 (S120 in Figure 14 ) is formed on the base substrate BSUB using the first photoresist PR1.

[0248] Meanwhile, the adhesive layer can be further formed to overlap with the plurality of semiconductor layers and be between the first protective material layer INS1L and the first reflective material layer RF1L. The adhesive layer can be made of Cr, Ti, etc. When the first photoresist PR1 is removed in a subsequent process, the adhesive layer can reduce or prevent the possibility of the first reflective layer RF1 being peeled off. If the adhesive layer is used in this way, the adhesive layer can remain between the first protective layer INS1 and the first reflective layer RF1 of the already manufactured light-emitting element LE.

[0249] First, referring to Figure 21 , a first reflective material layer RF1L is formed on the first photoresist PR1 where a part of the plurality of semiconductor layer stacks is exposed. The first reflective material layer RF1L can be deposited by a process such as filling, but is not limited thereto. For example, the first reflective material layer RF1L formed on the first photoresist PR1 is removed by a lift-off process. The lift-off process can be performed, for example, by jetting high-pressure water.

[0250] Then, referring to Figure 22 , the first photoresist PR1 remaining on the base substrate BSUB is removed by lift-off or ashing. In another example, a second photoresist protecting the plurality of semiconductor layer stacks can be applied on the plurality of semiconductor layer stacks, and the first reflective material layer RF1L formed on the first photoresist PR1 can be removed by an etching process.

[0251] Therefore, the first reflective layer RF1 can be formed on the first protective layer INS1 to at least surround the outer surface of the plurality of semiconductor layer stacks and be spaced apart from the sapphire substrate. In addition, the first reflective layer RF1 contacts the first semiconductor layer SEM1 through the first opening OP1, and the first reflective layer RF1 contacts the second semiconductor layer SEM2 through the second opening OP2.

[0252] Then, referring to Figure 23 , the first reflective layer RF1 in the second opening OP2 is etched using a mask. Therefore, a third opening OP3 of the first reflective layer RF1 can be formed so that the second semiconductor layer SEM2 can be exposed.

[0253] Next, referring to Figures 24 to 26 , a second protective layer INS2 is formed on the base substrate BSUB to cover the plurality of semiconductor layer stacks and the first reflective layer RF1 (S130 in Figure 14 ).

[0254] First, referring to Figure 24 , a second protective material layer INS2L is formed on the base substrate BSUB to cover the plurality of semiconductor layer stacks and the first reflective layer RF1. The method of forming the second protective material layer INS2L can be the same as the manufacturing process of the first protective material layer INS1L.

[0255] Next, referring to Figure 25 , the fourth opening OP4 and the fifth opening OP5 are formed to overlap with the first opening OP1 and the second opening OP2, respectively. For example, the fourth opening OP4 overlaps with the first opening OP1, and the fifth opening OP5 overlaps with the second opening OP2. Accordingly, the fourth opening OP4 exposes the first reflective layer RF1, and the fifth opening OP5 exposes the second semiconductor layer SEM2.

[0256] The process of forming the fourth opening OP4 and the fifth opening OP5 may be the same as the process of forming the first opening OP1 and the second opening OP2. For example, etching may be performed to partially remove the second protective material layer INS2L to form the fourth opening OP4 and the fifth opening OP5 that expose a part of the plurality of stacked semiconductor layers and the first reflective layer RF1.

[0257] Next, referring to Figure 26 , the first protective material layer INS1L and the second protective material layer INS2L on the base substrate BSUB except for the plurality of stacked semiconductor layers are etched and partially removed. By this process, in the light-emitting element transfer process described later, the light-emitting element can be easily separated from the base substrate BSUB.

[0258] Next, referring to Figure 27 , a first contact electrode CTE1 electrically connected to the first semiconductor layer SEM1 and a second contact electrode CTE2 electrically connected to the second semiconductor layer SEM2 are formed on the top surface of the plurality of stacked semiconductor layers (S140 in Figure 14 ).

[0259] After the electrode material layer is stacked on the entire surface of the base substrate BSUB to cover the fourth opening OP4 and the fifth opening OP5, a part of the electrode material layer is etched by an etching process to form the first contact electrode CTE1 overlapping with the fourth opening OP4 and the second contact electrode CTE2 overlapping with the fifth opening OP5. The first contact electrode CTE1 contacts the first reflective layer RF1 through the fourth opening OP4. Since the first reflective layer RF1 contacts the current diffusion layer CSL through the first opening OP1, the first contact electrode CTE1 can be electrically connected to the first semiconductor layer SEM1. The second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 through the fifth opening OP5, the third opening OP3, and the second opening OP2 formed in the groove HCTE.

[0260] Next, referring to Figure 28 and Figure 29 , the light-emitting element LE is transferred onto the first pixel electrode PXE1 and the first common electrode CE1 of the circuit board (S150 in Figure 14 ).

[0261] Transfer the light-emitting element LE of the base substrate BSUB fabricated in Figure 27 to a target substrate. In one or more embodiments, for ease of explanation, the target substrate is described as a circuit board, but it is not limited thereto. For example, the target substrate may be an intermediate substrate.

[0262] Align the light-emitting element LE of the base substrate BSUB to a desired position on the target substrate. For example, the first contact electrode CTE1 may be located on the first pixel electrode PXE1 of the circuit board, and the second contact electrode CTE2 may be located on the first common electrode CE1. Then, as Figure 29 shown, irradiate the base substrate BSUB with a laser beam through a laser device LS to separate the light-emitting element LE from the base substrate BSUB. The base substrate BSUB is separated from each undoped semiconductor layer USE of the plurality of light-emitting elements LE.

[0263] The process of separating the base substrate BSUB can be completed using a laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (e.g., having a wavelength of about 248 nm) can be used as the source. The energy density of the excimer laser is in the range of about 550 mJ / cm 2 to 950 mJ / cm 2 and the incident area can be in the range of about 50×50 μm 2 to about 1×1 cm 2 , but is not limited thereto. By irradiating the base substrate BSUB with a laser, the base substrate BSUB can be separated from the light-emitting element LE.

[0264] On the other hand, referring to Figure 30 , when the first protective material layer INS1L, the first reflective material layer RF1L, and the second protective material layer INS2L remain on the base substrate BSUB, abnormal separation or non-separation of the light-emitting element LE may occur when separating the light-emitting element LE from the base substrate BSUB. In addition, one end of the first reflective layer RF1 may be exposed and may react with a chemical solution during subsequent processes, thereby degrading the characteristics of the light-emitting element LE. For example, chemicals may penetrate from the outside of the first reflective layer RF1 to form voids, or the first reflective layer RF1 in contact with the chemicals may be deformed.

[0265] Next, as Figure 8 shown, form a third organic layer 191 on the substrate SUB on which the light-emitting element LE is formed. The third organic layer 191 may cover the dam 190 and a part of the side surfaces of the plurality of light-emitting elements LE. The third organic layer 191 can be formed by applying using a solution process (such as spin coating, inkjet printing, etc.) and patterning using an exposure process.

[0266] Then, as shown in Figure 7 , a first capping layer CAP1, a light blocking layer BM, a light transmissive layer TPL, a first light conversion layer QDL1, and a second light conversion layer QDL2 are formed on the light emitting element LE and the third organic layer 191, such that a display device 10 according to one or more embodiments can be manufactured.

[0267] Figures 31 to 34 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0268] Referring to Figure 19 , a process of forming a first reflective layer RF1 after a process of forming a first protective material layer INS1L defining a first opening OP1 and a second opening OP2 on a plurality of semiconductor layer stacks will be described.

[0269] First, referring to Figure 31 and Figure 32 , a first photoresist PR1 is applied to cover the plurality of semiconductor layer stacks, and the first photoresist PR1 is planarized. Then, the first photoresist PR1 is partially exposed using a mask pattern. The first photoresist PR1 can be a negative photoresist. The negative photoresist can remain as a first mask MS1 on a first portion overlapping the first opening OP1 of the plurality of semiconductor layer stacks. In addition, a portion of the first photoresist PR1 can be removed to expose at least a portion of the plurality of semiconductor layer stacks. The first photoresist PR1 remaining from this process can partially have a thickness of about 3 μm on the base substrate BSUB, but is not limited thereto.

[0270] Referring to Figure 33 , a first reflective material layer RF1L is deposited on the entire surface of the base substrate BSUB to cover the plurality of semiconductor layer stacks and the first photoresist PR1 on which the first mask MS1 is formed.

[0271] Then, referring to Figure 34 , the first photoresist PR1 and the first mask MS1 are removed. Through this process, a first reflective layer RF1 having a third opening OP3 overlapping the first opening OP1 can be formed on the outer surface of the plurality of semiconductor layer stacks. The first reflective layer RF1 can contact the second contact electrode CTE2 and can not contact the first contact electrode CTE1.

[0272] Figures 35 to 38 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0273] Referring to Figure 19, a process of forming a first reflective layer RF1 after forming a first protective material layer INS1L having a first opening OP1 and a second opening OP2 on a stack of multiple semiconductor layers will be described.

[0274] First, referring to Figure 35 , a first photoresist PR1 is applied to cover the stack of multiple semiconductor layers, and the first photoresist PR1 is planarized.

[0275] Then, referring to Figure 36 , the first photoresist PR1 is partially exposed using a mask pattern. The first photoresist PR1 can be a negative photoresist. The negative photoresist can remain as a second mask MS2 on a second portion overlapping the second opening OP2 of the stack of multiple semiconductor layers. The second mask MS2 can overlap with a trench HCTE and can be formed to fill the trench HCTE.

[0276] In addition, a portion of the first photoresist PR1 can be removed to expose at least a portion of the stack of multiple semiconductor layers. The first photoresist PR1 remaining from this process can partially have a thickness of approximately 3 μm on the base substrate BSUB, but is not limited thereto.

[0277] Referring to Figure 37 , a first reflective material layer RF1L is deposited on the entire surface of the base substrate BSUB to cover the stack of multiple semiconductor layers and the first photoresist PR1 on which the second mask MS2 is formed.

[0278] Then, referring to Figure 38 , the first photoresist PR1 and the second mask MS2 are removed. Through this process, a first reflective layer RF1 defining a third opening OP3-3 overlapping the second opening OP2 can be formed on the outer surface of the stack of multiple semiconductor layers. The first reflective layer RF1 is not located in the trench HCTE. The first reflective layer RF1 can contact a subsequently positioned first contact electrode CTE1, and the first reflective layer RF1 can not contact a second contact electrode CTE2.

[0279] Figures 39 to 42 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0280] Referring to Figure 19 , a process of forming a first reflective layer RF1 after forming a first protective material layer INS1L having a first opening OP1 and a second opening OP2 on a stack of multiple semiconductor layers will be described.

[0281] First, referring to Figure 39 and Figure 40, apply and planarize a first photoresist PR1 to cover a plurality of semiconductor layer stacks. Then, partially expose the first photoresist PR1 using a mask pattern. The first photoresist PR1 can be a negative photoresist. The negative photoresist can remain as a first mask MS1 on a first portion overlapping with a first opening OP1 of the plurality of semiconductor layer stacks. In addition, a second mask MS2 can remain on a second portion overlapping with a second opening OP2 of the plurality of semiconductor layer stacks. The second mask MS2 can be formed to overlap with and fill a trench HCTE.

[0282] In addition, a portion of the first photoresist PR1 can be removed to expose at least a portion of the plurality of semiconductor layer stacks. The first photoresist PR1 remaining from this process can partially have a thickness of approximately 3 μm on a base substrate BSUB, but is not limited thereto.

[0283] Reference Figure 41 , deposit a first reflective material layer RF1L on the entire surface of the base substrate BSUB to cover the first photoresist PR1 and the plurality of semiconductor layer stacks on which the first mask MS1 and the second mask MS2 are formed.

[0284] Then, reference Figure 42 , remove the first photoresist PR1, the first mask MS1, and the second mask MS2. In this process, a first reflective layer RF1 having a third opening OP3-4 overlapping the first opening OP1 and a sixth opening OP6 overlapping the second opening OP2 can be formed on the outer surface of the plurality of semiconductor layer stacks. The first reflective layer RF1 is not located in the trench HCTE. The first reflective layer RF1 can be not in contact with a first contact electrode CTE1 and a second contact electrode CTE2 subsequently located thereon.

[0285] Figures 43 to 46 is a diagram for forming a first reflective layer according to one or more other embodiments.

[0286] Reference Figure 19 , a process of forming a first reflective layer RF1 after forming a first protective material layer INS1L having a first opening OP1 and a second opening OP2 on a plurality of semiconductor layer stacks will be described.

[0287] First, reference Figure 43 and Figure 44 , apply a first photoresist PR1 to cover a plurality of semiconductor layer stacks, and planarize the first photoresist PR1. Then, partially expose the first photoresist PR1 using a mask pattern. The first photoresist PR1 can be a negative photoresist. The mask pattern can expose one side of the plurality of semiconductor layer stacks including the trench HCTE.

[0288] The negative photoresist can be left as the third mask MS3 to overlap with the trench HCTE of the stacked multiple semiconductor layers, and can cover one side of the stacked multiple semiconductor layers. In addition, the third mask MS3 can be formed to overlap with the trench HCTE and fill the trench HCTE.

[0289] In addition, a part of the first photoresist PR1 can be removed to expose at least a part of the stacked multiple semiconductor layers. The first photoresist PR1 remaining from this process can partially have a thickness of about 3 μm on the base substrate BSUB, but is not limited thereto.

[0290] Reference Figure 45 , a first reflective material layer RF1L is deposited on the entire surface of the base substrate BSUB to cover the stacked multiple semiconductor layers and the first photoresist PR1 on which the third mask MS3 is formed.

[0291] Then, reference Figure 46 , the first photoresist PR1 and the third mask MS3 are removed. Through this process, a first reflective layer RF1 exposing the trench HCTE and one side of the stacked multiple semiconductor layers can be formed on the outer surface of the stacked multiple semiconductor layers. The first reflective layer RF1 is not located in the trench HCTE. The first reflective layer RF1 can contact the subsequently positioned first contact electrode CTE1 and can not contact the second contact electrode CTE2.

[0292] Figure 47 is a diagram showing a virtual reality device including a display device according to one or more embodiments. Figure 47 A virtual reality device 1 in which a display device 10 according to one or more embodiments is used is shown.

[0293] Reference Figure 47 , a virtual reality device 1 according to one or more embodiments can be a device in the form of glasses. A virtual reality device 1 according to one or more embodiments can include a display device 10, a left eye lens 10a, a right eye lens 10b, a support frame 20, a left leg 30a and a right leg 30b, a reflection member 40, and a display device housing 50.

[0294] Figure 47 A virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. A virtual reality device 1 according to one or more embodiments can be used in a head-mounted display including a head-mounted band that can be worn on the head instead of the legs 30a and 30b. For example, a virtual reality device 1 according to one or more embodiments can be not limited to Figure 47 the example shown in, and can be applied to various forms and various electronic devices.

[0295] The display device housing 50 can accommodate the display device 10 and the reflection member 40. An image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the user's right eye through the right-eye lens 10b. Accordingly, the user can view a virtual reality image displayed on the display device 10 through the right eye.

[0296] Figure 47 It is shown that the display device housing 50 is located at the right end of the support frame 20. However, one or more embodiments of the present disclosure are not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20. In this case, an image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the user's left eye via the left-eye lens 10a. Accordingly, the user can view a virtual reality image displayed on the display device 10 through the left eye. As another example, the display device housing 50 may be located at each of the left and right ends of the support frame 20. In this case, the user can view a virtual reality image displayed on the display device 10 through both the left and right eyes.

[0297] Figure 48 FIG. is a diagram showing a smart device including a display device according to one or more embodiments.

[0298] Reference Figure 48 , the display device 10 according to one or more embodiments can be applied to a smart watch 2 which is one of smart devices.

[0299] Figure 49 FIG. is a diagram showing a vehicle including a display device according to one or more embodiments. Figure 49 It shows a vehicle in which a display device according to one or more embodiments is used.

[0300] Reference Figure 49 , the display devices 10_a, 10_b, and 10_c according to one or more embodiments can be applied to an instrument panel of a vehicle, applied to a center instrument panel of the vehicle, or applied to a CID (Central Information Display) located on the instrument panel of the vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments can be applied to each in-vehicle mirror display instead of each side-view mirror of the vehicle.

[0301] Figure 50 FIG. is a diagram showing a transparent display device including a display device according to one or more embodiments.

[0302] Reference Figure 50, the display device 10 according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light through it while displaying an image IM thereon. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10, but also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to the transparent display device, Figure 7 the substrate SUB of the display device 10 shown in

[0303] may include a light-transmitting portion through which light can be transmitted, or may be made of a material through which light can be transmitted. At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. Display equipment, including: substrate; a pixel electrode and a common electrode, over the substrate and spaced apart from each other; as well as Light-emitting element, comprising: A first contact electrode, above the pixel electrode; a second contact electrode, above the common electrode; Semiconductor layer stacking; A first protective layer stacked around the semiconductor layer in a plan view; a reflective layer, on the first protective layer, stacked around the semiconductor layer in a plan view, and not contacting the first contact electrode or the second contact electrode; and A second protective layer is on the reflective layer and the first protective layer and is stacked around the semiconductor layer in a plan view.

2. The display device according to claim 1, wherein: The reflective layer defines an opening overlapping the first contact electrode or the second contact electrode.

3. The display device according to claim 1, wherein: One end of the reflective layer is adjacent to a side surface of the semiconductor layer stack and has a height lower than that of the semiconductor layer stack.

4. The display device according to claim 3, wherein: The semiconductor layer stack includes an undoped semiconductor layer, a second semiconductor layer, an active layer, a first semiconductor layer and a current diffusion layer.

5. The display device according to claim 4, wherein: The reflective layer is adjacent to side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer, and is adjacent to a portion of a side surface of the undoped semiconductor layer.

6. The display device according to claim 3, wherein: The second protection layer covers one end of the reflective layer and directly contacts the first protection layer.

7. The display device according to claim 4, wherein: The semiconductor layer stack defines an upwardly concave groove that passes through the current diffusion layer, the first semiconductor layer, the active layer, and a portion of the second semiconductor layer, and The second contact electrode is in the groove and electrically connected to the second semiconductor layer.

8. The display device according to claim 7, wherein: The first protective layer directly contacts one surface of the semiconductor layer stack, defines a first opening and a second opening adjacent to another surface of the semiconductor layer stack, and is adjacent to one side of the groove, and Wherein, the second opening is adjacent to the bottom surface of the groove.

9. The display device according to claim 8, wherein: The reflective layer does not overlap with the first opening or the second opening, wherein the first contact electrode is electrically connected to the current diffusion layer through the first opening, and The second contact electrode is electrically connected to the second semiconductor layer through the second opening.

10. The display device according to claim 8, wherein: The reflective layer defines an opening overlapping with the first opening or the second opening.

11. The display device according to claim 8, wherein: The reflective layer extends along the side surfaces of the groove.

12. A method for manufacturing a display device, comprising: forming a semiconductor layer stack by stacking semiconductor material layers on a base substrate and performing mesa patterning; forming a first protective material layer over the base substrate to cover the semiconductor layer stack; forming a photoresist over the base substrate; forming a reflective material layer covering the photoresist and the semiconductor layer stack; removing the photoresist to form a reflective layer; forming a second protective material layer over the base substrate covering the semiconductor layer stack and the reflective layer; as well as A light emitting element is formed by forming a first contact electrode electrically connected to a first semiconductor layer of the semiconductor layer stack and a second contact electrode electrically connected to a second semiconductor layer of the semiconductor layer stack over a top surface of the semiconductor layer stack.

13. The method according to claim 12, further comprising forming a first protective layer and a second protective layer surrounding the semiconductor layer stack in a plan view by etching portions of the first protective material layer and the second protective material layer extending from the semiconductor layer stack to the base substrate. The method of claim 12 , further comprising forming an upwardly concave groove in the semiconductor layer stack by a local etching process.

15. The method according to claim 14, wherein: The semiconductor layer stack includes an undoped semiconductor layer, the second semiconductor layer, an active layer, the first semiconductor layer and a current diffusion layer, and The groove passes through the current diffusion layer, the first semiconductor layer, the active layer and a portion of the second semiconductor layer.

16. The method according to claim 15, wherein: The height of the photoresist is lower than the height of the undoped semiconductor layer.

17. The method according to claim 16, wherein: The reflective layer does not contact the first contact electrode or the second contact electrode.

18. The method according to claim 17, wherein: forming the photoresist over the base substrate includes forming the photoresist on the top surface of the semiconductor layer stack at a region overlapping the first contact electrode or a region overlapping the second contact electrode using a mask, and Wherein, removing the photoresist includes forming an opening in the reflective material layer.

19. The method according to claim 14, wherein: The reflective layer extends along inner sides of the trenches in the semiconductor layer stack.

20. The method according to claim 12, wherein: When the second protective material layer is formed, the second protective material layer covers one end of the reflective layer and directly contacts the first protective material layer.

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