Display device with connection wiring

Abstract

A display apparatus is provided. In the display device, each of the pixel regions may be electrically connected to the pad region through the connection wiring. The pixel region may be disposed in the active region. The pad region may be disposed outside the active region. The connection wiring may include a first connection, a second connection, and a third connection. The first connection may be disposed proximate to the pad region. The second connection may be electrically connected to the first connection. The third connection may be electrically connected to the second connection. The second connection may include a first end electrically connected to the first connection and a second end electrically connected to the third connection. The second end of the second connection may be disposed closer to the pad region than the first end of the second connection. Accordingly, in the display device, a distance between the pad region and the active region may be minimized.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0197028, filed on December 29, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device in which each of pixel regions is electrically connected to a pad region through one of connection wirings. Background art

[0004] Generally, a display device provides an image to a user. For example, the display device may include a plurality of pixel regions. Each of the pixel regions may implement a specific color. Various signals may be provided to each pixel region through signal wirings. The pixel regions may be disposed within an active region. For example, a pad region to which an external signal is applied may be disposed outside the active region.

[0005] Connection wirings may be disposed between the active region and the pad region. For example, each of the pixel regions may be electrically connected to the pad region through one of the connection wirings. The number of connection wirings may be proportional to the resolution of the display device. The distance between adjacent connection wirings may be a certain distance or greater to prevent distortion of signals applied through each connection wiring. Accordingly, in the display device, the area occupied by the connection wirings may increase as the resolution increases. Accordingly, in the display device, the distance between the active region and the pad region may increase. Summary of the invention

[0006] Accordingly, the present disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0007] One object of the present disclosure is to provide a display device capable of minimizing the distance between an active region and a pad region.

[0008] Another object of the present disclosure is to provide a display device in which the distance between adjacent connection wirings can be maintained at a certain distance or greater, and the area occupied by the connection wirings between the active region and the pad portion can be minimized.

[0009] Additional advantages, objects, and features of the present disclosure will be partly set forth in the description below, and partly will become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and claims of the present disclosure and the accompanying drawings.

[0010] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device including a device substrate is provided. The device substrate includes an active region and a border region. A pad region is provided on the border region of the device substrate. A display device is provided on the pixel region of the active region. Connecting wirings are provided between the pad region and the active region. The connecting wirings electrically connect the pixel region to the pad region. The connecting wirings include a first connection, a second connection, and a third connection. The first connection is electrically connected to the pad region. The second connection is electrically connected to the first connection. The third connection is electrically connected to the second connection. The second end of the second connection electrically connected to the third connection is arranged closer to the pad region than the first end of the second connection electrically connected to the first connection.

[0011] The pad region may be spaced apart from the active region in a first direction. The second end of the second connection may be spaced apart from the first end of the second connection in a second direction. The second direction may be perpendicular to the first direction.

[0012] The second connection may be provided on a different layer from the first connection. The third connection may be provided on a different layer from the second connection.

[0013] The second connection may include a different material from the first connection. The third connection may include a different material from the second connection.

[0014] The display device may be electrically connected to a driving circuit. The driving circuit may include a thin film transistor. The thin film transistor may be provided on the pixel region. A light blocking pattern may be provided between the device substrate and the semiconductor pattern of the thin film transistor. The first connection may be provided on the same layer as the light blocking pattern. The second connection may be provided on the same layer as the drain electrode of the thin film transistor. The third connection may be provided on the same layer as the gate electrode of the thin film transistor.

[0015] The first connection may include the same material as the light blocking pattern. The second connection may include the same material as the drain electrode. The third connection may include the same material as the gate electrode.

[0016] The third connection may be electrically connected to the driving circuit through a signal wiring. The signal wiring may be provided on the same layer as the drain electrode.

[0017] The display device may include a light emitting unit provided between a first electrode and a second electrode.

[0018] In another embodiment, a display device including a device substrate is provided. A driving circuit and a display device are disposed on a pixel region of the device substrate. The driving circuit of each pixel region is electrically connected to the display device of the corresponding pixel region. Connection wirings are disposed on a border region of the device substrate. The driving circuit of each pixel region is electrically connected to a pad region through one of the connection wirings. Each of the connection wirings includes a first connection, a second connection, and a third connection. The first connection is disposed to be close to the pad region. The second connection is electrically connected to the first connection. The third connection is electrically connected to the second connection. An angle between the first connection and the second connection is an acute angle.

[0019] An angle between the first connection and the second connection in each connection wiring may be proportional to a distance between the first connection of the corresponding connection wiring and a central region of the pad region.

[0020] The driving circuit of each pixel region may include a thin film transistor. A gate electrode of the thin film transistor may be disposed between the device substrate and a semiconductor pattern of the thin film transistor. The display device of each pixel region may include a pixel electrode and a common electrode. The pixel electrode of each pixel region may be electrically connected to a source electrode of the thin film transistor in the corresponding pixel region. The common electrode of each pixel region may be disposed between the device substrate and the pixel electrode of the corresponding pixel region.

[0021] The second connection may be disposed on the same layer as the source electrode. At least one of the first connection and the third connection may be disposed on the same layer as the common electrode.

[0022] The first connection of each connection wiring may be electrically connected to the pad region through one of output lines. The output lines may be disposed on a layer different from the first connection, the second connection, and the third connection.

[0023] The output lines may be disposed on the same layer as the gate electrode.

[0024] A distance between third connections of adjacent connection wirings may be greater than a distance between first connections of the corresponding connection wirings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0026] Figure 1 is a view schematically showing a display device according to an embodiment of the present disclosure;

[0027] Figure 2 is a view showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure;

[0028] Figure 3 is a view schematically showing a cross-section of a pixel region in a display device according to an embodiment of the present disclosure;

[0029] Figure 4 is Figure 1 an enlarged view of the K region in;

[0030] Figure 5 is a view taken along Figure 4 I-I' in; and

[0031] Figures 6 to 11 is a view showing a display device according to another embodiment of the present disclosure. Detailed Embodiments

[0032] Hereinafter, details related to the above objects, technical configurations, and operational effects of the embodiments of the present disclosure will be clearly understood through the following detailed description with reference to the drawings showing some embodiments of the present disclosure. Here, embodiments of the present disclosure are provided so that the technical spirit of the present disclosure can be satisfactorily conveyed to those skilled in the art, and thus the present disclosure can be embodied in other forms and is not limited to the embodiments described below.

[0033] In addition, throughout the specification, the same or extremely similar elements may be denoted by the same reference numerals, and in the drawings, for convenience, the lengths and thicknesses of layers and regions may be enlarged. It will be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to be in contact with the second element, a third element may be inserted between the first element and the second element.

[0034] Here, terms such as, for example, "first" and "second" may be used to distinguish any one element from another element. However, without departing from the technical spirit of the present disclosure, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art.

[0035] The terms used in the specification of the present disclosure are only used to describe specific embodiments and are not intended to limit the scope of the present disclosure. For example, an element described in the singular form is intended to include a plurality of elements unless the context clearly indicates otherwise. In addition, in the specification of the present disclosure, it will be further understood that the terms "comprising" and "including" indicate the presence of the claimed features, integers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations.

[0036] Moreover, unless the term "directly" is used, the terms "connected" and "coupled" can include that the two components are "connected" or "coupled" through one or more other components located between the two components.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0038] (Embodiment)

[0039] Figure 1 is a view schematically showing a display device according to an embodiment of the present disclosure. Figure 2 is a view showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure.

[0040] Referring to Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, a plurality of pixel regions PA may be provided in the display panel DP. Various signals may be provided in each pixel region PA through signal wirings GL, DL, and PL. For example, the signal wirings GL, DL, and PL may include a gate line GL for applying a gate signal, a data line DL for applying a data signal, and a power voltage supply line PL for supplying a power voltage. The gate line GL may be electrically connected to a gate driver GD. The data line DL may be electrically connected to a data driver. The power voltage supply line PL may be electrically connected to a power unit.

[0041] Each of the pixel regions PA may implement a specific color. For example, a driving circuit DC electrically connected to the display device 300 may be provided in each pixel region PA. The driving circuit DC of each pixel region PA may be electrically connected to the signal wirings GL, DL, and PL. For example, the driving circuit DC of each pixel region PA may be electrically connected to one of the gate lines GL, one of the data lines DL, and one of the power voltage supply lines PL. The driving circuit DC of each pixel region PA may supply a driving current corresponding to the data signal to the display device 300 of the corresponding pixel region PA according to the gate signal of one frame. For example, the driving circuit DC of each pixel region PA may include a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst.

[0042] Figure 3is a view schematically showing a cross-section of a pixel region in a display device according to an embodiment of the present disclosure.

[0043] Referring to Figure 2 and Figure 3 , the first thin film transistor TR1 may transfer a data signal to the second thin film transistor TR2 according to a gate signal. For example, the first thin film transistor TR1 may function as a switching thin film transistor. The first thin film transistor TR1 may include a first semiconductor pattern, a first gate electrode, a first drain electrode, and a first source electrode. For example, the first gate electrode may be electrically connected to a corresponding gate line GL, and the first drain electrode may be electrically connected to a corresponding data line DL.

[0044] The first semiconductor pattern may include a semiconductor material. For example, the first semiconductor pattern may include amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an oxide semiconductor such as IGZO. The first semiconductor pattern may include a first drain region, a first channel region, and a first source region. The first channel region may be disposed between the first drain region and the first source region. The resistance of the first drain region and the resistance of the first source region may be less than the resistance of the first channel region. For example, the first drain region and the first source region may include conductive regions of an oxide semiconductor. The first channel region may be a non-conductive region of the oxide semiconductor.

[0045] The first gate electrode may be disposed on a part of the first semiconductor pattern. For example, the first gate electrode may overlap with the first channel region of the first semiconductor pattern. The first drain region and the first source region of the first semiconductor pattern may be disposed outside the first gate electrode. The first gate electrode may include a conductive material. For example, the first gate electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first gate electrode may be spaced apart from the first semiconductor pattern. The first gate electrode may be insulated from the first semiconductor pattern. For example, the first drain region of the first semiconductor pattern may be electrically connected to the first source region of the first semiconductor pattern according to a signal applied to the first gate electrode.

[0046] The first drain electrode may include a conductive material. For example, the first drain electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode may include a material different from that of the first gate electrode. For example, the first drain electrode may be disposed on a layer different from the first gate electrode. The first drain electrode may be electrically connected to the first drain region of the first semiconductor pattern. The first drain electrode may be insulated from the first gate electrode.

[0047] The first source electrode may include a conductive material. For example, the first source electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode may include a material different from that of the first gate electrode. The first source electrode may be disposed on a layer different from that of the first gate electrode. For example, the first source electrode may be disposed on the same layer as the first drain electrode. The first source electrode may include the same material as the first drain electrode. The first source electrode may be formed by the same process as the first drain electrode. For example, the first source electrode may be formed simultaneously with the first drain electrode. The first source electrode may be electrically connected to the first source region of the first semiconductor pattern. The first source electrode may be insulated from the first gate electrode. The first source electrode may be spaced apart from the first drain electrode.

[0048] The second thin film transistor TR2 may generate a driving current corresponding to a data signal. For example, the second thin film transistor TR2 may be used as a driving thin film transistor. The second thin film transistor TR2 may include a second semiconductor pattern 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. For example, the second gate electrode 223 may be electrically connected to the first source electrode, and the second drain electrode 225 may be electrically connected to a corresponding power voltage supply line PL.

[0049] The second semiconductor pattern 221 may include a semiconductor material. For example, the second semiconductor pattern 221 may include amorphous silicon (a-Si), polysilicon (poly-Si), or an oxide semiconductor such as IGZO. The second semiconductor pattern 221 may include the same material as the first semiconductor pattern. The second semiconductor pattern 221 may be disposed on the same layer as the first semiconductor pattern. The second semiconductor pattern 221 may be formed by the same process as the first semiconductor pattern. For example, the second semiconductor pattern 221 may be formed simultaneously with the first semiconductor pattern.

[0050] The second semiconductor pattern 221 may include a second drain region, a second channel region, and a second source region. The second channel region may be disposed between the second drain region and the second source region. The second drain region and the second source region may have a lower resistance than the second channel region. For example, the second drain region and the second source region may include conductive regions of an oxide semiconductor. The second channel region may be a non-conductive region of the oxide semiconductor.

[0051] The second gate electrode 223 may be disposed on a part of the second semiconductor pattern 221. For example, the second gate electrode 223 may overlap with a second channel region of the second semiconductor pattern 221. A second drain region and a second source region of the second semiconductor pattern 221 may be disposed outside the second gate electrode 223. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second gate electrode 223 may be spaced apart from the second semiconductor pattern 221. The second gate electrode 223 may be insulated from the second semiconductor pattern 221. For example, the second channel region of the second semiconductor pattern 221 may have an electrical conductivity corresponding to the voltage applied to the second gate electrode 223.

[0052] The second gate electrode 223 may include the same material as the first gate electrode. The second gate electrode 223 may be disposed on the same layer as the first gate electrode. The second gate electrode 223 may be formed by the same process as the first gate electrode. For example, the second gate electrode 223 may be formed simultaneously with the first gate electrode.

[0053] The second drain electrode 225 may include a conductive material. For example, the second drain electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode 225 may include a different material from the second gate electrode 223. For example, the second drain electrode 225 may be disposed on a different layer from the second gate electrode 223. The second drain electrode 225 may be electrically connected to the second drain region of the second semiconductor pattern 221. The second drain electrode 225 may be insulated from the second gate electrode 223.

[0054] The second drain electrode 225 may include the same material as the first drain electrode. The second drain electrode 225 may be disposed on the same layer as the first drain electrode. The second drain electrode 225 may be formed by the same process as the first drain electrode. For example, the second drain electrode 225 may be formed simultaneously with the first drain electrode.

[0055] The second source electrode 227 may include a conductive material. For example, the second source electrode 227 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 227 may include a material different from that of the second gate electrode 223. The second source electrode 227 may be disposed on a layer different from that of the second gate electrode 223. For example, the second source electrode 227 may be disposed on the same layer as the second drain electrode 225. The second source electrode 227 may include the same material as the second drain electrode 225. The second source electrode 227 may be formed by the same process as the second drain electrode 225. For example, the second source electrode 227 may be formed simultaneously with the second drain electrode 225. The second source electrode 227 may be electrically connected to the second source region of the second semiconductor pattern 221. The second source electrode 227 may be insulated from the second gate electrode 223. The second source electrode 227 may be spaced apart from the second drain electrode 225.

[0056] The storage capacitor Cst may hold the voltage applied to the second gate electrode 223 for one frame. For example, the storage capacitor Cst may be electrically connected to the second gate electrode 223 and the second source electrode 227 of the second thin film transistor TR2. The storage capacitor Cst may have a stacked structure of capacitor electrodes 251, 252, and 253. For example, the storage capacitor Cst includes a second capacitor electrode 252 disposed on the first capacitor electrode 251 and a third capacitor electrode 253 disposed on the second capacitor electrode 252.

[0057] At least one of the capacitor electrodes 251, 252, and 253 of the storage capacitor Cst may be formed by using the process for forming the first thin film transistor TR1 and the second thin film transistor TR2. For example, the second capacitor electrode 252 may be disposed on the same layer as the second gate electrode 223, and the third capacitor electrode 253 may be disposed on the same layer as the second source electrode 227. The second capacitor electrode 252 may be electrically connected to the second gate electrode 223, and the third capacitor electrode 253 may be electrically connected to the second source electrode 227. The second capacitor electrode 252 may include the same material as the second gate electrode 223, and the third capacitor electrode 253 may include the same material as the second source electrode 227. The second capacitor electrode 252 may be formed by the same process as the second gate electrode 223, and the third capacitor electrode 253 may be formed by the same process as the second source electrode 227. For example, the second capacitor electrode 252 may be formed simultaneously with the second gate electrode 223, and the third capacitor electrode 253 may be formed simultaneously with the second source electrode 227.

[0058] The driving circuit DC of each pixel region PA can be provided on the device substrate 100. For example, the first thin film transistor TR1, the second thin film transistor TR2, and the storage capacitor Cst of each pixel region PA can be supported by the device substrate 100. The device substrate 100 can include an insulating material. For example, the device substrate 100 can include glass or plastic.

[0059] A plurality of insulating layers 110, 120, 130, 140, 150, and 160 for preventing unnecessary electrical connections can be provided on the device substrate 100. For example, a lower buffer layer 110, an upper buffer layer 120, a gate insulating layer 130, an interlayer insulating layer 140, a planarization layer 150, and a bank insulating layer 160 can be provided on the device substrate 100.

[0060] The lower buffer layer 110 can be provided close to the device substrate 100. The lower buffer layer 110 can prevent contamination caused by the device substrate 100 during the process of forming the driving circuit DC of each pixel region PA. For example, the upper surface of the device substrate 100 facing the driving circuit DC of each pixel region PA can be completely covered by the lower buffer layer 110. The driving circuit DC of each pixel region PA can be provided on the lower buffer layer 110. The lower buffer layer 110 can include an insulating material. For example, the lower buffer layer 110 can include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower buffer layer 110 can have a multilayer structure. For example, the lower buffer layer 110 can have a structure in which an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx) are stacked.

[0061] The upper buffer layer 120 can be provided on the lower buffer layer 110. The upper buffer layer 120 can include an insulating material. For example, the upper buffer layer 120 can include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0062] A light blocking pattern 105 may be disposed between the lower buffer layer 110 and the upper buffer layer 120 of each pixel region PA. The light blocking pattern 105 of each pixel region PA may include a material that reflects or absorbs light. For example, the light blocking pattern 105 of each pixel region PA may include a metal. The light blocking pattern 105 of each pixel region PA may overlap with the second semiconductor pattern 221 of the corresponding pixel region PA. Accordingly, in a display device according to an embodiment of the present disclosure, light traveling through the device substrate 100 toward the second semiconductor pattern 221 of each pixel region PA may be blocked by the light blocking pattern 105 of the corresponding pixel region PA. That is, in a display device according to an embodiment of the present disclosure, a change in characteristics of the second thin film transistor TR2 in each pixel region PA due to external light may be prevented. Accordingly, in a display device according to an embodiment of the present disclosure, the reliability of the driving circuit DC in each pixel region PA may be improved.

[0063] The first capacitor electrode 251 of each pixel region PA may be disposed on the same layer as the light blocking pattern 105 of the corresponding pixel region PA. For example, the first capacitor electrode 251 of each pixel region PA may be disposed between the lower buffer layer 110 and the upper buffer layer 120 of the corresponding pixel region PA. The first capacitor electrode 251 of each pixel region PA may include the same material as the light blocking pattern 105 of the corresponding pixel region PA. The first capacitor electrode 251 of each pixel region PA may be formed through the same process as the light blocking pattern 105 of the corresponding pixel region PA. For example, the first capacitor electrode 251 of each pixel region PA may be formed simultaneously with the light blocking pattern 105 of the corresponding pixel region PA. Accordingly, in a display device according to an embodiment of the present disclosure, the process of forming the driving circuit DC in each pixel region PA may be simplified. Accordingly, in a display device according to an embodiment of the present disclosure, the process efficiency may be improved.

[0064] The gate insulating layer 130 may be disposed on the upper buffer layer 120. The first gate electrode of each pixel region PA may be insulated from the first semiconductor pattern of the corresponding pixel region PA through the gate insulating layer 130. The second gate electrode 223 of each pixel region PA may be insulated from the second semiconductor pattern 221 of the corresponding pixel region PA through the gate insulating layer 130. For example, the gate insulating layer 130 may cover the first semiconductor pattern and the second semiconductor pattern 221 of each pixel region PA. The first gate electrode and the second gate electrode 223 of each pixel region PA may be disposed on the gate insulating layer 130. The gate insulating layer 130 may include an insulating material. For example, the gate insulating layer 130 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0065] The interlayer insulating layer 140 may be disposed on the gate insulating layer 130. The first drain electrode and the first source electrode of each pixel region PA may be insulated from the first gate electrode of the corresponding pixel region PA through the interlayer insulating layer 140. The second drain electrode 225 and the second source electrode 227 of each pixel region PA may be insulated from the second gate electrode 223 of the corresponding pixel region PA through the interlayer insulating layer 140. For example, the interlayer insulating layer 140 may cover the first gate electrode and the second gate electrode 223 of each pixel region PA. The first drain electrode, the first source electrode, the second drain electrode 225, and the second source electrode 227 of each pixel region PA may be disposed on the interlayer insulating layer 140. The interlayer insulating layer 140 may include an insulating material. For example, the interlayer insulating layer 140 may include an inorganic insulating material.

[0066] A planarization layer 150 may be disposed on the interlayer insulating layer 140. The thickness difference caused by the driving circuit DC of each pixel region PA may be removed by the planarization layer 150. For example, the upper surface of the planarization layer 150 facing the device substrate 100 may be a flat surface. The upper surface of the planarization layer 150 may be parallel to the upper surface of the device substrate 100. The first drain electrode, the first source electrode, the second drain electrode 225, and the second source electrode 227 of each pixel region PA may be covered by the planarization layer 150. For example, the first drain electrode of each pixel region PA may be in direct contact with the first drain region of the corresponding pixel region PA by penetrating the gate insulating layer 130 and the interlayer insulating layer 140, and the first source electrode of each pixel region PA may be in direct contact with the first source region of the corresponding pixel region PA by penetrating the gate insulating layer 130 and the interlayer insulating layer 140. The second drain electrode 225 of each pixel region PA may be in direct contact with the second drain region of the corresponding pixel region PA by penetrating the gate insulating layer 130 and the interlayer insulating layer 140, and the second source electrode 227 of each pixel region PA may be in direct contact with the second source region of the corresponding pixel region PA by penetrating the gate insulating layer 130 and the interlayer insulating layer 140. The planarization layer 150 may include an insulating material. The planarization layer 150 may include a material different from that of the interlayer insulating layer 140. The planarization layer 150 may include a material having relatively high fluidity. For example, the planarization layer 150 may include an organic insulating material.

[0067] The display device 300 of each pixel region PA may be disposed on the planarization layer 150. The display device 300 of each pixel region PA may emit light of a specific color. For example, the display device 300 of each pixel region PA may include a first electrode 310, a light-emitting unit 320, and a second electrode 330, which are sequentially stacked on the planarization layer 150 of the corresponding pixel region PA.

[0068] The first electrode 310 may include a conductive material. The first electrode 310 may include a material having a high reflectivity. For example, the first electrode 310 may include a metal such as aluminum (Al) and silver (Ag). The first electrode 310 may have a multilayer structure. For example, the first electrode 310 may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material such as ITO and IZO.

[0069] The light-emitting unit 320 may generate light having a luminance corresponding to a voltage difference between the first electrode 310 and the second electrode 330. For example, the light-emitting unit 320 may include an emissive material layer (EML). The emissive material layer may include an organic emissive material, an inorganic emissive material, or a hybrid emissive material. For example, a display device according to an embodiment of the present disclosure may be an organic light-emitting display device including an organic emissive material.

[0070] A plurality of emissive material layers (EML) may be disposed in the light-emitting unit 320. For example, the light-emitting unit 320 may include a plurality of emission stacks having at least one emissive material layer (EML) and at least one charge generation layer disposed between the emission stacks. The charge generation layer may supply electrons or holes to adjacent emission stacks. Thus, in a display device according to an embodiment of the present disclosure, light may be emitted from each emission stack. The light emitted from each emission stack may display the same color. Thus, in a display device according to an embodiment of the present disclosure, color reproduction may be improved.

[0071] The light-emitting unit 320 may include at least one functional layer. The functional layer may be one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Thus, in a display device according to an embodiment of the present disclosure, the emission efficiency of the light-emitting unit 320 may be increased.

[0072] The second electrode 330 may include a conductive material. The second electrode 330 may include a material different from that of the first electrode 310. The transmittance of the second electrode 330 may be greater than the transmittance of the first electrode 310. For example, the second electrode 330 may be a transparent electrode made of a transparent conductive material such as ITO and IZO, or a semi-transparent electrode in which a metal such as silver (Ag) and magnesium (Mg) is thinly formed. Thus, in a display device according to an embodiment of the present disclosure, the light generated by the light-emitting unit 320 may be emitted to the outside through the second electrode 330.

[0073] The display device 300 for each pixel region PA can be electrically connected to the second thin film transistor TR2 of the driving circuit DC in the corresponding pixel region PA. For example, the first electrode 310 of each pixel region PA can directly contact the second source electrode 227 of the corresponding pixel region PA by penetrating the planarization layer 150. The first electrode 310 of each pixel region PA can include a portion that directly contacts the upper surface of the planarization layer 150. For example, the light emitting unit 320 of the second electrode 330 of each pixel region PA can be stacked on the portion of the upper surface of the corresponding first electrode 310 that directly contacts the planarization layer 150.

[0074] The bank insulation layer 160 can be disposed on the planarization layer 150. The bank insulation layer 160 can include an insulating material. For example, the bank insulation layer 160 can be an organic insulating material. The bank insulation layer 160 can include a material different from that of the planarization layer 150. The bank insulation layer 160 can define an emission region in each pixel region PA. For example, the first electrode 310 of each pixel region PA can be partially exposed by the bank insulation layer 160. The edge of the first electrode 310 in each pixel region PA can be covered by the bank insulation layer 160. Therefore, in the display device according to an embodiment of the present disclosure, the first electrode 310 of each pixel region PA can be insulated from the first electrode 310 of an adjacent pixel region PA through the bank insulation layer 160.

[0075] The portion of the first electrode 310 exposed by the bank insulation layer 160 in each pixel region PA can overlap with the emission region of the corresponding pixel region PA. The portion of the first electrode 310 that overlaps with the emission region of each pixel region PA can directly contact the upper surface of the planarization layer 150. That is, in the display device according to an embodiment of the present disclosure, the light emitting unit 320 and the second electrode 330 of each pixel region PA can be stacked on the emission region defined by the bank insulation layer 160 in the corresponding pixel region PA. Therefore, in the display device according to an embodiment of the present disclosure, luminance deviation according to the generation position of light emitted from each pixel region PA can be prevented.

[0076] The voltage applied to the second electrode 330 of each pixel region PA may be the same as the voltage applied to the second electrode 330 of an adjacent pixel region PA. For example, the second electrode 330 of each pixel region PA may be electrically connected to the second electrode 330 of an adjacent pixel region PA. The second electrode 330 of each pixel region PA may include the same material as the second electrode 330 of an adjacent pixel region PA. The second electrode 330 of each pixel region PA may be formed by the same process as the second electrode of an adjacent pixel region PA. For example, the second electrode 330 of each pixel region PA may be formed simultaneously with the second electrode 330 of an adjacent pixel region PA. The second electrode 330 of each pixel region PA may be in direct contact with the second electrode 330 of an adjacent pixel region PA. For example, the second electrode 330 of each pixel region PA may extend on the bank insulating layer 160. Accordingly, in a display device according to an embodiment of the present disclosure, the process of forming the second electrode 330 in each pixel region PA may be simplified. Also, in a display device according to an embodiment of the present disclosure, the brightness of light generated by the light emitting unit 320 of each pixel region PA may be adjusted by a data signal applied to the driving circuit DC of the corresponding pixel region PA.

[0077] An image realized by the pixel region PA may include various colors. Light emitted from the display device 300 of each pixel region PA may display a different color from light emitted from the display device 300 of an adjacent pixel region PA. For example, each of the pixel regions PA may be one of a red pixel region in which light emitted from the display device 300 displays red, a blue pixel region in which light emitted from the display device 300 displays blue, and a green pixel region in which light emitted from the display device 300 displays green. Some of the light emitting units 320 in each pixel region PA may be spaced apart from the light emitting units 320 of an adjacent pixel region PA. For example, the emission material layer (EML) of each pixel region PA may be spaced apart from the emission material layer (EML) of an adjacent pixel region PA. The light emitting unit 320 of each pixel region PA may include an end portion disposed on the bank insulating layer 160.

[0078] An encapsulation structure 400 may be provided on the display device 300 in each pixel region PA. The encapsulation structure 400 may prevent the display device 300 from being damaged due to external moisture and impact. The encapsulation structure 400 may have a multi-layer structure. For example, the encapsulation structure 400 may have a stacked structure of a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may include an insulating material. The second encapsulation layer 420 may include a material different from that of the first encapsulation layer 410 and the third encapsulation layer 430. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may include an inorganic insulating material, and the second encapsulation layer 420 may include an organic insulating material. Therefore, in a display device according to an embodiment of the present disclosure, damage to the display device 300 caused by external moisture and impact can be effectively prevented. The thickness difference caused by the display device 300 in each pixel region PA may be removed by the second encapsulation layer 420. The thickness of the second encapsulation layer 420 may be greater than the thickness of the first encapsulation layer 410 and the thickness of the third encapsulation layer 430. For example, the upper surface of the encapsulation structure 400 opposite to the device substrate 100 may be a flat surface. The upper surface of the encapsulation structure 400 may be parallel to the upper surface of the device substrate 100.

[0079] Figure 4 is Figure 1 An enlarged view of the K region in. Figure 5 is a view taken along Figure 4 in I-I'.

[0080] Referring to Figures 1 to 5 , the display panel DP may include an active region AA in which a pixel region PA is provided and a border region BZ provided outside the active region AA. The border region BZ may be provided outside the pixel region PA. For example, the active region AA may be surrounded by the border region BZ. The gate driver GD, the data driver, and the power unit may be provided outside the active region AA. For example, each of the signal wirings GL, DL, and PL may include a region provided on the border region BZ.

[0081] At least one of the gate driver GD, the data driver, and the power unit may be provided on the border region BZ. For example, a display device according to an embodiment of the present disclosure may be a GIP (gate-in-panel) type display device in which the gate driver GD is formed on the border region BZ. The data driver and the power unit may be provided outside the display panel DP. A pad region PAD to which an external signal is applied may be provided on the border region BZ of the display panel DP.

[0082] The pad region PAD may be provided on one side of the active region AA. For example, the pad region PAD may be, for example, Figure 1is arranged side by side with the active region AA in a first direction in the horizontal direction. A connection region in which connection wirings 500 are provided may be provided between the active region AA and the pad region PAD. The driving circuit DC of each pixel region PA may be electrically connected to the pad region PAD through one of the connection wirings 500. For example, the data line DL may be electrically connected to the pad region PAD through the connection wiring 500. Each of the connection wirings 500 may be electrically connected to one of the output lines SL of the pad region PAD and one of the data lines DL. For example, the connection region LK may include a pad connection region PK in which each of the connection wirings 500 is electrically connected to one of the output lines SL of the pad region PAD, an active connection region AK in which each of the connection wirings 500 is electrically connected to one of the data lines DL, and a central region CA provided between the pad connection region PK and the active connection region AK. Each of the connection wirings 500 may pass through the central region CA of the connection region LK.

[0083] Each of the connection wirings 500 may include a first connection 510, a second connection 520, and a third connection 530. The first connection 510 of each connection wiring 500 may be arranged close to the pad region PAD. For example, the first connection 510 of each connection wiring 500 may be electrically connected to one of the output lines SL in the pad connection region PK. The third connection 530 of each connection wiring 500 may be arranged close to the active region AA. For example, the third connection 530 of each connection wiring 500 may be electrically connected to one of the data lines DL in the active connection region AK. The second connection 520 of each connection wiring 500 may be arranged between the first connection 510 and the third connection 530 of the corresponding connection wiring 500. For example, the second connection 520 of each connection wiring 500 may include a first end 521e electrically connected to the first connection 510 of the corresponding connection wiring 500 and a second end 522e electrically connected to the third connection 530 of the corresponding connection wiring 500. The second connection 520 of each connection wiring 500 may be arranged in the central region CA of the connection region LK.

[0084] The second connection 520 of each connection wiring 500 may extend in a direction different from that of the first connection 510 and the third connection 530 of the corresponding connection wiring 500. For example, the first connection 510 and the third connection 530 of each connection wiring 500 may extend from the pad connection region PK toward the active connection region AK, and the second connection 520 of each connection wiring 500 may extend from the active connection region AK toward the pad connection region PK. The second end 522e of each second connection 520 may be set closer to the pad region PAD than the first end 521e of the corresponding second connection 520. For example, the first end 521e of each second connection 520 may be set closer to the active connection region AK than the second end 522e of the corresponding second connection 520, and the second end 522e of each second connection 520 may be set closer to the pad connection region PK than the first end 521e of the corresponding second connection 520. Accordingly, in the display device according to an embodiment of the present disclosure, the region occupied by the connection wiring 500 between the active region AA and the pad region PAD may be reduced by the second connection 520 of each connection wiring 500. Accordingly, in the display device according to an embodiment of the present disclosure, the distance between the active region AA and the pad region PAD may be reduced.

[0085] The second end 522e of each second connection 520 may be spaced apart from the first end 521e of the corresponding second connection 520 in a second direction perpendicular to the first direction. For example, the angle θ between the first connection 510 and the second connection 520 of each connection wiring 500 may be greater than 0° and less than 90°. That is, in the display device according to an embodiment of the present disclosure, the angle θ between the first connection 510 and the second connection 520 of each connection wiring 500 may be an acute angle. Accordingly, in the display device according to an embodiment of the present disclosure, the distance between the active region AA and the pad region PAD may be reduced, and the path of the signal applied through each connection wiring 500 may be moved in the second direction by the second connection 520 of the corresponding connection wiring 500.

[0086] The angle θ between the first connection 510 and the second connection 520 of each connection wiring 500 may be proportional to the distance between the first connection 510 of the corresponding connection wiring 500 and the central region of the pad region PAD. For example, the angle θ between the first connection 510 and the second connection 520 of the connection wiring 500 connected to the output line SL extending from the edge of the pad region PAD may be greater than the angle θ between the first connection 510 and the second connection 520 of the connection wiring 500 connected to the output line SL extending from the central region of the pad region PAD. Accordingly, in a display device according to an embodiment of the present disclosure, the distance d2 between adjacent data lines DL may be greater than the distance d1 between adjacent output lines SL. For example, in a display device according to an embodiment of the present disclosure, the distance between the third connections 530 of adjacent connection wirings 500 may be greater than the distance between the first connections 510 of adjacent connection wirings 500. That is, in a display device according to an embodiment of the present disclosure, the spacing distance between the connection wirings 500 may be maintained at a certain distance or greater, and the area occupied by the connection wirings 500 between the active region AA and the pad region PAD may be minimized. Accordingly, in a display device according to an embodiment of the present disclosure, distortion of signals applied through each connection wiring 500 may be prevented, and the distance between the active region AA and the pad region PAD may be minimized.

[0087] Accordingly, a display device according to an embodiment of the present disclosure may include a plurality of connection wirings 500 that electrically connect each pixel region PA to the pad region PAD, wherein each of the connection wirings 500 may include a first connection 510 electrically connected to one of the output lines SL electrically connected to the pad region PAD, a second connection 520 electrically connected to the first connection 510, and a third connection 530 electrically connected to the second connection 520, and wherein the angle θ between the first connection 510 and the second connection 520 of each connection wiring 500 may be an acute angle. Accordingly, in a display device according to an embodiment of the present disclosure, the area occupied by the connection wirings 500 between the active region AA and the pad region PAD may be minimized without distorting the signals applied through each connection wiring 500. Accordingly, in a display device according to an embodiment of the present disclosure, the size of the bezel region BZ caused by an increase in the number of connection wirings 500 for implementing a high-resolution image may be minimized.

[0088] In a display device according to an embodiment of the present disclosure, the second connection 520 of each connection wiring 500 may be disposed on a different layer from the first connection 510 of the corresponding connection wiring 500, and the third connection 530 of each connection wiring 500 may be disposed on a different layer from the second connection 520 of the corresponding connection wiring 500. For example, as Figures 3 to 5As shown, the first connection 510 of each connection wiring 500 may be disposed on the same layer as the first capacitor electrode 251 of each pixel region PA, the second connection 520 of each connection wiring 500 may be disposed on the same layer as the third capacitor electrode 253 of each pixel region PA, and the third connection 530 of each connection wiring 500 may be disposed on the same layer as the second capacitor electrode 252 of each pixel region PA.

[0089] The planarization layer 150 and the bank insulating layer 160 do not extend onto the border region BZ. For example, the first connection 510 of each connection wiring 500 may be disposed between the lower buffer layer 110 and the upper buffer layer 120, the second connection 520 of each connection wiring 500 may be disposed between the interlayer insulating layer 140 and the first encapsulation layer 410, and the third connection 530 of each connection wiring 500 may be disposed between the gate insulating layer 130 and the interlayer insulating layer 140. The first connection 510 of each connection wiring 500 may include the same material as the light blocking pattern 105 of each pixel region PA, the second connection 520 of each connection wiring 500 may include the same material as the second drain electrode 225 and the second source electrode 227 of each pixel region PA, and the third connection 530 of each connection wiring 500 may include the same material as the second gate electrode 223 of each pixel region PA. The first connection 510 of each connection wiring 500 may be formed by the same process as the light blocking pattern 105 of each pixel region PA, the second connection 520 of each connection wiring 500 may be formed by the same process as the second drain electrode 225 and the second source electrode 227 of each pixel region PA, and the third connection 530 of each connection wiring 500 may be formed by the same process as the second gate electrode 223 of each pixel region PA. For example, the first connection 510 of each connection wiring 500 may be formed simultaneously with the light blocking pattern 105 of each pixel region PA, the second connection 520 of each connection wiring 500 may be formed simultaneously with the second drain electrode 225 and the second source electrode 227 of each pixel region PA, and the third connection 530 of each connection wiring 500 may be formed simultaneously with the second gate electrode 223 of each pixel region PA. That is, in the display device according to an embodiment of the present disclosure, the connection wiring 500 in the connection region LK may be formed by using the processes for forming the light blocking pattern 105 and the driving circuit DC in each pixel region PA.

[0090] The second end 522e of the second connection 520 of each connection wiring 500 is connected to the contact hole of the third connection 530 of the corresponding connection wiring 500, and the first end 521e of the second connection 520 of each connection wiring 500 is connected to the contact hole of the first connection 510 of the corresponding connection wiring 500, which can be formed simultaneously with the contact hole connecting the second drain electrode 225 of each pixel region PA to the second drain region of the corresponding pixel region PA and the contact hole connecting the second source electrode 227 of each pixel region PA to the second source region of the corresponding pixel region PA. Therefore, in the display device according to the embodiment of the present disclosure, no additional process is required to implement the electrical connection between the first connection 510 and the second connection 520 of each connection wiring 500 and between the second connection 520 and the third connection 530 of each connection wiring 500. Therefore, in the display device according to the embodiment of the present disclosure, a reduction in process efficiency caused by the process of forming the connection wiring 500 can be prevented.

[0091] The output line SL can be disposed on the same layer as the first connection 510 of each connection wiring 500. For example, the output line SL can be disposed between the lower buffer layer 110 and the upper buffer layer 120. The output line SL can include the same material as the first connection 510 of each connection wiring 500. The output line SL can be formed by the same process as the first connection 510 of each connection wiring 500. For example, the output line SL can be formed simultaneously with the first connection 510 of each connection wiring 500. The first connection 510 of each connection wiring 500 can be in direct contact with the corresponding output line SL. For example, the boundary between the first connection 510 of each connection wiring 500 and the corresponding output line SL cannot be recognized. Therefore, in the display device according to the embodiment of the present disclosure, the resistance between the first connection 510 of each connection wiring 500 and the corresponding output line SL can be minimized. Therefore, in the display device according to the embodiment of the present disclosure, the delay of the signal applied from the pad region PAD to each pixel region PA through each connection wiring 500 can be minimized. Also, in the display device according to the embodiment of the present disclosure, an increase in the distance between the active region AA and the pad region PAD caused by the electrical connection between the connection wiring 500 and the output line SL can be prevented.

[0092] The data line DL may be disposed on the same layer as the second drain electrode 225 and the second source electrode 227 of each pixel region PA. For example, the data line DL may be disposed between the interlayer insulating layer 140 and the first encapsulation layer 410. The contact holes connecting each data line DL to the third connection 530 of each connection wiring 500 may be formed simultaneously with the contact holes connecting the second drain electrode 225 of each pixel region PA to the second drain region of the corresponding pixel region PA and the contact holes connecting the second source electrode 227 of each pixel region PA to the second source region of the corresponding pixel region PA. Accordingly, in the display device according to an embodiment of the present disclosure, an additional process may not be required to implement an electrical connection between the third connection 530 of each connection wiring 500 and the corresponding data line DL. Accordingly, in the display device according to an embodiment of the present disclosure, a reduction in process efficiency caused by an electrical connection between the output line SL and the data line DL may be prevented.

[0093] The display device according to an embodiment of the present disclosure is described such that the driving circuit DC of each pixel region PA may be composed of a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst. However, in the display device according to another embodiment of the present disclosure, the driving circuit DC of each pixel region PA may include a driving thin film transistor and at least one switching thin film transistor. For example, in the display device according to another embodiment of the present disclosure, the driving circuit DC of each pixel region PA may further include a third thin film transistor that can initialize the storage capacitor Cst of the corresponding pixel region PA according to a gate signal. The third thin film transistor of each pixel region PA may include a third semiconductor pattern, a third gate electrode, a third drain electrode, and a third source electrode. The third semiconductor pattern of each pixel region PA may include a semiconductor material. The third gate electrode of each pixel region PA may be electrically connected to the corresponding gate line GL. The third drain electrode of each pixel region PA may be electrically connected to an initial line to which an initial signal is applied. The third source electrode of each pixel region PA may be electrically connected to the storage capacitor Cst of the corresponding pixel region PA. Accordingly, in the display device according to another embodiment of the present disclosure, the degree of freedom in configuring each driving circuit DC may be increased.

[0094] In a display device according to an embodiment of the present disclosure, the positions and electrical connections of the first drain electrode, the first source electrode, the second drain electrode 225, and the second source electrode 227 in each driving circuit DC may vary according to the configuration of the corresponding driving circuit DC and / or the types of the corresponding thin film transistors TR1 and TR2. For example, in a display device according to another embodiment of the present disclosure, the second gate electrode 223 of each driving circuit DC may be electrically connected to the first drain electrode of the corresponding driving circuit DC. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each driving circuit DC and the types of each thin film transistor TR1 and TR2 can be increased.

[0095] A display device according to another embodiment of the present disclosure may include a color filter disposed on a path of light emitted from a display device 300 of each pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the color filter may be disposed on the encapsulation structure 400. The light passing through the color filter disposed on each pixel region PA may display the same color as the light emitted from the display device 300 of the corresponding pixel region PA. Therefore, in a display device according to another embodiment of the present disclosure, color reproduction can be improved.

[0096] A display device according to an embodiment of the present disclosure has been described such that the light emitted from the display device 300 of each pixel region PA may display a different color from the light emitted from the display device 300 of an adjacent pixel region PA. However, in a display device according to another embodiment of the present disclosure, the light emitted from the display device 300 of each pixel region PA may display the same color as the light emitted from the display device 300 of an adjacent pixel region PA. For example, in a display device according to an embodiment of the present disclosure, white light may be emitted from the display device 300 of each pixel region PA. That is to say, in a display device according to another embodiment of the present disclosure, images of various colors can be realized by a color filter disposed on the pixel region PA. The light emitting unit 320 of each pixel region PA may have the same stacked structure as the light emitting unit 320 of an adjacent pixel region PA. The light emitting unit 320 of each pixel region PA may be formed by the same process as the light emitting unit 320 of an adjacent pixel region PA. For example, the light emitting unit 320 of each pixel region PA may be formed simultaneously with the light emitting unit 320 of an adjacent pixel region PA. Therefore, in a display device according to another embodiment of the present disclosure, the process of forming the light emitting unit 320 of each pixel region PA can be simplified. Therefore, in a display device according to another embodiment of the present disclosure, the process efficiency can be improved.

[0097] A display device according to an embodiment of the present disclosure is described such that each of the connection wirings 500 may include a first connection 510, a second connection 520, and a third connection 530 provided on different layers from each other. However, in a display device according to another embodiment of the present disclosure, each of the connection wirings 500 may include a plurality of connections 510, 520, and 530, and the plurality of connections 510, 520, and 530 may be provided on at least three different layers. For example, in a display device according to another embodiment of the present disclosure, each of the connection wirings 500 may include a fourth connection provided between the third connection 530 and the corresponding data line DL, and the fourth connection of each connection wiring 500 may be provided on the same layer as the first connection 510 of the corresponding connection wiring 500. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each connection wiring 500 can be increased.

[0098] A display device according to an embodiment of the present disclosure is described such that the planarization layer 150 may be in direct contact with the first drain electrode, the first source electrode, the second drain electrode 225, and the second source electrode 227 of each pixel region PA. However, in a display device according to another embodiment of the present disclosure, at least one insulating layer may be provided between the interlayer insulating layer 140 and the planarization layer 150. For example, in a display device according to another embodiment of the present disclosure, the first drain electrode, the first source electrode, the second drain electrode 225, and the second source electrode 227 of each pixel region PA may be covered by an intermediate insulating layer 145 provided between the interlayer insulating layer 140 and the planarization layer 150, as Figure 6 and Figure 7 shown. The intermediate insulating layer 145 may prevent the driving circuit DC in each pixel region PA from being damaged due to external shock and moisture. For example, the intermediate insulating layer 145 may extend along the surface of the driving circuit DC in each pixel region PA opposite to the device substrate 100. The intermediate insulating layer 145 may include an insulating material. For example, the intermediate insulating layer 145 may include an inorganic insulating material.

[0099] The third connection 530 of each connection wiring 500 may be provided on the same layer as the data line DL. For example, the output line SL and the first connection 510 of each connection wiring 500 may be provided between the gate insulating layer 130 and the interlayer insulating layer 140, the second connection 520 of each connection wiring 500 may be provided between the intermediate insulating layer 145 and the first encapsulation layer 410, and the third connection 530 of each connection wiring 500 may be provided between the interlayer insulating layer 140 and the intermediate insulating layer 145.

[0100] The lower buffer layer 110 of each pixel region PA may be omitted. The upper buffer layer 120 of each pixel region PA may be in direct contact with the upper surface of the device substrate 100. For example, the upper surface of the device substrate 100 may be completely covered by the upper buffer layer 120. A light blocking pattern may not be formed in each pixel region PA. The storage capacitor Cst of each pixel region PA may have a stacked structure of a first capacitor electrode 251 and a second capacitor electrode 252, the first capacitor electrode 251 being disposed on the same layer as the second gate electrode 223 of the corresponding pixel region PA, and the second capacitor electrode 252 being disposed on the same layer as the second source electrode 227 of the corresponding pixel region PA. The second capacitor electrode 252 of each pixel region PA may be covered by the intermediate insulating layer 145. Accordingly, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the driving circuit and the stacked structure of the connection wiring 500 may be increased.

[0101] A display device according to an embodiment of the present disclosure is described such that the first electrode 310 of each pixel region PA may be in direct contact with the second source electrode 227 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, at least one conductive layer may be disposed between the first electrode 310 of each pixel region PA and the second source electrode 227 of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the planarization layer 150 may have a stacked structure of a lower planarization layer 151 and an upper planarization layer 152, an intermediate electrode 270 may be disposed between the lower planarization layer 151 and the upper planarization layer 152 of each pixel region PA, and the first electrode 310 of each pixel region PA may be electrically connected to the second source electrode 227 of the corresponding pixel region PA through the intermediate electrode 270 disposed on the corresponding pixel region PA, as Figure 6 and Figure 7 shown. The intermediate electrode 270 of each pixel region PA may include a conductive material. For example, the intermediate electrode 270 of each pixel region PA may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The intermediate electrode 270 of each pixel region PA may be in direct contact with the second source electrode 227 of the corresponding pixel region PA by penetrating the intermediate insulating layer 145 and the lower planarization layer 151. The first electrode 310 of each pixel region PA may be in direct contact with the intermediate electrode 270 of the corresponding pixel region PA by penetrating the upper planarization layer 152. Accordingly, in a display device according to another embodiment of the present disclosure, the first electrode 310 of each pixel region PA may be stably connected to the second source electrode 227 of the corresponding pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, the reliability of each pixel region PA may be increased.

[0102] The intermediate electrode 270 of each pixel region PA may include the same material as the second connection 520 of each connection wiring 500. The intermediate electrode 270 of each pixel region PA may be formed by the same process as the second connection 520 of each connection wiring 500. For example, the intermediate electrode 270 of each pixel region PA may be formed simultaneously with the second connection 520 of each connection wiring 500. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom of the material of the second connection 520 of each connection wiring 500 can be increased.

[0103] A display device according to an embodiment of the present disclosure has been described as having the second semiconductor pattern 221 of each pixel region PA disposed between the device substrate 100 and the second gate electrode 223 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the first thin film transistor TR1 and the second thin film transistor TR2 of each pixel region PA may have various structures. For example, in a display device according to another embodiment of the present disclosure, the second gate electrode 223 of each pixel region PA may be disposed closer to the device substrate 100 than the second semiconductor pattern 221 of the corresponding pixel region PA, as Figure 8As shown. The second gate electrode 223 of each pixel region PA may be in direct contact with the upper surface of the device substrate 100. The second gate electrode 223 of each pixel region PA may be covered by the gate insulating layer 130. The second semiconductor pattern 221, the second drain electrode 225, and the second source electrode 227 of each pixel region PA may be disposed on the gate insulating layer 130. Each of the second drain electrode 225 and the second source electrode 227 in each pixel region PA may be in direct contact with a part of the second semiconductor pattern 221 of the corresponding pixel region PA. For example, an etch stop 229 may be disposed on the second channel region of the second semiconductor pattern 221 in each pixel region PA. Each of the second drain electrode 225 and the second source electrode 227 in each pixel region PA may include an end portion disposed on the etch stop 229 of the corresponding pixel region PA. That is, in a display device according to another embodiment of the present disclosure, the second thin film transistor TR2 of each pixel region PA may be a bottom gate type thin film transistor. The storage capacitor Cst of each pixel region PA may include a first capacitor electrode 251 disposed on the same layer as the second gate electrode 223 of the corresponding pixel region PA and a second capacitor electrode 252 disposed on the same layer as the second source electrode 227 of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the first capacitor electrode 251 of each pixel region PA may be disposed between the device substrate 100 and the gate insulating layer 130, and the second capacitor electrode 252 of each pixel region PA may be disposed between the gate insulating layer 130 and the planarization layer 150. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the driving circuit can be increased.

[0104] A display device according to an embodiment of the present disclosure is described such that the display device 300 of each pixel region PA may be a self-emitting device, wherein the light emitting unit 320 disposed between the first electrode 310 and the second electrode 330 includes at least one emission material layer (EML). However, in a display device according to another embodiment of the present disclosure, the display device 300 of each pixel region PA may have various configurations. For example, in a display device according to another embodiment of the present disclosure, the display device 300 of each pixel region PA may include a pixel electrode 610, a common electrode 620, and a liquid crystal layer LC disposed between the device substrate 100 and the encapsulation substrate 800, as Figure 9 and Figure 10 shown. That is, a display device according to another embodiment of the present disclosure may be a liquid crystal display device including a liquid crystal panel.

[0105] The common electrode 620 of each pixel region PA may be disposed between the device substrate 100 and the pixel electrode 610 of the corresponding pixel region PA. For example, the pixel electrode 610 of each pixel region PA may be disposed on the device passivation layer 180 covering the common electrode 620 of the corresponding pixel region PA. The device passivation layer 180 may include an insulating material. For example, the device passivation layer 180 may include an inorganic insulating material and / or an organic insulating material. The common electrode 620 of each pixel region PA may be disposed between the planarization layer 150 and the device passivation layer 180. The pixel electrode 610 of each pixel region PA may include at least one slit 610s overlapping with the common electrode 620 of the corresponding pixel region PA. The liquid crystal layer LC of each pixel region PA may include a plurality of liquid crystals that are rotated by a horizontal electric field formed between the pixel electrode 610 and the common electrode 620 of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the liquid crystal layer LC of each pixel region PA may include IPS mode liquid crystals.

[0106] A color filter 710, a black matrix 720, and a filter passivation layer 750 may be disposed on the surface of the encapsulation substrate 800 facing the liquid crystal layer LC of each pixel region PA. Each of the color filters 710 may overlap with the display device 600 of each pixel region PA. For example, the pixel electrode 610 of each pixel region PA may include at least one slit 610s overlapping with the color filter 710 of the corresponding pixel region PA. The black matrix 720 may be disposed outside the display device 600 of each pixel region PA. Thus, in a display device according to another embodiment of the present disclosure, light leakage and color mixing may be prevented. The filter passivation layer 750 may cover the color filter 710 and the black matrix 720. The thickness difference caused by the color filter 710 and the black matrix 720 may be removed by the filter passivation layer 750. For example, the lower surface of the filter passivation layer 750 facing the device substrate 100 may be parallel to the upper surface of the device substrate 100. The filter passivation layer 750 may include an insulating material. For example, the filter passivation layer 750 may include an inorganic insulating material and / or an organic insulating material.

[0107] A spacer 190 overlapping with the black matrix 720 may be provided between the device passivation layer 180 and the filter passivation layer 750. The spacer 190 may maintain the thickness of the liquid crystal layer LC in each pixel region PA. The spacer 190 may prevent the display device 600 in each pixel region PA from being damaged due to an external impact. For example, the spacer 190 may be spaced apart from the filter passivation layer 750. The spacer 190 may include an insulating material. For example, the spacer 190 may include an inorganic insulating material and / or an organic insulating material. Accordingly, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the display device 600 in each pixel region PA may be increased.

[0108] A display device according to an embodiment of the present disclosure is described such that a first connection 510 of each connection wiring 500 may be provided on the same layer as the corresponding output line SL. However, in a display device according to another embodiment of the present disclosure, the output line SL may be provided on a layer different from the first connection 510 of each connection wiring 500. For example, in a display device according to another embodiment of the present disclosure, a first connection 510 of each connection wiring 500 may be provided on the same layer as the common electrode 620 of each pixel region PA, a second connection 520 of each connection wiring 500 may be provided on the same layer as the drain electrode 215 and the source electrode 217 of each pixel region PA, and the output line SL and a third connection 530 of each connection wiring 500 may be provided on the same layer as the gate electrode 213 of each pixel region PA, as Figure 10 and Figure 11 shown.

[0109] The output line SL and the third connection 530 of each connection wiring 500 may include the same material as the gate electrode 213 of each pixel region PA. The output line SL and the third connection 530 of each connection wiring 500 may be formed by the same process as the gate electrode 213 of each pixel region PA. For example, the output line SL and the third connection 530 of each connection wiring 500 may be formed simultaneously with the gate electrode 213 of each pixel region PA. The output line SL, the third connection 530 of each connection wiring 500, and the gate electrode 213 of each pixel region PA may be in direct contact with the device substrate 100.

[0110] The first connection 510 of each connection wiring 500 may be disposed on the planarization layer 150 covering the second connection 520 of each connection wiring 500 and the thin film transistor Tr of each pixel region PA. For example, the first connection 510 of each connection wiring 500 may be disposed between the planarization layer 150 and the device passivation layer 180. The first connection 510 of each connection wiring 500 may include the same material as the common electrode 620 of each pixel region PA. The first connection 510 of each connection wiring 500 may be formed by the same process as the common electrode 620 of each pixel region PA. For example, the first connection 510 of each connection wiring 500 may be formed simultaneously with the common electrode 620 of each pixel region PA.

[0111] The data line DL may be disposed on the same layer as the drain electrode 215 and the source electrode 217 of each pixel region PA. The second connection 520 of each connection wiring 500 may be disposed on the same layer as the data line DL. For example, the second connection 520 of each connection wiring 500 and the data line DL may be disposed between the gate insulating layer 130 and the planarization layer 150. The second connection 520 of each connection wiring 500 and the data line DL may include the same material as the drain electrode 215 and the source electrode 217 of each pixel region PA. The second connection 520 of each connection wiring 500 and the data line DL may be formed by the same process as the drain electrode 215 and the source electrode 217 of each pixel region PA. For example, the second connection 520 of each connection wiring 500 and the data line DL may be formed simultaneously with the drain electrode 215 and the source electrode 217 of each pixel region PA. In a display device according to another embodiment of the present disclosure, regardless of the type of the thin film transistor Tr in each pixel region PA and the configuration of the display device 600, the area occupied by each connection wiring 500 between the active region and the pad region may be minimized. Therefore, in a display device according to another embodiment of the present disclosure, the size of the bezel region may be minimized without distorting the signals applied through each connection wiring 500 in a display panel having various configurations, so as to achieve a high-resolution image.

[0112] In a display device according to an embodiment of the present disclosure, the second end 522e of each second connection 520 may be spaced apart from the first end 521e of the corresponding second connection 520 in a second direction perpendicular to the first direction. For example, the angle θ between the first connection 510 and the second connection 520 of each connection wiring 500 may be greater than 0° and less than 180°. That is, in a display device according to an embodiment of the present disclosure, the angle θ between the first connection 510 and the second connection 520 of each connection wiring 500 may be an obtuse angle or an acute angle, which is not restrictive. As the distance between the first connection of the corresponding connection wiring and the central region of the pad region increases, the angle between the first connection and the second connection increases. Therefore, in a display device according to an embodiment of the present disclosure, the distance between the active region AA and the pad region PAD can be reduced, and the path of the signal applied through each connection wiring 500 can be moved in the second direction by the second connection 520 of the corresponding connection wiring 500.

[0113] Therefore, a display device according to an embodiment of the present disclosure may include connection wirings disposed between an active region and a pad region, wherein each of the connection wirings may include a first connection disposed close to the pad region, a second connection electrically connected to the first connection, and a third connection electrically connected to the second connection, and wherein the second end of the second connection electrically connected to the third connection may be disposed closer to the pad region than the first end of the second connection electrically connected to the first connection. Therefore, in a display device according to an embodiment of the present disclosure, the area occupied by the connection wirings between the active region and the pad region can be minimized. Therefore, in a display device according to an embodiment of the present disclosure, distortion of the signal applied through each connection wiring can be prevented, and the distance between the active region and the pad region can be minimized. Also, in a display device according to an embodiment of the present disclosure, production energy can be reduced through process optimization.

Claims

1. A display device, comprising: a device substrate including an active region and a border region; a pad region disposed on the frame region of the device substrate; a display device disposed on a pixel region of the active region; as well as a connection wiring disposed between the pad region and the active region, the connection wiring electrically connecting the pixel region to the pad region, wherein the connection wiring includes a first connection electrically connected to the pad area, a second connection electrically connected to the first connection, and a third connection electrically connected to the second connection, and Wherein, a second end of the second connection electrically connected to the third connection is arranged closer to the pad area than a first end of the second connection electrically connected to the first connection.

2. The display device according to claim 1, wherein: The pad region is spaced apart from the active region in a first direction, and The second end of the second connection is spaced apart from the first end of the second connection in a second direction perpendicular to the first direction.

3. The display device according to claim 1, wherein: The second connection is provided on a different layer than the first connection, and The third connection is arranged on a layer different from that of the second connection.

4. The display device according to claim 3, wherein: The second connection comprises a different material than the first connection, and Wherein, the third connection comprises a different material than the second connection.

5. The display device according to claim 1, further comprising: A driving circuit electrically connected to the display device, the driving circuit comprising a thin film transistor disposed on the pixel region; as well as a light blocking pattern disposed between the device substrate and the semiconductor pattern of the thin film transistor, wherein the first connection is provided on the same layer as the light blocking pattern, wherein the second connection is provided on the same layer as the drain electrode of the thin film transistor, and Wherein, the third connection is arranged on the same layer as the gate electrode of the thin film transistor.

6. The display device according to claim 5, wherein: The first connection includes a same material as the light blocking pattern, the second connection includes a same material as the drain electrode, and the third connection includes a same material as the gate electrode.

7. The display device according to claim 5, further comprising a signal wiring electrically connecting the third connection to the drive circuit, in, The signal wiring is provided on the same layer as the drain electrode.

8. The display device according to claim 1, wherein: The display device includes a light emitting unit disposed between a first electrode and a second electrode.

9. A display device, comprising: A driving circuit disposed on a pixel region of a device substrate; Display devices are arranged on the pixel regions, each of the display devices on each pixel region is electrically connected to the driving circuit on the corresponding pixel region; as well as A connection wiring is provided on the frame area of ​​the device substrate, the connection wiring electrically connecting the driving circuit of each pixel area to the pad area, wherein each of the connection wirings includes a first connection disposed close to the pad region, a second connection electrically connected to the first connection, and a third connection electrically connected to the second connection, the third connection being electrically connected to the drive circuit, and Wherein, the angle between the first connection and the second connection is an acute angle.

10. The display device according to claim 9, wherein: An angle between the first connection and the second connection in each connection wiring is proportional to a distance between the first connection of the corresponding connection wiring and a central area of ​​the pad region.

11. The display device according to claim 9, wherein: The driving circuit of each pixel region includes a thin film transistor, Wherein, the gate electrode of the thin film transistor is arranged between the device substrate and the semiconductor pattern of the thin film transistor, and The display device of each pixel area includes a pixel electrode electrically connected to a source electrode of the thin film transistor in the corresponding pixel area and a common electrode arranged between the device substrate and the pixel electrode of the corresponding pixel area.

12. The display device according to claim 11, wherein: The second connection is provided on the same layer as the source electrode, and Wherein, at least one of the first connection and the third connection is arranged on the same layer as the common electrode.

13. The display device according to claim 11, further comprising an output line of the first connection electrically connected to the pad area and each connection wiring, in, The output line is disposed on a different layer from the first connection.

14. The display device according to claim 13, wherein: The output line is provided on the same layer as the gate electrode.

15. The display device according to claim 9, wherein: A distance between the third connections of adjacent connection wirings is greater than a distance between the first connections of corresponding connection wirings.

16. A display device comprising: A driving circuit disposed on a pixel region of a device substrate; Display devices are arranged on the pixel regions, each of the display devices on each pixel region is electrically connected to the driving circuit on the corresponding pixel region; as well as A connection wiring is provided on the frame area of ​​the device substrate, the connection wiring electrically connecting the driving circuit of each pixel area to the pad area, wherein each of the connection wirings includes a first connection electrically connected to the pad region, a second connection electrically connected to the first connection, and a third connection electrically connected to the second connection, the third connection being electrically connected to the drive circuit, The first connection, the second connection and the third connection of the connection wiring are arranged so that a distance between third connections of adjacent connection wirings is greater than a distance between first connections of adjacent connection wirings.

17. The display device according to claim 16, wherein: An angle between the first connection and the second connection is in the range of 0° to 180°; and Among them, the angle between the first connection and the second connection of the connection wiring with a larger distance between the first connection and the central area of ​​the pad area is larger.

18. The display device according to claim 16, further comprising an output line of the first connection electrically connected to the pad area and each connection wiring, in, The first connection is in contact with a corresponding output line.

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