Display panel and display device

Abstract

The present disclosure provides a display panel and a display device including: a break inducing layer disposed on a first insulating layer and having a first open area exposing a portion of an upper surface of the first insulating layer; and a second insulating layer disposed over the substrate and including at least one open portion in the at least one sub-pixel and including a second open region in a region overlapping the first open region, a portion of the second insulating layer overlapping a portion of the first open region of the break-inducing layer, and the display panel and the display device can prevent a leakage current from flowing between the sub-pixels by breaking the organic layer through a first opening region and a second opening region formed in one or more non-light-emitting regions between the sub-pixels.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of Korean Patent Application No. 10 - 2023 - 0197853, filed on December 29, 2023, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to an electronic device having a display, and more particularly, to a display panel and a display device. Background art

[0004] Displays capable of displaying information and images on a screen are widely used in various electronic devices or systems, and as a core technology for presenting various information in today's society, displays are becoming increasingly important. To meet various needs, various types of displays, such as liquid crystal displays (LCDs), organic light - emitting displays (OLEDs), micro light - emitting displays (micro LEDs), mini light - emitting displays (mini LEDs), quantum dot light - emitting displays (QLEDs), etc., have been developed and widely used.

[0005] Although display devices are required to present excellent display quality, there may be a situation where, due to the common layer among the layers included in the light - emitting element (e.g., one or more organic layers) having a low resistance, an undesired current may be generated between sub - pixels. This undesired current may cause sub - pixels that are not supposed to emit light to emit light, whereby the display device may suffer from deteriorated display quality. Summary of the invention

[0006] To solve this problem, one or more aspects of the present disclosure may provide a display panel and a display device capable of preventing leakage current from flowing between sub - pixels.

[0007] One or more aspects of the present disclosure may provide a structure in which one sub - pixel includes a plurality of light - emitting regions that emit light of the same color, whereby a display panel and a display device capable of being driven at low power with high - brightness characteristics can be provided.

[0008] According to one or more exemplary embodiments of the present invention, a display panel may be provided, including: a substrate on which a plurality of sub-pixels are disposed; a first insulating layer disposed on the substrate; a disconnection inducing layer disposed on the first insulating layer and including a first opening region exposing a part of the upper surface of the first insulating layer; a second insulating layer disposed on the substrate and including at least one open portion in at least one of the plurality of sub-pixels; a first electrode disposed on the second insulating layer and overlapping with the at least one open portion; a bank disposed on a part of the upper surfaces of the first electrode and the second insulating layer and including corresponding openings in each of the plurality of sub-pixels; an organic layer disposed on the first electrode; and a second electrode disposed on the organic layer. The second insulating layer may include a second opening region in a region overlapping with the first opening region, and a part of the second insulating layer may overlap with a part of the first opening region of the disconnection inducing layer.

[0009] According to one or more exemplary embodiments of the present disclosure, a display device may be provided, including: a substrate on which a plurality of sub-pixels are disposed; a first insulating layer disposed on the substrate; a disconnection inducing layer disposed on the first insulating layer and including a first opening region exposing a part of the upper surface of the first insulating layer; and a second insulating layer disposed on the substrate and including at least one open portion in at least one of the plurality of sub-pixels. The second insulating layer may include a second opening region in a region overlapping with the first opening region, and a part of the second insulating layer may overlap with a part of the first opening region of the disconnection inducing layer.

[0010] According to one or more exemplary embodiments of the present invention, a display device may be provided, including: a substrate on which a plurality of sub-pixels are disposed; and a first resistance region, a second resistance region, and a third resistance region disposed on the substrate. The first resistance region may be configured to surround the second resistance region and the third resistance region, the second resistance region may be configured to surround each of the plurality of sub-pixels, and the third resistance region may be disposed between the plurality of sub-pixels. A resistance value of the third resistance region may be greater than resistance values of the first resistance region and the second resistance region.

[0011] According to one or more aspects of the present disclosure, a display panel and a display device may be provided which have a structure in which a first opening region and a second opening region are formed in a non-light-emitting region between sub-pixels, and which can prevent leakage current from flowing between sub-pixels by disconnecting an organic layer.

[0012] According to one or more aspects of the present disclosure, a display panel and a display device may be provided which have a structure in which one sub-pixel includes a plurality of light-emitting regions and a plurality of non-light-emitting regions, whereby driving at low power with excellent luminous efficiency can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings included to provide a further understanding of the present disclosure and incorporated in and constituting a part of the present disclosure illustrate aspects of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 Schematically illustrates a system configuration of an exemplary display device according to an aspect of the present disclosure;

[0015] Figure 2 is a plan view of an exemplary part of an effective area of a display device according to an aspect of the present disclosure;

[0016] Figure 3 is along Figure 2 an exemplary cross-sectional view taken along line A-B;

[0017] Figure 4 Schematically illustrates an exemplary part of an effective area of a display device according to an aspect of the present disclosure;

[0018] Figures 5 to 9 Schematically illustrates an exemplary method of manufacturing a display device according to an aspect of the present disclosure;

[0019] Figures 10 to 13 Illustrates an exemplary structure to which a display device according to an aspect of the present disclosure is applied; and

[0020] Figure 14 is along Figure 10 a cross-sectional view taken along line C-D. DETAILED DESCRIPTION

[0021] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the following description, unless otherwise specified, the structures, embodiments, implementations, methods, and operations described herein are not limited to the specific examples or individual examples set forth herein and may be varied as known in the art. Unless otherwise specified, the same reference numerals always denote the same elements. The names of the corresponding elements used in the following description are only selected for convenience in writing this application and may thus be different from those used in actual products. The advantages and features of the present disclosure and methods for implementing the same will be clarified by the following exemplary embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that the present disclosure can be thorough and complete and can help those skilled in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of related known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of the present disclosure. The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing various exemplary embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the accompanying drawings. When using terms such as "comprising", "having", "including", "containing", "constituting", "composing", "forming", etc., one or more other elements may be added unless a term such as "only" is used. Unless the context clearly indicates otherwise, an element described in the singular is intended to include a plurality of elements and vice versa.

[0022] Although terms such as "first", "second", "A", "B", "(a)", or "(b)" may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a specific order or priority. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0023] When referring to a first element being "connected or coupled" to a second element, "contacting or overlapping" with the second element, etc., it should be understood that not only can the first element be "directly connected or coupled" to the second element or "directly contact or overlap" with the second element, but also a third element may be "interposed" between the first element and the second element, or the first element and the second element may be "connected or coupled", "contacting or overlapping", etc. with each other via a fourth element. Herein, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacting or overlapping", etc. with each other.

[0024] When describing a positional relationship, for example, in a case where the positional relationship between two parts is described using "above", "upper", "lower", "on top of", "beneath", "next to", etc., one or more other parts may be located between the two parts, unless more restrictive terms such as "immediately", "directly", or "closely" are used. For example, in a case where one element or layer is disposed "on" another element or layer, a third element or layer may be interposed therebetween. In addition, terms such as "left", "right", "top", "bottom", "downward", "upward", "upper part", "lower part", etc. refer to an arbitrary reference system.

[0025] In addition, when referring to any dimension, relative size, etc., even when no relevant description is specified, the numerical value of an element or feature, or the corresponding information (e.g., level, range, etc.) should be considered to include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0026] In the following description, various exemplary aspects of the present disclosure are described in detail with reference to the accompanying drawings. For the reference numerals of the elements in each of the drawings, the same elements may be shown in other drawings, and the same reference numerals may represent the same elements, unless otherwise specified. Even if the same or similar elements are shown in different drawings, they may be represented by the same reference numerals. In addition, for ease of description, the ratios, dimensions, sizes, and thicknesses of the respective elements shown in the drawings may be different from the actual ratios, dimensions, sizes, and thicknesses, and thus the aspects of the present disclosure are not limited to the ratios, dimensions, sizes, and thicknesses shown in the drawings.

[0027] Figure 1 Schematically illustrates a system configuration of an exemplary display device according to an aspect of the present disclosure.

[0028] In one or more aspects, the display device 100 may include an organic light-emitting display device, a lighting device, a light-emitting device, an inorganic light-emitting display device, etc. Hereinafter, for ease of description, a discussion of the display device 100 is provided based on an example in which the display device 100 is implemented as an organic light-emitting display device 100. However, it should be understood that, in addition to the organic light-emitting display device 100, the aspects, examples, or embodiments described herein can be applied to various display devices such as lighting devices, light-emitting devices, inorganic light-emitting display devices, etc., as long as they include at least one transistor.

[0029] In one or more aspects, the organic light-emitting display device 100 may include: a display panel PLN configured to display an image or output light; and one or more driving circuits for driving the display panel PLN.

[0030] In one or more aspects, the organic light-emitting display device 100 may be configured with a bottom-emission structure in which light emitted from a light-emitting element is directed toward the bottom of the substrate on which the light-emitting element is disposed, but the aspects of the present disclosure are not limited thereto. In one or more aspects, the organic light-emitting display device 100 may be configured to have a top-emission structure in which light emitted from a light-emitting element is directed toward the surface opposite to the substrate on which the light-emitting element is disposed, or may be configured to have a dual-emission structure in which light emitted from a light-emitting element is directed toward both the substrate and the surface opposite to the substrate.

[0031] A plurality of data lines DL and a plurality of gate lines GL may be provided in the display panel PLN. A plurality of sub-pixels SP defined by the plurality of data lines DL and the plurality of gate lines GL may be arranged in a matrix in the display panel PLN.

[0032] The plurality of data lines DL and the plurality of gate lines GL may be configured to intersect each other in the display panel PLN. For example, the plurality of gate lines GL may be arranged in rows or columns, and the plurality of data lines DL may be arranged in columns or rows. Hereinafter, for ease of description, an example in which the plurality of gate lines GL are arranged in rows and the plurality of data lines DL are arranged in columns is provided for discussion.

[0033] In addition to the plurality of data lines DL and the plurality of gate lines GL, one or more other types of signal lines may be provided in the display panel PLN. Depending on the sub-pixel structure and the like, different types of signal lines may be provided in the display panel PLN. One or more driving power lines, one or more reference power lines, and / or one or more common power lines may be further provided in the display panel PLN.

[0034] Depending on the sub-pixel structure and the like, the number or type of signal lines provided in the display panel PLN may vary. In one or more aspects, at least one signal line may include an electrode to which a signal is applied. For example, a part of at least one signal line may be used as an electrode to which a signal is applied.

[0035] The display panel PLN may include an active area A / A where an image can be displayed and a non-active area N / A where an image is not displayed. For example, the non-active area N / A may be located outside the active area A / A. The non-active area N / A may be referred to as a non-display area, a border area, or a border.

[0036] A plurality of sub-pixels SP for image display may be provided in the active area A / A.

[0037] A pad region including at least one pad electrically connected to a data driver DDR or the like may be located in a non-effective region N / A. A plurality of data connection lines for connecting a plurality of data lines to the pads in the pad region may be provided in the non-effective region N / A. In one or more aspects, the plurality of data connection lines may be portions of a plurality of data lines DL extending from an effective region A / A to the non-effective region N / A, or may be separate patterns or line segments electrically connected to the plurality of data lines DL.

[0038] In one or more aspects, gate drive related lines may be provided in the non-effective region N / A to transmit at least one type or level of voltage (signal) required for gate driving to a gate driver GDR through at least one pad electrically connected to a data driver DDR or the like. For example, the gate drive related lines may include a clock line for transmitting a clock signal, gate power supply lines for transmitting gate voltages (VGH and VGL), and gate drive control signal lines for transmitting various types of control signals required to generate scan signals. Although at least a portion of the gate lines GL may be provided in the effective region A / A, the gate drive related lines may be provided in the non-effective region N / A.

[0039] The display device 100 may include a data driver DDR for driving a plurality of data lines DL, a gate driver GDR for driving a plurality of gate lines GL, and a controller CTR for controlling the data driver DDR and the gate driver GDR as a driving circuit for driving a display panel PLN.

[0040] The data driver DDR may drive a plurality of data lines DL by supplying data voltages to the plurality of data lines DL.

[0041] The gate driver GDR may drive a plurality of gate lines GL by supplying scan signals to the plurality of gate lines GL. As Figure 1 shown, for example, the plurality of gate lines GL may include a plurality of scan lines SCL, a plurality of sense lines SENL, and a plurality of emission control lines EML.

[0042] The controller CTR may control the driving operations of the data driver DDR and the gate driver GDR by supplying various types or levels of control signals (DCS and GCS) required for the driving operations of the data driver DDR and the gate driver GDR. The controller CTR may supply image data DATA to the data driver DDR.

[0043] The controller CTR can start scanning pixels according to the timing arranged in each frame. The controller CTR can convert the image data received from an internal or external image source (e.g., a host system, or an internal or external image providing device or system) into image data DATA in the form of a data signal that can be read by the data driver DDR, and then output the image data DATA obtained through the conversion to the data driver DDR. The controller CTR can control the data driving such that the data voltage corresponding to the image data DATA can be written into the corresponding pixels during a preset scanning time.

[0044] To control the data driver DDR and the gate driver GDR, the controller CTR can receive timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, a clock signal, etc. from an internal or external image source (e.g., a host system, or an internal or external image providing device or system), and generate control signals of different types or levels based on the received timing signals. After that, the controller CTR can supply the generated signals to the data driver DDR and the gate driver GDR.

[0045] For example, to control the gate driver GDR, the controller CTR can output various types of gate control signals GCS including a gate start pulse, a gate shift clock, a gate output enable signal, etc.

[0046] In addition, to control the data driver DDR, the controller CTR can output various types of data control signals DCS including a source start pulse, a source sampling clock, a source output enable signal, etc.

[0047] For example, the controller CTR can be a timing controller used in display technology. The controller CTR can be a control device or apparatus that can additionally perform one or more other control functions in addition to the function of the timing controller.

[0048] The controller CTR can be implemented in a component separate from the data driver DDR. The controller CTR can be integrated with the data driver DDR into an integrated circuit such that the controller CTR and the data driver DDR can be implemented in a single integrated circuit.

[0049] The data driver DDR can drive a plurality of data lines DL by receiving the image data DATA from the controller CTR and supplying a data voltage corresponding to the image data to the plurality of data lines DL. The data driver DDR can be referred to as a data driving circuit, a source driving circuit, or a source driver.

[0050] The data driver DDR can transmit various signals to the controller CTR or receive various signals from the controller CTR through various interfaces.

[0051] The gate driver GDR can sequentially drive a plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. The gate driver GDR can be referred to as a gate driving circuit, a scan driving circuit, or a scan driver.

[0052] According to the control of the controller CTR, the gate driver GDR can sequentially supply scan signals representing a turn-on voltage or a turn-off voltage to the plurality of gate lines GL.

[0053] When a specific gate line is selected and driven by a scan signal from the gate driver GDR, the data driver DDR can convert the image data DATA received from the controller CTR into an analog data voltage and supply the obtained data voltage to the plurality of data lines DL.

[0054] The data driver DDR can be disposed on and / or electrically connected to one side or edge (e.g., upper or lower) of the display panel PLN, but is not limited thereto. However, aspects of the present disclosure are not limited thereto. In some aspects, depending on the driving scheme, panel design scheme, etc., the data driver DDR can be disposed on or electrically connected to at least two of two sides or edges (e.g., upper and lower) or four sides or edges (e.g., upper, lower, left, and right) of the display panel PLN, but is not limited thereto.

[0055] The gate driver GDR can be disposed on and / or electrically connected to one side or edge (e.g., left or right) of the display panel PLN, but is not limited thereto. However, aspects of the present disclosure are not limited thereto. In some aspects, depending on the driving scheme, panel design scheme, etc., the gate driver GDR can be disposed on or electrically connected to at least two of two sides or edges (e.g., left and right) or four sides or edges (e.g., left, right, upper, and lower) of the display panel PLN, but is not limited thereto.

[0056] The data driver DDR can be implemented by including one or more source driver integrated circuits SDIC.

[0057] Each source driver integrated circuit SDIC can include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. In some aspects, the data driver DDR can further include one or more analog-to-digital converters (ADC).

[0058] Each source driver integrated circuit (SDIC) can be connected to a conductive pad such as a bonding pad of a display panel (PLN) through tape automated bonding (TAB) technology or chip on glass (COG) technology. Each source driver integrated circuit (SDIC) can be directly disposed in the display panel (PLN). In some aspects, each source driver integrated circuit (SDIC) can be integrated into the display panel (PLN) in the form of an integrated circuit. In some aspects, each source driver integrated circuit (SDIC) can be connected to the display panel (PLN) through chip on film (COF) technology. In this implementation, each source driver integrated circuit (SDIC) can be mounted on a circuit film. For example, each source driver integrated circuit (SDIC) mounted on the circuit film can be electrically connected to a data line (DL) in the display panel (PLN) through the circuit film.

[0059] The gate driver (GDR) can include a plurality of gate driving circuits (GDC). The plurality of gate driving circuits (GDC) can respectively correspond to a plurality of gate lines (GL).

[0060] Each gate driving circuit (GDC) can include a shift register, a level shifter, etc.

[0061] Each gate driving circuit (GDC) can be connected to a conductive pad such as a bonding pad of a display panel (PLN) through tape automated bonding (TAB) technology or chip on glass (COG) technology. In some aspects, each gate driving circuit (GDC) can be connected to the display panel (PLN) through chip on film (COF) technology. In this implementation, each gate driving circuit (GDC) can be mounted on a circuit film. For example, each gate driving circuit (GDC) mounted on the circuit film can be electrically connected to a gate line (GL) in the display panel (PLN) through the circuit film. In some aspects, each gate driving circuit (GDC) can be built into the display panel (PLN) through gate in panel (GIP) technology. In this implementation, each gate driving circuit (GDC) can be directly formed in the display panel (PLN).

[0062] Figure 2 is a plan view of an example portion of an effective area of a display device according to an aspect of the present disclosure.

[0063] Referring to Figure 2 , a plurality of light-emitting regions (EA) and a plurality of non-light-emitting regions (NEA) can be formed in the effective area A / A.

[0064] As Figure 2 shown, the areas of the corresponding light-emitting regions (EA) of at least two sub-pixels (SP) can be different, but the aspects of the present disclosure are not limited thereto.

[0065] Referring to Figure 2, in one or more aspects, the display device may include a plurality of light-emitting regions (EA1 and EA2) and a plurality of non-light-emitting regions (NEA1 and NEA2).

[0066] For example, a plurality of light-emitting regions (EA1 and EA2) and a plurality of non-light-emitting regions (NEA1 and NEA2) may be set by one sub-pixel.

[0067] For example, the first light-emitting region EA1 and the second light-emitting region EA2 may be located in one opening of the bank, and at least one first non-light-emitting region NEA1 may be located in the one opening of the bank.

[0068] When the display device is in a powered-on state, the first non-light-emitting region NEA1 may be in a black state, or may be in a state of emitting light with a lower luminance than the first light-emitting region EA1 and the second light-emitting region EA2 due to light from at least one of the first light-emitting region EA1 and the second light-emitting region EA2.

[0069] In one or more aspects, each sub-pixel may have a structure in which the first non-light-emitting region NEA1 may surround the first light-emitting region EA1, the second light-emitting region EA2 may surround the first non-light-emitting region NEA1, and the second non-light-emitting region NEA2 may surround the second light-emitting region EA2.

[0070] Referring to Figure 2 , the first light-emitting region EA1, the first non-light-emitting region NEA1, and the second light-emitting region EA2 formed in one sub-pixel may be configured to be separated from another first light-emitting region EA1, another first non-light-emitting region NEA1, and another second light-emitting region EA2 formed in another adjacent sub-pixel.

[0071] In one or more aspects, among the first light-emitting regions EA1 provided in the display panel PLN, at least one first light-emitting region EA1 may be a region that emits red light, at least another first light-emitting region EA1 may be a region that emits green light, and at least yet another first light-emitting region EA1 may be a region that emits blue light, but the aspects of the present disclosure are not limited thereto.

[0072] In one or more aspects, a second light-emitting region EA2 surrounding a first light-emitting region EA1 that emits red light may emit red light, a second light-emitting region EA2 surrounding a first light-emitting region EA1 that emits green light may emit green light, and a second light-emitting region EA2 surrounding a first light-emitting region EA1 that emits blue light may emit blue light. However, the color of the light emitted from the second light-emitting region EA2 according to aspects of the present disclosure is not limited thereto. For example, even when the second light-emitting region EA2 surrounding the first light-emitting region EA1 that emits red light emits red light, the color coordinates of the first light-emitting region EA1 may be different from those of the second light-emitting region EA2.

[0073] As Figure 2 shown, in a plan view, the first light-emitting region EA1, the second light-emitting region EA2, and the first non-light-emitting region NEA1 may have, for example, a hexagonal shape. However, aspects of the present disclosure are not limited thereto. For example, in a plan view, the first light-emitting region EA1, the second light-emitting region EA2, and the first non-light-emitting region NEA1 may have a circular shape, an elliptical shape, a polygon such as a triangle, a square, or a pentagon, or a shape generated by combining two or more of them.

[0074] A pair of the first light-emitting region EA1 and the second light-emitting region EA2 may be separated from another pair of the first light-emitting region EA1 and the second light-emitting region EA2, and a second non-light-emitting region NEA2 may be present therebetween.

[0075] Each second non-light-emitting region NEA2 may be a region corresponding to all or at least a part of a circuit portion in which circuit elements required to drive the first light-emitting region EA1 and the second light-emitting region EA2 are provided.

[0076] Referring to Figure 2 , at least one opening region 418b may be provided in the second non-light-emitting region NEA2.

[0077] At least one opening region 418b (which may be referred to as a second opening region as described below) may be an opening region provided in an insulating layer and have a structure in which a plurality of bars are connected in a plan view, as Figure 2 shown.

[0078] In one or more aspects, referring to Figure 2 , the display device 100 may include at least one hole region H, and at least one hole region H may be surrounded by the second non-light-emitting region NEA2. Herein, the term "hole region" may also be referred to as a hole.

[0079] In one or more aspects, referring to Figure 2, the display device 100 may include a first resistance region RA1, a second resistance region RA2, a third resistance region RA3, and a fourth resistance region RA4.

[0080] Each first resistance region RA1 may be disposed in a corresponding second non-light-emitting region. The first resistance region RA1 may not be located in the first light-emitting region EA1, the first non-light-emitting region NEA1, and the second light-emitting region EA2 included in each of the plurality of sub-pixels. In one or more aspects, the first resistance region RA1 may not be disposed in at least one opening region and at least one hole H.

[0081] Each second resistance region RA2 may be configured to surround a corresponding one of the plurality of sub-pixels. Each second resistance region RA2 may be configured to overlap with a corresponding first non-light-emitting region NEA1 and a corresponding second light-emitting region EA2.

[0082] Each third resistance region RA3 may be disposed between adjacent sub-pixels among the plurality of sub-pixels. Each third resistance region RA3 may overlap with a part of a corresponding opening region. The third resistance region RA3 may overlap with a first width of the opening region, but may not overlap with a second width.

[0083] Each fourth resistance region RA4 may be configured to surround a corresponding hole H. The fourth resistance region RA4 may overlap with an edge of the hole H.

[0084] For example, the first resistance region RA1 may correspond to a flat surface on which the organic layer 470 is disposed flat, and the second to fourth resistance regions RA2, RA3, and RA4 may correspond to inclined surfaces on which the organic layer 470 is disposed at a predetermined angle with respect to the flat surface.

[0085] The slope of the inclined surface where the second resistance region RA2 is located may be smaller than the slopes of the inclined surfaces where the third resistance region RA3 and the fourth resistance region RA4 are located.

[0086] As the slope of the inclined surface on which the organic layer 470 is disposed increases, the thickness of the stacked organic layer 470 may become thinner, whereby the area of the organic layer 470 may decrease (i.e., the area is proportional to the thickness). As a result, the resistance value of the organic layer 470 may increase.

[0087] Therefore, the resistance values of the third resistance region RA3 and the fourth resistance region RA4 may be greater than the resistance values of the first resistance region RA1 and the second resistance region RA2.

[0088] When the resistance value of the third resistance region RA3 increases, lateral leakage current flowing between sub-pixels may be prevented.

[0089] Refer to the followingFigure 3 An example configuration for preventing lateral leakage current will be discussed in more detail.

[0090] Figure 3 is an example cross-sectional view taken along line A-B Figure 2 of.

[0091] Referring to Figure 3 , a transistor TR provided on a substrate 400 and a light-emitting element EL electrically connected to the transistor TR may be provided in a part of the active region A / A (i.e., the cross-sectional area cut along line A-B).

[0092] At least one hole region H may be provided in the active region A / A. For example, the hole region H may be a region where the substrate 400, the transistor TR, and the light-emitting element EL are not provided.

[0093] The transistor TR may include an active layer 421, a gate electrode 431, a source electrode 442, and a drain electrode 441.

[0094] A light-emitting element EL such as an organic light-emitting diode may include a first electrode 460, an organic layer 470 including a light-emitting layer, and a second electrode 480. In one or more aspects, the first electrode 460 may be an anode electrode, and the second electrode 480 may be a cathode electrode, but the aspects of the present disclosure are not limited thereto.

[0095] Referring to Figure 3 , the substrate 400 may include a first substrate 401 and a second substrate 403, and an intermediate layer 402 may be provided between the first substrate 401 and the second substrate 403. For example, the intermediate layer 402 may be an inorganic layer and may be used to shield the penetration of moisture. However, the structure of the substrate 400 according to the aspects of the present disclosure is not limited thereto. For example, in addition to the multi-layer structure, the substrate 400 may have a single-layer structure.

[0096] A first buffer layer 410 may be provided on the substrate 400, and the first buffer layer 410 may be a single layer or include multiple layers.

[0097] A light-shielding portion 411 may be provided on the first buffer layer 410.

[0098] A second buffer layer 414 may be provided on the light-shielding portion 411.

[0099] The active layer 421 and a first storage capacitor electrode 422 may be provided on the second buffer layer 414. In one or more aspects, the active layer 421 may include a channel region, and the channel region may overlap at least a part of the light-shielding portion 411 and the gate electrode 431.

[0100] Regions other than the channel region of the active layer 421 may be regions in which the active layer 421 is modified to become conductive (which may be referred to as conductive enabling regions). The active layer 421 may include an oxide semiconductor material.

[0101] The first storage capacitor electrode 422 may be disposed on the same layer as the active layer 421. The first storage capacitor electrode 422 may be in a conductive enabling state in which the oxide semiconductor material is modified to become conductive, but aspects of the present disclosure are not limited thereto.

[0102] A gate insulating layer 415 may be disposed on the active layer 421 and the first storage capacitor electrode 422.

[0103] A gate electrode 431 and a second storage capacitor electrode 432 may be disposed on the gate insulating layer 415.

[0104] The gate electrode 431 may overlap with the channel region of the active layer 421, and the second storage capacitor electrode 432 may overlap with the first storage capacitor electrode 422. The second storage capacitor electrode 432 may be electrically connected to a metal layer 412 disposed on the same layer as the light shielding portion 411, but aspects of the present disclosure are not limited thereto.

[0105] An interlayer insulating layer 430 may be disposed on the gate electrode 431 and the second storage capacitor electrode 432.

[0106] A third storage capacitor electrode 433 may be disposed on the interlayer insulating layer 430. The third storage capacitor electrode 433 may overlap with the second storage capacitor electrode 432.

[0107] A protective layer 416 may be disposed on the third storage capacitor electrode 433. The protective layer 416 may include an organic insulating material or an inorganic insulating material.

[0108] A source electrode 442, a drain electrode 441, and a fourth storage capacitor electrode 443 may be disposed on the protective layer 416.

[0109] The source electrode 442 and the drain electrode 441 may be configured to be separated from each other and electrically connected to the conductive enabling regions of the active layer 421.

[0110] The fourth storage capacitor electrode 443 may overlap with the third storage capacitor electrode 433.

[0111] Referring to Figure 3 , the first storage capacitor electrode to the fourth storage capacitor electrodes 422, 432, 433, and 443 may be configured to overlap with each other and may form a storage capacitor Cst.

[0112] A first insulating layer 417 may be provided on the source electrode 442, the drain electrode 441, and the fourth storage capacitor electrode 443.

[0113] The first insulating layer 417 may be used to planarize the surface of the substrate 400.

[0114] A disconnection inducing layer 450 may be provided on the first insulating layer 417.

[0115] The disconnection inducing layer 450 may include an inorganic insulating material, but aspects of the present disclosure are not limited thereto.

[0116] The disconnection inducing layer 450 may include a first opening region 452 in a region corresponding to the second non-light-emitting region NEA2, and the first opening region 452 exposes a part of the upper surface of the first insulating layer 417.

[0117] A second insulating layer 418 may be provided on the disconnection inducing layer 450.

[0118] Referring to Figure 3 , the thickness of the disconnection inducing layer 450 may be smaller than the thickness of each of the first insulating layer 417 and the second insulating layer 418.

[0119] Referring to Figure 3 , the second insulating layer 418 may include a hole in a region overlapping with a part of the upper surface of the source electrode 442 or the drain electrode 441 of the transistor.

[0120] In one or more aspects, the second insulating layer 418 may include an open portion 418a, and the open portion 418a exposes a part of the upper surface of the disconnection inducing layer 450.

[0121] In one or more aspects, the second insulating layer 418 may include a second opening region 418b overlapping with a part of the first opening region 452 of the disconnection inducing layer 450.

[0122] Referring to Figure 3 , in a cross-sectional view, a first width L1 of the first opening region 452 may be greater than a second width L2 of the second opening region 418b. Here, each of the first width L1 and the second width L2 may refer to the shortest length in a direction perpendicular to the direction in which the first buffer layer 410 is stacked on the substrate 400.

[0123] Therefore, a part of the second insulating layer 418 may overlap with a part of the first opening region 452 of the disconnection inducing layer 450.

[0124] Referring to Figure 3 , an edge of the first opening region 452 may be covered by the second insulating layer 418. For example, as shown in Figure 3 , an undercut structure may be formed at the edge of the first opening region 452.

[0125] An undercut structure formed by the disconnection inducing layer 450 and the second insulating layer 418 may be located between light-emitting regions that emit light of different colors. For example, at least one undercut structure may be provided in a part of the second non-light-emitting region NEA2 between the light-emitting regions (EA1 and EA2) that emit red light and the light-emitting regions (EA1 and EA2) that emit green light. However, this is merely an example, and any configuration in which at least one undercut structure is provided in the second non-light-emitting region NEA2 of the effective region A / A may be sufficient to meet the aspects of the present disclosure.

[0126] Referring to Figure 3 , a first electrode 460 of the light-emitting element EL may be provided on the second insulating layer 418.

[0127] The first electrode 460 may include a first region 461 in which the upper surface of the first electrode 460 is parallel to the surface of the substrate 400 in a region overlapping with the open portion 418a, and a second region 462 that extends from the first region 461 and is a region in which the upper surface of the first electrode 460 has a predetermined angle with respect to the substrate 400. For example, the surface of the second region 462 may not be parallel to the surface of the substrate 400. In one or more aspects, the first electrode 460 may include a third region 463 that extends from the second region 462 and is a region in which the upper surface of the first electrode 460 is parallel to the surface of the substrate 400. The third region 463 may be a region that overlaps a part of the upper surface of the second insulating layer 418 but does not overlap the holes, the open portion 418a, and the second opening region 418b of the second insulating layer 418.

[0128] In one or more aspects, in at least one sub-pixel region, the transistor TR and the first electrode 460 of the light-emitting element EL may be electrically connected through the holes of the second insulating layer 418.

[0129] A bank 419 may be provided on a part of the second insulating layer 418 and the first electrode 460.

[0130] Referring to Figure 3 , a spacer 420 may be provided on a part of the upper surface of the bank 419. The spacer 420 may be provided in the second non-light-emitting region NEA2.

[0131] The bank 419 may be configured to expose a part of the upper surface of the first electrode 460 provided in the open portion 418a of the second insulating layer 418. In one or more aspects, the bank 419 may not overlap the first opening region 452 and the second opening region 418b.

[0132] An organic layer 470 of the light-emitting element EL may be provided on the substrate 400 on which the bank 419 is provided.

[0133] Referring to Figure 3 , the organic layer 470 may be interrupted in the area where the first opening region 452 and the second insulating layer 418 overlap each other.

[0134] For example, referring to Figure 3 , the organic layer 470 may be disposed on the upper surface of the bank portion 419, the upper surface of the first electrode 460, and the upper surface of the first insulating layer 417 in the area overlapping with the second opening region 418b. In addition, in the area where the first opening region 452 of the disconnection inducing layer 450 and the second insulating layer 418 overlap each other, the organic layer 470 may not be disposed on or on the upper surface of the disconnection inducing layer 450.

[0135] When the first sub-pixel is in the on state and the second sub-pixel adjacent to the first sub-pixel is in the off state, only the light-emitting region included in the first sub-pixel needs to emit light.

[0136] However, when the organic layer (e.g., the organic common layer) is continuously disposed in the active region A / A without a disconnection portion, even when only the first sub-pixel is in the on state, light emission may occur in the adjacent second sub-pixel due to leakage current.

[0137] In one or more aspects, in the display device 100, the organic layer 470 may not be disposed in at least a part of the second non-light-emitting region NEA2 located between two different sub-pixels, thereby preventing one or more adjacent sub-pixels in the off state from emitting light due to leakage current.

[0138] Referring to Figure 3 , the second electrode 480 of the light-emitting element EL may be disposed on the substrate 400 on which the organic layer 470 may be disposed.

[0139] The second electrode 480 may be disposed in the area of all at least one first light-emitting region EA1, at least one first non-light-emitting region NEA1, at least one second light-emitting region EA1, and at least one second non-light-emitting region NEA2.

[0140] For example, the second electrode 480 may be disposed on the upper surface of the organic layer 470, and may also be disposed in the area where the first opening region 452 and the second insulating layer 418 overlap each other, and in the area where the organic layer 470 is not disposed.

[0141] The first electrode 460 of the light-emitting element EL may include at least one of aluminum (Al), neodymium (Nd), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), silver (Ag), and aluminum alloy, but the aspects of the present disclosure are not limited thereto.

[0142] The second electrode 480 may include a conductive material that allows light to be completely or partially transmitted. For example, the second electrode 480 may include at least one of transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide, tin oxide, etc., or may include a semi-transmissive metal such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. In an example where the second electrode 480 includes a semi-transmissive metal, the thickness of the second electrode 480 may be less than the thickness of the first electrode 460.

[0143] At least one sub-pixel SP may include at least one light-emitting region EA, and at least one light-emitting region EA may include at least two light-emitting regions (EA1 and EA2). A non-light-emitting region NEA1 may be provided between the two light-emitting regions (EA1 and EA2).

[0144] In one or more aspects, Figure 3 the first light-emitting region EA1 in may be a region corresponding to a part of the open portion 418a of the second insulating layer 418.

[0145] In one or more aspects, the first light-emitting region EA1 may be a region that overlaps with a part of the first electrode 460 disposed in the open portion 418a and corresponds to a region where the open portion 418a and the bank portion 419 do not overlap with each other.

[0146] The first light-emitting region EA1 may be a region where some of the light emitted from the organic layer 470 is guided to the outside of the display panel through the organic layer 470 and the second electrode 480.

[0147] In one or more aspects, the first light-emitting region EA1 may be a region where some of the light (which may be referred to as the first light) among the light emitted from the organic layer 470 reaches the first electrode 460, is reflected from the first electrode 460, and is then guided to the outside of the display panel through the organic layer 470 and the second electrode 480.

[0148] The first light-emitting region EA1 may be surrounded by the first non-light-emitting region NEA1.

[0149] The first non-light-emitting region NEA1 may correspond to a region where the bank portion 419 overlaps with the open portion 418a and the first electrode 460 and where the upper surface of the first electrode 460 is set to be parallel to the surface of the substrate 400 (hereinafter, it may be referred to as a flat portion). For example, the first non-light-emitting region NEA1 may be a region where the bank portion 419 overlaps with the open portion 418a and the first electrode 460 and does not include a region corresponding to the inclined surface of the open portion 418a.

[0150] The first non-emitting region NEA1 may be a region where some of the light emitted from the organic layer 470 is guided in a direction parallel to the flat portion of the first electrode 460, reaches the first electrode 460, and is then trapped in the sub-pixel without being reflected from the first electrode 460 to be guided outside the display panel.

[0151] The second emitting region EA2 may be configured to surround the first non-emitting region NEA1. The second emitting region EA2 may be a region corresponding to a region where the first electrode 460 overlaps with the inclined surface of the open portion 418a of the second insulating layer 418. In one or more aspects, the second emitting region EA2 may be a region corresponding to the second region 462 of the first electrode 460.

[0152] Some of the light emitted from the organic layer 470 (which may be referred to as second light) may move to a region corresponding to the second region 462 of the first electrode 460.

[0153] For example, the second light may pass through the bank 419 and reach a region corresponding to a part of the second region 462 of the first electrode 460. The second light reaching the first electrode 460 may be reflected by the first electrode 460 and guided outside the display panel through the bank 419, the organic layer 470, and the second electrode 480.

[0154] The first non-emitting region NEA1 located between the first emitting region EA1 and the second emitting region EA2 may be a region where both the visible light of the first emitting region EA1 and the visible light of the second emitting region EA2 exist, but aspects of the present disclosure are not limited thereto.

[0155] The second non-emitting region NEA2 may be configured to surround the second emitting region EA2. The second non-emitting region NEA2 may correspond to the remaining region in the active area A / A other than the plurality of first emitting regions EA1, the plurality of second emitting regions EA2, and the plurality of first non-emitting regions NEA1 formed in the active area A / A.

[0156] The second non-emitting region NEA2 may include a first opening region 452 and a second opening region 418b.

[0157] Refer to Figure 3 , in one or more aspects, the display device may include at least one hole region H.

[0158] The hole region H may include a region where a part of at least one insulating layer (e.g., the first buffer layer 410) provided on the substrate 400 is disposed.

[0159] Although Figure 2 and Figure 3The second opening region 418b is shown to have a structure in which a plurality of stripes (or stripe shapes) are connected in a plan view, but aspects of the present disclosure are not limited thereto.

[0160] Referring Figure 3 , the first resistance region RA1 may correspond to a flat surface of the organic layer 470 where the organic layer 470 is uniformly formed. For example, the first resistance region may correspond to the flat surface of the bank 419, the flat surface of the spacer 420, and the like.

[0161] The second resistance region RA2 may correspond to an inclined surface of the organic layer 470 where the organic layer 470 is stacked on a side surface (e.g., an inclined surface) of the bank 419 in the opening of the bank 419. The second resistance region RA2 may be configured to overlap with the first non-light-emitting region NEA1 and the second light-emitting region EA2. The portion of the organic layer 470 stacked on the inclined surface in the opening may have a thickness smaller than that of the portion of the organic layer 470 stacked on the flat surface. Accordingly, the resistance value of the second resistance region RA2 may be greater than the resistance value of the first resistance region RA1.

[0162] The third resistance region RA3 may correspond to an inclined surface of the organic layer 470 where the organic layer 470 is stacked on a side surface (e.g., an inclined surface) of the bank 419 provided in the first opening region 452.

[0163] The third resistance region RA3 may overlap with a part of the first opening region 452. The third resistance region RA3 may not overlap with the second width L2 of the second opening region 418b, but may overlap with a part of the first width L1 of the first opening region 452. The slope of the inclined surface of the bank 419 in the first opening region 452 may be greater than the slope of the inclined surface of the bank 419 in the opening. The thickness of the organic layer 470 stacked on the inclined surface of the bank 419 in the first opening region 452 may be smaller than the thickness of the organic layer 470 stacked on the inclined surface in the opening. Accordingly, the resistance value of the third resistance region RA3 may be greater than the resistance value of the second resistance region RA2.

[0164] When the resistance value of the third resistance region RA3 is greater than the resistance values of the first resistance region RA1 and the second resistance region RA2, lateral leakage current flowing between sub-pixels can be prevented.

[0165] The fourth resistance region RA4 may correspond to an inclined surface of the organic layer 470 where the organic layer 470 is stacked on a side surface (e.g., an inclined surface) of the bank 419 provided adjacent to the hole H. The fourth resistance region RA4 may overlap with an edge of the hole H. The slope of the inclined surface of the bank 419 provided adjacent to the hole H may be greater than the slope of the inclined surface of the bank 419 in the opening. A part of the organic layer 470 stacked on the inclined surface of the bank 419 provided adjacent to the hole H may have a thickness less than that of a part of the organic layer 470 stacked on the inclined surface of the bank 419 in the opening. Accordingly, the resistance value of the fourth resistance region RA4 may be greater than the resistance value of the second resistance region RA2.

[0166] Figure 4 Schematically illustrates an example portion of an active area of a display device according to aspects of the present disclosure.

[0167] Referring to Figure 4 , the second opening region 418b may be provided between light-emitting regions that emit different colors of light.

[0168] In a plan view, the second opening region 418b may be configured to surround outer edges of each of a second light-emitting region EA2 that emits red light, a second light-emitting region EA2 that emits green light, and a second light-emitting region EA that emits blue light.

[0169] Referring to Figure 4 , the second opening region 418b located in the active area A / A may be provided in a part of the second non-light-emitting region NEA2, and the second opening region 418b may include a plurality of curved portions X.

[0170] As Figure 4 shown, in a region corresponding to the curved portion X of the second opening region 418b, a taper angle 518 of the second insulating layer 418 in a region overlapping with the first opening region 452 may be formed to be 60° to 80°. Accordingly, the slope of a side surface of the second insulating layer 418 in a region corresponding to the second opening region 418b may be greater than Figure 2 the slope of the structure of

[0171] As the taper angle 518 of the second insulating layer 418 is formed to be 60° to 80°, the thickness of the organic layer 470 provided on the side surface of the second insulating layer 418 overlapping with the first opening region 452 may become thinner. Accordingly, in a region where the first opening region 452 overlaps with the second insulating layer 418, the organic layer 470 may not be formed under the second insulating layer 418.

[0172] In addition, as the thickness of the organic layer 470 provided on the side surface of the second insulating layer 418 overlapping the first opening region 452 becomes thinner, the area of the organic layer 470 may decrease (i.e., the area is proportional to the thickness). Accordingly, the resistance value of the organic layer 470 may increase. As the resistance value of the organic layer 470 increases, the organic layer 470 provided on the side surface of the second insulating layer 418 overlapping the first opening region 452 may be made non-luminous.

[0173] Figures 5 to 9 Schematically illustrates an example method of manufacturing a display device according to aspects of the present disclosure.

[0174] Referring Figure 5 , a first buffer layer 410 may be provided on the substrate 400.

[0175] A light-shielding part 411 and a metal layer 412 may be provided on the first buffer layer 410.

[0176] A second buffer layer 414 may be provided on the substrate 400 on which the first buffer layer 410, the light-shielding part 411, and the metal layer 412 are provided.

[0177] An active layer 421 and a first storage capacitor electrode 422 may be provided on the second buffer layer 414.

[0178] A gate insulating layer 415 may be provided on the substrate 400 on which the active layer 421 and the first storage capacitor electrode 422 are provided.

[0179] A gate electrode 431 and a second storage capacitor electrode 432 may be provided on the gate insulating layer 415.

[0180] An interlayer insulating layer 430 may be provided on the gate electrode 431 and the second storage capacitor electrode 432.

[0181] A third storage capacitor electrode 433 may be provided on the interlayer insulating layer 430.

[0182] A protective layer 416 may be provided on the third storage capacitor electrode 433.

[0183] A source electrode 442, a drain electrode 441, and a fourth storage capacitor electrode 443 may be provided on the protective layer 416.

[0184] A first insulating layer 417 may be provided on the source electrode 442, the drain electrode 441, and the fourth storage capacitor electrode 443.

[0185] Referring Figure 5 , a hole (hereinafter, which may be referred to as a first contact hole) may be formed in the first insulating layer 417 and the hole may expose at least a part of the upper surface of the source electrode 442 of the corresponding transistor.

[0186] Reference Figure 6 , a disconnection inducing layer material 650 can be formed on the first insulating layer 417.

[0187] The disconnection inducing layer material 650 can be disposed inside a first contact hole of the first insulating layer 417 and contact the top surface of the source electrode 442.

[0188] A second insulating layer 418 can be formed on the disconnection inducing layer material 650.

[0189] The second insulating layer 418 can include a second contact hole in a region corresponding to the first contact hole of the first insulating layer 417.

[0190] The second insulating layer 418 can include an open portion 418a and a second opening region 418b separated from the open portion 418a.

[0191] Reference Figure 6 , the open portion 418a and the second opening region 418b of the second insulating layer 418 can expose corresponding portions of the upper surface of the disconnection inducing layer material 650.

[0192] After that, reference Figure 7 , a photoresist pattern 700 can be disposed on the second insulating layer 418.

[0193] Reference Figure 7 , the photoresist pattern 700 can include at least two holes in one sub-pixel region. One of the at least two holes of the photoresist pattern 700 can be located in a region overlapping with the first contact hole of the first insulating layer 417 and the second contact hole of the second insulating layer 418, and the first contact hole and the second contact hole are configured to overlap with the source electrode 442 of the transistor.

[0194] Another hole of the photoresist pattern 700 can be located in a region overlapping with the second opening region 418b of the second insulating layer 418.

[0195] Reference Figure 7 , the disconnection inducing layer material 650 can be patterned by a photolithography process using the photoresist pattern 700 as a mask.

[0196] For example, a portion of the disconnection inducing layer material 650 disposed in a region corresponding to the holes of the photoresist pattern 700 can be patterned and removed.

[0197] Through this process, a disconnection inducing layer 450 can be formed, and the disconnection inducing layer 450 may not be disposed in a region overlapping with the source electrode 442 of the transistor. The disconnection inducing layer 450 may not be disposed in a region overlapping with the second opening region 418b of the second insulating layer 418.

[0198] The disconnection inducing layer 450 may include a first opening region 452 in a region overlapping with the second opening region 418b. The area of the first opening region 452 overlapping with the upper surface of the first insulating layer 417 may be larger than the area of the second opening region 418b overlapping with the upper surface of the first insulating layer 417.

[0199] The photoresist pattern 700 provided on the second insulating layer 418 may be removed.

[0200] Referring to Figure 8 , a first electrode 460 of the light-emitting element may be provided. The first electrode 460 may contact the upper surface of the source electrode 442 of the transistor and be provided in the open portion 418a of the second insulating layer 418.

[0201] The bank 419 and the spacer 420 may be provided on the substrate 400 on which the first electrode 460 is provided.

[0202] The bank 419 may expose the upper surface of the first electrode 460 in a part of the open portion 418a of the second insulating layer 418 and include a hole in a region corresponding to the second opening region 418b.

[0203] After that, referring to Figure 9 , the organic layer 470 and the second electrode 480 of the light-emitting element may be sequentially provided on the substrate 400.

[0204] The display device manufactured by the above process may be used in various ways. For example, the display device may be used as a vehicle display device, which will be discussed below with reference to Figures 10 to 14 this.

[0205] Figures 10 to 13 Illustrates an example structure of a display device applying aspects according to the present disclosure.

[0206] Figure 10 And Figure 11 schematically illustrates the positions of the gate line GL provided on the substrate 400 and the hole H in the substrate 400, and Figure 12 and Figure 13 schematically illustrates the positions of the data line DL provided on the substrate 400 and the hole H in the substrate 400.

[0207] Referring to Figure 10 and Figure 11 , in one or more aspects, the display device may be used as a vehicle display device.

[0208] In one or more aspects, the substrate 400 may be provided with at least one hole H.

[0209] For example, the substrate 400 may be provided with three holes H1, H2, and H3.

[0210] Refer to Figure 10 and Figure 11 The substrate 400 may be provided with a first hole H1, a second hole H2, and a third hole H3. The first hole H1, the second hole H2, and the third hole H3 may be configured to be separated from each other. Components included in the associated vehicle may be placed in the first hole H1, the second hole H2, and the third hole H3.

[0211] For example, the first hole H1 and the second hole H2 may be arranged side by side in one direction. The remaining third hole H3 may be provided between the first hole H1 and the second hole H2.

[0212] Refer to Figure 10 and Figure 11 Multiple circuit boards 1100 and multiple circuit films 1120 may be provided in the edge of the substrate 400. At least one chip 1130 may be mounted on each circuit film 1120.

[0213] In one or more aspects, except for the first through third holes H1, H2, and H3, the wiring 1000, and the pad areas provided in the edge of the substrate 400 and including pad electrodes electrically connected to the circuit film 1120, all or most of the remaining areas may be the active area A / A.

[0214] For example, each of the first through third holes H1, H2, and H3 may be surrounded by the active area A / A.

[0215] Figure 10 and Figure 11 All or at least a part of the active area A / A of Figure 3 may include a

[0216] Refer to Figure 10 and Figure 11 Multiple gate lines GL may be provided on the substrate 400.

[0217] Refer to Figure 10 Multiple gate lines GL may be configured to extend from one side of the substrate 400 to the opposite side of the substrate 400. Multiple gate lines GL may be connected to the wiring 1000 arranged along the edge of the substrate. The wiring 1000 connected to the multiple gate lines GL may be electrically connected to a circuit area provided in the non-active area of the substrate.

[0218] In one or more aspects, refer to Figure 10 One or more of the multiple gate lines GL may be configured to bypass at least one of the first through third holes H1, H2, and H3.

[0219] For example, among a plurality of gate lines GL, at least one gate line GL can be configured to bypass the first hole H1 and the second hole H2, at least another gate line GL can be configured to bypass the third hole H3, and at least yet another gate line GL can be configured to extend from one side of the substrate 400 to the opposite side of the substrate 400 without bypassing the first to third holes H1, H2, and H3.

[0220] In one or more aspects, referring to Figure 11 , among a plurality of gate lines GL provided on the substrate 400, at least one gate line GL can be configured to extend from one side of the substrate 400 to the opposite side of the substrate 400. At least one gate line GL can be electrically connected to at least one wiring 1000 provided along the edge of the substrate 400.

[0221] In one or more aspects, referring to Figure 11 , an in - gate - array (GIA) region in which a gate driving circuit is provided can be set in a part of the active region A / A of the substrate 400. In one or more aspects, at least one gate line GL among the gate lines GL can be configured to extend from one side of the substrate 400 to the opposite side of the substrate 400 and further includes bypassing a part of the GIA region.

[0222] In one or more aspects, referring to Figure 11 , a plurality of gate lines GL provided between the first hole H1 and the second hole H1 can be electrically connected to at least one connection line 1110, and the at least one connection line 1110 can be electrically connected to a gate driving circuit provided in the GIA region.

[0223] In one or more aspects, referring to Figure 11 , a plurality of gate lines GL provided between one side of the substrate 400 (for example, Figure 11 the side of the substrate 400 on which the circuit film 1120 is not provided in Figure 11 ) and the first hole H1 can be electrically connected to the wiring 1000, and a plurality of gate lines GL provided between the opposite side of the substrate 400 (for example,

[0224] the opposite side of the substrate 400 on which the circuit film 1120 is not provided in

[0225] ) and the second hole H2 can be electrically connected to the wiring 1000. In one or more aspects, a plurality of gate lines GL provided between one side of the substrate 400 and the third hole H3, and a plurality of gate lines GL provided between the opposite side of the substrate 400 and the third hole H3 can be electrically connected to the wiring 1000. Therefore, even when the first to third holes H1, H2, and H3 are provided in the substrate 400, a plurality of gate lines GL can be provided on the substrate 400 without electrical disconnection. Referring toFigure 12 and Figure 13 , a plurality of data lines DL may be provided on the substrate 400.

[0226] The plurality of data lines DL may be configured to intersect with Figure 10 and Figure 11 the plurality of gate lines GL shown in. The plurality of data lines DL may be electrically connected to a circuit film 1120 that is electrically connected to a pad region of the substrate 400.

[0227] The data lines DL may be arranged on the substrate 400 in various ways.

[0228] For example, referring to Figure 12 , one or more of the plurality of data lines DL may be configured to extend from one side of the substrate 400 on which the circuit film 1120 is provided to the opposite side of the substrate 400 on which another circuit film 1120 is provided.

[0229] In one or more aspects, a first hole H1, a second hole H2, or a third hole H3 may be provided in the direction in which one or more of the plurality of data lines DL extend. In this implementation, as Figure 12 shown in, each of one or more of the data lines DL may include a corresponding portion that bypasses the first hole H1, the second hole H2, or the third hole H3.

[0230] In one or more aspects, as Figure 13 shown in, one or more of the data lines DL extending in the direction in which the first hole H1 is provided may be provided between the first hole H1 and the first circuit film 1120a. In this implementation, one or more of the data lines DL provided between the first hole H1 and the first circuit film 1120a may be electrically connected to the first circuit film 1120a. In one or more aspects, one or more other data lines DL among the data lines DL extending in the direction in which the first hole H1 is provided may be provided between the first hole H1 and the second circuit film 1120b. In this implementation, one or more other data lines DL provided between the first hole H1 and the second circuit film 1120b may be electrically connected to the second circuit film 1120b.

[0231] For example, the first circuit film 1120a and the second circuit film 1120b may be configured to be separated from each other and may be arranged parallel to each other in the direction in which the data lines DL extend.

[0232] Referring to Figure 13, one or more data lines DL extending in the direction in which the second hole H2 is provided may be provided between the second hole H2 and the third circuit film 1120c. In this implementation, one or more data lines DL provided between the second hole H2 and the third circuit film 1120c may be electrically connected to the third circuit film 1120c. In one or more aspects, one or more other data lines DL among the data lines DL extending in the direction in which the second hole H2 is provided may be provided between the second hole H2 and the fourth circuit film 1120d. In this implementation, one or more other data lines DL provided between the second hole H2 and the fourth circuit film 1120d may be electrically connected to the fourth circuit film 1120d.

[0233] For example, the third circuit film 1120c and the fourth circuit film 1120d may be configured to be separated from each other and may be arranged parallel to each other in the direction in which the data line DL extends.

[0234] Referring to Figure 13 , one or more data lines DL extending in the direction in which the third hole H3 is provided may be provided between the third hole H3 and the fifth circuit film 1120e. In this implementation, one or more data lines DL provided between the third hole H3 and the fifth circuit film 1120e may be electrically connected to the fifth circuit film 1120e. In one or more aspects, one or more other data lines DL among the data lines DL extending in the direction in which the third hole H3 is provided may be provided between the third hole H3 and the sixth circuit film 1120f. In this implementation, one or more other data lines DL provided between the third hole H3 and the sixth circuit film 1120f may be electrically connected to the sixth circuit film 1120f.

[0235] For example, the fifth circuit film 1120e and the sixth circuit film 1120f may be configured to be separated from each other and may be arranged parallel to each other in the direction in which the data line DL extends.

[0236] In this way, even when the substrate 400 is provided with a plurality of holes (H1, H2, and H3), a plurality of gate lines GL and a plurality of data lines DL may be provided in various structures. Through these configurations, in the substrate 400 including a plurality of holes (H1, H2, and H3), the area of the effective region A / A including a plurality of light-emitting regions can be enlarged.

[0237] Figure 14 is a cross-sectional view taken along the Figure 10 line C-D.

[0238] In the following, for convenience of description, a discussion of some configurations, structures, and effects that are equivalent, substantially equivalent, or with necessary modifications to the discussion provided above may not be repeated. However, it should be understood that the scope of the present disclosure includes these omitted configurations that have been discussed above. In addition, in the following discussion, the same reference numerals are used for configurations or elements that are equal to or substantially or almost equal to the above-described configurations or elements.

[0239] Referring to Figure 14 , in one or more aspects, a plurality of transistors, a plurality of storage capacitors Cst, and a plurality of light-emitting elements EL may be provided on a substrate 400, and a packaging layer 1400 may be provided on a second electrode 480 of the light-emitting element.

[0240] Figure 14 The packaging layer 1400 is shown as a single-layer structure, but the aspects of the present disclosure are not limited thereto. For example, the packaging layer 1400 may include at least two or more packaging layers. In one or more aspects, at least one of the at least two or more layers included in the packaging layer 1400 may include an organic material or an inorganic material.

[0241] Referring to Figure 14 , in one or more aspects, an active area A / A of the display device may include a plurality of light-emitting areas, a plurality of non-light-emitting areas, and at least one hole H3 (e.g., Figure 10 the third hole in ).

[0242] For example, as shown in Figure 14 , at least two light-emitting areas (EA1 and EA2) and at least two non-light-emitting areas (NEA1 and NEA2) may be formed in at least one sub-pixel provided in the active area A / A.

[0243] Referring to Figure 14 , an edge of the third hole H3 may be surrounded by a second non-light-emitting area NEA2.

[0244] In one or more aspects, the second non-light-emitting area NEA2 may include an area in which a plurality of weirs (DAM1 and DAM2) are provided. For example, a plurality of first weirs DAM1 and at least one second weir DAM2 may be provided in at least a part of the second non-light-emitting area NEA2 surrounding the third hole H3. For example, the second weir DAM2 may be closer to the light-emitting areas (EA1 and EA2) than the first weir DAM1. For example, a height of the second weir DAM2 may be greater than a height of at least one of the first weirs DAM1.

[0245] In one or more aspects, the structure of the first dam portion DAM1 can be described as follows. A disconnection inducing layer 450 can be disposed in the gate insulating layer 415 adjacent to the third hole H3 in the second non-light emitting region NEA2. In the second non-light emitting region NEA2 adjacent to the third hole H3, the disconnection inducing layer 450 can have a plurality of protruding portions 1410. In this implementation, the plurality of protruding portions 1410 can be integrally formed with the disconnection inducing layer 450 as one piece.

[0246] The plurality of protruding portions 1410 can be configured to be separated from each other.

[0247] Referring to Figure 14 , a second insulating layer pattern 1420 can be disposed on a corresponding one of the plurality of protruding portions 1410. An organic layer pattern 1470 and a second electrode pattern 1480 can be disposed on the second insulating layer pattern 1420.

[0248] In one or more aspects, the width of each of the plurality of protruding portions 1410 can be less than the width of the second insulating layer pattern 1420, whereby the structure in which each protruding portion 1410 and each second insulating layer pattern 1420 are stacked can be an inverted conical shape toward the substrate 400.

[0249] Referring to Figure 14 , the second dam portion DAM2 can include a second insulating layer pattern 1420 disposed on the protruding portion 1410 and a bank pattern 1419 disposed on the second insulating layer pattern 1420. The organic layer 470 and the second electrode 480 of the light emitting element EL can extend and be disposed on the bank pattern 1419.

[0250] Referring to Figure 14 , since the first dam portion DAM1 has an inverted conical structure, the organic layer 470 and the second electrode 480 may not continuously or integrally extend from the region where the second dam portion DAM2 is provided. For example, the organic layer 470 and the second electrode 480 can be disposed only on the second insulating layer pattern 1420, so at least one of the organic layer 470 and the second electrode 480 can be disconnected in the region between the second dam portion DAM2 and the adjacent first dam portion DAM1 and / or the region between the adjacent first dam portions DAM1.

[0251] By applying this configuration, even when moisture and oxygen penetrate the third hole H3, since the organic layer 470 and the second electrode 480 of the light emitting element EL are arranged in a disconnected form due to the plurality of first dam portions DMA1 adjacent to the third hole H3, the display device can provide the advantage of protecting the light emitting regions (EA1 and EA2) from the penetration of moisture and oxygen.

[0252] As described above, the display panel and the display device 100 according to various examples, aspects, and embodiments of the present disclosure have been discussed with reference to the drawings.

[0253] According to aspects described herein, a display panel and a display device can be provided that have a structure in which a first opening region and a second opening region are formed in a non-light-emitting region between sub-pixels, and that can prevent leakage current from flowing between sub-pixels by disconnecting a part of an organic layer.

[0254] According to aspects described herein, a display panel and a display device can be provided that have a structure in which one sub-pixel includes a plurality of light-emitting regions and a plurality of non-light-emitting regions, whereby driving at low power with excellent luminous efficiency can be achieved.

[0255] The foregoing description has been presented to enable any person skilled in the art to make, use, and practice the technical features of the present invention, and the foregoing description has been provided as an example in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of the present invention. The foregoing description and the drawings have provided examples of the technical features of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present invention.

Claims

1. A display panel, comprising: a substrate on which a plurality of sub-pixels are arranged; a first insulating layer, wherein the first insulating layer is disposed on the substrate; a disconnection inducing layer disposed on the first insulating layer and comprising a first opening region exposing a portion of an upper surface of the first insulating layer; a second insulating layer disposed on the substrate and including at least one open portion in at least one sub-pixel among the plurality of sub-pixels; a first electrode disposed on the second insulating layer and overlapping the at least one open portion; a bank disposed on a portion of upper surfaces of the first electrode and the second insulating layer and including a corresponding opening in each of the plurality of sub-pixels; an organic layer, wherein the organic layer is disposed on the first electrode; as well as a second electrode, the second electrode being disposed on the organic layer, wherein the second insulating layer includes a second opening region in a region overlapping with the first opening region, and A portion of the second insulating layer overlaps a portion of the first opening region of the disconnection inducing layer. 2 . The display panel according to claim 1 , wherein a width of the first opening area is greater than a width of the second opening area. 3 . The display panel according to claim 1 , wherein the second opening region overlaps the portion of the upper surface of the first insulating layer exposed by the first opening region. 4 . The display panel according to claim 1 , wherein the organic layer is provided on the upper surface of the first insulating layer in a region where the first opening region and the second opening region overlap each other. 5 . The display panel according to claim 1 , wherein the organic layer is not provided on the upper surface of the first insulating layer in a region where the first opening region and the second opening region overlap each other. 6 . The display panel according to claim 5 , wherein the second electrode is provided on the upper surface of the first insulating layer in a region where the first opening region and the second opening region overlap each other. 7 . The display panel according to claim 1 , wherein the at least one sub-pixel comprises at least two light-emitting regions and at least two non-light-emitting regions.

8. The display panel according to claim 7, wherein the at least one sub-pixel comprises a first light-emitting region, a first non-light-emitting region surrounding the first light-emitting region, a second light-emitting region surrounding the first non-light-emitting region, and a second non-light-emitting region surrounding the second light-emitting region. 9 . The display panel according to claim 8 , wherein the first light emitting region is a region in which the first electrode overlaps the open portion and in which the first electrode and the bank do not overlap each other. 10 . The display panel according to claim 8 , wherein the first non-light emitting region is a region in which the bank overlaps a flat portion of the open portion. 11 . The display panel according to claim 8 , wherein the second light emitting region corresponds to a region where the first electrode overlaps an inclined surface of the open portion. 12 . The display panel according to claim 8 , wherein a brightness of the second light emitting area is equal to or smaller than a brightness of the first light emitting area. 13 . The display panel according to claim 8 , wherein the second non-light emitting area overlaps with the first opening area and the second opening area. 14 . The display panel according to claim 8 , wherein the first opening area and the second opening area are disposed between corresponding second light emitting areas of adjacent sub-pixels among the plurality of sub-pixels. 15 . The display panel according to claim 1 , wherein the second opening region has a structure in which a plurality of strips are connected in a plan view, or at least one of the plurality of strips is bent. 16 . The display panel of claim 1 , wherein the substrate comprises an active area and an inactive area surrounding the active area, and at least one hole is provided in the active area of ​​the substrate. 17 . The display panel of claim 16 , wherein a plurality of dam portions are disposed on the substrate and disposed adjacent to the at least one hole. 18 . The display panel of claim 17 , wherein at least one of the plurality of dam portions comprises a protruding portion, a second insulating layer pattern disposed on the protruding portion, an organic layer pattern disposed on the second insulating layer pattern, and a second electrode pattern disposed on the organic layer pattern. The display panel according to claim 18 , wherein the protruding portion is formed integrally with the disconnection inducing layer. 20 . The display panel of claim 18 , wherein a width of the protruding portion is smaller than a width of the second insulating layer pattern. 21 . The display panel according to claim 20 , wherein at least one of the organic layer and the second electrode is disconnected in a region between the at least one dam portion and an adjacent dam portion.

22. The display panel according to claim 1, wherein the second opening area comprises a plurality of bent portions. 23 . The display panel according to claim 22 , wherein a taper angle of the second insulating layer in a region overlapping the first opening region is formed to be 60° to 80°.

24. A display device comprising: a substrate on which a plurality of sub-pixels are arranged; a first insulating layer, wherein the first insulating layer is disposed on the substrate; a disconnection inducing layer disposed on the first insulating layer and comprising a first opening region exposing a portion of an upper surface of the first insulating layer; as well as a second insulating layer disposed on the substrate and including at least one open portion in at least one sub-pixel among the plurality of sub-pixels, The second insulating layer includes a second opening region in a region overlapping with the first opening region, and a portion of the second insulating layer overlaps with a portion of the first opening region of the disconnection inducing layer.

25. A display device comprising: a substrate on which a plurality of sub-pixels are arranged; as well as A first resistance region, a second resistance region and a third resistance region are arranged on the substrate, wherein the first resistance region is configured to surround the second resistance region and the third resistance region, the second resistance region is configured to surround each of the plurality of sub-pixels, and the third resistance region is disposed between the plurality of sub-pixels, and The resistance value of the third resistance region is greater than the resistance value of the first resistance region and the resistance value of the second resistance region.

26. The display device according to claim 25, wherein the substrate further comprises a hole, wherein a fourth resistance region surrounding the hole is further provided above the substrate, and The resistance value of the fourth resistance region is greater than the resistance value of the first resistance region and the resistance value of the second resistance region.

27. The display device according to claim 26, wherein the first resistance region corresponds to a flat planar surface on which an organic layer of a light emitting element is disposed, and Each of the second resistance region, the third resistance region, and the fourth resistance region corresponds to an inclined surface on which the organic layer is disposed at a predetermined angle with respect to the flat surface.

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