Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes: a first pixel electrode on a substrate; a pixel defining layer on the substrate and exposing the first pixel electrode; a first light emitting layer on the first pixel electrode; a first common electrode on the first light emitting layer; a first bank on the pixel defining layer; a second bank on the first bank and including a side surface protruding beyond a side surface of the first bank; a first inorganic layer including a body portion on the first common electrode and a wing portion protruding from the body portion and spaced apart from a top surface of the second bank; a first reinforcement layer between the wing portion of the first inorganic layer and the top surface of the second bank and on the first inorganic layer; and an organic encapsulation layer on the first enhancement layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0188083, filed with the Korean Intellectual Property Office on December 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device and a method for manufacturing a display device. Background Art

[0004] With the development of an information - oriented society, there is an increasing demand for display devices that display images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat - panel display device such as a liquid - crystal display device, a field - emission display device, and an organic - light - emitting display device. Among flat - panel display devices, in a self - emissive display device, since each pixel of the display panel includes a light - emitting element capable of emitting light by itself, an image can be displayed without a backlight unit for providing light to the display panel.

[0005] The above information disclosed in this background - art section is for enhancing the understanding of the background of the present disclosure, and thus, it may include information that does not constitute the prior art. Summary of the Invention

[0006] Recently, display devices are used in glass - type devices for providing virtual reality and augmented reality. For use in glass - type devices, the display device may be implemented in a very small size of 2 inches or less, or may have a high pixel pitch to be implemented at a high resolution. For example, the display device may have a high pixel pitch of 400 pixels per inch (PPI) or more.

[0007] When the display device is implemented in a very small size or has a high pixel pitch, since the area of the emission region where the light - emitting elements are disposed may be reduced, it may be difficult to implement light - emitting elements separated for each emission region through a mask process.

[0008] One or more embodiments of the present disclosure may relate to a display device in which light - emitting elements separated for each emission region are formed without a mask process.

[0009] One or more embodiments of the present disclosure may relate to a display device having a reduced light - emission difference in each pixel, which may be caused by etchant penetration into the light - emitting element during an etching process performed during the manufacturing process of the display device.

[0010] However, aspects and features of the present disclosure are not limited to those set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those of ordinary skill in the art by reference to the following detailed description of the present disclosure and the accompanying drawings.

[0011] According to one or more embodiments of the present disclosure, a display device includes: a first pixel electrode on a substrate; a pixel defining layer on the substrate and exposing the first pixel electrode; a first light-emitting layer on the first pixel electrode; a first common electrode on the first light-emitting layer; a first bank on the pixel defining layer; a second bank on the first bank and including side surfaces protruding beyond the side surfaces of the first bank; a first inorganic layer including a main portion on the first common electrode and a wing portion protruding from the main portion and spaced apart from the top surface of the second bank; a first reinforcing layer between the wing portion of the first inorganic layer and the top surface of the second bank and on the first inorganic layer; and an organic encapsulation layer on the first reinforcing layer.

[0012] In an embodiment, the first reinforcing layer may have the same thickness on the second bank and the first inorganic layer.

[0013] In an embodiment, the thickness of the first reinforcing layer may be equal to or greater than and may be equal to or less than the distance between the bottom surface of the wing portion of the first inorganic layer and the top surface of the second bank.

[0014] In an embodiment, the first reinforcing layer may include silicon oxide, aluminum oxide, zirconium oxide, hafnium oxide, cesium oxide, iron oxide, indium oxide, molybdenum oxide, or tin oxide.

[0015] In an embodiment, the display device may further include: a second pixel electrode on the substrate and spaced apart from the first pixel electrode; a second light-emitting layer on the second pixel electrode; a second common electrode on the second light-emitting layer and spaced apart from the first common electrode; a second inorganic layer including a main portion on the second common electrode and a wing portion protruding from the main portion of the second inorganic layer and spaced apart from the top surface of the second bank; and a second reinforcing layer between the first reinforcing layer and the organic encapsulation layer and between the wing portion of the second inorganic layer and the top surface of the second bank.

[0016] In an embodiment, the thickness of the first reinforcing layer and the thickness of the second reinforcing layer may be different from each other.

[0017] In an embodiment, the second bank may include a first opening overlapping the first common electrode and a second opening overlapping the second common electrode. The first reinforcing layer may overlap the first opening of the second bank and may not overlap the second opening of the second bank.

[0018] In an embodiment, the second reinforcing layer may overlap with the first opening and the second opening of the second bank.

[0019] In an embodiment, in a region where the wing portion of the second inorganic layer and the second bank overlap each other in the thickness direction of the substrate, the second bank, the first reinforcing layer, the second reinforcing layer, and the wing portion of the second inorganic layer may be sequentially located on top of each other.

[0020] In an embodiment, the first reinforcing layer, the second reinforcing layer, and the organic encapsulation layer may be sequentially located on the main body portion of the first inorganic layer.

[0021] In an embodiment, the second reinforcing layer may be located on the main body portion and the wing portion of the second inorganic layer.

[0022] In an embodiment, the second inorganic layer may be in contact with the second bank, the first reinforcing layer, and the second reinforcing layer.

[0023] In an embodiment, the display device may further include: a third pixel electrode spaced apart from the first pixel electrode and the second pixel electrode on the substrate; a third light-emitting layer on the third pixel electrode; a third common electrode on the third light-emitting layer and spaced apart from the first common electrode and the second common electrode; and a third inorganic layer including a main body portion on the third common electrode and a wing portion protruding from the main body portion of the third inorganic layer and spaced apart from the top surface of the second bank.

[0024] In an embodiment, the second bank may further include a third opening overlapping with the third common electrode, and the first reinforcing layer and the second reinforcing layer may not overlap with the third opening of the second bank.

[0025] In an embodiment, the bottom surface of the wing portion of the first inorganic layer may be in contact with the first reinforcing layer, the bottom surface of the wing portion of the second inorganic layer may be in contact with the second reinforcing layer, and the bottom surface of the wing portion of the third inorganic layer may be in contact with the organic encapsulation layer.

[0026] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: forming a plurality of pixel electrodes spaced apart from each other on a substrate; forming a pixel defining layer exposing the pixel electrodes; forming a first bank on the pixel defining layer; forming a second bank on the first bank, the side surface of the second bank protruding beyond the side surface of the first bank; forming a first light-emitting layer on the first pixel electrode among the pixel electrodes and a first emission pattern layer on the second bank; forming a first common electrode on the first light-emitting layer and a first electrode pattern layer on the first emission pattern layer; forming a first inorganic material layer on the first common electrode; etching a part of the first inorganic material layer; etching the first emission pattern layer and the first electrode pattern layer to expose the second bank; and forming a first reinforcing material layer on the second bank and the first inorganic material layer by using an atomic layer deposition (ALD) method.

[0027] In an embodiment, etching the first emission pattern layer and the first electrode pattern layer to expose the second bank may include: removing the first emission pattern layer and the first electrode pattern layer between the second bank and the first inorganic material layer.

[0028] In an embodiment, forming the first light-emitting layer on the first pixel electrode among the pixel electrodes and the first emission pattern layer on the second bank may include: depositing a material on a substrate, the material being cut off by the protruding side surface of the second bank and separated into the first light-emitting layer and the first emission pattern layer.

[0029] In an embodiment, the method may further include: forming a second light-emitting layer on the second pixel electrode among the pixel electrodes and a second emission pattern layer on the first reinforcing material layer; forming a second common electrode on the second light-emitting layer and a second electrode pattern layer on the second emission pattern layer; forming a second inorganic material layer on the second common electrode; etching a part of the second inorganic material layer; etching the second emission pattern layer and the second electrode pattern layer to expose the first reinforcing material layer; and forming a second reinforcing material layer on the first reinforcing material layer and the second inorganic material layer.

[0030] In an embodiment, the method may further include: forming a third light-emitting layer on the third pixel electrode among the pixel electrodes and a third emission pattern layer on the second reinforcing material layer; forming a third common electrode on the third light-emitting layer and a third electrode pattern layer on the third emission pattern layer; forming a third inorganic material layer on the third common electrode; etching a part of the third inorganic material layer; etching the third emission pattern layer and the third electrode pattern layer to expose the second reinforcing material layer; and forming an organic encapsulation layer on the second reinforcing material layer and the third inorganic material layer.

[0031] According to one or more embodiments of the present disclosure, by providing a reinforcing layer inside the undercut structure covering the lower inorganic encapsulation layer, moisture penetration can be prevented or substantially prevented. In addition, damage to the light-emitting element due to an etchant or moisture can be prevented or substantially prevented, so that the difference in brightness between the light-emitting elements can be reduced.

[0032] However, the aspects and features of the present disclosure are not limited to those described above. Additional aspects and features will be partly set forth in the following detailed description with reference to the accompanying drawings, and partly will be obvious from it, or can be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of exemplary, non-limiting embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1 is a perspective view showing a display device according to an embodiment;

[0035] Figure 2 is Figure 1 a cross-sectional view of the display device when viewed from the side;

[0036] Figure 3 is a plan view showing a part of a display device according to an embodiment;

[0037] Figure 4 is a cross-sectional view showing a part of a display device according to an embodiment;

[0038] Figure 5 is a cross-sectional view showing a light-emitting element layer and a thin-film encapsulation layer of a display device according to an embodiment;

[0039] Figure 6 is a cross-sectional view showing a light-emitting element layer and a thin-film encapsulation layer of a display device according to another embodiment; and

[0040] Figures 7 to 24 is a cross-sectional view sequentially showing a manufacturing process of a display device according to an embodiment. Detailed Embodiments

[0041] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always denote like elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the drawings and the written description, and thus, redundant descriptions thereof may not be repeated.

[0042] When a particular embodiment can be implemented differently, a specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in an order opposite to the described order.

[0043] In addition, as will be understood by those of ordinary skill in the art, given the present disclosure as a whole, each suitable feature of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, and can be interlocked and operated technically in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0044] In the drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the drawing is flipped, an element described as "below" or "beneath" or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both upward and downward orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0045] In the drawings, the first direction, the second direction, and the third direction are not limited to the directions of the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction, the second direction, and the third direction may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0046] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the spirit and scope of the present disclosure, the first element, the first component, the first region, the first layer, or the first portion described below may be referred to as the second element, the second component, the second region, the second layer, or the second portion.

[0047] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. Further, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0048] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the disclosure. As used herein, the singular forms "a" and "an" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "includes," "including," "has," "have," and "having," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" means A, B, or A and B. When an expression such as "at least one of" is used with a list of elements, it modifies the entire list of elements and not individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent variations that would be recognized by one of ordinary skill in the art in measured or calculated values. Further, when describing embodiments of the disclosure, the use of "may" means "one or more embodiments of the disclosure." As used herein, the terms "use," "using," and "used" can be considered to be synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Figure 1 is a perspective view showing a display device 10 according to an embodiment.

[0052] Reference Figure 1 , the display device 10 according to an embodiment may be included in an electronic device and may provide a screen displayed on the electronic device. The electronic device may refer to any suitable electronic device for providing a display screen. Examples of the electronic device may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, smart glasses, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a gaming machine, a digital camera, a video camera, etc.

[0053] The shape of the display device 10 may be variously modified according to needs or expectations. For example, the display device 10 may have a shape similar to a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2. An edge or corner where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 meet may be rounded to have a curvature, but the present disclosure is not limited thereto and may be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape and may be formed into another shape similar to another polygon shape, a circular shape, or an oval shape.

[0054] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (for example, see Figure 2 ).

[0055] The display panel 100 may include a main area MA and a sub-area SBA.

[0056] The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA provided around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer for defining an emission area or an opening area, and a self-emitting element.

[0057] For example, the self-emitting element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but the present disclosure is not limited thereto.

[0058] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit that emits light, and each of the self-emitting elements may correspond to a pixel among the plurality of pixels. The plurality of scan lines may provide scan signals received from the scan driver to the plurality of pixels. The plurality of data lines may provide data voltages received from the display driver 200 to the plurality of pixels. The plurality of power lines may provide power voltages received from the display driver 200 to the plurality of pixels.

[0059] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a scan driver that provides scan signals to the scan lines and fan-out lines that connect the display driver 200 to the display area DA.

[0060] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3). The sub-area SBA may include the display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted as needed or desired, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0061] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may provide data voltages to the data lines. The display driver 200 may provide power voltages to the power lines and may provide scan control signals to the scan driver. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be provided in the sub-area SBA and may overlap with the main area MA in the thickness direction (e.g., the third direction DR3) by bending the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0062] The circuit board 300 can be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0063] Figure 2 is Figure 1 A cross-sectional view of the display device 10 as viewed from the side. More specifically, Figure 2 is the Figure 1 side view of the display device 10 in the folded state.

[0064] Reference Figure 2 , the display panel 100 can include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0065] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. In another embodiment, the substrate SUB can include a glass material or a metal material.

[0066] The thin film transistor layer TFTL can be disposed on the substrate SUB. The thin film transistor layer TFTL can include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL can also include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 to the data line, and a lead connecting the display driver 200 to the pad portion. Each of the thin film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver can include a thin film transistor.

[0067] The thin film transistor layer TFTL can be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, scan lines, data lines, and power lines of each pixel of the thin film transistor layer TFTL can be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL can be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL can be disposed in the sub-area SBA.

[0068] The light emitting element layer EML can be disposed on the thin film transistor layer TFTL. The light emitting element layer EML can include a plurality of light emitting elements each including a first electrode, a second electrode, and a light emitting layer to emit light, and a pixel defining layer defining a pixel. The plurality of light emitting elements of the light emitting element layer EML can be disposed in the display area DA.

[0069] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be transferred to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may recombine with each other in the organic light-emitting layer to emit light.

[0070] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0071] The thin-film encapsulation layer TFEL may cover the top surface and the side surface of the light-emitting element layer EML and may protect the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light-emitting element layer EML.

[0072] The color filter layer CFL may be disposed on the thin-film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to a plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a desired wavelength (e.g., a specific or predetermined wavelength) and may block or absorb light of different wavelengths. The color filter layer CFL may absorb a part of light (e.g., external light) from the outside of the display device 10 to reduce the reflected light caused by the external light. Accordingly, the color filter layer CFL may prevent or substantially prevent color distortion caused by the reflection of the external light.

[0073] Since the color filter layer CFL may be directly disposed on the thin-film encapsulation layer TFEL, the display device 10 may not use a separate substrate for the color filter layer CFL. Accordingly, the thickness of the display device 10 may be reduced (e.g., may be relatively small).

[0074] In some embodiments, the display device 10 may further include an optical device. The optical device may emit and / or receive light in an infrared, ultraviolet, and / or visible light band. For example, the optical device may be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illuminance sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0075] Figure 3 is a plan view showing a part of the display device 10 according to an embodiment. Figure 3 is a plan view showing the layout of the light-emitting elements ED1, ED2, and ED3, the first inorganic layer TL1, the second inorganic layer TL2, the third inorganic layer TL3, and the second bank BN2 in the display area DA of the display device 10 according to an embodiment.

[0076] Reference Figure 3 , the second bank BN2 can cover the display area DA and can expose a part of the display area DA. An opening (e.g., indicated by the dashed line in Figure 3 ) is formed in the area that is exposed and not covered by the second bank BN2, and the light-emitting elements ED1, ED2, and ED3 can be respectively disposed in the opening. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can cover the boundary of the opening on the second bank BN2 and can cover the light-emitting elements ED1, ED2, and ED3 within the opening. The portions of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 that cover the boundary of the opening on the second bank BN2 can be referred to as wing portions.

[0077] Although Figure 3 shows that the exposed area not covered by the second bank BN2 is circular in shape, the present disclosure is not limited thereto, and the exposed area can have a polygonal shape such as a triangle, a square, or a hexagon, and the shapes of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 that cover the exposed area and its vicinity can also be variously modified as needed or desired. A part (e.g., the wing portion) of each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be disposed at a height higher than the height of the second bank BN2, and the light-emitting elements ED1, ED2, and ED3 can be disposed at a height lower than the height of the second bank BN2.

[0078] The plurality of light-emitting elements ED1, ED2, and ED3 can be arranged in an RGBG arrangement (e.g., type arrangement, e.g., such as a rhombus type arrangement, is a registered trademark of Samsung Display Co., Ltd.). For example, the first light-emitting element ED1 and the third light-emitting element ED3 can be arranged to be spaced apart from each other in the first direction DR1 and can be alternately arranged along the first direction DR1 and the second direction DR2. The second light-emitting element ED2 can be spaced apart from other adjacent second light-emitting elements ED2 in the first direction DR1 and the second direction DR2. The second light-emitting element ED2 and the first light-emitting element ED1 or the second light-emitting element ED2 and the third light-emitting element ED3 can be alternately arranged along any suitable direction on the plane formed by the first direction DR1 and the second direction DR2. The shapes and layouts of the plurality of light-emitting elements ED1, ED2, and ED3 and the exposed area not covered by the second bank BN2 are not limited to Figure 3 shown in the figure.

[0079] Figure 4It is a cross-sectional view showing a part of the display device 10 according to an embodiment. More specifically, Figure 4 is a cross-sectional view taken along the line Figure 3 I-I' and shows the cross-sections of the substrate SUB, the thin film transistor layer TFTL, the light-emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL.

[0080] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0081] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing or substantially preventing the penetration of air and / or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers stacked alternately.

[0082] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or multiple layers including any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or a suitable alloy thereof (e.g., made of).

[0083] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing or substantially preventing the penetration of air and / or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers stacked alternately.

[0084] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute the pixel circuit of a corresponding one of a plurality of pixels. For example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0085] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction (e.g., the third direction DR3) and may be insulated from the gate electrode GE by the gate insulating layer GI. In a part of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made into a conductor to form the source electrode SE and the drain electrode DE.

[0086] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the semiconductor layer ACT in the thickness direction (e.g., the third direction DR3), and the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor layer ACT.

[0087] The gate insulating layer GI can be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI can include a contact hole through which the first connection electrode CNE1 passes.

[0088] The first interlayer insulating layer ILD1 can cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 can include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 can be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0089] The capacitor electrode CPE can be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE in the thickness direction (e.g., the third direction DR3). The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0090] The second interlayer insulating layer ILD2 can cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 can be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0091] The first connection electrode CNE1 can be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 can be inserted into the contact holes provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0092] The first passivation layer PAS1 can cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 can protect the thin film transistor TFT. The first passivation layer PAS1 can include a contact hole through which the second connection electrode CNE2 passes.

[0093] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0094] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3 pass.

[0095] The light-emitting element layer EML may be disposed on the thin-film transistor layer TFTL. The light-emitting element layer EML may include light-emitting elements ED1, ED2, and ED3, a pixel defining layer PDL, a capping layer CAP, and a bank structure BNS. The light-emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0096] Figure 5 is a cross-sectional view showing the light-emitting element layer EML and the thin-film encapsulation layer TFEL in the display area DA of the display device 10 according to an embodiment. More specifically, Figure 5 is a cross-sectional view showing Figure 4 the light-emitting element layer EML.

[0097] In addition to Figure 4 and also referring to Figure 5 , the display device 10 may include a plurality of emission regions EA1, EA2, and EA3 disposed in the display area DA. The emission regions EA1, EA2, and EA3 may be defined as regions where the pixel electrodes AE1, AE2, and AE3, the light-emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 overlap each other in the thickness direction of the substrate SUB. The emission regions EA1, EA2, and EA3 may include regions where light is emitted from the light-emitting elements ED1, ED2, and ED3 in which the pixel electrodes AE1, AE2, and AE3, the light-emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 are stacked in sequence and travels toward the color filter layer CFL in the third direction DR3. The emission regions EA1, EA2, and EA3 may include a first emission region EA1, a second emission region EA2, and a third emission region EA3 spaced apart from each other and configured to emit light of the same or different colors.

[0098] In an embodiment, the areas or sizes of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be the same as or substantially the same as each other. For example, in the display device 10, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have the same or substantially the same area as each other. However, the present disclosure is not limited thereto. In the display device 10, the areas or sizes of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other. For example, the area of the second emission region EA2 may be larger than the areas of the first emission region EA1 and the third emission region EA3, and the area of the third emission region EA3 may be larger than the area of the first emission region EA1. The intensities of the light emitted from the respective emission regions EA1, EA2, and EA3 may vary according to the areas of the emission regions EA1, EA2, and EA3, and the areas of the emission regions EA1, EA2, and EA3 may be adjusted to control the color of the image displayed on the display device 10. Although Figure 4 the emission regions EA1, EA2, and EA3 are shown as having the same or substantially the same area as each other, the present disclosure is not limited thereto.

[0099] In the display device 10, one first emission region EA1, one second emission region EA2, and one third emission region EA3 that are adjacent to each other may form a pixel group. A pixel group may include the emission regions EA1, EA2, and EA3 that emit lights of different colors from each other to present a white gray scale. However, the present disclosure is not limited thereto, and the combination of the emission regions EA1, EA2, and EA3 constituting a pixel group may be variously modified as needed or desired (e.g., depending on the arrangement of the emission regions EA1, EA2, and EA3, the colors of the lights emitted from the emission regions EA1, EA2, and EA3, etc.).

[0100] A plurality of openings OPE1, OPE2, and OPE3 may be formed in the bank structure BNS of the light-emitting element layer EML and may be defined along the boundary of the bank structure BNS. The second bank BN2 may include the openings OPE1, OPE2, and OPE3 that respectively overlap the light-emitting elements ED1, ED2, and ED3, and each of the openings OPE1, OPE2, and OPE3 may include a corresponding one of the emission regions EA1, EA2, and EA3.

[0101] The display device 10 may include a plurality of light-emitting elements ED1, ED2, and ED3 provided in different emission regions EA1, EA2, and EA3. The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1 provided in the first emission region EA1, a second light-emitting element ED2 provided in the second emission region EA2, and a third light-emitting element ED3 provided in the third emission region EA3.

[0102] The light-emitting elements ED1, ED2, and ED3 may respectively include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, and the light-emitting elements ED1, ED2, and ED3 disposed in different emission regions EA1, EA2, and EA3 may emit light of different colors from each other depending on the materials of the light-emitting layers EL1, EL2, and EL3. For example, the first light-emitting element ED1 disposed in the first emission region EA1 may emit first red light having a peak wavelength in the range of 610 nm to 650 nm. The second light-emitting element ED2 disposed in the second emission region EA2 may emit second green light having a peak wavelength in the range of 510 nm to 550 nm. The third light-emitting element ED3 disposed in the third emission region EA3 may emit third blue light having a peak wavelength in the range of 440 nm to 480 nm. The first emission region EA1, the second emission region EA2, and the third emission region EA3 constituting one pixel may respectively include the light-emitting elements ED1, ED2, and ED3 that emit light of different colors from each other to present white grayscale. As another example, the light-emitting layers EL1, EL2, and EL3 may include two or more materials that emit light of different colors from each other, such that one of the light-emitting layers EL1, EL2, or EL3 may emit mixed light. For example, the light-emitting layers EL1, EL2, and EL3 may include a red light-emitting material and a green light-emitting material to emit yellow light, or may include a red light-emitting material, a green light-emitting material, and a blue light-emitting material to emit white light.

[0103] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be respectively disposed in the plurality of emission regions EA1, EA2, and EA3. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first emission region EA1, a second pixel electrode AE2 disposed in the second emission region EA2, and a third pixel electrode AE3 disposed in the third emission region EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed to be spaced apart from each other on the second passivation layer PAS2.

[0104] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin-film transistor TFT through a first connection electrode CNE1 and a second connection electrode CNE2. The edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other may be covered by a pixel defining layer PDL, such that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other.

[0105] The pixel electrodes AE1, AE2, and AE3 may include a transparent electrode material and / or a conductive metal material. The metal material may be at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The pixel electrodes AE1, AE2, and AE3 may have a multilayer structure of a transparent electrode material and a conductive metal material.

[0106] The pixel defining layer PDL may be disposed on the second passivation layer PAS2, the remaining pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be disposed on the entire or substantially the entire second passivation layer PAS2, and may cover the side surfaces of the pixel electrodes AE1, AE2, and AE3 and the remaining pattern RP to partially expose the top surfaces of the pixel electrodes AE1, AE2, and AE3. For example, the pixel defining layer PDL may expose the first pixel electrode AE1 in the first emission region EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1.

[0107] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, tantalum oxide, hafnium oxide, zinc oxide, and an amorphous silicon layer, but the present disclosure is not limited thereto.

[0108] According to an embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the top surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may partially overlap the top surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB, but may not be in direct contact with the top surfaces of the pixel electrodes AE1, AE2, and AE3. The remaining pattern RP may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3. The side surface of the pixel defining layer PDL may protrude much more toward the emission regions EA1, EA2, and EA3 (e.g., in a plan view) than the side surface of the second bank BN2.

[0109] The remaining pattern RP may be disposed on the edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the remaining pattern RP, the pixel defining layer PDL may not be in direct contact with the top surfaces of the pixel electrodes AE1, AE2, and AE3. The remaining pattern RP may be formed by removing a sacrificial layer SFL disposed on the pixel electrodes AE1, AE2, and AE3 (e.g., seeFigure 7 ) to form a part of. The remaining pattern RP may include a metal or an oxide semiconductor material. In the drawings, side surfaces of the remaining pattern RP facing the emission regions EA1, EA2, and EA3 are shown to be aligned with side surfaces of the pixel defining layer PDL, but the present disclosure is not limited thereto. The side surfaces of the remaining pattern RP may further protrude beyond the side surfaces of the pixel defining layer PDL toward the emission regions EA1, EA2, and EA3, or may be recessed compared to the side surfaces of the pixel defining layer PDL. The side surfaces of the pixel defining layer PDL may be the outermost side surfaces positioned toward the emission regions EA1, EA2, and EA3.

[0110] The light emitting layers EL1, EL2, and EL3 may be respectively disposed on the pixel electrodes AE1, AE2, and AE3. The light emitting layers EL1, EL2, and EL3 may be organic light emitting layers including an organic material (e.g., made of an organic material), and may be respectively formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light emitting layers EL1, EL2, and EL3 may have a multilayer structure, and each of a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material may form a layer. When the thin film transistor TFT applies a voltage (e.g., a predetermined voltage) to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3, and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported. And may be recombined with each other in the light emitting layers EL1, EL2, and EL3 to emit light.

[0111] The light emitting layers EL1, EL2, and EL3 may include a first light emitting layer EL1, a second light emitting layer EL2, and a third light emitting layer EL3 disposed in different emission regions EA1, EA2, and EA3. The first light emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first emission region EA1, the second light emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second emission region EA2, and the third light emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third emission region EA3. The plurality of light emitting layers EL1, EL2, and EL3 may emit lights of different colors from each other, or one of the light emitting layers EL1, EL2, or EL3 may emit mixed light. In an embodiment, the first light emitting layer EL1 may emit red light, the second light emitting layer EL2 may emit green light, and the third light emitting layer EL3 may emit blue light. In another embodiment, the first light emitting layer EL1 may emit yellow light as a mixed light of red light and green light, and the second light emitting layer EL2 may emit blue light. In another embodiment, the first light emitting layer EL1 may emit white light as a mixed light of red light, green light, and blue light.

[0112] The light-emitting layers EL1, EL2, and EL3 may be disposed on the top surface of the pixel defining layer PDL. In an embodiment, the side surface of the remaining pattern RP may be recessed compared to the side surface of the pixel defining layer PDL, and portions of the light-emitting layers EL1, EL2, and EL3 may be disposed in the space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In an embodiment, the light-emitting layers EL1, EL2, and EL3 may be in contact with the pixel defining layer PDL, the remaining pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0113] The common electrodes CE1, CE2, and CE3 may be respectively disposed on the light-emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material such that the light generated in the light-emitting layers EL1, EL2, and EL3 can be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low-potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive voltages corresponding to data voltages and the common electrodes CE1, CE2, and CE3 receive a low-potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, such that the light-emitting layers EL1, EL2, and EL3 can emit light.

[0114] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 disposed in different emission regions EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light-emitting layer EL1 in the first emission region EA1, the second common electrode CE2 may be disposed on the second light-emitting layer EL2 in the second emission region EA2, and the third common electrode CE3 may be disposed on the third light-emitting layer EL3 in the third emission region EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0115] The capping layers CAP1, CAP2, and CAP3 may be respectively disposed on the common electrodes CE1, CE2, and CE3. The capping layers CAP1, CAP2, and CAP3 may include an organic or inorganic insulating material to cover the patterns disposed on the light-emitting elements ED1, ED2, and ED3. The capping layers CAP1, CAP2, and CAP3 may prevent or substantially prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the capping layers CAP1, CAP2, and CAP3 may include an organic material such as a-NPD, NPB, TPD, m-MTDATA, Alq3, LiF, and / or CuPc or an inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0116] The capping layers CAP1, CAP2, and CAP3 may include a first capping layer CAP1, a second capping layer CAP2, and a third capping layer CAP3 disposed in different emission regions EA1, EA2, and EA3, respectively. The first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3 may be spaced apart from each other.

[0117] The display device 10 may include a plurality of bank structures BNS disposed on the pixel defining layer PDL. The bank structure BNS may have a structure in which a first bank BN1 and a second bank BN2 including different materials from each other are stacked in sequence. The bank structure BNS may include a plurality of openings OPE1, OPE2, and OPE3 including the emission regions EA1, EA2, and EA3, and may be disposed to overlap with the light blocking regions of the color filter layer CFL to be described in more detail below. The light emitting elements ED1, ED2, and ED3 of the display device 10 may be disposed to overlap with the openings OPE1, OPE2, and OPE3 of the bank structure BNS.

[0118] The first bank BN1 may be disposed on the pixel defining layer PDL. The side surface of the first bank BN1 may be recessed much more than the side surface of the pixel defining layer PDL in a direction opposite to the direction facing the emission regions EA1, EA2, and EA3. The side surface of the first bank BN1 may be recessed much more than the side surface of the second bank BN2 to be described in more detail below in a direction opposite to the direction facing the emission regions EA1, EA2, and EA3.

[0119] According to an embodiment, the first bank BN1 may include a metal material. In an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0120] According to an embodiment, the common electrodes CE1, CE2, and CE3 may be in direct contact with the side surface of the first bank BN1. One end and the other end of the common electrodes CE1, CE2, and CE3 may be in contact with the side surface of the first bank BN1. The common electrodes CE1, CE2, and CE3 of different light emitting elements ED1, ED2, and ED3 may be in direct contact with the first bank BN1, and the first bank BN1 may include a metal material. Accordingly, the common electrodes CE1, CE2, and CE3 may be electrically connected to each other through the first bank BN1.

[0121] The light-emitting layers EL1, EL2, and EL3 may be in direct contact with the side surfaces of the first bank BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surfaces of the first bank BN1 may be larger than the contact area between the light-emitting layers EL1, EL2, and EL3 and the side surfaces of the first bank BN1. The common electrodes CE1, CE2, and CE3 may be disposed over a larger area on the side surfaces of the first bank BN1 compared to the light-emitting layers EL1, EL2, and EL3, or may be disposed at a higher position on the side surfaces of the first bank BN1 compared to the light-emitting layers EL1, EL2, and EL3. Since the common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank BN1, according to some embodiments, they may contact the first bank BN1 over a larger area.

[0122] The first bank BN1 may have a top surface at a position higher than the top surfaces of the common electrodes CE1, CE2, and CE3 and the capping layers CAP1, CAP2, and CAP3. The height from the substrate SUB to the top surface of the first bank BN1 may be greater than the height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0123] The second bank BN2 may be disposed on the first bank BN1. The second bank BN2 may include openings OPE1, OPE2, and OPE3 that respectively overlap the emission regions EA1, EA2, and EA3, and each of the openings OPE1, OPE2, and OPE3 may be defined by side surfaces. The second bank BN2 may include a tip or an eave that is a region protruding much more than the first bank BN1. The side surfaces of the second bank BN2 may protrude much more toward the emission regions EA1, EA2, and EA3 than the side surfaces of the first bank BN1.

[0124] Since the side surfaces of the second bank BN2 have a shape that protrudes much more toward the emission regions EA1, EA2, and EA3 than the side surfaces of the first bank BN1, an undercut structure of the first bank BN1 may be formed under the tip of the second bank BN2.

[0125] In the display device 10 according to the embodiment, since the bank structure BNS includes tips protruding toward the emission regions EA1, EA2, and EA3, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other can be formed by deposition and etching processes instead of a mask process. In addition, it may be possible to separately form different layers in the different emission regions EA1, EA2, and EA3 by a deposition process. For example, even when the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed by a deposition process without using a mask, the deposition material can be cut (e.g., separated) by the tip of the second bank BN2 and the bank structure BNS is interposed therebetween without being connected between the emission regions EA1, EA2, and EA3. By forming a material for forming a specific layer on the entire surface of the display device 10; and then removing the layer formed in an undesired region by etching, different layers can be separately formed in the different emission regions EA1, EA2, and EA3. In the display device 10, different light-emitting elements ED1, ED2, and ED3 can be formed in the different emission regions EA1, EA2, and EA3 by deposition and etching processes without using a mask process, and unnecessary components in the display device 10 can be omitted to minimize or reduce the area of the non-display region NDA.

[0126] The second bank BN2 may include a metal material different from the metal material of the first bank BN1. More specifically, the metal material of the second bank BN2 may be a material that is removed together with the metal material of the first bank BN1 by dry etching, but may have an etching rate slower (e.g., much slower) than that of the first bank BN1 when wet-etched, or may not be etched by wet etching. In an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al), and the second bank BN2 may include titanium (Ti), an oxide of titanium (Ti), or an alloy of titanium (Ti).

[0127] The tip of the second bank BN2 can overlap with the common electrodes CE1, CE2, and CE3 in a third direction DR3 perpendicular or substantially perpendicular to the substrate SUB. In addition, the tip of the second bank BN2 can overlap with the light-emitting layers EL1, EL2, and EL3 in a third direction DR3 perpendicular or substantially perpendicular to the substrate SUB. In addition, the tip of the second bank BN2 can overlap with the pixel definition layer PDL in a third direction DR3 perpendicular or substantially perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 can be formed under the bottom surface of the tip of the second bank BN2. One end and the other end of each of the common electrodes CE1, CE2, and CE3 can overlap with the second bank BN2 in the thickness direction of the substrate SUB (e.g., the third direction DR3). The maximum vertical distance from the substrate SUB to the top surface of the common electrodes CE1, CE2, and CE3 can be less than the maximum vertical distance from the substrate SUB to the top surface of the first bank BN1.

[0128] The thin-film encapsulation layer TFEL can be disposed on the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS, and can cover the plurality of light-emitting elements ED1, ED2, and ED3 and the bank structure BNS. The thin-film encapsulation layer TFEL can include at least one inorganic layer to prevent oxygen and / or moisture from penetrating into the light-emitting element layer EML. The thin-film encapsulation layer TFEL can include at least one organic layer to protect the light-emitting element layer EML from foreign substances such as dust.

[0129] In an embodiment, the thin-film encapsulation layer TFEL can include a lower inorganic encapsulation layer TFE1, a first reinforcement layer EHL1, a second reinforcement layer EHL2, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked in sequence.

[0130] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 can include one or more inorganic insulators (e.g., one or more inorganic insulating materials). The inorganic insulating material can be any one of silicon oxide, silicon nitride, and silicon oxynitride, and can include, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide.

[0131] The organic encapsulation layer TFE2 can include a polymer-based material. Examples of the polymer-based material can include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the organic encapsulation layer TFE2 can include, for example, an acrylic resin such as polymethyl methacrylate, polyacrylic acid, or the like. The organic encapsulation layer TFE2 can be formed by curing a monomer or applying a polymer.

[0132] The lower inorganic encapsulation layer TFE1 can be disposed on the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS. The lower inorganic encapsulation layer TFE1 can include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 that are respectively disposed corresponding to different emission regions EA1, EA2, and EA3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can include an inorganic insulating material to respectively cover the light-emitting elements ED1, ED2, and ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can prevent or substantially prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0133] Since the lower inorganic encapsulation layer TFE1 (e.g., the first inorganic layer TL1, the second inorganic layer TL2, the third inorganic layer TL3) can be formed by a chemical vapor deposition (CVD) method, it can be formed along the stepped portion of the layer to be deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can form a thin film even under the undercut at the tip of the bank structure BNS. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be disposed along the top surface, side surface, and bottom surface of the second bank BN2, the side surface of the first bank BN1, and the top surfaces of the common electrodes CE1, CE2, and CE3.

[0134] The first inorganic layer TL1 may not overlap with the second opening OPE2 and the third opening OPE3, and may overlap with the first opening OPE1 and be disposed on the first light-emitting element ED1 and the bank structure BNS in its periphery (e.g., only on it). The second inorganic layer TL2 may not overlap with the first opening OPE1 and the third opening OPE3, and may overlap with the second opening OPE2 and be disposed on the second light-emitting element ED2 and the bank structure BNS in its periphery (e.g., only on it). The third inorganic layer TL3 may not overlap with the first opening OPE1 and the second opening OPE2, and may overlap with the third opening OPE3 and be disposed on the third light-emitting element ED3 and the bank structure BNS in its periphery (e.g., only on it).

[0135] The first inorganic layer TL1 can be formed after the formation of the first common electrode CE1. The second inorganic layer TL2 can be formed after the formation of the second common electrode CE2. The third inorganic layer TL3 can be formed after the formation of the third common electrode CE3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be spaced apart from each other on the bank structure BNS.

[0136] The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include main body portions TL1_B, TL2_B, and TL3_B surrounded (e.g., around their perimeters) by a bank structure BNS, and wing portions TL1_W, TL2_W, and TL3_W that protrude from the main body portions TL1_B, TL2_B, and TL3_B and are spaced apart from the top surface of the second bank BN2.

[0137] The main body portions TL1_B, TL2_B, and TL3_B of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may cover the bottom surface of the second bank BN2, the side surfaces of the first bank BN1, the capping layers CAP1, CAP2, and CAP3, and the common electrodes CE1, CE2, and CE3, and may include portions surrounded (e.g., around their perimeters) by a bank structure BNS.

[0138] The wing portions TL1_W, TL2_W, and TL3_W of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be disposed on the side surface and the top surface of the second bank BN2. The wing portions TL1_W, TL2_W, and TL3_W of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be spaced apart from the top surface of the second bank BN2, and each of the wing portions TL1_W, TL2_W, and TL3_W may have a bottom surface facing the top surface of the second bank BN2. Each of the wing portions TL1_W, TL2_W, and TL3_W of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have an undercut structure below its bottom surface, and may include a first side surface and a second side surface, the first side surface being in the undercut structure. The first side surface of the wing portions TL1_W, TL2_W, and TL3_W of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be adjacent to or aligned with the side surface of the second bank BN2 below the bottom surface of the wing portions TL1_W, TL2_W, and TL3_W, and may not overlap with the first bank BN1. The second side surface of the wing portions TL1_W, TL2_W, and TL3_W of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be disposed above the bottom surface of the wing portions TL1_W, TL2_W, and TL3_W, and may overlap with the first bank BN1.

[0139] The enhanced layer EHL can be disposed on the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3, and can cover the undercut structures of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The enhanced layer EHL can include a first enhanced layer EHL1 disposed on the first inorganic layer TL1 and a second enhanced layer EHL2 disposed on the second inorganic layer TL2. The first enhanced layer EHL1 and the second enhanced layer EHL2 can prevent or substantially prevent the first inorganic layer TL1 and the second inorganic layer TL2 from deforming or separating from the tip of the second bank BN2 during an etching or cleaning process after the formation of the first inorganic layer TL1 and the second inorganic layer TL2. The first enhanced layer EHL1 and the second enhanced layer EHL2 can enhance the encapsulation effect of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. As an example, the enhanced layer EHL can be formed by atomic layer deposition (ALD) having excellent step coverage, and can have a thin thickness while covering the undercut structures of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3.

[0140] The first enhanced layer EHL1 can be disposed on the first inorganic layer TL1 and the second bank BN2. The first enhanced layer EHL1 can cover the undercut structure of the first inorganic layer TL1 and the gap space between the wing portion TL1_W of the first inorganic layer TL1 and the second bank BN2. More specifically, the first enhanced layer EHL1 can cover the first side surface and the bottom surface of the wing portion TL1_W of the first inorganic layer TL1 and the top surface of the second bank BN2. In the undercut region of the first inorganic layer TL1, or in other words, in the region where the wing portion TL1_W of the first inorganic layer TL1 overlaps the second bank BN2 in the thickness direction (e.g., the third direction DR3) of the substrate SUB, the second bank BN2, the first enhanced layer EHL1, and the wing portion TL1_W of the first inorganic layer TL1 can be sequentially disposed. Depending on the thickness of the first enhanced layer EHL1, the second enhanced layer EHL2 and the organic encapsulation layer TFE2 can be additionally disposed between the first enhanced layer EHL1 and the wing portion TL1_W of the first inorganic layer TL1.

[0141] The first enhanced layer EHL1 can be formed after the formation of the first inorganic layer TL1. The first enhanced layer EHL1 can overlap with the first opening OPE1 and the first emission region EA1, and can not overlap with the second opening OPE2, the second emission region EA2, the third opening OPE3, and the third emission region EA3.

[0142] The second enhanced layer EHL2 can be disposed on the second inorganic layer TL2 and the first enhanced layer EHL1. The second enhanced layer EHL2 can cover the undercut structure of the second inorganic layer TL2 and the gap space between the wing portion TL2_W of the second inorganic layer TL2 and the first enhanced layer EHL1. More specifically, the second enhanced layer EHL2 can cover the first side surface and the bottom surface of the wing portion TL2_W of the second inorganic layer TL2 and the top surface of the first enhanced layer EHL1. In the undercut region of the second inorganic layer TL2, or in other words, in the region where the wing portion TL2_W of the second inorganic layer TL2 overlaps with the second bank BN2 in the thickness direction of the substrate SUB (e.g., the third direction DR3), the second bank BN2, the first enhanced layer EHL1, the second enhanced layer EHL2, and the wing portion TL2_W of the second inorganic layer TL2 can be sequentially disposed.

[0143] The second enhanced layer EHL2 can be formed after the second inorganic layer TL2 is formed, so the second enhanced layer EHL2 can also be formed on the first enhanced layer EHL1. The second enhanced layer EHL2 can overlap with the first opening OPE1, the first emission region EA1, the second opening OPE2, and the second emission region EA2, but it may not overlap with the third opening OPE3 and the third emission region EA3.

[0144] The wing portions TL1_W, TL2_W, and TL3_W of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be covered by different layers, and the heights of their bottom surfaces can be different from each other. The bottom surface of the wing portion TL2_W of the second inorganic layer TL2 can be located at a height higher than the height of the bottom surface of the wing portion TL1_W of the first inorganic layer TL1. The bottom surface of the wing portion TL3_W of the third inorganic layer TL3 can be located at a height higher than the height of the bottom surface of the wing portion TL2_W of the second inorganic layer TL2.

[0145] The wing portion TL1_W of the first inorganic layer TL1 can be covered by the first enhanced layer EHL1. The bottom surface and the first side surface of the wing portion TL1_W of the first inorganic layer TL1 can be in contact with the first enhanced layer EHL1. The first inorganic layer TL1 can be in contact with the first enhanced layer EHL1, the second bank BN2, and the first bank BN1. The first enhanced layer EHL1, the second enhanced layer EHL2, and the organic encapsulation layer TFE2 can be sequentially disposed on the main body portion TL1_B of the first inorganic layer TL1.

[0146] The wing portion TL2_W of the second inorganic layer TL2 may be covered by the second reinforcing layer EHL2. The bottom surface and the first side surface of the wing portion TL2_W of the second inorganic layer TL2 may be in contact with the second reinforcing layer EHL2. The second inorganic layer TL2 may be in contact with the first reinforcing layer EHL1, the second reinforcing layer EHL2, the second bank BN2, and the first bank BN1. The second reinforcing layer EHL2 and the organic encapsulation layer TFE2 may be sequentially provided on the main body portion TL2_B of the second inorganic layer TL2.

[0147] The wing portion TL3_W of the third inorganic layer TL3 may be covered by the organic encapsulation layer TFE2. The bottom surface and the first side surface of the wing portion TL3_W of the third inorganic layer TL3 may be in contact with the organic encapsulation layer TFE2. The third inorganic layer TL3 may be in contact with the first reinforcing layer EHL1, the second reinforcing layer EHL2, the organic encapsulation layer TFE2, the second bank BN2, and the first bank BN1. In the undercut region of the third inorganic layer TL3, or in other words, in the region where the wing portion TL3_W of the third inorganic layer TL3 overlaps with the second bank BN2 in the thickness direction of the substrate SUB (e.g., the third direction DR3), the second bank BN2, the first reinforcing layer EHL1, the second reinforcing layer EHL2, the organic encapsulation layer TFE2, and the wing portion TL3_W of the third inorganic layer TL3 may be sequentially provided. The third opening OPE3 and the third emission region EA3 may not overlap with the first reinforcing layer EHL1 and the second reinforcing layer EHL2.

[0148] Each of the first reinforcing layer EHL1 and the second reinforcing layer EHL2 may have a constant or substantially constant thickness throughout the cross-section. The first reinforcing layer EHL1 may have the same or substantially the same thickness t1 on the second bank BN2, the main body portion TL1_B of the first inorganic layer TL1, and the bottom surface, the first side surface, and the second side surface of the wing portion TL1_W. The second reinforcing layer EHL2 may have the same or substantially the same thickness t2 on the first reinforcing layer EHL1, the main body portion TL2_B of the second inorganic layer TL2, and the bottom surface, the first side surface, and the second side surface of the wing portion TL2_W. The thickness of each of the first reinforcing layer EHL1 and the second reinforcing layer EHL2 may be controlled by adjusting its film formation process. The thickness t1 of the first reinforcing layer EHL1 and the thickness t2 of the second reinforcing layer EHL2 may be equal or substantially equal to each other, or may be different from each other. In an embodiment, the thickness t1 of the first reinforcing layer EHL1 and the thickness t2 of the second reinforcing layer EHL2 may be different from each other.

[0149] The thickness t1 of the first reinforcing layer EHL1 and the thickness t2 of the second reinforcing layer EHL2 may be equal to or greater than The first enhanced layer EHL1 and the second enhanced layer EHL2 can be formed to have a thin thickness by using an atomic layer deposition (ALD) method. The first enhanced layer EHL1 and the second enhanced layer EHL2 can be formed not to exceed the thickness of the undercut structure of the first inorganic layer TL1 and the second inorganic layer TL2. The thickness t1 of the first enhanced layer EHL1 can be equal to or less than the distance t3 between the bottom surface of the wing portion TL1_W of the first inorganic layer TL1 and the top surface of the second bank BN2. The thickness t2 of the second enhanced layer EHL2 can be equal to or less than the distance t4 between the bottom surface of the wing portion TL2_W of the second inorganic layer TL2 and the top surface of the first enhanced layer EHL1.

[0150] Figure 6 is a cross-sectional view showing the light-emitting element layer EML and the thin film encapsulation layer TFEL of the display device 10 according to another embodiment. In Figure 6 which, the thickness t1_1 of the first enhanced layer EHL1 is different from Figure 5 those of Figure 5 Since the first enhanced layer EHL1 of Figure 6 has a thinner thickness, the first enhanced layer EHL1, the second enhanced layer EHL2, and the organic encapsulation layer TFE2 can be disposed in the undercut structure of the wing portion TL1_W of the first inorganic layer TL1. Since

[0151] the thickness t1_1 of the first enhanced layer EHL1 of

[0152] is equal to or substantially equal to the distance t3 between the bottom surface of the wing portion TL1_W of the first inorganic layer TL1 and the top surface of the second bank BN2, the undercut structure of the wing portion TL1_W of the first inorganic layer TL1 can be filled with the first enhanced layer EHL1. Although not shown in the drawings, the thickness t2_1 of the second enhanced layer EHL2 can also be equal to or close to the distance t4 between the bottom surface of the wing portion TL2_W of the second inorganic layer TL2 and the top surface of the first enhanced layer EHL1.

[0151] There is no particular limitation on the materials of the first enhanced layer EHL1 and the second enhanced layer EHL2 as long as they can be formed by the ALD method. In an embodiment, each of the first enhanced layer EHL1 and the second enhanced layer EHL2 may include, but is not limited to, silicon oxide, aluminum oxide, zirconium oxide, hafnium oxide, cesium oxide, iron oxide, indium oxide, molybdenum oxide, or tin oxide. The first enhanced layer EHL1 and the second enhanced layer EHL2 may include the same material as each other, or may include different materials from each other. For example, the first enhanced layer EHL1 and the second enhanced layer EHL2 may include silicon oxide or aluminum oxide.

[0152] The organic encapsulation layer TFE2 is disposed on the first inorganic layer TL1, the second inorganic layer TL2, the third inorganic layer TL3, the first reinforcing layer EHL1, and the second reinforcing layer EHL2. A portion of the organic encapsulation layer TFE2 may be disposed between the top surface of the second reinforcing layer EHL2 and the wing portion TL3_W of the third inorganic layer TL3. Depending on the thicknesses t1_1 and t2_1 of the first reinforcing layer EHL1 and the second reinforcing layer EHL2, a portion of the organic encapsulation layer TFE2 may or may not be disposed in the undercut regions of the wing portions TL1_W and TL2_W of the first inorganic layer TL1 and the second inorganic layer TL2. The organic encapsulation layer TFE2 may not contact the first inorganic layer TL1 and the second inorganic layer TL2, but may contact the third inorganic layer TL3. The organic encapsulation layer TFE2 may not contact the second bank BN2 in the display area DA.

[0153] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0154] The light blocking layer may be selectively disposed on the thin film encapsulation layer TFEL. The light blocking layer may be positioned between the emission regions EA1, EA2, and EA3. The light blocking layer may include a light absorbing material. For example, the light blocking layer may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer may prevent or substantially prevent visible light from infiltrating and color mixing between the first emission region EA1, the second emission region EA2, and the third emission region EA3, which may improve the color reproducibility of the display device 10.

[0155] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the emission regions EA1, EA2, and EA3 (see, for example, Figure 4 ). Each of the plurality of color filters CF1, CF2, and CF3 may include a filtering pattern region and a light blocking region. The filtering pattern region may be formed to overlap with the emission regions EA1, EA2, and EA3 or the openings OPE1, OPE2, and OPE3 of the bank structure BNS, and may form a light emitting region from which light emitted from the emission regions EA1, EA2, and EA3 is emitted. The light blocking region is a region where the plurality of color filters CF1, CF2, and CF3 are stacked such that light cannot be transmitted.

[0156] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are set to correspond to different emission regions EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include colorants, such as dyes or pigments, that absorb and remove light in wavelength bands other than a specific wavelength band, and may be set to correspond to the colors of light emitted from the emission regions EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is set to overlap with the first emission region EA1 and transmit only the first light of red. The second color filter CF2 may be a green color filter that is set to overlap with the second emission region EA2 and transmit only the second light of green. The third color filter CF3 may be a blue color filter that is set to overlap with the third emission region EA3 and transmit only the third light of blue.

[0157] In the display device 10, the color filters CF1, CF2, and CF3 are set to overlap with each other so that the intensity of the reflected light of external light can be reduced. In addition, the color of the reflected light of external light can be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in a plan view.

[0158] The outer coating OC may be provided on the color filters CF1, CF2, and CF3 to flatten or substantially flatten the tops of the color filters CF1, CF2, and CF3. The outer coating OC may be a colorless light-transmitting layer that does not have a color in the visible light band. For example, the outer coating OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0159] Hereinafter, the manufacturing process of the display device 10 according to an embodiment will be described in more detail with reference to other drawings.

[0160] Figures 7 to 24 are cross-sectional views sequentially showing the manufacturing process of the display device 10 according to an embodiment. Figures 7 to 24 Schematically shows a process of forming the light-emitting elements ED1, ED2, and ED3, the bank structure BNS, and the thin-film encapsulation layer TFEL, where the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS serve as the light-emitting element layer EML of the display device 10. Hereinafter, regarding the manufacturing process of the display device 10, the detailed description of the formation process of each layer will be omitted, and the formation order of each layer will be described in more detail.

[0161] Refer to Figure 7 , a plurality of pixel electrodes AE1, AE2, and AE3, a sacrificial layer SFL, a pixel defining layer PDL, and a plurality of bank material layers BNL1 and BNL2 are formed on the entire or substantially entire second passivation layer PAS2, where the plurality of pixel electrodes AE1, AE2, and AE3 are spaced apart from each other.

[0162] Although not shown in the drawings, the thin film transistor layer TFTL may be disposed on the substrate SUB, and the structure of the thin film transistor layer TFTL is the same as that described above with reference to Figure 4 and thus, its redundant description will not be repeated.

[0163] Next, referring to Figure 8 , a photoresist is formed on the second bank material layer BNL2, and a first etching process (first etch) is performed to partially etch the first bank material layer BNL1 and the second bank material layer BNL2 using the photoresist as a mask. Holes can be formed by the first etching process. The photoresists can be disposed spaced apart from each other on the second bank material layer BNL2, and can be disposed to expose an area overlapping with the first pixel electrode AE1 among the plurality of pixel electrodes AE1, AE2, and AE3.

[0164] In an embodiment, the first etching process (first etch) can be performed as an anisotropic dry etching. A first opening OPE1 of the second bank material layer BNL2 can be formed by the first etching process (for example, see Figure 4 ).

[0165] Next, referring to Figure 9 , an undercut structure of the first bank material layer BNL1 can be formed by a second etching process (second etch). The etching rate of the first bank material layer BNL1 can be higher than that of the second bank material layer BNL2, and the side surface of the second bank material layer BNL2 can be formed to protrude much more than the side surface of the first bank material layer BNL1. An undercut structure of the first bank material layer BNL1 can be formed under the second bank material layer BNL2. In an embodiment, the second etching process can be an isotropic wet etching. The second etching process can use an alkali-based etchant.

[0166] Subsequently, as shown in Figure 10 , a part of the pixel defining layer PDL can be removed by a third etching process (third etch) to expose the sacrificial layer SFL. In an embodiment, the third etching process can be a dry etching process.

[0167] Next, referring to Figure 11 , a part of the sacrificial layer SFL can be removed by a fourth etching process (fourth etch) to expose the first pixel electrode AE1. In an embodiment, the fourth etching process can be a wet etching process.

[0168] The sacrificial layer SFL can protect the pixel electrodes AE1, AE2, and AE3 from plasma in a dry etching process. The sacrificial layer SFL may not be completely removed in the fourth etching process, and a part of the sacrificial layer SFL between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3 may be retained as a remaining pattern RP.

[0169] Subsequently, as shown in Figure 12 , a first light-emitting layer EL1 and a first common electrode CE1 are sequentially stacked on a first pixel electrode AE1 to form a first light-emitting element ED1, and a first capping layer CAP1 is formed on the first common electrode CE1. Here, since the first light-emitting layer EL1, the first common electrode CE1, and the first capping layer CAP1 are formed over the entire or substantially the entire surface of the substrate SUB, a first emission pattern layer ELP1, a first electrode pattern layer CEP1, and a first capping pattern layer CPP1 may also be formed on the second bank material layer BNL2.

[0170] Since the materials deposited over the entire or substantially the entire surface of the substrate SUB can be cut (e.g., separated) by the protruding side surfaces and tips of the second bank material layer BNL2, the first light-emitting layer EL1 and the first emission pattern layer ELP1 can be separated from each other, the first common electrode CE1 and the first electrode pattern layer CEP1 can be separated from each other, and the first capping layer CAP1 and the first capping pattern layer CPP1 can be separated from each other. The first light-emitting layer EL1 can be formed on the first pixel electrode AE1, and the first emission pattern layer ELP1 can be formed on the second bank material layer BNL2. When the first common electrode CE1 is formed on the first light-emitting layer EL1, the first electrode pattern layer CEP1 can be formed on the first emission pattern layer ELP1.

[0171] The first light-emitting layer EL1 and the first common electrode CE1 can be formed by a thermal deposition process. Inside the opening, due to the tips of the second bank material layer BNL2, the deposition of materials may not be carried out smoothly. However, since the materials of the first light-emitting layer EL1 and the first common electrode CE1 can be deposited in an inclined direction rather than in a direction perpendicular or substantially perpendicular to the top surface of the substrate SUB, they can be deposited even in the areas hidden by the tips of the second bank material layer BNL2.

[0172] Compared with the deposition processes for forming the light-emitting layers EL1, EL2, and EL3, the deposition processes for forming the common electrodes CE1, CE2, and CE3 can be carried out at an angle inclined relatively closer to the horizontal direction. Therefore, compared with the areas of the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3 can contact the side surfaces of the first bank material layer BNL1 with a larger area. As another example, compared with the positions of the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3 can be deposited at higher positions on the side surfaces of the first bank material layer BNL1. The different common electrodes CE1, CE2, and CE3 can be electrically connected to each other while being in contact with the first bank material layer BNL1 having high conductivity.

[0173] Next, a first inorganic material layer TLL1 covering the first capping layer CAP1 and the first capping pattern layer CPP1 is formed. In an embodiment, the first inorganic material layer TLL1 can be formed by a chemical vapor deposition (CVD) method. The first inorganic material layer TLL1 can be formed along the stepped portions of the first light-emitting element ED1 and the bank structure BNS.

[0174] Next, referring to Figure 13 , a fifth etching process (fifth etch) is performed to remove a portion of the first inorganic material layer TLL1, thereby exposing the first electrode pattern layer CEP1 (or the first capping pattern layer CPP1). A photoresist is formed as a mask in an area overlapping with the first emission region EA1 and an edge region surrounding the first emission region EA1 (e.g., around the periphery of the first emission region EA1), and the first inorganic material layer TLL1 that is not covered by the mask is removed. By the fifth etching process, the first inorganic layer TL1 remains in the area overlapping with the first emission region EA1 and the edge region surrounding it. In an embodiment, the fifth etching process can be an anisotropic dry etching.

[0175] Subsequently, referring to Figure 14 , a sixth etching process (sixth etch) is performed to remove the first capping pattern layer CPP1, the first electrode pattern layer CEP1, and the first emission pattern layer ELP1, thereby exposing the second bank material layer BNL2. In an embodiment, the sixth etching process can include an isotropic wet etching process. The first emission pattern layer ELP1, the first electrode pattern layer CEP1, and the first capping pattern layer CPP1 provided between the wing portion TL1_W of the first inorganic layer TL1 and the second bank material layer BNL2 can also be removed, thereby forming an undercut structure of the first inorganic layer TL1.

[0176] Next, as shown in Figure 15 , a first reinforcing material layer EHLL1 is formed on the first inorganic layer TL1 and the second bank material layer BNL2. The first reinforcing material layer EHLL1 can be formed by using an atomic layer deposition (ALD) method. Since the ALD method has excellent step coverage, the first reinforcing material layer EHLL1 can also be formed inside the undercut structure of the first inorganic layer TL1. The first reinforcing material layer EHLL1 can cover all of the bottom surface, the first side surface, and the top surface of the wing portion TL1_W of the first inorganic layer TL1 and can have a thin thickness.

[0177] Subsequently, by repeating the process shown in Figures 8 to 11 , a second opening OPE2 of the bank structure BNS can be formed (e.g., see Figure 4 ), as shown in Figure 16 . By this process, the second pixel electrode AE2 can be exposed.

[0178] Figure 17 and Figure 18 Figure 19 illustrates a process of forming a second light-emitting element ED2 and a second inorganic layer TL2. This process can be similar to Figures 12 to 14 's process. However, during the etching or cleaning process in this process, the first inorganic layer TL1 is protected by the first reinforcing material layer EHLL1, so that the penetration and damage of moisture to the first light-emitting element ED1 can be avoided. Through this process, the first reinforcing material layer EHLL1 can be exposed. Figures 17 to 19 The second inorganic material layer TLL2, the second emission pattern layer ELP2, the second electrode pattern layer CEP2, and the second capping pattern layer CPP2 of Figures 12 to 14 can be respectively similar to the first inorganic material layer TLL1, the first emission pattern layer ELP1, the first electrode pattern layer CEP1, and the first capping pattern layer CPP1 of

[0179] Refer to Figure 20 , a second reinforcing material layer EHLL2 is formed on the second inorganic layer TL2 and the first reinforcing material layer EHLL1. This process can be performed in a manner similar to Figure 15 's manner.

[0180] Next, refer to Figure 21 , Figure 22 , Figure 23 and Figure 24 , a third light-emitting element ED3 and a third inorganic layer TL3 can be formed on the third pixel electrode AE3. This process can be performed in a manner similar to Figures 8 to 14 's manner, so that an undercut structure of the third inorganic layer TL3 can be obtained. Figures 21 to 24 The third inorganic material layer TLL3, the third emission pattern layer ELP3, the third electrode pattern layer CEP3, and the third capping pattern layer CPP3 of Figures 12 to 14 can be respectively similar to the first inorganic material layer TLL1, the first emission pattern layer ELP1, the first electrode pattern layer CEP1, and the first capping pattern layer CPP1 of

[0181] Subsequently, an organic encapsulation layer TFE2 can be formed on the third inorganic layer TL3. A part of the organic encapsulation layer TFE2 can be disposed inside the undercut structure between the wing portion TL3_W of the third inorganic layer TL3 and the second reinforcing layer EHL2.

[0182] In addition, a display device 10 can be manufactured by forming an organic encapsulation layer TFE2 and an upper inorganic encapsulation layer TFE3 of a thin film encapsulation layer TFEL, a color filter layer CFL, and an outer coating OC on the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS. The structures of the thin film encapsulation layer TFEL, the color filter layer CFL, and the outer coating OC are the same as the above-described structures, and thus, redundant descriptions thereof are not repeated.

[0183] The above is an example of some embodiments of the present disclosure and should not be construed as limiting it. Although some embodiments have been described, those skilled in the art will readily understand that various modifications are possible in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Thus, as will be apparent to those of ordinary skill in the art, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it is to be understood that the above is an example of various exemplary embodiments and should not be construed as limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: A first pixel electrode, on the substrate; a pixel defining layer, on the substrate and exposing the first pixel electrode; a first light-emitting layer, on the first pixel electrode; a first common electrode, on the first light-emitting layer; a first bank on the pixel defining layer; a second bank on the first bank and including a side surface protruding beyond the side surface of the first bank; The first inorganic layer comprises: a main body portion, on the first common electrode; and a wing portion protruding from the main body portion and spaced apart from a top surface of the second bank; a first reinforcement layer between the wing portion of the first inorganic layer and the top surface of the second bank and on the first inorganic layer; and An organic encapsulation layer is on the first reinforcement layer.

2. The display device according to claim 1, wherein: The first reinforcement layer has the same thickness on the second bank and the first inorganic layer.

3. The display device according to claim 1, wherein: The thickness of the first reinforcement layer is equal to or greater than and is equal to or smaller than a distance between a bottom surface of the wing portion of the first inorganic layer and a top surface of the second bank.

4. The display device according to claim 1, wherein: The first reinforcement layer includes silicon oxide, aluminum oxide, zirconium oxide, hafnium oxide, cesium oxide, iron oxide, indium oxide, molybdenum oxide or tin oxide.

5. The display device according to claim 1, further comprising: a second pixel electrode, spaced apart from the first pixel electrode on the substrate; a second light emitting layer, on the second pixel electrode; a second common electrode, on the second light emitting layer and spaced apart from the first common electrode; The second inorganic layer comprises: a main body portion, on the second common electrode; and a wing portion protruding from the main portion of the second inorganic layer and spaced apart from the top surface of the second bank; and A second reinforcement layer is between the first reinforcement layer and the organic encapsulation layer, and between the wing portion of the second inorganic layer and the top surface of the second bank.

6. The display device according to claim 5, wherein: A thickness of the first reinforcement layer and a thickness of the second reinforcement layer are different from each other.

7. The display device according to claim 5, wherein: The second bank includes a first opening overlapping the first common electrode and a second opening overlapping the second common electrode, and The first reinforcement layer overlaps with the first opening of the second bank and does not overlap with the second opening of the second bank.

8. The display device according to claim 7, wherein: The second reinforcement layer overlaps the first opening and the second opening of the second bank.

9. The display device according to claim 5, wherein: In a region where the wing portion of the second inorganic layer and the second bank overlap each other in the thickness direction of the substrate, the second bank, the first reinforcement layer, the second reinforcement layer, and the wing portion of the second inorganic layer are sequentially located on each other.

10. The display device according to claim 5, wherein: The first reinforcement layer, the second reinforcement layer, and the organic encapsulation layer are sequentially located on the main portion of the first inorganic layer.

11. The display device according to claim 5, wherein: The second reinforcement layer is located on the body portion of the second inorganic layer and the wing portion of the second inorganic layer.

12. The display device according to claim 5, wherein: The second inorganic layer contacts the second bank, the first reinforcement layer, and the second reinforcement layer.

13. The display device according to claim 7, further comprising: a third pixel electrode, spaced apart from the first pixel electrode and the second pixel electrode on the substrate; a third light-emitting layer, on the third pixel electrode; a third common electrode, on the third light emitting layer and spaced apart from the first common electrode and the second common electrode; as well as The third inorganic layer comprises: A main body portion, on the third common electrode; as well as A wing portion protrudes from the body portion of the third inorganic layer and is spaced apart from the top surface of the second bank.

14. The display device according to claim 13, wherein: The second bank further includes a third opening overlapping the third common electrode, and The first reinforcement layer and the second reinforcement layer do not overlap with the third opening of the second bank.

15. The display device according to claim 13, wherein: A bottom surface of the wing portion of the first inorganic layer is in contact with the first reinforcement layer, wherein a bottom surface of the wing portion of the second inorganic layer is in contact with the second reinforcement layer, and Wherein, a bottom surface of the wing portion of the third inorganic layer contacts the organic encapsulation layer.

16. A method for manufacturing a display device, comprising: forming a plurality of pixel electrodes spaced apart from each other on a substrate; forming a pixel defining layer exposing the pixel electrode; forming a first bank on the pixel defining layer; forming a second bank on the first bank, wherein a side surface of the second bank protrudes beyond a side surface of the first bank; forming a first light emitting layer on a first pixel electrode among the pixel electrodes and a first emission pattern layer on the second bank; forming a first common electrode on the first light-emitting layer and a first electrode pattern layer on the first emission pattern layer; forming a first inorganic material layer on the first common electrode; etching a portion of the first inorganic material layer; etching the first emission pattern layer and the first electrode pattern layer to expose the second bank; as well as A first reinforcement material layer is formed on the second bank and the first inorganic material layer by using an atomic layer deposition method.

17. The method according to claim 16, wherein: Etching the first emission pattern layer and the first electrode pattern layer to expose the second bank includes removing the first emission pattern layer and the first electrode pattern layer between the second bank and the first inorganic material layer.

18. The method according to claim 16, wherein: Forming the first light-emitting layer on the first pixel electrode among the pixel electrodes and the first emission pattern layer on the second embankment includes: depositing material on the substrate, the material being cut off by the protruding side surface of the second embankment and separated into the first light-emitting layer and the first emission pattern layer.

19. The method according to claim 16, further comprising: forming a second light-emitting layer on a second pixel electrode among the pixel electrodes and a second emission pattern layer on the first enhancement material layer; forming a second common electrode on the second light emitting layer and a second electrode pattern layer on the second emission pattern layer; forming a second inorganic material layer on the second common electrode; etching a portion of the second inorganic material layer; etching the second emission pattern layer and the second electrode pattern layer to expose the first enhancement material layer; as well as A second reinforcing material layer is formed on the first reinforcing material layer and the second inorganic material layer.

20. The method according to claim 19, further comprising: forming a third light-emitting layer on a third pixel electrode among the pixel electrodes and a third emission pattern layer on the second enhancement material layer; forming a third common electrode on the third light-emitting layer and a third electrode pattern layer on the third emission pattern layer; forming a third inorganic material layer on the third common electrode; etching a portion of the third inorganic material layer; etching the third emission pattern layer and the third electrode pattern layer to expose the second enhancement material layer; as well as An organic encapsulation layer is formed on the second reinforcement material layer and the third inorganic material layer.

Images