Display device

Abstract

The present disclosure provides a display device including: a substrate defined with a display area including a plurality of sub-pixels and a non-display area located outside the display area and including a pad area; at least one pad disposed in the pad region; at least one data line disposed in the display area and extending in a column direction; at least one horizontal link line electrically connected to the at least one data line and extending in the row direction; at least one vertical link line electrically connecting the at least one horizontal link line and the at least one pad and extending in the column direction; at least one horizontal metal pattern spaced apart from the at least one horizontal link line and extending in a row direction; at least one vertical metal pattern spaced apart from the at least one vertical link line and extending in the column direction; the first area comprises at least one first connecting hole; a second region including at least one first dummy connection hole; and a third region including at least one second dummy connection hole.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0193791, filed with the Korean Intellectual Property Office on December 28, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device including a data link structure. Background art

[0004] A display device may include a display area configured to be able to display an image and a non - display area where no image is displayed. To enable the display device to perform various functions such as displaying an image, sensing a touch event, etc., various structures, circuits, lines, etc. may be arranged in the non - display area (which may also be referred to as a "bezel") of the display panel. To meet the market demand for a large display area, it is desirable to reduce the bezel of the display panel. However, since various control elements of the display panel are located in the non - display area, it is not easy to reduce the bezel of the display panel. In particular, since link lines for transmitting data signals to data lines may be provided in the non - display area of the display panel, reducing the bezel of the display panel has become a major challenge. Summary of the invention

[0005] To solve these problems, one or more aspects of the present disclosure may provide a display device having a data link structure capable of reducing the bezel of a display panel.

[0006] One or more aspects of the present disclosure may provide a display device having a bezel - reducing data link structure capable of improving image quality.

[0007] One or more aspects of the present disclosure may provide a display device having a bezel - reducing data link structure capable of improving the performance of transmitting a common driving voltage.

[0008] One or more aspects of the present disclosure may provide a display device having a bezel - reducing data link structure capable of correcting display artifacts (e.g., some image display defects perceived as patterns).

[0009] According to one or more example embodiments of the present disclosure, a display device may be provided. The display device includes: a substrate defining a display area including a plurality of sub-pixels and a non-display area located outside the display area and including a pad area; at least one pad disposed in the pad area; at least one data line disposed in the display area and extending in a column direction; at least one horizontal link line electrically connected to at least one data line and extending in a row direction; at least one vertical link line electrically connecting at least one horizontal link line and at least one pad and extending in the column direction; at least one horizontal metal pattern spaced apart from at least one horizontal link line and extending in the row direction; at least one vertical metal pattern spaced apart from at least one vertical link line and extending in the column direction; a first area including at least one first connection hole through which at least one data line and at least one horizontal metal pattern are electrically connected; a second area including at least one first dummy connection hole in an area where at least one data line and at least one vertical metal pattern respectively overlap at least one horizontal link line; and a third area including at least one second dummy connection hole in an area where at least one vertical link line and at least one horizontal metal pattern overlap each other.

[0010] In one or more aspects, the display device may further include: at least one second connection hole through which at least one data line and at least one horizontal link line are electrically connected; and at least one third connection hole through which at least one horizontal link line and at least one vertical link line are electrically connected. At least one second connection hole may be disposed in a first inclined direction with respect to a horizontal direction or a vertical direction, and at least one third connection hole may be disposed in a second inclined direction different from the first inclined direction.

[0011] In one or more aspects, a boundary between the first area and the second area may be formed in the first inclined direction in which at least one second connection hole is disposed, and a boundary between the second area and the third area may be formed in the second inclined direction in which at least one third connection hole is disposed.

[0012] According to one or more aspects of the present disclosure, a display device having a data link structure capable of reducing a border of a display panel may be provided.

[0013] According to one or more aspects of the present disclosure, a display device having a border reduction data link structure capable of improving image quality may be provided.

[0014] According to one or more aspects of the present disclosure, a display device having a border reduction data link structure capable of improving the performance of transmitting a common driving voltage may be provided.

[0015] According to one or more aspects of the present disclosure, a display device having a border reduction data link structure capable of correcting display artifacts (e.g., some image display defects perceived as patterns) can be provided.

[0016] According to one or more aspects of the present disclosure, a weight-reduced display device and / or display panel can be provided by reducing the border of a display panel based on an improved data link structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present disclosure includes drawings to provide a further understanding of the present disclosure. The drawings are incorporated in and constitute a part of this application. The drawings illustrate aspects of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0018] Figure 1 An example of a system configuration of a display device according to an aspect of the present disclosure is shown;

[0019] Figure 2 An example of a display panel according to an aspect of the present disclosure is shown;

[0020] Figure 3 An example of a cross-sectional view of a display panel according to an aspect of the present disclosure;

[0021] Figure 4 An example of a substrate of a display panel according to an aspect of the present disclosure is shown;

[0022] Figure 5 An example of a plan view of a display panel according to an aspect of the present disclosure, and a data link structure configured in the display panel is shown;

[0023] Figure 6 Another example of a plan view of a display panel according to an aspect of the present disclosure, and an example data link structure capable of reducing the border of the display panel is shown;

[0024] Figure 7 An example of three regions defined by a border reduction data link structure of a display panel according to an aspect of the present disclosure in a display area is shown;

[0025] Figure 8 An example of a region of a display panel having a border reduction data link structure according to an aspect of the present disclosure is shown; and

[0026] Figure 9 is an example of a cross-sectional view taken along line Figure 8 A - A' of. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to aspects of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, detailed descriptions of well-known functions, structures, or configurations may be omitted for the sake of brevity when they may unnecessarily obscure aspects of the present disclosure. In addition, repetitive descriptions may be omitted for the sake of brevity. The processes of the processing steps and / or operations are non-limiting examples.

[0028] The order of the steps and / or operations is not limited to the order described herein and may occur in an order different from the order described herein, except in cases where the steps and / or operations must occur in a specific order. In one or more examples, two consecutive operations may be performed substantially simultaneously, or the two operations may be performed in a reverse order or a different order depending on the functions or operations involved.

[0029] Unless otherwise specified, the same reference numerals refer to the same elements even if shown in different drawings. In one or more aspects, unless otherwise specified, the same elements (or elements with the same name) in different drawings may have the same or substantially the same functions and characteristics. The names of the various elements used in the following description are chosen for convenience only and may therefore be different from the names used in actual products.

[0030] The advantages and features of the present disclosure and its implementation methods become clear by referring to the aspects described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the example aspects set forth herein. On the contrary, these example aspects are examples, and these examples are provided so that the present disclosure can be thorough and complete to help those skilled in the art understand the inventive concept without limiting the scope of the present disclosure.

[0031] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), dimensions, ratios, angles, quantities, etc. (including the shapes, ratios, angles, quantities, etc. shown in the figures) disclosed herein and shown in the accompanying drawings are only examples, and thus, the present disclosure is not limited to the details shown. Any implementation described as an "example" herein is not necessarily to be construed as superior to or more beneficial than other implementations. However, it should be noted that the relative sizes of the components shown in the drawings are part of the present disclosure.

[0032] When terms such as "comprising", "having", "including", "containing", "constituting", "consisting of", "formed from", etc. are used with respect to one or more other elements, one or more other elements may be added unless terms such as "only" are used. The terms used in the present disclosure are only used to describe example aspects and are not intended to limit the scope of the present disclosure. Unless the context clearly indicates otherwise, singular terms may include plural forms.

[0033] Unless otherwise specified, the term "exemplary" is used to denote an example or illustration. An aspect is an example aspect. An aspect is an example aspect. "Aspect", "example", "example aspect", "aspect", etc. should not be construed as being superior to or more advantageous than other embodiments. Unless otherwise specified, an aspect, an example, an example aspect, an aspect, etc. may refer to one or more aspects, one or more examples, one or more example aspects, one or more aspects, etc. Additionally, the term "may" encompasses all meanings of the term "can".

[0034] In one or more aspects, unless otherwise explicitly stated, an element, a feature, or the corresponding information (e.g., level, range, dimension, size, etc.) is interpreted as including a margin of error or tolerance, even if no explicit description of such margin of error or tolerance is provided. The margin of error or tolerance may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). When interpreting a numerical value, unless otherwise explicitly stated, the value is interpreted as including the margin of error.

[0035] When describing positional relationships, when describing the positional relationship between two parts (e.g., layer, film, region, component, section, etc.), such as using "on", "above", "at the top of", "over", "under", "below", "beneath", "near", "close to", "adjacent to", "next to", "abutting", "on or at one side of", etc., one or more other parts may be located between the two parts, unless more restrictive terms are used, such as "abuttingly", "directly", or "proximally". For example, when a structure is described as being "on", "above", "at the top of", "over", "under", "below", "beneath", "near", "close to", "adjacent to", "next to", "abutting", "on or at one side of", etc. another structure, such description should be understood to include the case where the structures are in contact with each other and the case where one or more additional structures are disposed or interposed therebetween. Additionally, the terms "front", "rear", "back", "left", "right", "top", "bottom", "down", "up", "upper", "lower", "on", "off", "column", "row", "vertical", "horizontal", etc. refer to an arbitrary reference frame.

[0036] Spatial relative terms such as "below", "beneath", "lower", "on", "above", "upper", etc. may be used to describe the correlation between various elements (e.g., layers, films, regions, components, sections, etc.) shown in the drawings. The spatial relative terms should be understood to include terms for different orientations of the elements in use or operation in addition to the orientation shown in the drawings. For example, if the elements shown in the drawings are flipped, an element described as "below" or "beneath" other elements will be positioned "above" the other elements. Thus, the term "below" as an example term may include all orientations of "above" and "below". Similarly, the exemplary terms "above" or "on" may include both orientations of "above" and "below".

[0037] When describing temporal relationships, when the chronological order is described as, for example, "after", "subsequently", "next", "before", "prior to", "preceding", etc., non - consecutive or non - sequential cases may be included, and thus one or more other events may occur in between, unless more restrictive terms such as "just", "immediately", or "directly" are used.

[0038] Terms such as "below", "lower", "above", "upper", etc. that may be used herein can be used to describe the relationship between the elements shown in the drawings. It should be understood that these terms are spatially relative and based on the orientation shown in the drawings.

[0039] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements (e.g., layers, films, regions, components, sections, etc.), these elements should not be limited by these terms, such as the order, precedence, or quantity of any particular element. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. In addition, without departing from the scope of the present disclosure, the first element, the second element, etc. can be arbitrarily named according to the convenience of those skilled in the art. For clarity, the function or structure of these elements (e.g., the first element, the second element, etc.) is not limited by the ordinal number or name in front of the element. In addition, the first element may include one or more first elements. Similarly, the second element, etc. may include one or more second elements, etc.

[0040] When describing the elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", or "(b)", etc. may be used. These terms are intended to distinguish the corresponding elements from other elements and are not used to define the nature, basis, order, or quantity of the elements.

[0041] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements (e.g., layers, films, regions, components, segments, etc.), these elements should not be limited by these terms, such as any specific element order, precedence order, or quantity. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. In addition, without departing from the scope of the present disclosure, the first element, the second element, etc. may be arbitrarily named according to the convenience of those skilled in the art. For clarity, the functions or structures of these elements (e.g., the first element, the second element, etc.) are not limited by the ordinal numbers or names in front of the elements. In addition, the first element may include one or more first elements. Similarly, the second element, etc. may include one or more second elements, etc.

[0042] For the expressions of describing an element (e.g., a layer, a film, a region, a component, a segment, etc.) as "connected", "bonded", "attached", "adhered", etc. to another element, unless otherwise specified, this element can not only be directly connected, bonded, attached, adhered, etc. to another element, but also be indirectly connected, bonded, attached, adhered, etc. to another element when one or more intermediate elements are provided or interposed between the elements.

[0043] For the expressions of an element (e.g., a layer, a film, a region, a component, a segment, etc.) "contacting", "overlapping", etc. with another element, unless otherwise specified, this element can not only directly contact, overlap, etc. with another element, but also indirectly contact, overlap, etc. with another element when one or more intermediate elements are provided or interposed between the elements.

[0044] The expressions of an element (e.g., a layer, a film, a region, a component, a segment, etc.) being "disposed", "arranged", etc. in another element can be understood as at least a part of this element being disposed, arranged, etc. in another element, or the whole of this element being disposed, arranged, etc. in another element. The expressions of an element (e.g., a layer, a film, a region, a component, a segment, etc.) "contacting", "overlapping", etc. with another element can be understood as at least a part of this element contacting, overlapping, etc. with at least a part of another element, the whole of this element contacting, overlapping, etc. with at least a part of another element, or at least a part of this element contacting, overlapping, etc. with the whole of another element.

[0045] Terms such as "line" or "direction" should not be interpreted solely based on the geometric relationship that the respective lines or directions are parallel or perpendicular to each other. Such terms may mean a wider range of lines or directions within which the components of the present disclosure can operate functionally. For example, terms such as "first direction", "second direction", etc., such as directions parallel or perpendicular to the "X-axis", "Y-axis", or "Z-axis", should not be interpreted solely based on the geometric relationship that the respective directions are parallel or perpendicular to each other, and can represent directions having a wider directivity within the range in which the components of the present disclosure can operate functionally.

[0046] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, each of the expressions "at least one of the first item, the second item, or the third item" and "at least one of the first item, the second item, and the third item" can represent: (i) a combination of items provided by more than two of the first item, the second item, and the third item; or (ii) only one provided by the first item, the second item, or the third item.

[0047] The expression of the first element, the second element, "and / or" the third element should be understood to include one of the first element, the second element, and the third element, as well as any and all combinations of the first element, the second element, and the third element. For example, A, B, and / or C includes: only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); or some combinations of A, B, and C (e.g., A and B; A and C; or B and C); and all of A, B, and C. In addition, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to only A, only B, A or B, or A and B.

[0048] In one or more aspects, unless otherwise specified, for convenience, the terms "between" and "among" can be used interchangeably. For example, the expression "between a plurality of elements" can be understood as among a plurality of elements. In another example, the expression "among a plurality of elements" can be understood as between a plurality of elements. In one or more examples, the number of elements can be two. In one or more examples, the number of elements can be more than two. In addition, when an element (e.g., a layer, a film, a region, a component, a section, etc.) is referred to as being "between" at least two elements, the element can be the only element between the at least two elements, or there can also be one or more intermediate elements.

[0049] In one or more aspects, unless otherwise specified, for convenience, the expressions "each other" and "one another" may be used interchangeably. For example, the expression "different from each other" can be understood as different from one another. In another example, the expression "different from each other" can be understood as different from each other. In one or more examples, the number of elements involved in the above expressions can be two. In one or more examples, the number of elements involved in the above expressions can be more than two.

[0050] In one or more aspects, unless otherwise specified, for convenience, the expressions "one or more of which" and "one or more" may be used interchangeably.

[0051] The term "or" means "including or" rather than "exclusive or". That is, unless otherwise specified or the context clearly indicates, the expression "x uses a or b" means any one of the naturally inclusive arrangements. For example, "a or b" can mean "a", "b", or "a and b". For example, "a, b, or c" can mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0052] The features of the various aspects of the present disclosure can be partially or fully combined or combined with each other, can be technically interrelated, and can be operatively combined, linked, or driven in various ways. The various aspects of the present disclosure can be implemented or executed independently of each other, or can be implemented or executed together in a mutually dependent or related relationship. In one or more aspects, the components of each device according to the various aspects of the present disclosure can be operatively combined and configured.

[0053] Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meaning as those commonly understood by a person of ordinary skill in the art to which the example aspects belong. It should also be understood that unless otherwise clearly defined herein, the terms (for example, terms defined in a common dictionary) should be interpreted as having a meaning consistent with the meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense.

[0054] The terms used herein are selected as common terms in the relevant technical field. However, due to the development and / or changes in technology, conventions, preferences of those skilled in the art, etc., there may be other terms. Therefore, the terms used herein should not be understood as limiting the technical concept, but should be understood as examples of the terms used to describe the example aspects.

[0055] In addition, in certain cases, the applicant can arbitrarily select terms, and in such cases, their detailed meanings are described herein. Therefore, the terms used herein should be understood not only based on the name of the terms, but also based on the meaning of the terms and the content herein.

[0056] The "X-axis direction", "Y-axis direction", and "Z-axis direction" should not be understood as geometric relationships having only a perpendicular relationship with each other, but can have a broader directivity within the range where the elements of the present disclosure can function.

[0057] In the following description, various exemplary aspects of the present disclosure will be described in detail with reference to the accompanying drawings. Regarding the reference numerals of the elements of each drawing, unless otherwise specified, the same elements may be shown in other drawings, and the same reference numerals may refer to the same elements. Even if the same or similar elements are shown in different drawings, they may be represented by the same reference numerals. Additionally, for ease of description, the ratios, dimensions, sizes, and thicknesses of the various elements shown in the drawings may be different from the actual ratios, dimensions, sizes, and thicknesses. Therefore, the various aspects of the present disclosure are not limited to the ratios, dimensions, sizes, and thicknesses shown in the drawings.

[0058] Figure 1 An example of the system configuration of the display device 100 according to an aspect of the present disclosure is shown. According to all aspects of the present disclosure, all components of each display device are operably combined and configured.

[0059] Referring to Figure 1 , in one or more aspects, the display device 100 may include a display panel 110 and a display driving circuit as elements configured to display an image. The display driving circuit may be a circuit configured to drive the display panel 110 and includes a data driving circuit 120, a gate driving circuit 130, a controller 140, and other circuit components.

[0060] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP provided on the substrate 111.

[0061] The substrate 111 may include a display area AA capable of displaying an image and a non-display area NA provided outside the display area.

[0062] A plurality of sub-pixels SP for displaying an image may be provided in the display area AA. The non-display area NA may include a pad area PA and the like. For example, the pad area PA may be a part of the non-display area NA provided along a first direction (e.g., column direction or row direction) from the display area AA.

[0063] According to aspects of the present disclosure, the display panel 110 can be configured to have a very small non-display area NA. Here, the non-display area NA can also be referred to as a "border". For example, the non-display area NA can include a first non-display area disposed outside the display area AA in a first direction, a second non-display area disposed outside the display area AA in a second direction, a third non-display area disposed outside the display area AA in a direction opposite to the first direction, and a fourth non-display area disposed outside the display area AA in a direction opposite to the second direction. The first non-display area among the first non-display area to the fourth non-display area can include a pad area for connecting or bonding (or attaching) a driving circuit. Among the first non-display area to the fourth non-display area, the second non-display area to the fourth non-display area that do not include a pad area can have a very small size compared to the first non-display area.

[0064] In another example, a boundary area can be located between the display area AA and the non-display area NA. In this example, the non-display area NA can be bent at an angle to the display area AA so that it can be located below the display area AA. In this embodiment, when a user views the display device 100 in front of him / her, all or most of the non-display area NA can be invisible to the user. However, aspects of the present disclosure are not limited thereto.

[0065] Various types of signal lines for driving a plurality of sub-pixels SP can be provided on the substrate 111 of the display panel 110.

[0066] In some aspects, the display device 100 herein can be a liquid crystal display device or the like, or can be a self-emitting display device that emits light from the display panel 110 itself. In an example where the display device 100 is a self-emitting display device, each of the plurality of sub-pixels SP can include a light-emitting element. However, aspects of the present disclosure are not limited thereto.

[0067] For example, according to aspects of the present disclosure, the display device 100 can be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to implement a light-emitting element. In another example, according to aspects of the present disclosure, the display device 100 can be an inorganic light-emitting display device that uses a light-emitting diode based on an inorganic material to implement a light-emitting element. In another example, according to aspects of the present disclosure, the display device 100 can be a quantum dot display device that uses quantum dots to implement a light-emitting element, and quantum dots are self-emitting semiconductor crystals. However, aspects of the present disclosure are not limited thereto.

[0068] The structure of each of the plurality of sub-pixels SP may vary according to the type of the display device 100. For example, in an example where the display device 100 is a self-emitting display device including self-emitting sub-pixels SP, each sub-pixel SP may include a self-emitting light-emitting element, one or more transistors, and one or more capacitors.

[0069] The various types of signal lines may include, for example, a plurality of data lines DL for transmitting data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for transmitting gate signals (which may be referred to as scan signals), and the like.

[0070] In one or more aspects, the plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be configured to extend in a first direction, and each of the plurality of gate lines GL may be configured to extend in a second direction. For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction. In another example, the first direction may be a row direction or a horizontal direction, and the second direction may be a column direction or a vertical direction. Hereinafter, for ease of explanation, an example in which each of the plurality of data lines DL is arranged in the column direction and each of the plurality of gate lines GL is arranged in the row direction will be discussed, but the aspects of the present disclosure are not limited thereto.

[0071] The data driving circuit 120 may be a circuit for driving the plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0072] The data driving circuit 120 may receive the image data DATA in digital form from the controller 140, convert the received image data DATA into an analog form of data signal, and output the converted data signal to the plurality of data lines DL.

[0073] In some aspects, the data driving circuit 120 may be connected to the display panel 110 by tape automated bonding (TAB) technology, or connected to a conductive pad (e.g., a bonding pad) of the display panel 110 by chip on glass (COG) technology or chip on panel (COP) technology, or connected to the display panel 110 by chip on film (COF) technology. However, the aspects of the present disclosure are not limited thereto.

[0074] The data driving circuit 120 may be disposed only on one side or one edge (e.g., the upper or lower part) of the display panel 110, and / or only on one side or one edge (e.g., the upper or lower part) electrically connected to the display panel 110, but is not limited thereto. In some aspects, according to the driving method, panel design method, etc., the data driving circuit 120 may be disposed on both sides or two edges (e.g., the upper and lower parts) of the display panel 110, or on at least two sides or two edges of the four sides or four edges (e.g., the upper, lower, left, and right parts) of the display panel 110, and / or electrically connected to both sides or two edges (e.g., the upper and lower parts) of the display panel 110 or at least two sides or two edges of the four sides or four edges (e.g., the upper, lower, left, and right parts) of the display panel 110, but is not limited thereto.

[0075] The data driving circuit 120 may be connected to the outside or periphery of the display area AA of the display panel 110, or disposed within the display area AA of the display panel 110.

[0076] The gate driving circuit 130 may be a circuit configured to drive a plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL.

[0077] The gate driving circuit 130 may receive various types of gate driving control signals GCS. In addition, the gate driving circuit 130 also receives a first gate voltage corresponding to the conduction level voltage and a second gate voltage corresponding to the cut-off level voltage. Therefore, the gate driving circuit 130 may generate gate signals and supply the generated gate signals to the plurality of gate lines GL.

[0078] In some aspects, the gate driving circuit 130 in the display device 100 may be embedded in the display panel 110 by the gate-in-panel (GIP) technology. In an example where the gate driving circuit 130 is implemented by the gate-in-panel (GIP) technology, the gate driving circuit 130 may be disposed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110 or the display device 100.

[0079] In one aspect, the gate driving circuit 130 may be disposed in the non-display area NA of the display panel 110.

[0080] In another aspect, the gate driving circuit 130 may be disposed in the display area AA of the display panel 110. In this embodiment, for example, the gate driving circuit 130 may be disposed in and / or electrically connected to a part of the first area (e.g., the left area or the right area) of the display area AA of the display panel 110, but is not limited thereto. In another example, the gate driving circuit 130 may be disposed in and / or electrically connected to a part of the first area (e.g., the left area or the right area) and a part of the second area (e.g., the right area or the left area) of the display area AA of the display panel 110, but is not limited thereto.

[0081] Here, the gate driving circuit 130 embedded in the display panel 110 by the gate-in-panel (GIP) technology may also be referred to as an "in-panel gate circuit".

[0082] The controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130, and may control the driving timings of the plurality of data lines DL and the plurality of gate lines GL.

[0083] The controller 140 may supply a data control signal DCS to the data driving circuit 120 to control the data driving circuit 120, and supply a gate control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0084] The controller 140 may receive image data input from the host system 150, and supply image data DATA readable by the data driving circuit 120 to the data driving circuit 120 according to the input image data.

[0085] The controller 140 may be implemented as a component separate from the data driving circuit 120, or integrated with the data driving circuit 120, such that the controller 140 and the data driving circuit 120 may be implemented as a single integrated circuit.

[0086] The controller 140 may be a timing controller used in typical display technologies, or may be a control device / unit capable of additionally performing other control functions in addition to the functions of a typical timing controller. In one or more embodiments, the controller 140 may be one or more other control circuits different from the timing controller, or may be a circuit or component in the control device / unit. The controller 140 may be implemented using various circuits or electronic components (e.g., integrated circuits (ICs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), processors, etc.).

[0087] The controller 140 can be mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc.

[0088] The controller 140 can send signals to and receive signals from the data driving circuit 120 through one or more predetermined interfaces. For example, such interfaces can include a low-voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc. However, aspects of the present disclosure are not limited thereto.

[0089] In one or more aspects, in order to provide a touch sensing function as well as an image display function, the display device 100 can include a touch sensor and a touch sensing circuit, and the touch sensing circuit is configured to sense the touch sensor and detect whether a touch is applied by an object such as a finger, a pen, etc., or the position (or touch coordinates) of the touch.

[0090] The touch sensing circuit can include: a touch driving circuit configured to drive and sense the touch sensor and generate and output touch sensing data; and a touch controller configured to detect whether a touch is applied or the position (or touch coordinates) of the touch based on the touch sensing data.

[0091] The touch sensor can include a plurality of touch electrodes. The touch sensor can also include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit.

[0092] The touch sensor can be provided outside the display panel 110 in the form of a touch panel, or can be provided inside the display panel 110. The touch sensor provided outside the display panel 110 can be referred to as an add-on type touch sensor. In an example where the add-on type touch sensor is provided in the display device 100, the touch panel and the display panel 110 can be manufactured separately and combined together in the assembly process. The add-on type touch panel can include a touch panel substrate and a plurality of touch electrodes provided on the touch panel substrate.

[0093] In an example where the touch sensor is provided inside the display panel 110, the touch sensor can be formed on the substrate together with the signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0094] The touch driving circuit can supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0095] The touch sensing circuit can perform touch sensing through self-capacitance sensing technology or mutual-capacitance sensing technology.

[0096] In an example where the touch sensing circuit performs touch sensing through self - capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between one or more touch electrodes and an object (e.g., a finger, a pen, etc.). According to the self - capacitance sensing technology, each of the multiple touch electrodes can be used as a driving touch electrode and a sensing touch electrode simultaneously. The touch driving circuit can drive all of the multiple touch electrodes or one or more of the multiple touch electrodes, and sense all of the multiple touch electrodes or one or more of the multiple touch electrodes.

[0097] In an example where the touch sensing circuit performs touch sensing through mutual - capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes. According to the mutual - capacitance sensing technology, the multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0098] In one or more aspects, the touch driving circuit and the touch controller included in the touch sensing circuit can be implemented as separate devices, or can be implemented as a single device. In one or more aspects, the touch driving circuit and the data driving circuit can be implemented as separate devices, or can be implemented as a single device.

[0099] The display device 100 may further include a power supply circuit configured to supply various types of power to the display driving circuit and / or the touch sensing circuit.

[0100] In some aspects, the display device 100 can be a mobile terminal, such as a smart phone, a tablet computer, etc., or a display, a television (TV), etc. These devices can be configured in various types, sizes, and shapes. The display device 100 according to the aspects of the present disclosure is not limited thereto, and can include various types, sizes, and shapes configured to display information or images. The display device according to the aspects of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, stretchable devices, curved devices, sliding devices, variable devices, electronic notebooks, e - books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop computers, laptop computers, netbook computers, workstations, navigation devices, automotive navigation devices, in - vehicle display devices, vehicle devices, cinema devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, video cameras, and household appliances, etc.

[0101] In one or more aspects, the display device 100 may further include electronic devices such as a camera (e.g., an image sensor), a sensor capable of detecting an object, etc. For example, the sensor may be a sensor capable of detecting an object or a human body by receiving light such as infrared light, ultrasonic light, ultraviolet light, etc.

[0102] Figure 2 An example configuration of the display panel 110 according to an aspect of the present disclosure is shown.

[0103] Referring to Figure 2 , the display panel 110 may include a substrate 111 provided with a plurality of sub-pixels SP and a encapsulation layer 200 above the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate, an encapsulation stack, etc.

[0104] Referring to Figure 2 , in an example where the display device 100 is a self-emitting display device, each of the plurality of sub-pixels SP provided on the substrate 111 may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0105] Referring to Figure 2 , the sub-pixel circuit SPC may include a plurality of transistors and at least one capacitor for driving the light-emitting element ED. The sub-pixel circuit SPC may drive the light-emitting element ED by supplying a driving current to the light-emitting element ED at a predetermined timing. The light-emitting element ED may emit light by the driving of the driving current.

[0106] The plurality of transistors may include a driving transistor DT for driving the light-emitting element ED and a scanning transistor ST configured to be turned on or off according to a scan signal SC.

[0107] The driving transistor DT may supply a driving current to the light-emitting element ED.

[0108] The scanning transistor ST may be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC or control the state or operation of the driving transistor DT.

[0109] The at least one capacitor may include a storage capacitor Cst configured to maintain a constant voltage during a display frame or a certain period of the display frame.

[0110] Referring to Figure 2 , in order to drive the sub-pixel SP, a data signal VDATA (which is an image signal) and a scan signal SC (which is a gate signal) may be applied to the sub-pixel SP. In addition, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the sub-pixel SP.

[0111] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[0112] For example, the pixel electrode PE may be an electrode disposed in each sub-pixel SP, and the common electrode CE may be an electrode disposed in all of the plurality of sub-pixels SP or in a part of the plurality of sub-pixels SP. For example, the pixel electrode PE may be an anode, and the common electrode CE may be a cathode. In another example, the pixel electrode PE may be a cathode, and the common electrode CE may be an anode. Hereinafter, for the sake of convenience of description, an example in which the pixel electrode PE is an anode and the common electrode CE is a cathode will be discussed.

[0113] In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be referred to as a common intermediate layer EL_COM.

[0114] The light-emitting layer EML may be disposed in each sub-pixel SP, and the common intermediate layer EL_COM may be commonly disposed on all or a part of the plurality of sub-pixels SP.

[0115] The light-emitting layer EML may be disposed in each light-emitting region, and the common intermediate layer EL_COM may be commonly disposed in all or a part of the plurality of light-emitting regions and all or a part of the plurality of non-light-emitting regions.

[0116] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL), a hole transport layer (HTL), etc. The second common intermediate layer COM2 may include an electron transport layer (ETL), an electron injection layer (EIL), etc. However, the aspects of the present disclosure are not limited thereto.

[0117] The hole injection layer may inject holes from the pixel electrode PE into the hole transport layer, the hole transport layer may transport the holes to the light-emitting layer EML, the electron injection layer may inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer may transport the electrons to the light-emitting layer EML.

[0118] For example, the common electrode CE can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS as the common pixel driving voltage can be applied to the common electrode CE through the second common driving voltage line VSSL. The pixel electrode PE can be directly or indirectly (through another transistor) electrically connected to the first node N1 of the corresponding driving transistor DT of each sub-pixel SP. Here, the second common driving voltage VSS can also be referred to as the "base voltage", and the second common driving voltage line VSSL can also be referred to as the "low power supply voltage line", "low voltage line", or "base voltage line".

[0119] Each light-emitting element ED can be formed by the overlap of the pixel electrode PE, the light-emitting layer in the intermediate layer EL, and the common electrode CE. Each light-emitting element ED can form a corresponding light-emitting region. For example, the corresponding light-emitting region of each light-emitting element ED can include the overlapping region of the pixel electrode PE, the light-emitting layer in the intermediate layer EL, and the common electrode CE.

[0120] In some aspects, the light-emitting element ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot light-emitting element. For example, in the example where the light-emitting element ED is an organic light-emitting diode OLED, the intermediate layer EL of the light-emitting element ED can be a layer containing an organic material. However, the aspects of the present disclosure are not limited thereto.

[0121] The driving transistor DT is a transistor configured to supply a driving current to the light-emitting element ED. The driving transistor DT can be connected between the first common driving voltage line VDDL and the light-emitting element ED.

[0122] The driving transistor DT can include a first node N1, a second node N2, and a third node N3. The first node N1 can be electrically connected to the light-emitting element ED. The data signal VDATA can be applied to the second node N2. The first common driving voltage VDD can be applied to the third node N3 through the first common driving voltage line VDDL.

[0123] In the driving transistor DT, the second node N2 can be a gate node, the first node N1 can be a source node or a drain node, and the third node N3 can be a drain node or a source node. Hereinafter, for the sake of convenience of description only, the example where the first node, the second node, and the third node (N1, N2, and N3) of the driving transistor DT are the source node, the gate node, and the drain node respectively will be discussed. However, the aspects of the present disclosure are not limited thereto.

[0124] Figure 2 The scan transistor ST included in the shown sub-pixel circuit SPC can be a switching transistor for supplying the data signal VDATA as an image signal to the second node N2 serving as the gate node of the driving transistor DT.

[0125] The scanning transistor ST can be turned on or off by a scanning signal SC (which is a gate signal) applied through a scanning line SCL (which is a gate line GL), and controls the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain or source of the scanning transistor ST can be electrically connected to the data line DL. The source or drain of the scanning transistor ST can be electrically connected to the second node N2 of the driving transistor DT. The gate of the scanning transistor ST can be electrically connected to the scanning line SCL.

[0126] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst can include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0127] The storage capacitor Cst can be an external capacitor designed to be located or disposed outside the driving transistor DT. Therefore, it is different from an internal capacitor such as a parasitic capacitor (e.g., Cgs, Cgd) that may be formed between the first node N1 and the second node N2 of the driving transistor DT.

[0128] Both the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0129] The display panel 110 can have a top-emitting structure or a bottom-emitting structure.

[0130] In an example where the display panel 110 has a top-emitting structure, at least a part of the sub-pixel circuit SPC can overlap at least a part of the light-emitting element ED in the vertical direction. In this configuration, the area or size of the corresponding light-emitting region can be increased, and the corresponding aperture ratio can be increased.

[0131] In an example where the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC may not overlap with the light-emitting element ED in the vertical direction.

[0132] As Figure 2 shown, the sub-pixel circuit SPC can include two transistors (2T: DT and ST) and one capacitor (1C: Cst) (which can be referred to as a "2T1C structure"). In some implementations, it can also include one or more transistors, and / or also include one or more capacitors.

[0133] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and one capacitor. In another example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. In yet another example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and one capacitor.

[0134] The type and number of gate signals supplied to the sub-pixel SP, and / or the type and number of gate lines connected to the sub-pixel SP may vary according to the structure of the corresponding sub-pixel circuit SPC. In addition, the type and number of common pixel driving voltages supplied to the sub-pixel SP may vary according to the structure of the corresponding sub-pixel circuit SPC.

[0135] Since circuit elements (e.g., light-emitting element ED, such as an organic light-emitting diode (OLED) including an organic material) in each sub-pixel SP are vulnerable to external moisture or oxygen, a encapsulation layer 200 may be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit elements (e.g., light-emitting element ED). The encapsulation layer 200 may be provided in various shapes and configurations to prevent the light-emitting element ED from contacting moisture or oxygen. For example, the encapsulation layer 200 may include two or more alternating organic and inorganic layers, but aspects of the present disclosure are not limited thereto.

[0136] Referring to Figure 2 , in one or more aspects, to sense a user's touch, the display device 100 may include: a touch sensor stack 210 including a plurality of sensor electrodes; a touch driving circuit 220 configured to sense the plurality of sensor electrodes; and a touch controller 230 configured to determine whether a touch has been applied or the location of the touch (e.g., touch coordinates) based on the sensing result of the touch driving circuit 220 (e.g., touch sensing data).

[0137] The touch sensor stack 210 may be embedded in the display panel 110. For example, the touch sensor stack 210 may be provided on the encapsulation layer 200 of the display panel 110.

[0138] The display panel 110 may include: a plurality of touch pads TP electrically connected to the touch driving circuit 220; and a plurality of touch wirings for electrically connecting the plurality of sensor electrodes included in the touch sensor stack 210 to the plurality of touch pads TP connected to the touch driving circuit 220.

[0139] Figure 3 is an example of a cross-sectional view of the display panel 110 according to an aspect of the present disclosure.

[0140] Referring to Figure 3, in some aspects, in terms of the stacked configuration, the display panel 110 may include a sub-pixel circuit stack, a light-emitting element stack, and a packaging stack.

[0141] The sub-pixel circuit stack may include a substrate 111, various types of insulating layers (311, 312, 313, 321, 322, and 323) on the substrate 111, various types of transistors (TFT1 and TFT2), a storage capacitor Cst, and various electrodes or signal lines.

[0142] The transistors (TFT1 and TFT2) included in the sub-pixel circuit stack may include a first transistor TFT1, a second transistor TFT2, and the like.

[0143] The first transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, but the aspects of the present disclosure are not limited thereto. For example, the first active layer ACT1 may be composed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), etc., but the aspects of the present disclosure are not limited thereto. The first transistor TFT1 may be a p-channel transistor or an n-channel transistor, but the aspects of the present disclosure are not limited thereto.

[0144] The first electrode E1a may be a gate, the second electrode E1b may be a source or a drain, and the third electrode E1c may be a drain or a source. Hereinafter, for the sake of convenience of description, a discussion will be made based on an example in which the first electrode, the second electrode, and the third electrode (E1a, E1b, E1c) are the first gate E1a, the first source E1b, and the first drain E1c, respectively.

[0145] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, but aspects of the present disclosure are not limited thereto. For example, the second active layer ACT2 may be composed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), etc., but aspects of the present disclosure are not limited thereto. The second transistor TFT2 may be a p-channel transistor or an n-channel transistor, but aspects of the present disclosure are not limited thereto. For example, one of the first transistor TFT1 and the second transistor TFT2 may have an active layer including an oxide semiconductor. In another example, one of the first transistor TFT1 and the second transistor TFT2 may include an active layer having low-temperature polycrystalline silicon. In yet another example, the first transistor TFT1 and the second transistor TFT2 may have an active layer including an oxide semiconductor. In another example, one or more transistors in a gate driver configured as a gate-in-panel (GIP) type may have an active layer including an oxide semiconductor or low-temperature polycrystalline silicon. In another example, all transistors disposed on the substrate and transistors included in a gate driver configured as a gate-in-panel (GIP) type may have an active layer including an oxide semiconductor.

[0146] The fourth electrode E2a may be a gate, the fifth electrode E2b may be a source or a drain, and the sixth electrode E2c may be a drain or a source. Hereinafter, for ease of explanation, discussion will be based on an example in which the fourth electrode, the fifth electrode, and the sixth electrode (E2a, E2b, E2c) are the second gate E2a, the second source E2b, and the second drain E2c, respectively.

[0147] The second active layer ACT2 of the second transistor TFT2 may be disposed higher than the first active layer ACT1 of the first transistor TFT1 with respect to the substrate 111.

[0148] A first buffer layer 311 may be disposed under the first active layer ACT1 of the first transistor TFT1, and a second buffer layer 321 may be disposed under the second active layer ACT2 of the second transistor TFT2. For example, the first active layer ACT1 of the first transistor TFT1 may be disposed on the first buffer layer 311, and the second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 321. The second buffer layer 321 may be disposed higher than the first buffer layer 311.

[0149] The storage capacitor Cst may be disposed in each metal layer in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2.

[0150] The light-emitting element stack may include a plurality of light-emitting elements ED disposed on at least one planarization layer (331 and / or 332). Each light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0151] The encapsulation stack may include an encapsulation layer 200 disposed on the plurality of light-emitting elements ED. The encapsulation layer 200 may include a single layer or multiple layers. In addition to the encapsulation layer 200, the encapsulation stack may further include at least one dam DAM.

[0152] Hereinafter, with reference to Figure 3 the stack configuration of the display panel 110 according to aspects of the present disclosure will be described in more detail.

[0153] With reference to Figure 3 , a first buffer layer 311 may be disposed on the substrate 111. The first buffer layer 311 may include a single layer or multiple layers. In an example where the first buffer layer 311 has a stack of multiple layers, the first buffer layer 311 may include a multi-buffer layer 311a and an active buffer layer 311b.

[0154] The first active layer ACT1 of the first transistor TFT1 may be disposed on the first buffer layer 311. The first active layer ACT1 may include a channel region forming a channel, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0155] With reference to Figure 3 , a first gate insulating layer 312 may be disposed on the first active layer ACT1 of the first transistor TFT1. The first gate E1a of the first transistor TFT1 may be disposed on the first gate insulating layer 312. A first interlayer insulating layer 313 may be disposed on the first gate E1a of the first transistor TFT1.

[0156] With reference to Figure 3 , a second buffer layer 321 may be disposed on the first interlayer insulating layer 313.

[0157] With reference to Figure 3 , the second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 321. The first active layer ACT2 may include a channel region formed with a channel, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0158] With reference to Figure 3 , a second gate insulating layer 322 may be disposed on the second active layer ACT2 of the second transistor TFT2. The second gate E2a of the second transistor TFT2 may be disposed on the second gate insulating layer 322. A second interlayer insulating layer 323 may be disposed on the second gate E2a of the second transistor TFT2.

[0159] Reference Figure 3 As shown in Figure 3 , the first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may be disposed on the second interlayer insulating layer 323.

[0160] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 may be respectively connected to the source connection region and the drain connection region of the first active layer ACT1 through corresponding holes in each of the second interlayer insulating layer 323, the second gate insulating layer 322, the second buffer layer 321, the first interlayer insulating layer 313, and the first gate insulating layer 312.

[0161] The second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may be respectively connected to the source connection region and the drain connection region of the second active layer ACT2 through corresponding holes in each of the second interlayer insulating layer 323 and the second gate insulating layer 322.

[0162] Reference Figure 3 As shown in Figure 3 , the first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may include a first metal and may be disposed in a first metal layer. The first metal and the first metal layer may be respectively referred to as the first source-drain metal and the first source-drain metal layer.

[0163] Reference Figure 3 In one or more aspects, the storage capacitor Cst may be composed of a first capacitor electrode CE1 and a second capacitor electrode CE2. In one or more aspects, the storage capacitor Cst may include more than three capacitor electrodes, or may include two or more capacitors connected in parallel.

[0164] Reference Figure 3 As shown in Figure 3 , each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be disposed in respective metal layers in the display panel 110.

[0165] In one or more aspects, the first capacitor electrode CE1 may contain the same first gate metal as the first gate E1a of the first transistor TFT1 on the first gate insulating layer 312 and may be disposed in the first gate metal layer.

[0166] In one or more aspects, the second capacitor electrode CE2 may be disposed on the first interlayer insulating layer 313.

[0167] Reference Figure 3, the second source electrode E2b of the second transistor TFT2 can be electrically connected to the second capacitor electrode CE2 through the respective holes of the second interlayer insulating layer 323, the second gate insulating layer 322, and the second buffer layer 321.

[0168] In one or more aspects, the first transistor TFT1 can be Figure 2 the driving transistor DT, and the second transistor TFT2 can be Figure 2 the scanning transistor ST.

[0169] Referring to Figure 3 , the sub-pixel circuit stack can also include various metal patterns (e.g., the first metal pattern MP1, the second metal pattern MP2, etc.). For example, the first metal pattern MP1 can be disposed between the multi-buffer layer 311a and the active buffer layer 311b included in the first buffer layer 311. The second metal pattern MP2 can include the same first gate metal as the first gate E1a of the first transistor TFT1 and can be disposed in the first gate metal layer. In one or more aspects, the first metal pattern MP1 can be the first metal layer, and the second metal pattern MP2 can be the second metal layer. However, the aspects of the present disclosure are not limited thereto.

[0170] The first metal pattern MP1, the second metal pattern MP2, and the common driving voltage pattern CVP can be disposed in the display area AA or the non-display area NA.

[0171] Referring to Figure 3 , the sub-pixel circuit stack can also include a shielding layer BSM, which is disposed on the substrate 111, overlaps with the second active layer ACT2 of the second transistor TFT2, and is disposed below the second active layer ACT2 of the second transistor TFT2.

[0172] For example, the shielding layer BSM can be disposed in the same first gate metal layer as the first gate E1a of the first transistor TFT1. In another example, the shielding layer BSM can be disposed in the same metal layer as the first metal pattern MP1 on the first buffer layer 311.

[0173] Another shielding layer BSM can be disposed below and overlap with the first active layer ACT1 of the first transistor TFT1. In the present embodiment, the shielding layer BSM can be disposed in the same metal layer as the first metal layer MP1.

[0174] Referring to Figure 3 , the sub-pixel circuit stack can also include a common driving voltage pattern CVP to which a common driving voltage is applied. The common driving voltage applied to the common driving voltage pattern CVP can be a power signal, such as Figure 2the first common driving voltage VDD or the second common driving voltage VSS therein. The first common driving voltage VDD may be referred to as a high power supply voltage (or high power supply signal), and the second common driving voltage VSS may be referred to as a low power supply voltage (or low power supply signal) or a ground voltage.

[0175] The common driving voltage mode CVP may be set in the display area AA or the non-display area NA.

[0176] At least one planarization layer may be provided on the first transistor TFT1 and the second transistor TFT2. Figure 3 Two planarization layers (a first planarization layer 331 and a second planarization layer 332) provided on the first transistor TFT1 and the second transistor TFT2 are shown, for example. In one or more aspects, three or more planarization layers may be provided on the first transistor TFT1 and the second transistor TFT2 according to design requirements. However, the aspects of the present disclosure are not limited thereto.

[0177] Referring to Figure 3 , the first planarization layer 331 may be provided on the first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2. In one or more aspects, the first planarization layer 331 may be configured to cover both the first transistor TFT1 and the second transistor TFT2.

[0178] Referring to Figure 3 , a relay electrode RE may be provided on the first planarization layer 331. The relay electrode RE may be electrically connected to the first source electrode E1b of the first transistor TFT1 through a hole in the first planarization layer 331.

[0179] The relay electrode RE may be provided in a second metal layer on the first planarization layer 331 and include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer, respectively.

[0180] Referring to Figure 3 , the second planarization layer 332 may be provided on the relay electrode RE.

[0181] Referring to Figure 3 , a light-emitting element stack may be provided on the second planarization layer 332. A light-emitting element ED may be formed on the second planarization layer 332. The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting area of the light-emitting element ED may be formed in an area where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[0182] The pixel electrode PE can be disposed on the second planarization layer 332, and a bank 333 can be disposed on the pixel electrode PE. An opening of the bank 333 can expose a part of the pixel electrode PE to form a light-emitting region. For example, the opening of the bank 333 can overlap with a part of the pixel electrode PE.

[0183] An intermediate layer EL of the light-emitting element ED can be disposed on a part of the pixel electrode PE and the bank 333. A common electrode CE can be disposed on the intermediate layer EL.

[0184] Refer to Figure 3 , an encapsulation stack can be disposed on the light-emitting element stack and on the common electrode CE. The encapsulation stack can include an encapsulation layer 200 disposed on the common electrode CE.

[0185] The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting element ED. For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic materials included in the intermediate layer EL of the light-emitting element ED. In one or more aspects, the encapsulation layer 200 can include a single layer or multiple layers, but the aspects of the present disclosure are not limited thereto.

[0186] Refer to Figure 3 , for example, the encapsulation layer 200 can include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343. The first encapsulation layer 341 and the third encapsulation layer 343 can include, for example, an inorganic layer, and the second encapsulation layer 342 can include, for example, an organic layer.

[0187] In one or more aspects, as described above, a touch sensor can be embedded in the display panel 110. In these aspects, the display panel 110 can include a touch sensor stack 210 disposed on the encapsulation layer 200.

[0188] Refer to Figure 3 , the touch sensor stack 210 can include a plurality of touch electrodes TE, and include a touch sensor metal TSM and a bridging metal BRG to form the plurality of touch electrodes TE. For example, the touch sensor metal TSM can be formed by a grid of a conductive grid structure having one or more openings (hereinafter, it can be referred to as a grid-type touch electrode).

[0189] Refer to Figure 3 , the touch sensor stack 210 can further include one or more insulating layers on the encapsulation layer 200, for example, a sensor buffer layer 351, a sensor interlayer insulating layer 352 on the sensor buffer layer 351, and / or a sensor protection layer 353 on the sensor interlayer insulating layer 352.

[0190] Each of the plurality of touch electrodes TE may be composed of one or more touch sensor metals TSM. In this embodiment, each of the plurality of touch electrodes TE may be a grid-type touch electrode having a plurality of openings.

[0191] The plurality of touch electrodes TE may include one or more first touch electrodes TE1 and one or more second touch electrodes TE2. Two or more touch sensor metals TSM included in each of the respective first touch electrodes TE1 or each of the respective second touch electrodes TE2, or two or more portions of one touch sensor metal TSM, may be electrically connected by one or more bridging metals BRG.

[0192] The sensor buffer layer 351 may be disposed on the encapsulation layer 200, the bridging metal BRG may be disposed on the sensor buffer layer 351, and the sensor interlayer insulating layer 352 may be disposed on the bridging metal BRG.

[0193] The touch sensor metal TSM may be disposed on the sensor interlayer insulating layer 352. In one or more aspects, the touch sensor metal TSM may include one or more first touch sensor metals and one or more second touch sensor metals, and the bridging metal BRG may include one or more first bridging metals BRG and one or more second bridging metals BRG. In this embodiment, the respective portions of the first touch sensor metal TSM may be connected to the corresponding one or more first bridging metals BRG through holes in the sensor interlayer insulating layer 352.

[0194] Refer to Figure 3 , one or more first touch sensor metals TSM and one or more second bridging metals BRG may be configured not to overlap each other. The touch sensor metal TSM and the bridging metal BRG may overlap the dam 333.

[0195] In one or more aspects, the plurality of touch sensor metals TSM may be included in one touch electrode TE, may be a grid-type touch electrode and electrically connected to each other. In one or more aspects, among the plurality of touch sensor metals TSM, one or more touch sensor metals TSM and one or more other touch sensor metals TSM may be electrically connected to each other by one or more bridging metals BRG to form one touch electrode TE.

[0196] The sensor protection layer 353 may be configured to cover the touch sensor metal TSM and the bridging metal BRG.

[0197] Refer to Figure 3, the touch line TL can electrically connect the touch electrode TE and the touch pad TP. The touch line TL can be formed by at least one of the touch sensor metal TSM and the bridging metal BRG. For example, the touch line TL can be a part of the touch sensor metal TSM or the bridging metal BRG.

[0198] In an example where the display panel 110 is a display panel embedded with a touch sensor, the touch line TL can extend along the outer slope SLP_ENCAP of the encapsulation layer 200 and the upper part of at least one dam DAM and extend to the touch pad TP provided in the non-display area NA.

[0199] Figure 4 An example structure of a substrate (e.g., Figure 3 the substrate 111) included in the display panel 110 according to an aspect of the present disclosure is shown.

[0200] Referring to Figure 4 , in one or more aspects, the substrate 111 of the display panel 110 can include a display area AA capable of displaying an image and a non-display area NA that does not display an image.

[0201] Referring to Figure 4 , the non-display area NA can include, for example, a first non-display area, a second non-display area NA2, a third non-display area NA3, and a fourth non-display area NA4. However, the aspects of the present disclosure are not limited thereto.

[0202] The first non-display area NA1 can be located on the first side of the display area AA. The second non-display area NA2 can be located on the second side of the display area AA. The third non-display area NA3 can be located on the third side of the display area AA. The fourth non-display area NA4 can be located on the fourth side of the display area AA.

[0203] For example, the first side and the third side can be two sides in the column direction. The second side and the fourth side can be two sides in the row direction. In another example, the first side and the third side can be two sides in the row direction. The second side and the fourth side can be two sides in the column direction. Hereinafter, for the sake of convenience of description, discussion will be made based on an example where the first side and the third side are two sides in the column direction and the second side and the fourth side are two sides in the row direction.

[0204] For example, the column direction can be the direction in which the data line DL extends, and the row direction can be the direction in which the gate line GL extends. In another example, the column direction can be the direction in which the gate line GL extends, and the row direction can be the direction in which the data line DL extends. Hereinafter, for the sake of convenience of description, discussion will be made based on an example where the column direction is the direction in which the data line DL extends and the row direction is the direction in which the gate line GL extends.

[0205] Referring to Figure 4, the first non-display area NA1 may include a pad area PA. A plurality of pads electrically connected to at least one driving circuit or a printed circuit board may be provided at the pad area PA. In one or more aspects, a plurality of data lines DL, a first common driving voltage line VDDL, and a second common driving voltage line VSSL may be electrically connected to the plurality of pads.

[0206] Referring to Figure 4 , the first non-display area NA1 may further include a bending area BA. In this embodiment, the substrate 111 may be a flexible substrate. In one or more aspects, the first non-display area NA1 may not include the bending area BA.

[0207] Referring to Figure 4 , the display panel 110 may further include a ground wire provided in the non-display area NA of the substrate 111. The ground wire may be provided to extend from a point of the pad area PA via a second non-display area NA2, a third non-display area NA3, and a fourth non-display area NA4 to another point of the pad area PA.

[0208] Referring to Figure 4 , in one or more aspects, the encapsulation layer 200 provided in the display panel 110 may have a structure in which at least one inorganic layer and at least one organic layer are stacked. In these aspects, the edge of the encapsulation layer 200 may be the edge of the organic layer. The encapsulation layer 200 may extend from the display area AA to a part of the non-display area NA.

[0209] Referring to Figure 4 , in one or more aspects, in order to prevent the overflow of the organic layer included in the encapsulation layer 200, the display panel 110 may further include at least one dam or at least one stopper provided more outward than the organic layer included in the encapsulation layer 200. The at least one dam or the at least one stopper may include an organic layer, but the aspects of the present disclosure are not limited thereto.

[0210] Figure 5 is an example of a plan view of the display panel 110 according to an aspect of the present disclosure, and shows a data link structure configured in the display panel 110.

[0211] Referring to Figure 5 , in one or more aspects, the display panel 110 may include a plurality of data lines DL configured to transmit a data voltage VDATA and a plurality of pads PD provided in the pad area PA and configured to be electrically connectable to a data driving circuit 120.

[0212] Referring to Figure 5, in one or more aspects, the display panel 110 may include a data link structure configured to electrically connect a plurality of data lines DL to a plurality of pads PD. In one or more aspects, the data link structure may include a plurality of data link lines LINK.

[0213] Referring to Figure 5 , the plurality of data link lines LINK may be disposed in the non-display area NA. For example, the plurality of data link lines LINK may be disposed in a first non-display area NA1 including a pad area PA.

[0214] Referring to Figure 5 , the first non-display area NA1 may further include a link area LA in addition to the pad area PA and the bending area BA.

[0215] For example, each of the plurality of data link lines LINK may be arranged to span across the pad area PA, the bending area BA, and the link area LA. Each of the plurality of data link lines LINK may include a first end (or first edge) electrically connected to the pad PD disposed in the pad area PA and a second end (or second edge) electrically connected to the data line DL disposed in the display area AA. The portion between the two ends (i.e., the first end and the second end, or the first edge and the second edge) of each of the plurality of data link lines LINK may be arranged to span across the bending area BA and the link area LA.

[0216] For example, each of the plurality of data link lines LINK may be formed by one line or two or more lines. Each of the plurality of data link lines LINK may be disposed in one metal layer or two or more metal layers.

[0217] Referring to Figure 5 , the bending area BA may be bent during the manufacturing process of the display panel 110. Therefore, when the user views the display device 100 in front of him / her, the bending area BA and the pad area PA may be invisible to the user.

[0218] However, when the user views the display device 100 in front of him / her, even if the link area LA is covered by a housing or a cover member, it may be recognized as a border. Therefore, in order to achieve a narrow border, it may be necessary to reduce the area or size of the link area LA.

[0219] Referring to Figure 5 , since all of the plurality of data link lines LINK in the link area LA of the first non-display area NA1 need to be electrically connected to the plurality of data lines DL, the area or size of the link area LA becomes large.

[0220] For example, when the length of the pad region PA in the second direction (row direction) is less than the length of the display region AA in the second direction (row direction), multiple data link lines LINK in the left and right regions (LBZ and RBZ) of the link region LA need to extend at an angle with respect to the row direction or the column direction, respectively, and then be electrically connected to a corresponding one of the multiple data lines DL. This configuration increases the length of the link region LA in the first direction (column direction) and increases the area of the link region LA.

[0221] Therefore, as Figure 5 shown, in an example where the display panel 110 has a data link structure in which multiple data link lines LINK are provided in the first non-display region NA1, the area or size of the link region LA of the first non-display region NA1 may become large. In this embodiment, when a user views the display device 100 in front of him / her, the link region LA may be recognized as a wide border.

[0222] Therefore, in order to achieve a narrow border, a data link structure capable of reducing the area of the link region LA needs to be provided. To meet such a requirement, a data link structure capable of achieving a narrow border will be discussed below.

[0223] Hereinafter, a data link structure capable of achieving a narrow border according to an aspect of the present disclosure will be described.

[0224] Figure 6 is another example of a plan view of the display panel 110 according to an aspect of the present disclosure, and shows an example data link structure ("border reduction data link structure") capable of reducing the border of the display panel 110. Figure 7 Shows an example of three regions (A, B, and C regions) defined in the display region AA of the border reduction data link structure of the display panel 110 according to an aspect of the present disclosure.

[0225] Referring to Figure 6 , the non-display region NA may include a first non-display region NA1 provided along the column direction from the display region AA. The first non-display region NA1 may include a pad region PA and a link region LA provided along the column direction from the display region AA.

[0226] In one or more aspects, the display panel 110 may include a data link structure configured to supply a data voltage VDATA to a plurality of sub-pixels SP provided in the display region AA and reduce the border of the display panel 110.

[0227] Referring to Figure 6 , in one or more aspects, the border reduction data link structure may include multiple data link lines LINK for electrically connecting the multiple data lines DL to a plurality of pads PD.

[0228] A plurality of data lines DL may be provided in the display area AA, extend in the column direction, and be connected to a plurality of sub-pixels SP provided in the display area AA.

[0229] A plurality of pads PD may be provided in a pad area PA included in the first non-display area NA1.

[0230] A plurality of data link lines LINK may electrically connect the plurality of pads PD in the pad area PA provided in the first non-display area NA1 to the plurality of data lines DL provided in the display area AA.

[0231] Referring to Figure 6 , in a data link structure with a narrow border implemented according to an aspect of the present disclosure, a portion LIA of each of the plurality of data link lines LINK may be provided in the display area AA.

[0232] In a border-reducing data link structure according to an aspect of the present disclosure, the plurality of data link lines LINK and the plurality of data lines DL may be electrically connected to each other in the display area AA. For example, in a border-reducing data link structure according to an aspect of the present disclosure, a connection point CNT_DL where the plurality of data link lines LINK and the plurality of data lines DL are connected to each other may be provided in the display area AA.

[0233] According to these configurations, each of the plurality of data link lines LINK may not need to extend at an angle with respect to the row direction or the column direction in the left and right regions of the link area LA, and each of the plurality of data link lines LINK may pass through the link area LA in the column direction with a shorter length, enter the display area AA, and be connected to a corresponding data line DL in the display area AA.

[0234] As Figure 6 shown, in an example where the display panel 110 has a border-reducing data link structure, the length of the link area LA in the column direction may be very short or zero. Thus, the first non-display area NA1 that a user sees in front of the display panel 110 may become very small.

[0235] Referring to Figure 6 , in a border-reducing data link structure according to an aspect of the present disclosure, each of the plurality of data link lines LINK may include a link line LIA (which may be referred to as a display area link line LIA) of the display area AA that may be provided in the display area AA.

[0236] Each display area link line LIA may include a horizontal link line HLIA disposed in the display area AA and extending in the row direction (i.e., the horizontal direction), and a vertical link line VLIA at least partially disposed within the display area AA and extending in the column direction (i.e., the vertical direction).

[0237] Referring Figure 6 , each vertical link line VLIA may electrically connect a corresponding pad PD to a corresponding horizontal link line HLIA, and each horizontal link line HLIA may electrically connect a corresponding vertical link line VLIA to a corresponding data line DL.

[0238] Referring Figure 6 , each horizontal link line HLIA and each vertical link line VLIA may be electrically connected to each other through corresponding link line connection holes CNT_LIA. Each horizontal link line HLIA and each data line DL may be electrically connected to each other through corresponding data line connection holes CNT_DL.

[0239] In one or more aspects, since one or more data line connection holes CNT_DL or one or more link line connection holes CNT_LIA may be unevenly distributed over the entire area of the display panel 110, differences in the distribution density of the connection holes may occur. Due to these differences in the distribution density of the connection holes, the display device may suffer from display artifacts, such as some image display defects perceived as patterns.

[0240] Referring Figure 6 , each of the plurality of data link lines LINK may further include a link line LIN in the non-display area NA (which may be referred to as a non-display area link line LIN), which may be disposed in a first non-display area NA1 of the non-display area NA.

[0241] For example, each non-display area link line LIN and the corresponding vertical link line VLIA may be formed as one line. In another example, each non-display area link line LIN may be electrically connected to the corresponding vertical link line VLIA and be disposed in a different metal layer from the metal layer in which the vertical link line VLIA is disposed. In yet another example, each non-display area link line LIN may include a line electrically connected to the corresponding vertical link line VLIA and disposed in a different metal layer from the metal layer in which the vertical link line VLIA is disposed.

[0242] In an example where the display panel 110 has a border-reduced data link structure as Figure 6 shown, the horizontal link line HLIA included in each of the plurality of data link lines LINK may extend in parallel with a plurality of gate lines GL disposed in the display area AA and extending in the row direction (horizontal direction).

[0243] In addition, in an example where the display panel 110 has a reduced-bezel data link structure as shown in Figure 6 , each of the horizontal link lines HLIA included in each of the plurality of data link lines LINK may overlap with at least one gate line GL in the vertical direction.

[0244] Referring to Figure 6 , among the plurality of vertical link lines VLIA, the length of the vertical link line VLIA electrically connected to the data line DL disposed closer to the center of the display area AA may be relatively short. Among the plurality of vertical link lines VLIA, the length of the vertical link line VLIA electrically connected to the data line DL farther from the center of the display area AA may be longer than the length of the vertical link line VLIA electrically connected to the data line DL disposed closer to the center of the display area AA. Among the plurality of vertical link lines VLIA, the length of the vertical link line VLIA electrically connected to the data line DL closer to the center of the display area AA may be shorter than the length of the vertical link line VLIA electrically connected to the data line DL farther from the center of the display area AA. However, aspects of the present disclosure are not limited thereto.

[0245] Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA electrically connected to the data line DL disposed closer to the center of the display area AA may be relatively short. Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA electrically connected to the data line DL farther from the center of the display area AA may be longer than the length of the horizontal link line HLIA electrically connected to the data line DL disposed closer to the center of the display area AA. Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA electrically connected to the data line DL disposed closer to the center of the display area AA may be shorter than the length of the horizontal link line HLIA electrically connected to the data line DL farther from the center of the display area AA. However, aspects of the present disclosure are not limited thereto.

[0246] Referring to Figure 6 , among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA closer to the pad area PA may be relatively short. Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA farther from the pad area PA may be relatively long. Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA closer to the pad area PA may be shorter than the length of the horizontal link line HLIA farther from the pad area PA. However, aspects of the present disclosure are not limited thereto.

[0247] Referring to Figure 6 , the first link line LINK1 may include a first display area link line LIA1 and a first non-display area link line LIN1. The first display area link line LIA1 may include a first horizontal link line HLIA1 and a first vertical link line VLIA1.

[0248] Refer to Figure 6 , the second link line LINK2 may include a second display area link line LIA2 and a second non-display area link line LIN2. The second display area link line LIA2 may include a second horizontal link line HLIA2 and a second vertical link line VLIA2.

[0249] Refer to Figure 6 , among the first vertical link line VLIA1 and the second vertical link line VLIA2, the length of the first vertical link line VLIA1 electrically connected to the first data line DL1, which is set to be more outward among the first data line DL1 and the second data line DL2, may be longer than the length of the second vertical link line VLIA2.

[0250] Refer to Figure 6 , among the first horizontal link line HLIA1 and the second horizontal link line HLIA2, the length of the first horizontal link line HLIA1 electrically connected to the first data line DL1, which is set to be more outward among the first data line DL1 and the second data line DL2, may be longer than the length of the second horizontal link line HLIA2.

[0251] Refer to Figure 6 , since the length of the first horizontal link line HLIA1 is longer than the length of the second horizontal link line HLIA2, the first area where the first horizontal link line HLIA1 overlaps with at least one gate line GL may be larger than the second area where the second horizontal link line HLIA2 overlaps with at least one gate line GL.

[0252] As described above, as Figure 6 shown, the connection point CNT_DL between the data line DL and the horizontal link line HLIA may be set on two first virtual diagonal lines SLT_DL. In addition, the connection point CNT_LIA between the vertical link line VLIA and the horizontal link line HLIA may be set on two second virtual diagonal lines SLT_LIA.

[0253] As Figure 6 shown, the two first virtual diagonal lines SLT_DL and the two second virtual diagonal lines SLT_LIA may form two triangles. In each of the two triangles, one of the three sides may be a horizontal side parallel to the horizontal link line HLIA, and the vertex facing this horizontal side may be located at the boundary between the display area AA and the first non-display area NA1 or at a position near the boundary.

[0254] Refer to Figure 6 , the display area AA may include a central area Ac, a first area A1 on the first side of the central area Ac, and a second area A2 on the second opposite side of the central area Ac.

[0255] Refer toFigure 6 In the first region A1 and the second region A2, the data lines DL can be connected to the non-display region link line LIN through the display region link line LIA.

[0256] Refer to Figure 6 In one or more aspects, at least one data line DL provided in the central region Ac can be directly connected to the corresponding non-display region link line LIN without the display region link line LIA.

[0257] As described above, in an example where the display panel 110 has a border-reducing data link structure as Figure 6 shown, each of the horizontal link lines HLIA among the multiple link lines LINK can be parallel to the multiple gate lines GL provided in the display region AA and extending in the row direction (horizontal direction), and each of the horizontal link lines HLIA among the multiple link lines LINK can overlap at least one gate line GL in the vertical direction.

[0258] Refer to Figure 7 According to the above border-reducing data link structure, the display region AA can include three clearly defined regions (A, B, and C).

[0259] Refer to Figure 7 The first region (region A) can be a region where the border-reducing data link structure is not configured. The second region (region B) and the third region (region C) can be regions where the border-reducing data link structure is provided. The second region (region B) can be a region configured with the horizontal link line HLIA, and the third region (region C) can be a region provided with the vertical link line VLIA.

[0260] Refer to Figure 7 Among the first non-display region to the fourth non-display region (NA1 to NA4) included in the non-display region NA, the first non-display region NA1 including the pad region PA can be in contact with one side of each of the third regions (region C).

[0261] Refer to Figure 7 The second region (region B) can have an inverted triangular shape or an isosceles triangular shape, but the aspects of the present disclosure are not limited thereto. The display region AA can include two second regions (region B). The two second regions (region B) can be respectively provided on both sides of the first region (region A) provided in the central region of the display region AA.

[0262] Refer to Figure 7, the third region (Region C) may have a right triangle shape, but aspects of the present disclosure are not limited thereto. The display region AA may include two third regions (Region C). The two third regions (Region C) may be respectively disposed on both sides of the first region (Region A) located in the central region of the display region AA.

[0263] Referring to Figure 7 , the first region (Region A) may be disposed on (or on top of) the two second regions (Region B), may be disposed between the two third regions (Region C), or may be disposed outside the two second regions (Region B). The first region (Region A) disposed between the two third regions (Region C) may correspond to Figure 6 the central region Ac. Referring to Figure 6 and Figure 7 , in other aspects of the present disclosure, the first region (Region A), the second region (Region B), and the third region (Region C) may be arranged in different ways and / or may each have a shape different from that shown in Figure 6 and Figure 7 . For example, Figure 7 shows adjacent third regions (Region C) with a part of the first region (Region A) interposed therebetween and overlapping with the central region of the display panel 110. However, it is not necessary for a part of the first region (Region A) of the display region AA to overlap or coincide with the central region of the display panel 110. Instead, the adjacent third regions (Region C) may be combined to form a single third region (Region C) in the form of an isosceles triangle. In addition, referring to Figure 6 and Figure 7 , it is not necessary for the shape of the second region (Region B) to be an isosceles triangle as shown in the figure, but it may be a polygon, such as a trapezoid, a parallelogram, or other shapes. When the second region (Region B) is a parallelogram, the length of the first link line HLIA1 or the length of the second link line HLIA2 may be the same.

[0264] Referring to Figure 6 and Figure 7 , the boundary between the first region (Region A) and each of the two second regions (Region B) may correspond to the connection point CNT_DL of the horizontal link line HLIA and the data line DL, and form a first virtual slant line SLT_DL.

[0265] Referring to Figure 6 and Figure 7 , the boundary between each second region (Region B) and each third region (Region C) may correspond to the connection point CNT_LIA of the vertical link line VLIA and the horizontal link line HLIA, and form a second virtual slant line SLT_LIA. As Figure 7As shown, the first virtual diagonal line SLT_DL and the second virtual diagonal line SLT_LIA are inclined in different directions with respect to the horizontal direction or the vertical direction. However, aspects of the present disclosure are not limited thereto. For example, the first virtual diagonal line SLT_DL and the second virtual diagonal line SLT_LIA may be parallel, or may be inclined in the same direction.

[0266] Figure 8 is an example of a region of the display panel 110 having a data link structure (e.g., the border reduction data link structure discussed above) according to an aspect of the present disclosure. Figure 9 is a cross-sectional view taken along Figure 8 line A-A' of.

[0267] Referring to Figure 8 , the first non-display region NA1 may include a pad region PA provided with a plurality of data pads (DP1 to DP6). The plurality of data pads (DP1 to DP6) may include a first data pad DP1, a second data pad DP2, a third data pad DP3, a fourth data pad DP4, a fifth data pad DP5, and a sixth data pad DP6. However, aspects of the present disclosure are not limited thereto, and additional data pads may be provided.

[0268] Referring to Figure 8 , a plurality of data lines DL may be provided in the display region AA, and include a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a fifth data line DL5, and a sixth data line DL6. However, aspects of the present disclosure are not limited thereto, and additional data lines may be provided. Each of the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 may be provided in the display region AA and extend in the column direction. A corresponding data voltage may be applied to each of the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6.

[0269] Referring to Figure 8 and Figure 6 , a data link structure (e.g., the border reduction data link structure discussed above) may be configured in a portion of the display region AA adjacent to the first non-display region NA1.

[0270] Referring to Figure 8 and Figure 6 , the border reduction data link structure may include a display region link line LIA, and the display region link line LIA may include a horizontal link line HLIA and a vertical link line VLIA.

[0271] Each horizontal link line HLIA can be disposed in the display area AA. All or at least a part of each vertical link line VLIA can be disposed in the display area AA.

[0272] In one or more aspects, in the display panel 110, the data line connection hole CNT_DL (the horizontal link line HLIA and the data line DL are electrically connected through the data line connection hole CNT_DL) can be referred to as the second connection hole CTH2, and the link line connection hole CNT_LIA (the horizontal link line HLIA and the vertical link line VLIA are electrically connected through the link line connection hole CNT_LIA) can be referred to as the third connection hole CTH3.

[0273] Referring to Figure 8 , the horizontal link line HLIA can include a first horizontal link line HLIA1, which is electrically connected to the first data line DL1, disposed in the display area AA, extends in the row direction, and is disposed in the first metal layer ML1. The first horizontal link line HLIA1 can be electrically connected to the first data line DL1 through the second connection hole CTH2.

[0274] In addition, the vertical link line VLIA can include a first vertical link line VLIA1, which electrically connects the first horizontal link line HLIA1 and the first data pad DP1, extends in the column direction, and is disposed in a second metal layer ML2 different from the first metal layer ML1. The first vertical link line VLIA1 can be electrically connected to the first horizontal link line HLIA1 through the third connection hole CTH3. All or at least a part of the first vertical link line VLIA1 can be disposed in the display area AA.

[0275] Referring to Figure 8 , the horizontal link line HLIA can include a second horizontal link line HLIA2, which is electrically connected to the second data line DL2, disposed in the display area AA, extends in the row direction, and is disposed in the first metal layer ML1. The second horizontal link line HLIA2 can be electrically connected to the second data line DL2 through the second connection hole CTH2.

[0276] In addition, the vertical link line VLIA can include a second vertical link line VLIA2, which electrically connects the second horizontal link line HLIA2 and the second data pad DP2, extends in the column direction, and is disposed in a second metal layer ML2 different from the first metal layer ML1. The second vertical link line VLIA2 can be electrically connected to the second horizontal link line HLIA2 through the third connection hole CTH3. All or at least a part of the second vertical link line VLIA2 can be disposed in the display area AA.

[0277] Referring toFigure 8 The horizontal link line HLIA may include a third horizontal link line HLIA3, which is electrically connected to a third data line DL3, is disposed in the display area AA, extends in the row direction, and is disposed in the first metal layer ML1. The third horizontal link line HLIA3 may be electrically connected to the third data line DL3 through a second connection hole CTH2.

[0278] In addition, the vertical link line VLIA may include a third vertical link line VLIA3, which electrically connects the third horizontal link line HLIA3 and the third data pad DP3, extends in the column direction, and is disposed in a second metal layer ML2 different from the first metal layer ML1. The third vertical link line VLIA3 may be electrically connected to the third horizontal link line HLIA3 through a third connection hole CTH3. All or at least a part of the third vertical link line VLIA3 may be disposed in the display area AA.

[0279] Referring to Figure 8 The horizontal link line HLIA may include a fourth horizontal link line HLIA4, which is electrically connected to a fourth data line DL4, is disposed in the display area AA, extends in the row direction, and is disposed in the first metal layer ML1. The fourth horizontal link line HLIA4 may be electrically connected to the fourth data line DL4 through a second connection hole CTH2.

[0280] In addition, the vertical link line VLIA may include a fourth vertical link line VLIA4, which electrically connects the fourth horizontal link line HLIA4 and the fourth data pad DP4, extends in the column direction, and is disposed in a second metal layer ML2 different from the first metal layer ML1. The fourth vertical link line VLIA4 may be electrically connected to the fourth horizontal link line HLIA4 through a third connection hole CTH3. All or at least a part of the fourth vertical link line VLIA4 may be disposed in the display area AA.

[0281] Referring to Figure 8 The horizontal link line HLIA may include a fifth horizontal link line HLIA5, which is electrically connected to a fifth data line DL5, is disposed in the display area AA, extends in the row direction, and is disposed in the first metal layer ML1. The fifth horizontal link line HLIA5 may be electrically connected to the fifth data line DL5 through a second connection hole CTH2.

[0282] In addition, the vertical link line VLIA may include a fifth vertical link line VLIA5. The fifth vertical link line VLIA5 electrically connects the fifth horizontal link line HLIA5 and the fifth data pad DP5, extends along the column direction, and is disposed in a second metal layer ML2 different from the first metal layer ML1. The fifth vertical link line VLIA5 may be electrically connected to the fifth horizontal link line HLIA5 through a third connection hole CTH3. All or at least a part of the fifth vertical link line VLIA5 may be disposed in the display area AA.

[0283] Referring Figure 8 , the horizontal link line HLIA may include a sixth horizontal link line HLIA6. The sixth horizontal link line HLIA6 is electrically connected to the sixth data line DL6, is disposed in the display area AA, extends along the row direction, and is disposed in the first metal layer ML1. The sixth horizontal link line HLIA6 may be electrically connected to the sixth data line DL6 through a second connection hole CTH2.

[0284] In addition, the vertical link line VLIA may include a sixth vertical link line VLIA6. The sixth vertical link line VLIA6 electrically connects the sixth horizontal link line HLIA6 and the sixth data pad DP6, extends along the column direction, and is disposed in a second metal layer ML2 different from the first metal layer ML1. The sixth vertical link line VLIA6 may be electrically connected to the sixth horizontal link line HLIA6 through a third connection hole CTH3. All or at least a part of the sixth vertical link line VLIA6 may be disposed in the display area AA.

[0285] Referring Figure 8 and Figure 7 , in one or more aspects, in the display panel 110, the second connection hole CTH2 (the data line DL and the horizontal link line HLIA are electrically connected through the second connection hole CTH2) may be disposed in a first inclined direction SLT_DL with respect to the horizontal direction or the vertical direction. The boundary between the first region (region A) and the second region (region B) may be formed in the first inclined direction STL_DL where the second connection hole CTH2 is disposed.

[0286] In one or more aspects, in the display panel 110, the third connection hole CTH3 (the horizontal link line HLIA and the vertical link line VLIA are electrically connected through the third connection hole CTH3) may be arranged in a second inclined direction with respect to the horizontal direction or the vertical direction. The boundary between the second region (region B) and the third region (region C) may be formed in the second inclined direction STL_LIA where the third connection hole CTH3 is disposed.

[0287] Referring Figure 8 and Figure 7, in one or more aspects, the display panel 110 may further include a first horizontal metal pattern HLIA1_DC, which is spaced apart from the first horizontal link line HLIA1, extends in the row direction, and is disposed in the first metal layer ML1. The first horizontal metal pattern HLIA1_DC may include one first horizontal metal pattern HLIA1_DC disposed in the first region (region A) and another first horizontal metal pattern HLIA1_DC disposed in the third region (region C). The first horizontal metal pattern HLIA1_DC disposed in the first region (region A) may be electrically connected to the second to sixth data lines (DL2 to DL6) through the first connection hole CTH1.

[0288] In addition, the display panel 110 may further include a first vertical metal pattern VLIA1_DC, which is spaced apart from the first vertical link line VLIA1, extends in the column direction, and is disposed in the second metal layer ML2.

[0289] Referring to Figure 8 and Figure 7 , in one or more aspects, the display panel 110 may further include a second horizontal metal pattern HLIA2_DC, which is spaced apart from the second horizontal link line HLIA2, extends in the row direction, and is disposed in the first metal layer ML1. The second horizontal metal pattern HLIA2_DC may include one second horizontal metal pattern HLIA2_DC disposed in the first region (region A) and another second horizontal metal pattern HLIA2_DC disposed in the third region (region C). The second horizontal metal pattern HLIA2_DC disposed in the first region (region A) may be electrically connected to the third to sixth data lines (DL3 to DL6) through the first connection hole CTH1.

[0290] In addition, the display panel 110 may further include a second vertical metal pattern VLIA2_DC, which is spaced apart from the second vertical link line VLIA2, extends in the column direction, and is disposed in the second metal layer ML2.

[0291] Referring to Figure 8 and Figure 7, in one or more aspects, the display panel 110 may further include a third horizontal metal pattern HLIA3_DC, which is spaced apart from the third horizontal link line HLIA3, extends in the row direction, and is disposed in the first metal layer ML1. The third horizontal metal pattern HLIA3_DC may include one third horizontal metal pattern HLIA3_DC disposed in the first region (region A) and another third horizontal metal pattern HLIA3_DC disposed in the third region (region C). The third horizontal metal pattern HLIA3_DC disposed in the first region (region A) may be electrically connected to the fourth to sixth data lines (DL4 to DL6) through the first connection hole CTH1.

[0292] In addition, the display panel 110 may further include a third vertical metal pattern VLIA3_DC, which is spaced apart from the third vertical link line VLIA3, extends in the column direction, and is disposed in the second metal layer ML2.

[0293] Referring to Figure 8 and Figure 7 , in one or more aspects, the display panel 110 may further include a fourth horizontal metal pattern HLIA4_DC, which is spaced apart from the fourth horizontal link line HLIA4, extends in the row direction, and is disposed in the first metal layer ML1. The fourth horizontal metal pattern HLIA4_DC may include one fourth horizontal metal pattern HLIA4_DC disposed in the first region (region A) and another fourth horizontal metal pattern HLIA4_DC disposed in the third region (region C). The fourth horizontal metal pattern HLIA4_DC disposed in the first region (region A) may be electrically connected to the fifth to sixth data lines (DL5 to DL6) through the first connection hole CTH1.

[0294] In addition, the display panel 110 may further include a fourth vertical metal pattern VLIA4_DC, which is spaced apart from the fourth vertical link line VLIA4, extends in the column direction, and is disposed in the second metal layer ML2.

[0295] Referring to Figure 8 and Figure 7, in one or more aspects, the display panel 110 may further include a fifth horizontal metal pattern HLIA5_DC, which is spaced apart from the fifth horizontal link line HLIA5, extends in the row direction, and is disposed in the first metal layer ML1. The fifth horizontal metal pattern HLIA5_DC may include one fifth horizontal metal pattern HLIA5_DC disposed in the first region (region A) and another fifth horizontal metal pattern HLIA5_DC disposed in the third region (region C). The fifth horizontal metal pattern HLIA5_DC disposed in the first region (region A) may be electrically connected to the sixth data line DL6 through the first connection hole CTH1.

[0296] In addition, the display panel 110 may further include a fifth vertical metal pattern VLIA5_DC, which is spaced apart from the fifth vertical link line VLIA5, extends in the column direction, and is disposed in the second metal layer ML2.

[0297] Referring to Figure 8 and Figure 7 , in one or more aspects, the display panel 110 may further include a sixth horizontal metal pattern HLIA6_DC, which is spaced apart from the sixth horizontal link line HLIA6, extends in the row direction, and is disposed in the first metal layer ML1.

[0298] In addition, the display panel 110 may further include a sixth vertical metal pattern VLIA6_DC, which is spaced apart from the sixth vertical link line VLIA6, extends in the column direction, and is disposed in the second metal layer ML2.

[0299] The first horizontal metal pattern to the sixth horizontal metal pattern (HLIA1_DC to HLIA6_DC) and the first vertical metal pattern to the sixth vertical metal pattern (VLIA1_DC to VLIA6_DC) may be used as lines for conveying the low power supply voltage VSS (i.e., the second common driving voltage).

[0300] The first through sixth horizontal metal patterns (HLIA1_DC to HLIA6_DC) and the first through sixth vertical metal patterns (VLIA1_DC to VLIA6_DC) can be formed of a mesh of a conductive grid structure having one or more openings. Thus, since the low power supply voltage VSS (i.e., the second common driving voltage) is delivered through the first through sixth horizontal metal patterns (HLIA1_DC to HLIA6_DC) and the first through sixth vertical metal patterns (VLIA1_DC to VLIA6_DC), the area for delivering the low power supply voltage VSS can be increased, and the transmission characteristics of the low power supply voltage VSS can also be greatly improved.

[0301] In addition, since the first horizontal link line is divided into the first horizontal link line HLIA1 and the first horizontal metal pattern HLIA1_DC, and the first vertical link line is divided into the first vertical link line VLIA1 and the first vertical metal pattern VLIA1_DC, the length and area of the path for transmitting the data voltage can be reduced. Accordingly, the parasitic capacitance associated with the first data line DL1 can be reduced.

[0302] Similarly, since the second through sixth horizontal link lines are divided into the second through sixth horizontal link lines (HLIA2 to HLIA6) and the second through sixth horizontal metal patterns (HLIA2_DC to HLIA6_DC), respectively, and the second through sixth vertical link lines are divided into the second through sixth vertical link lines (VLIA2 to VLIA6) and the second through sixth vertical metal patterns (VLIA2_DC to VLIA6_DC), respectively, the length and area of the path for transmitting the data voltage can be reduced. Accordingly, the parasitic capacitance associated with the second through sixth data lines DL2 to DL6 can be reduced.

[0303] Reduction of the parasitic capacitance associated with the first through sixth data lines (DL1 to DL6) can contribute to improving the image quality.

[0304] Referring to Figure 8 and Figure 7 , in one or more aspects, in the first region (region A) of the display panel 110, the horizontal metal pattern HLIA_DC and the data line DL can be electrically connected to each other through the first connection hole CTH1 at a point where the horizontal metal pattern HLIA_DC and the data line DL overlap each other.

[0305] In one or more aspects, at the boundary between the first region (region A) and the second region (region B), the data line DL and the horizontal link line HLIA can be electrically connected to each other through the second connection hole CTH2.

[0306] In one or more aspects, at the boundary between the second region (Region B) and the third region (Region C), the horizontal link line HLIA and the vertical link line VLIA can be electrically connected to each other through the third connection hole CTH3.

[0307] In one or more aspects, in the second region (Region B), the first dummy connection hole DCTH1 can be disposed in the region where each data line DL of the vertical metal pattern VLIA_DC overlaps with the horizontal link line HLIA.

[0308] In one or more aspects, in the third region C, the second dummy connection hole DCTH2 can be disposed in the region where the vertical link line VLIA and the horizontal metal pattern HLIA_DC overlap with each other.

[0309] In one or more aspects, in the display panel 110, the first to third connection holes (CTH1 to CTH3) can be respectively disposed at the boundary between the first region (Region A), the boundary between the first region (Region A) and the second region (Region B), and the boundary between the second region (Region B) and the third region (Region C), and the first dummy connection hole DCTH1 and the second dummy connection hole DCTH2 can be respectively disposed in the second region (Region B) and the third region (Region C). According to these configurations, by uniformly distributing the connection holes and the dummy connection holes over the entire region of the display panel 110, display artifacts, such as some image display defects perceived as patterns, can be corrected.

[0310] Refer to Figure 8 and Figure 9 , the first horizontal link line HLIA1 and the first horizontal metal pattern HLIA1_DC can be disposed in the first metal layer ML1. Accordingly, the first opening region where the first horizontal link line HLIA1 and the first horizontal metal pattern HLIA1_DC are separated from each other can also be referred to as the first opening region of the first metal layer ML1.

[0311] Refer to Figure 8 and Figure 9 , the first vertical link line VLIA1 and the first vertical metal pattern VLIA1_DC can be disposed in the second metal layer ML2. Accordingly, the second opening region where the first vertical link line VLIA1 and the first vertical metal pattern VLIA1_DC are separated from each other can also be referred to as the second opening region of the second metal layer ML2.

[0312] In one or more aspects, refer to Figure 7, one of the first opening regions in the first metal layer ML1 (where one of the first horizontal link lines HLIA1 and one of the first horizontal metal patterns HLIA1_DC are separated from each other) can be set at the boundary between the first region (region A) and the second region (region B) among the three regions (region A, region B, and region C), and these three regions are different regions of the border reduction data link structure in the display area AA.

[0313] In one or more aspects, the other of the first opening regions in the first metal layer ML1 (where the other of the first horizontal link lines HLIA1 and the other of the first horizontal metal patterns HLIA1_DC are separated from each other) and the second opening region of the second metal layer ML2 can be set at the boundary between the second region (region B) and the third region (region C) among the three regions (region A, region B, and region C), and these three regions are different regions of the border reduction data link structure in the display area AA.

[0314] Refer to Figure 8 and Figure 9 , the fourth horizontal link line HLIA4 and the fourth horizontal metal pattern HLIA4_DC can be set on the second interlayer insulating layer 323 (e.g., Figure 3 the second interlayer insulating layer 323) and are spaced apart from each other.

[0315] Refer to Figure 8 and Figure 9 , the first planarization layer 331 (e.g., Figure 3 the first planarization layer 331) can be set on the fourth horizontal link line HLIA4 and the fourth horizontal metal pattern HLIA4_DC.

[0316] Refer to Figure 8 and Figure 9 , the data lines (DL1 to DL6), the first vertical metal pattern to the third vertical metal pattern (VLIA1_DC to VLIA3_DC), and the fourth vertical link line to the sixth vertical link line (VLIA4 to VLIA6) can be set on the first planarization layer 331.

[0317] Refer to Figure 9 , the fifth data line and the sixth data line (DL5 and DL6) can be connected to one of the fourth horizontal metal patterns HLIA4_DC through the first via hole CTH1 in the first planarization layer 331.

[0318] Refer to Figure 9 , the fourth data line DL4 can be connected to the fourth horizontal link line HLIA4 through the second via hole CTH2 in the first planarization layer 331.

[0319] Refer to Figure 9, the first data line to the third data line (DL1 to DL3) can be configured to overlap with the fourth horizontal link line HLIA4 in the first dummy connection hole DCTH1 in the first planarization layer 331. The first vertical metal pattern to the third vertical metal pattern (VLIA1_DC to VLIA3_DC) can be configured to overlap with the fourth horizontal link line HLIA4 in the first dummy connection hole DCTH1 in the first planarization layer 331.

[0320] Referring to Figure 9 , the fourth vertical link line VLIA4 can be connected to the fourth horizontal link line HLIA4 through the third connection hole CTH3 in the first planarization layer 331.

[0321] Referring to Figure 9 , the fifth vertical link line and the sixth vertical link line (VLIA5 and VLIA6) can be configured to overlap with the fourth horizontal metal pattern HLIA4_DC in the second dummy connection hole DCTH2 in the first planarization layer 331.

[0322] Referring to Figure 9 , the second planarization layer 332 (e.g., Figure 3 the second planarization layer 332) can be disposed on the first data line to the sixth data line (DL1 to DL6), the first vertical metal pattern to the third vertical metal pattern (VLIA1_DC to VLIA3_DC), and the fourth vertical link line to the sixth vertical link line (VLIA4 to VLIA6).

[0323] Hereinafter, the display panel 110 having a border-reduced data link structure according to aspects of the present disclosure will be described in more detail with reference to Figure 8 .

[0324] Referring to Figure 8 , in one or more aspects, the display panel 110 may include: a substrate 111 including a display area AA provided with a plurality of substrates SP and a non-display area NA located outside the display area AA and including a pad area PA; a first data pad DP1 provided in the pad area PA; and a first data line DL1 provided in the display area AA, extending in a column direction, and capable of being applied with a data voltage.

[0325] In one or more aspects, the display panel 110 having a border-reduced data link structure may include a first horizontal link line HLIA1 and a first vertical link line VLIA1 electrically connected to the first data line DL1.

[0326] The first horizontal link line HLIA1 can be electrically connected to the first data line DL1 and extend in the row direction, and the first vertical link line VLIA1 can be electrically connected to the first horizontal link line HLIA1 and the first data pad DP1 and extend in the column direction.

[0327] The first horizontal link line HLIA1 can be disposed in the display area AA capable of displaying an image, and all or at least a part of the first vertical link line VLIA1 can be placed in the display area AA. According to these configurations, the border size required for applying the data link structure can be reduced.

[0328] The first data line DL1 can be disposed in the second metal layer ML2. The first horizontal link line HLIA1 can be disposed in the first metal layer ML1, and the first vertical link line VLIA1 can be disposed in the second metal layer ML2 different from the first metal layer ML1.

[0329] According to these configurations, a horizontal line extending in the horizontal direction (row direction) can be disposed in the first metal layer ML1, and a vertical line extending in the vertical direction (column direction) can be disposed in the second metal layer ML2.

[0330] In one or more aspects, the second metal layer ML2 can be disposed at a position higher than the first metal layer ML1 from the substrate 111. For example, the first metal layer ML1 can be the first source-drain metal layer, and the second metal layer ML2 can be the second source-drain metal layer.

[0331] In one or more aspects, in combination with the border-reducing data link structure, the display panel 110 can further include a first horizontal metal pattern HLIA1_DC spaced apart from the first horizontal link line HLIA1 and extending in the row direction, and a first vertical metal pattern VLIA1_DC spaced apart from the first vertical link line VLIA1 and extending in the column direction.

[0332] The first horizontal metal pattern HLIA1_DC can be disposed in the first metal layer ML1, and the first vertical metal pattern VLIA1_DC can be disposed in the second metal layer ML2.

[0333] Since the first horizontal metal pattern HLIA1_DC can be set in the same shape and arrangement as the first horizontal link line HLIA1, and the first vertical metal pattern VLIA1_DC can be set in the same shape and arrangement as the first vertical link line VLIA1, the display panel 110 can have the advantage of reducing display artifacts such as image anomalies and image display defects.

[0334] In one or more aspects, the first horizontal metal pattern HLIA1_DC and the first vertical metal pattern VLIA1_DC can be electrically floating.

[0335] In one or more aspects, as the second common drive voltage (see Figure 2 ) may be applied to the first horizontal metal pattern HLIA1_DC and the first vertical metal pattern VLIA1_DC.

[0336] A path transmitting the low power voltage VSS may be configured in a mesh pattern through the first horizontal metal pattern HLIA1_DC and the first vertical metal pattern VLIA1_DC, so that a transmission characteristic of the low power voltage VSS may be significantly improved.

[0337] In one or more aspects, as described above, the display panel 110 may include a low power supply line VSSL (eg, Figure 2 A low power line VSSL in the embodiment is used to transmit a low power voltage VSS corresponding to a common driving voltage to a plurality of sub-pixels SP.

[0338] The low power supply voltage line VSSL may be electrically connected to the first horizontal metal pattern HLIA1_DC and the first vertical metal pattern VLIA1_DC.

[0339] In one or more aspects, each of the plurality of sub-pixels SP may include a light emitting element ED including a pixel electrode PE, an intermediate layer EL, and a common electrode CE, and the first horizontal metal pattern HLIA1_DC and the first vertical metal pattern VLIA1_DC may be electrically connected to the common electrode CE to which a low power supply voltage VSS is applied.

[0340] In one or more aspects, a low power voltage VSS, which is a signal having a constant voltage level, may be applied to the first horizontal metal pattern HLIA1_DC and the first vertical metal pattern VLIA1_DC.

[0341] In one or more aspects, as described above, in order to provide a data link structure for the second data line DL2 , the display panel 110 may include a second horizontal link line HLIA2 and a second vertical link line VLIA2 electrically connected to the second data line DL2 .

[0342] The second horizontal link line HLIA2 may be electrically connected to the second data line DL2 and extend in a row direction, and the second vertical link line VLIA2 may electrically connect the second horizontal link line HLIA2 and the second data pad DP2 and extend in a column direction.

[0343] The second horizontal link line HLIA2 may be disposed in a display area AA capable of displaying an image, and all or at least a portion of the second vertical link line VLIA2 may be disposed in the display area AA. According to these configurations, the frame size required to enable the data link structure to be applied may be reduced.

[0344] The second horizontal link line HLIA2 can be disposed in the first metal layer ML1, and the second vertical link line VLIA2 can be disposed in a second metal layer ML2 different from the first metal layer ML1.

[0345] In one or more aspects, in combination with the border-reducing data link structure, the display panel 110 may further include a second horizontal metal pattern HLIA2_DC spaced apart from the second horizontal link line HLIA2 and extending in the row direction, and a second vertical metal pattern VLIA2_DC spaced apart from the second vertical link line VLIA2 and extending in the column direction.

[0346] The second horizontal metal pattern HLIA2_DC can be disposed in the first metal layer ML1, and the second vertical metal pattern VLIA2_DC can be disposed in the second metal layer ML2.

[0347] Since the second horizontal metal pattern (HLIA2_DC) can be disposed in the same shape and arrangement as the second horizontal link line HLIA2, and the second vertical metal pattern VLIA2_DC can be disposed in the same shape and arrangement as the second vertical link line VLIA2, the display panel 110 can have the advantage of reducing display artifacts such as image anomalies and image display defects.

[0348] In one or more aspects, the second horizontal metal pattern HLIA2_DC and the second vertical metal pattern VLIA2_DC can be electrically floating.

[0349] In one or more aspects, a low power supply voltage VSS as the second common driving voltage can be applied to the second horizontal metal pattern HLIA2_DC and the second vertical metal pattern VLIA2_DC.

[0350] A path for transmitting the low power supply voltage VSS can be configured as a grid pattern through the second horizontal metal pattern HLIA2_DC and the second vertical metal pattern VLIA2_DC, thereby significantly improving the transmission characteristics of the low power supply voltage VSS.

[0351] In one or more aspects, as described above, the display panel 110 may include a low power supply line VSSL (e.g., Figure 2 the low power supply line VSSL in

[0352] ), for transmitting the low power supply voltage VSS corresponding to the common driving voltage to a plurality of sub-pixels SP.

[0353] In one or more aspects, each of the plurality of sub-pixels SP may include a light-emitting element ED, the light-emitting element ED including a pixel electrode PE, an intermediate layer EL, and a common electrode CE, and a second horizontal metal pattern HLIA2_DC and a second vertical metal pattern VLIA2_DC may be electrically connected to the common electrode CE to which a low power supply voltage VSS is applied.

[0354] In one or more aspects, a low power supply voltage VSS (which is a signal having a constant voltage level) may be applied to the second horizontal metal pattern HLIA2_DC and the second vertical metal pattern VLIA2_DC.

[0355] Hereinafter, reference will be made to Figure 3 briefly describe the application of the first metal layer ML1 and the second metal layer ML2 in the display panel 110.

[0356] In the display panel 110, horizontal lines extending in the horizontal direction (row direction) may be provided in the first metal layer ML1, and vertical lines extending in the vertical direction (column direction) may be provided in the second metal layer ML2.

[0357] Refer to Figure 3 , each of the plurality of sub-pixels SP may include a light-emitting element ED and two or more transistors (TFT1 and TFT2). The two or more transistors (TFT1 and TFT2) may include sources (E1b and E2b) and drains (E1c and E2c).

[0358] The sources (E1b and E2b) and the drains (E1c and E2c) may include a first metal included in a first horizontal link line HLIA1 and a first horizontal metal pattern HLIA1_DC. For example, the first metal may be a metal forming the first metal layer ML1. The first horizontal link line HLIA1 and the first horizontal metal pattern HLIA1_DC may be included in the horizontal lines.

[0359] Refer to Figure 3 , the light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE, and a relay electrode RE may electrically connect the source E1b or the drain E1c of the first transistor TFT1 among the two or more transistors (TFT1 and TFT2) to the pixel electrode PE.

[0360] The relay electrode RE may include a second metal included in a first vertical link line VLIA1 and a first vertical metal pattern VLIA1_DC. For example, the second metal may be a metal forming the second metal layer ML2. The first vertical link line VLIA and the first vertical metal pattern VLIA1_DC may be included in the vertical lines.

[0361] The first data line DL1 serving as a vertical line may also be disposed in the second metal layer ML2.

[0362] A brief description will be given below of the exemplary embodiments described herein.

[0363] According to the exemplary embodiments described herein, a display device may be provided, including: a substrate defining a display area including a plurality of sub-pixels and a non-display area located outside the display area and including a pad area; at least one pad disposed in the pad area; at least one data line disposed in the display area and extending in a column direction; at least one horizontal link line electrically connected to at least one data line and extending in a row direction; at least one vertical link line electrically connecting at least one horizontal link line and at least one pad and extending in a column direction; at least one horizontal metal pattern spaced apart from at least one horizontal link line and extending in a row direction; at least one vertical metal pattern spaced apart from at least one vertical link line and extending in a column direction; a first area including at least one first connection hole through which at least one data line and at least one horizontal metal pattern are electrically connected; a second area including at least one first dummy connection hole in an area where at least one data line and at least one vertical metal pattern respectively overlap at least one horizontal link line; and a third area including at least one second dummy connection hole in an area where at least one vertical link line and at least one horizontal metal pattern overlap each other.

[0364] In one or more aspects, at least one horizontal link line and at least one horizontal metal pattern may be disposed in the first metal layer.

[0365] In one or more aspects, at least one vertical link line and at least one vertical metal pattern may be disposed in a second metal layer different from the first metal layer.

[0366] In one or more aspects, at least one data line may be disposed in the second metal layer.

[0367] In one or more aspects, the second metal layer may be disposed at a position higher from the substrate than the first metal layer.

[0368] In one or more aspects, the display device may further include: at least one second connection hole through which at least one data line and at least one horizontal link line are electrically connected; and at least one third connection hole through which at least one horizontal link line and at least one vertical link line are electrically connected. At least one second connection hole may be disposed in a first inclined direction with respect to a horizontal direction or a vertical direction, and at least one third connection hole may be disposed in a second inclined direction different from the first inclined direction.

[0369] In one or more aspects, the boundary between the first region and the second region may be formed in a first inclined direction provided with at least one second connection hole, and the boundary between the second region and the third region may be formed in a second inclined direction provided with at least one third connection hole.

[0370] In one or more aspects, the display device may further include a planarization layer disposed on at least one horizontal link line and at least one horizontal metal pattern, and at least one first connection hole, at least one second connection hole, at least one third connection hole, at least one first dummy connection hole, and at least one second dummy connection hole may be provided in the planarization layer.

[0371] In one or more aspects, the display device may further include a low voltage line for supplying a low power supply voltage corresponding to a common driving voltage to a plurality of sub-pixels, and the low voltage line may be electrically connected to at least one horizontal metal pattern and at least one vertical metal pattern.

[0372] In one or more aspects, each of the plurality of sub-pixels may include a light-emitting element including a pixel electrode, an intermediate layer, and a common electrode, and at least one horizontal metal pattern and at least one vertical metal pattern may be electrically connected to the common electrode.

[0373] In one or more aspects, the display device may further include: at least one first opening region where at least one horizontal link line is spaced apart from at least one horizontal metal pattern; and at least one second opening region where at least one vertical link line is spaced apart from at least one vertical metal pattern.

[0374] In one or more aspects, at least one horizontal link line may be provided in the display region, and all or at least a part of at least one vertical link line may be provided in the display region.

[0375] In one or more aspects, each of the plurality of sub-pixels may include a light-emitting element and two or more transistors, and the light-emitting element may include a pixel electrode, an intermediate layer, and a common electrode. The source or drain of each of the two or more transistors may include a first metal included in at least one of at least one horizontal link line and at least one horizontal metal pattern.

[0376] In one or more aspects, the display device may further include a relay electrode for electrically connecting the pixel electrode to the source or drain of one of the two or more transistors, and the relay electrode may include a second metal included in at least one of at least one vertical link line and at least one vertical metal pattern.

[0377] According to aspects described herein, a display device having a data link structure capable of reducing the bezel of a display panel can be provided.

[0378] According to one or more aspects of the present disclosure, a display device having a bezel-reducing data link structure capable of improving image quality can be provided.

[0379] According to one or more aspects of the present disclosure, a display device having a bezel-reducing data link structure capable of improving the performance of transmitting a common driving voltage can be provided.

[0380] According to aspects described herein, a display device having a bezel-reducing data link structure capable of correcting display artifacts (e.g., some image display defects perceived as patterns) can be provided.

[0381] According to aspects described herein, a display device and / or a display panel with reduced weight can be provided by reducing the bezel of the display panel using an improved data link structure.

[0382] The above description is provided to enable those skilled in the art to make, use, and practice the technical features of the present disclosure, and is provided as an example in the context of a specific application and its requirements. Without departing from the scope of the present disclosure, those skilled in the art will readily understand various modifications, additions, and substitutions to the described embodiments, and the principles described herein can be applied to other embodiments and applications. The above description and the accompanying drawings are provided only for illustrative purposes to exemplify the technical features of the present disclosure. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.

Claims

1. A display device, comprising: A substrate, wherein the substrate defines a display area including a plurality of sub-pixels and a non-display area located outside the display area and including a pad area; At least one pad is disposed in the pad area; at least one data line, disposed in the display area and extending along a column direction; at least one horizontal link line, electrically connected to the at least one data line and extending in a row direction; at least one vertical link line electrically connecting at least one horizontal link line and the at least one pad and extending along the column direction; at least one horizontal metal pattern spaced apart from the at least one horizontal link line and extending along the row direction; at least one vertical metal pattern spaced apart from the at least one vertical link line and extending along the column direction; A first region includes at least one first connection hole, and the at least one data line is electrically connected to the at least one horizontal metal pattern through the at least one first connection hole; A second region including at least one first dummy connection hole in a region where the at least one data line and the at least one vertical metal pattern respectively overlap with the at least one horizontal link line; as well as The third region includes at least one second dummy connection hole in a region where the at least one vertical link line and the at least one horizontal metal pattern overlap with each other.

2. The display device according to claim 1, wherein: The at least one horizontal link line and the at least one horizontal metal pattern are disposed in a first metal layer, and the at least one vertical link line and the at least one vertical metal pattern are disposed in a second metal layer different from the first metal layer.

3. The display device according to claim 2, wherein: The at least one data line is disposed in the second metal layer.

4. The display device according to claim 2, wherein: The second metal layer is disposed at a position higher than the first metal layer from the substrate.

5. The display device according to claim 4, further comprising a planarization layer disposed between the first metal layer and the second metal layer, in, The at least one first connection hole, the at least one first dummy connection hole, and the at least one second dummy connection hole are disposed in the planarization layer.

6. The display device according to claim 1, further comprising: at least one second connection hole, the at least one data line and the at least one horizontal link line are electrically connected through the at least one second connection hole; as well as at least one third connection hole, the at least one horizontal link line and the at least one vertical link line are electrically connected through the at least one third connection hole, The at least one second connection hole is arranged in a first inclined direction relative to a horizontal direction or a vertical direction, and the at least one third connection hole is arranged in a second inclined direction different from the first inclined direction.

7. The display device according to claim 6, wherein: A boundary between the first region and the second region is formed in the first inclined direction where the at least one second connection hole is provided, and a boundary between the second region and the third region is formed in the second inclined direction where the at least one third connection hole is provided.

8. The display device according to claim 6, further comprising a planarization layer disposed on the at least one horizontal link line and the at least one horizontal metal pattern, in, The at least one first connection hole, the at least one second connection hole, the at least one third connection hole, the at least one first dummy connection hole, and the at least one second dummy connection hole are disposed in the planarization layer.

9. The display device according to claim 1 , further comprising a low voltage line for supplying a low power supply voltage corresponding to a common driving voltage to the plurality of sub-pixels, in, The low voltage line is electrically connected to the at least one horizontal metal pattern and the at least one vertical metal pattern.

10. The display device according to claim 1, wherein: Each of the plurality of sub-pixels includes a light emitting element, the light emitting element including a pixel electrode, an intermediate layer and a common electrode, and Wherein, the at least one horizontal metal pattern and the at least one vertical metal pattern are electrically connected to the common electrode.

11. The display device according to claim 1, further comprising: at least one first opening region, in which the at least one horizontal link line is spaced apart from the at least one horizontal metal pattern; as well as At least one second opening region, in which the at least one vertical link line is spaced apart from the at least one vertical metal pattern.

12. The display device according to claim 1, wherein: The at least one horizontal link line is disposed in the display area, and all or at least a portion of the at least one vertical link line is disposed in the display area.

13. The display device according to claim 1, wherein: Each of the plurality of sub-pixels includes a light emitting element and two or more transistors. Wherein, the light emitting element comprises a pixel electrode, an intermediate layer and a common electrode, and The source or drain of each of the two or more transistors includes a first metal included in at least one of the at least one horizontal link line and the at least one horizontal metal pattern.

14. The display device according to claim 13, further comprising: a relay electrode, the relay electrode being used to electrically connect the pixel electrode to a source or a drain of one of the two or more transistors, The relay electrode includes a second metal included in at least one of the at least one vertical link line and the at least one vertical metal pattern.

15. A display device comprising: A substrate, wherein the substrate defines a display area including a plurality of sub-pixels and a non-display area located outside the display area and including a pad area; A plurality of pads are arranged in the pad area; A plurality of data lines are arranged in the display area and extend in a first direction; A plurality of horizontal link lines extending in a second direction perpendicular to the first direction; as well as a plurality of vertical link lines extending in the first direction; wherein a first end of at least one of the plurality of vertical link lines is electrically connected to a corresponding pad among the plurality of pads, and a second end is connected to a first end of a corresponding horizontal link line among the plurality of horizontal link lines via a second connection hole, and Wherein, the second end of the corresponding horizontal link line is connected to the corresponding data line among the plurality of data lines via a third connection hole.

16. The display device according to claim 15, wherein: At least one of the plurality of vertical link lines has a first end connected to a corresponding pad among the plurality of pads, and a second end connected to a corresponding data line among the plurality of data lines via a first connection hole.

Images