Display device and electronic device

Abstract

There is provided a display device including a plurality of pixels two-dimensionally arranged in a matrix form on a semiconductor substrate, in which each pixel includes: a light emitting element whose brightness varies according to a supplied current; and a plurality of transistors including at least a first transistor having a first channel formation region in the semiconductor substrate and a second transistor having a first gate electrode including a first vertical gate portion extending in a film thickness direction of the semiconductor substrate, and electrically connected to the light emitting element, and a second channel formation region located within the oxide semiconductor layer stacked over the semiconductor substrate and in contact with the first gate electrode via the insulating film.

Description

Technical Field

[0001] The present disclosure relates to a display device and an electronic device. Background Art

[0002] In recent years, display devices using electroluminescence (EL) elements as light-emitting elements have been developed. For example, a display device includes a plurality of light-emitting elements including a lower electrode, a light-emitting layer stacked on the lower electrode, and an upper electrode stacked on the light-emitting layer. Then, the display device includes a drive circuit for driving the light-emitting elements other than the above-described light-emitting elements. For example, as an example of the display device, the display device disclosed in Patent Document 1 below can be exemplified.

[0003] Citation List

[0004] Patent Document

[0005] Patent Document 1: JP 2021-9401 A Summary of the Invention

[0006] Technical Problem

[0007] With the miniaturization of light-emitting elements and the like, in consideration of the withstand voltage and characteristics required for various transistors included in the drive circuit, it is required that the display device reduce the layout size of the drive circuit. In addition, even in the case of miniaturizing the light-emitting elements and multiple pixels, it is required that the display device further reduce power consumption during standby.

[0008] Therefore, the present disclosure proposes a display device and an electronic device that can reduce the layout size of the drive circuit and reduce power consumption during standby while satisfying the required characteristics of the transistors included in the drive circuit.

[0009] Solution to the Problem

[0010] According to the present disclosure, there is provided a display device including a plurality of pixels two-dimensionally arranged in a matrix on a semiconductor substrate. In the display device, each pixel includes: a light-emitting element whose brightness changes according to a provided current; and a plurality of transistors electrically connected to the light-emitting element, which at least include a first transistor and a second transistor, the first transistor including a first channel formation region in the semiconductor substrate, and the second transistor including a first gate electrode including a first vertical gate portion extending in the film thickness direction of the semiconductor substrate; and a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film.

[0011] In addition, according to the present disclosure, an electronic device on which a display device is mounted is provided. In the electronic device, the display device includes a plurality of pixels two-dimensionally arranged in a matrix form on a semiconductor substrate. In the display device, each pixel includes: a light-emitting element whose brightness changes according to the supplied current; and a plurality of transistors electrically connected to the light-emitting element, which at least include a first transistor and a second transistor. The first transistor includes a first channel formation region in the semiconductor substrate, and the second transistor includes a first gate electrode, which includes a first vertical gate portion extending in the film thickness direction of the semiconductor substrate; and a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, and the second channel formation region is in contact with the first gate electrode via an insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram showing an example of the overall configuration of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 is a circuit diagram showing an embodiment of a pixel of a display device according to an embodiment of the present disclosure.

[0014] Figure 3 is a schematic diagram showing an example of the cross-sectional configuration of a pixel according to a comparative example.

[0015] Figure 4A is a schematic diagram showing an example of the cross-sectional configuration of a pixel according to a first embodiment of the present disclosure.

[0016] Figure 4B is a schematic diagram showing an example of the planar configuration of a pixel according to a first embodiment of the present disclosure.

[0017] Figure 5 is a schematic diagram (part 1) showing an example of the cross-sectional configuration of a pixel according to a modified example of a first embodiment of the present disclosure.

[0018] Figure 6 is a schematic diagram (part 2) showing an example of the cross-sectional configuration of a pixel according to a modified example of a first embodiment of the present disclosure.

[0019] Figure 7 is a schematic diagram showing an example of the cross-sectional configuration of a pixel according to a second embodiment of the present disclosure.

[0020] Figure 8 is a schematic diagram (part 1) showing an example of the cross-sectional configuration of a pixel according to a modified example of a second embodiment of the present disclosure.

[0021] Figure 9 is a schematic diagram (part 2) showing an example of the cross-sectional configuration of a pixel according to a modified example of a second embodiment of the present disclosure.

[0022] Figure 10 It is a schematic diagram showing an example of a planar arrangement of pixels according to a third embodiment of the present disclosure.

[0023] Figure 11 It is a schematic diagram showing an example of a cross-sectional arrangement of pixels according to a fourth embodiment of the present disclosure.

[0024] Figure 12 It is a schematic diagram showing an example of a cross-sectional arrangement of pixels according to a fifth embodiment of the present disclosure.

[0025] Figure 13 It is a schematic diagram showing an example of a cross-sectional arrangement of pixels according to a sixth embodiment of the present disclosure (part 1).

[0026] Figure 14 It is a schematic diagram showing an example of a cross-sectional arrangement of pixels according to a sixth embodiment of the present disclosure (part 2).

[0027] Figure 15A It is a cross-sectional view (part 1) for describing a method of manufacturing pixels according to a seventh embodiment of the present disclosure.

[0028] Figure 15B It is a cross-sectional view (part 2) for describing a method of manufacturing pixels according to a seventh embodiment of the present disclosure.

[0029] Figure 15C It is a cross-sectional view (part 3) for describing a method of manufacturing pixels according to a seventh embodiment of the present disclosure.

[0030] Figure 15D It is a cross-sectional view (part 4) for describing a method of manufacturing pixels according to a seventh embodiment of the present disclosure.

[0031] Figure 16 It is a schematic diagram showing an example of a cross-sectional arrangement of a main part of pixels according to an eighth embodiment of the present disclosure.

[0032] Figure 17 It is a schematic diagram showing an example of a cross-sectional arrangement of pixels according to an eighth embodiment of the present disclosure.

[0033] Figure 18A It is a schematic diagram (part 1) showing an example of a cross-sectional arrangement of pixels according to Modification 1 of the eighth embodiment of the present disclosure.

[0034] Figure 18B It is a schematic diagram (part 2) showing an example of a cross-sectional arrangement of pixels according to Modification 1 of the eighth embodiment of the present disclosure.

[0035] Figure 18CIt is a schematic diagram (part 3) showing an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure.

[0036] Figure 19A It is a schematic diagram (part 1) showing an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.

[0037] Figure 19B It is a schematic diagram (part 2) showing an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.

[0038] Figure 19C It is a schematic diagram (part 3) showing an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.

[0039] Figure 19D It is a schematic diagram (part 4) showing an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.

[0040] Figure 20A It is a schematic diagram (part 1) showing an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure.

[0041] Figure 20B It is a schematic diagram (part 2) showing an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure.

[0042] Figure 20C It is a schematic diagram (part 3) showing an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure.

[0043] Figure 21A It is a schematic diagram (part 1) showing an example of a cross-sectional configuration of a main part of a pixel according to Modification 4 of the eighth embodiment of the present disclosure.

[0044] Figure 21B It is a schematic diagram (part 2) showing an example of a cross-sectional configuration of a main part of a pixel according to Modification 4 of the eighth embodiment of the present disclosure.

[0045] Figure 22 It is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to Modification 5 of the eighth embodiment of the present disclosure.

[0046] Figure 23A It is a schematic diagram (part 1) showing an example of a planar configuration of a pixel according to Modification 6 of the eighth embodiment of the present disclosure.

[0047] Figure 23BIt is a schematic diagram (part 2) showing an example of the planar arrangement of pixels according to Modification 6 of the eighth embodiment of the present disclosure.

[0048] Figure 23C It is a schematic diagram (part 3) showing an example of the planar arrangement of pixels according to Modification 6 of the eighth embodiment of the present disclosure.

[0049] Figure 23D It is a schematic diagram (part 4) showing an example of the planar arrangement of pixels according to Modification 6 of the eighth embodiment of the present disclosure.

[0050] Figure 23E It is a schematic diagram (part 5) showing an example of the planar arrangement of pixels according to Modification 6 of the eighth embodiment of the present disclosure.

[0051] Figure 24A It is a cross-sectional view (part 1) for describing a method of manufacturing pixels according to the eighth embodiment of the present disclosure.

[0052] Figure 24B It is a cross-sectional view (part 2) for describing a method of manufacturing pixels according to the eighth embodiment of the present disclosure.

[0053] Figure 25A It is a front view showing an example of the appearance of a digital camera.

[0054] Figure 25B It is a rear view showing an example of the appearance of a digital still camera.

[0055] Figure 26 It is an external view of a head-mounted display.

[0056] Figure 27 It is an external view of a see-through head-mounted display.

[0057] Figure 28 It is an external view of a television device.

[0058] Figure 29 It is an external view of a smartphone.

[0059] Figure 30A It is a view (part 1) showing the internal configuration of a car.

[0060] Figure 30B It is a view (part 2) showing the internal configuration of a car. Detailed Description

[0061] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that, in this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions are omitted. In addition, in this specification and the drawings, a plurality of components having substantially the same or similar functional configurations may be distinguished by attaching different letters after the same reference numeral. However, when it is not particularly necessary to distinguish each of a plurality of components having substantially the same or similar functional configurations, only the same reference numeral is attached.

[0062] In addition, the accompanying drawings referred to in the following description are drawings for facilitating the description and understanding of the embodiments of the present disclosure, and for the sake of clarity, the shapes, sizes, ratios, etc. shown in the drawings may be different from the actual shapes, sizes, ratios, etc. In addition, considering the following description and well-known techniques, the display devices shown in the drawings may be appropriately modified in design.

[0063] In the following description, the description of a specific length and shape does not merely mean the same value as a numerically defined value or a geometrically defined shape in mathematics. Specifically, the description of a specific length and shape in the following description includes cases where there are allowable differences (errors / distortions) in light-emitting elements, display devices, their manufacturing processes, during use and operation, and shapes similar to the shape.

[0064] In addition, in the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means that a plurality of elements are connected so that electricity (signals) can be conducted. In addition, in the following description, "electrically connected" includes not only cases where a plurality of elements are directly and electrically connected, but also cases where a plurality of elements are indirectly and electrically connected via other elements.

[0065] In addition, in the following description, "shared" means that one other element (e.g., a diffusion region, etc.) is used in common among different elements (e.g., transistors, etc.).

[0066] Note that the description will be given in the following order.

[0067] 1. Display device according to an embodiment of the present disclosure

[0068] 1.1 Display device

[0069] 1.2 Pixel

[0070] 2. Background leading to the creation of the embodiments of the present disclosure

[0071] 3. First embodiment

[0072] 3.1 Detailed configuration

[0073] 3.2 Variation

[0074] 4. Second Embodiment

[0075] 4.1 Detailed Configuration

[0076] 4.2 Variations

[0077] 5. Third Embodiment

[0078] 6. Fourth Embodiment

[0079] 7. Fifth Embodiment

[0080] 8. Sixth Embodiment

[0081] 9. Seventh Embodiment

[0082] 10. Eighth Embodiment

[0083] 10.1 Background

[0084] 10.2 Detailed Configuration

[0085] 10.3 Variation 1

[0086] 10.4 Variation 2

[0087] 10.5 Variation 3

[0088] 10.6 Variation 4

[0089] 10.7 Variation 5

[0090] 10.8 Variation 6

[0091] 10.9 Manufacturing Method

[0092] 11. Summary

[0093] 12. Application Example

[0094] 13. Supplementary

[0095] <<Display Device According to Embodiment of the Present Disclosure>>

[0096] <1.1 Display Device>

[0097] First, an example of the overall configuration of the display device 10, which is used as a display device or a lighting device according to an embodiment of the present disclosure, will be described with reference to Figure 1 FIG. which is a schematic diagram showing an example of the overall configuration of the display device 10 according to an embodiment of the present disclosure. Figure 1 FIG. is a schematic diagram showing an example of the overall configuration of the display device 10 according to an embodiment of the present disclosure.

[0098] For example, the display device 10 is a device in which light-emitting elements such as organic light-emitting diodes (OLEDs) or micro-OLEDs are formed in an array. Such a display device 10 can be applied to, for example, display devices for virtual reality (VR), mixed reality (MR), or augmented reality (AR), electronic viewfinders (EVFs), small projectors, and the like.

[0099] Furthermore, in the embodiments of the present disclosure, the light-emitting element only needs to be self-luminous and can also be a current-driven electro-optical element. Examples of current-driven electro-optical elements in addition to OLEDs may include inorganic EL elements, LED elements, and semiconductor laser elements. In addition, an organic EL display device using an OLED as a light-emitting element has the following characteristics. Specifically, in an organic EL display device, since an OLED is a self-luminous element, compared with a liquid crystal display device which is the same flat panel display device, the organic EL display device has high image visibility. Moreover, no illumination member such as a backlight is required, and thus it is easy to reduce the weight and thickness. Also, since the response speed of an OLED is as high as several microseconds, no afterimage appears in the organic EL display device during moving image display.

[0100] Here, as an example, the case of an active matrix organic EL display device using, for example, an OLED as a light-emitting element will be described. The OLED is a current-driven light-emitting element, and its emission luminance varies according to the value of the current flowing through the device. Hereinafter, the "active matrix organic EL display device" is simply referred to as the "display device".

[0101] As Figure 1 shown, the display device 10 includes: a pixel array unit 30 in which a plurality of pixels 20 including light-emitting elements are two-dimensionally arranged in a matrix form on a semiconductor substrate (not shown); and a driving circuit unit arranged around the pixel array unit 30. For example, the driving circuit unit includes a writing and scanning unit 40, a first driving and scanning unit 50, a second driving and scanning unit 60, and a signal output unit 70 mounted on the same display panel 80 as the pixel array unit 30, and drives each pixel 20 of the pixel array unit 30.

[0102] Here, in the case where the display device 10 is compatible with color display, one pixel (unit pixel / pixel) serving as a unit for forming a color image includes a plurality of sub-pixels (sub-pixels). At this time, each sub-pixel corresponds to Figure 1The pixel 20 in [it]. More specifically, in the display device 10 compatible with color display, one pixel 20 may include, for example, three sub-pixels of a sub-pixel emitting red light, a sub-pixel emitting green light, and a sub-pixel emitting blue light, and may include, for example, one, two, or more sub-pixels, and is not particularly limited. In addition, one pixel 20 is not limited to, for example, a combination of sub-pixels of the three primary colors of red, green, and blue, and one pixel 20 may be configured by further adding a sub-pixel of one color or sub-pixels of multiple colors to the sub-pixels of the three primary colors. More specifically, in the display device 10, for example, one pixel 20 may be configured by adding a sub-pixel emitting white light to increase the brightness, or one pixel 20 may be configured by adding at least one sub-pixel emitting complementary color light to expand the color reproduction range.

[0103] In the pixel array unit 30, with respect to the array of pixels 20 in m rows and n columns, along the row direction (the array direction of the pixels 20 in the pixel row / horizontal direction), scanning lines 31 (311 to 31 m ) and driving lines 32 (321 to 32 m ) are wired for each pixel row. In addition, with respect to the array of pixels 20 in m rows and n columns, along the column direction (the array direction of the pixels 20 in the pixel column / vertical direction), signal lines 34 (341 to 34 n ) are wired for each pixel column.

[0104] The scanning lines 311 to 31 m are electrically connected to the output ends of the corresponding rows of the writing and scanning unit 40. The driving lines 321 to 32 m are electrically connected to the output ends of the corresponding rows of the driving and scanning unit 50. Each of the signal lines 341 to 34 n is electrically connected to the output end of the corresponding column of the signal output unit 70.

[0105] The writing and scanning unit 40 includes a shift register circuit and the like. When writing the signal voltage of the video signal to each pixel 20 of the pixel array unit 30, the writing and scanning unit 40 sequentially supplies the writing and scanning signal WS (WS1 to WS m ) to the scanning lines 31 (311 to 31 m ), so that each pixel 20 of the pixel array unit 30 can be scanned row by row sequentially.

[0106] Similar to the writing and scanning unit 40, the first driving and scanning unit 50 includes a shift register circuit and the like. The driving and scanning unit 50 can control the light emission / non-light emission (extinction) of the pixel 20 by supplying the light emission control signal DS (DS1 to DS m ) to the driving lines 32 (321 to 32 m ) synchronously with the line sequential scanning of the writing and scanning unit 40.

[0107] The signal output unit 70 selectively outputs a signal voltage Vsig (hereinafter simply referred to as "signal voltage") corresponding to the luminance information provided from a signal source (not shown) and a reference voltage Vofs. Here, the reference voltage Vofs is a voltage corresponding to a reference of the signal voltage Vsig serving as a video signal or a voltage in the vicinity thereof.

[0108] The signal voltage Vsig / reference voltage Vofs alternately output from the signal output unit 70 is written into each pixel 20 of the pixel array unit 30 via the signal lines 34 (341 to 34 n ), in units of pixel rows selected by the write scan unit 40 through line sequential scanning. That is, the signal output unit 70 can write the signal voltage Vsig in units of pixel rows (lines).

[0109] In the display device 10, by turning off the driving transistor Tr1 (see Figure 2 ), which is included in the pixel 20 described later, the current supply to the light emitting element EL (see Figure 2 ), which is included in the pixel 20, is cut off, and thus, the light emission of the light emitting element EL is suppressed, so that a black gradation can be displayed. However, when the driving transistor Tr1 is switched to the off state, current leakage occurs between the source and the drain of the driving transistor Tr1, and the contrast during black gradation display may be reduced. Therefore, in order to avoid a reduction in contrast during black gradation display, the driving unit of the display device 10 includes a second driving scan unit 60, and in addition, the second driving lines 33 (331 to 33 m ) are wired for each pixel row in the row direction. The second driving lines 331 to 33 m are connected to the output terminals of the corresponding rows of the second driving scan unit 60.

[0110] Specifically, like the write scan unit 40, the second driving scan unit 60 includes a shift register circuit and the like. The second driving scan unit 60 supplies driving signals AZ (AZ1 to AZ m ) to the second driving lines 33 (331 to 33 m ) in synchronization with the line sequential scanning by the write scan unit 40, so that the pixels 20 can be controlled not to emit light during the non-light emission period.

[0111] It should be noted that Figure 1 the overall configuration example shown in Figure 1 is an example of the configuration of the display device 10 according to an embodiment of the present disclosure, and the path configuration of the display device 10 according to an embodiment of the present disclosure is not limited to the configuration shown in

[0112] <1.2 Pixel>

[0113] Next, the circuit configuration of the pixel (pixel circuit) 20 of the display device 10 according to an embodiment of the present disclosure shown in Figure 1 will be described. Figure 2 FIG. is a circuit diagram showing an example of the pixel 20 of the display device 10 according to an embodiment of the present disclosure.

[0114] In an embodiment of the present disclosure, as shown in Figure 2 , the pixel 20 includes a light-emitting element EL and a driving circuit that drives the light-emitting element EL. The light-emitting element EL is an example of a current-driven electro-optical element, in which the light-emitting luminance changes according to the current value flowing through the device, and is constituted by, for example, an OLED. The cathode of the light-emitting element EL is electrically connected to, for example, a node Vss for generating a current.

[0115] Further, the driving circuit includes a plurality of transistors (driving transistor Tr1, writing transistor Tr2, light-emitting control transistor Tr3, and switching transistor Tr4) electrically connected to the light-emitting element EL, and capacitors C1 and C2. The anode of the light-emitting element EL is electrically connected to the driving transistor Tr1, and can emit light when a current flows through the driving transistor Tr1.

[0116] In addition, for example, the driving transistor (also referred to as a light-emitting transistor) (first transistor) Tr1 and the writing transistor (also referred to as a data writing control transistor) (fourth transistor) Tr2 are field effect transistors (FETs). More specifically, the driving transistor Tr1 includes a P-channel transistor, and the writing transistor Tr2 includes an N-channel transistor. Further, the light-emitting control transistor (also referred to as a power supply control transistor) Tr3 (third transistor) and the switching transistor (also referred to as an extinction control transistor) (second transistor) Tr4 are, for example, field effect transistors. More specifically, the light-emitting control transistor Tr3 is a P-channel transistor, and the switching transistor Tr4 is an N-channel transistor.

[0117] More specifically, as shown in Figure 2 , the source and drain of the driving transistor Tr1 are electrically connected to the power node (current source) of the power supply voltage V DD and the anode electrode of the light-emitting element EL via the drain of the light-emitting control transistor Tr3 described later. In addition, the source and drain of the writing transistor Tr2 are electrically connected to the signal line (Vsig) and the gate of the driving transistor Tr1, respectively, and the gate of the writing transistor Tr2 is electrically connected to the scan line (WS). Further, the light-emitting control transistor Tr3 is electrically connected between the power node of the power supply voltage V DD and the source of the driving transistor Tr1. In addition, the switching transistor Tr4 is electrically connected between the drain of the driving transistor Tr1 and the current discharge target node Vss.

[0118] The driving transistor Tr1 can drive the light-emitting element EL by supplying a driving current corresponding to the holding voltage (signal voltage) of a capacitor C1, which will be described later, to the light-emitting element EL.

[0119] The writing transistor Tr2 can write the signal voltage Vsig supplied from the signal output unit 70 to the gate of the driving transistor Tr1 by sampling. Note that the term "write" here means applying a signal voltage to the gate node and holding the potential of the gate node at a potential based on the signal voltage.

[0120] In addition, the light-emission control transistor Tr3 controls the light emission / non-light emission of the light-emitting element EL under the drive of a light-emission control signal DS.

[0121] The switching transistor Tr4 performs control such that the light-emitting element EL does not emit light during the non-light-emission period of the light-emitting element EL driven by a drive signal AZ. That is, when the switching transistor Tr4 enters the on state, the switching transistor Tr4 is used to form a path that bypasses the light-emitting element EL (i.e., performs bypass), so that current supply to the light-emitting element EL can be prevented. In this way, even when there is current leakage between the source and drain of the driving transistor Tr1 when the driving transistor Tr1 is switched to the off state, the switching transistor Tr4 enters the on state, so that current supply to the light-emitting element EL can be prevented. As a result, according to this configuration, a decrease in contrast during black gradation display can be suppressed.

[0122] In addition, the capacitor C1 is connected between the gate and the source of the driving transistor Tr1 and holds the signal voltage Vsig sampled and written through the writing transistor Tr2. The driving transistor Tr1 drives the light-emitting element EL by causing a driving current corresponding to the holding voltage of the capacitor C1 to flow through the light-emitting element EL.

[0123] In addition, the capacitor C2 is connected between the source of the driving transistor Tr1 and a node at a fixed potential (e.g., a power node of the power supply voltage V DD ). The capacitor C2 has an operation of suppressing fluctuations in the source voltage of the driving transistor Tr1 when the signal voltage Vsig is written and setting the gate-source voltage Vgs of the driving transistor Tr1 to the threshold voltage Vth of the driving transistor Tr1.

[0124] It should be noted that the circuit configuration example shown in Figure 2 is an example of the circuit configuration of the pixel 20 of the present embodiment, and the circuit configuration of the pixel 20 according to the present embodiment is not limited to the circuit configuration shown in Figure 2 .

[0125] <<2. Background of the Embodiment Leading to the Creation of the Present Disclosure>>

[0126] Next, before describing the details of the embodiments of the present disclosure, reference will be made to Figure 3 describe the background that led to the creation of the embodiments of the present disclosure by the present inventors. Figure 3 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20a according to a comparative example. It should be noted that here, the comparative example refers to the pixel 20a that has been studied by the present inventors before the embodiments of the present disclosure were made.

[0127] The inventors studied the configuration of the pixel 20a as Figure 3 shown. In Figure 3 the comparative example shown, a plurality of transistors (such as a driving transistor Tr1) included in the driving circuit of the pixel 20a are provided on a semiconductor substrate 100. In other words, the plurality of transistors have channel formation regions in the semiconductor substrate 100. Further, a light-emitting element EL is provided on these transistors.

[0128] Specifically, the plurality of transistors include a gate electrode 102, and the gate electrode 102 is provided via an insulating film 202 on a region having an n-type conductivity type, and the n-type conductivity type serves as a channel provided in the semiconductor substrate 100. Further, these transistors include a source and a drain provided in the semiconductor substrate 100 with a channel region therebetween, and include a diffusion region 104 containing an impurity having a p-type conductivity type. Further, these transistors are separated from other elements by an element isolation portion (shallow trench isolation (STI)) 106 provided in the semiconductor substrate 100.

[0129] Further, as Figure 3 shown, a wiring layer 200 is provided on the semiconductor substrate 100 on which a plurality of transistors are provided. The wiring layer 200 includes an insulating film 202, wirings 204, and vias 206. Further, a light-emitting unit 300 as the light-emitting element EL is provided on the wiring layer 200. The light-emitting element EL includes an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 stacked on the anode electrode 310 and emitting light, and a cathode electrode 312 stacked on the light-emitting layer 314 and transmitting light from the light-emitting layer 314.

[0130] Meanwhile, considering the withstand voltage and characteristics required for various transistors in the driving circuit of the pixel 20a and the miniaturization of the light-emitting element EL and a plurality of pixels, the display device 10 needs to have a reduced layout size of the driving circuit. However, as can be seen from Figure 3As can be seen, when multiple transistors are provided on the semiconductor substrate 100, it is difficult to reduce the layout size of the drive circuit. For example, in order to reduce the layout size of the drive circuit, it may be conceivable to reduce elements such as the source and drain that make up each transistor. However, in this case, the areas of the source and drain are reduced, and thus the contacts electrically connected to the source and drain are also reduced, and thus positional deviation may occur between the source and drain and the contacts during mass production.

[0131] In addition, there are limitations in reducing the size of the transistors included in the drive circuit while satisfying the desired withstand voltage, and thus there are also limitations in reducing the layout size of the drive circuit. Specifically, when an OLED is used as the light-emitting element EL, since a high voltage is applied to drive the OLED, for example, the drive transistor Tr1 requires a high withstand voltage, and thus there are limitations in reducing the layout size of the drive transistor Tr1.

[0132] In addition, by reducing the size of the transistors included in the drive circuit, when the manufacturing conditions change even slightly, the characteristics of the transistors change, and thus more precise control of the manufacturing conditions is required. That is, it is difficult to obtain transistors having desired characteristics by reducing the size of the transistors included in the drive circuit.

[0133] In addition, even when miniaturizing the light-emitting element EL and multiple pixels are realized, it is necessary to further reduce the power consumption of the display device 10 during standby. However, as the number of pixels 20a increases, the number of transistors included in the drive circuit also increases, and thus there are limitations in reducing the power consumption.

[0134] Therefore, in view of this situation, the present inventors have created the embodiments of the present disclosure described below. According to the embodiments of the present disclosure created by the present inventors, the layout size of the drive circuit can be reduced and the power consumption during standby can be reduced while satisfying the required characteristics of the transistors included in the drive circuit.

[0135] <<3. First Embodiment>>

[0136] <3.1 Detailed Configuration>

[0137] First, reference will be made to Figure 4A and Figure 4B to describe the detailed structure of the pixel 20 according to the first embodiment of the present disclosure. Figure 4A is a schematic diagram showing an example of the cross-sectional configuration of the pixel 20 according to the first embodiment of the present disclosure, and specifically, is shown corresponding to the cross-section when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100, and the semiconductor substrate 100 is located on the lower side. In addition, Figure 4Bis a schematic diagram showing an example of the planar configuration of pixel 20 according to the first embodiment of the present disclosure, and specifically corresponds to the cross-section when pixel 20 is cut along the line A-A' shown in Figure 4A . It should be noted that pixel 20 having the configuration shown in Figure 4A and Figure 4B has the circuit configuration shown in the above Figure 2 .

[0138] As Figure 4A shown, pixel 20 according to the present embodiment has a stacked structure including, for example, a semiconductor substrate 100 made of n-type conductive silicon or the like, a wiring layer 200 stacked on the semiconductor substrate 100, and a light-emitting element EL provided on the wiring layer 200. As described above, the light-emitting element EL is a current-driven electro-optical element, and the light-emitting luminance changes according to the current value flowing through the device. In addition, in the present embodiment, the semiconductor substrate 100 and the wiring layer 200 include a driving circuit for driving the light-emitting element EL. Further, in addition to the elements described later, the wiring layer 200 includes an insulating film 202 (e.g., made of a silicon oxide film (SiO2), a silicon nitride film (Si3N4), etc.), a wiring 204 (e.g., made of a metal film such as tungsten (W), etc.), and a via hole 206 (e.g., made of a metal film such as tungsten, etc.).

[0139] In addition, as described with reference to Figure 2 , the driving circuit includes a driving transistor Tr1 (denoted as "Drv" in Figure 4A ), a writing transistor Tr2 (denoted as "WS" in Figure 4A ), a light-emitting control transistor Tr3 (denoted as "DS" in Figure 4A ), a switching transistor Tr4 (denoted as "AZ" in Figure 4A ), and capacitors C1 and C2. Hereinafter, the stacked structure of pixel 20 will be described, but the description will start from the semiconductor substrate 100 located on the lower side in Figure 4A . Note that capacitors C1 and C2 are not shown in Figure 4A .

[0140] The driving transistor Tr1 is a field-effect transistor provided on the semiconductor substrate 100, and specifically is a P-channel transistor. Specifically, as Figure 4AAs shown, the driving transistor Tr1 includes a gate electrode 102 provided on a region having an n-type conductivity type (first channel formation region), and the n-type conductivity type serves as a channel of the driving transistor Tr1 provided in the semiconductor substrate 100 via the insulating film 202. In addition, the driving transistor Tr1 includes a source and a drain provided in the semiconductor substrate 100 (with a channel formation region therebetween), and includes a diffusion region 104 containing impurities having a p-type conductivity type. As described above, in the present embodiment, by providing the driving transistor Tr1 on the semiconductor substrate 100, the characteristics of the driving transistor Tr1 can be stabilized and a transistor with high breakdown voltage can be obtained. It should be noted that, in the present embodiment, the driving transistor Tr1 can be an N-channel transistor.

[0141] The source and drain of the driving transistor Tr1 are electrically connected to a wiring 204 connected to a power supply (V DD ) provided in the wiring layer 200 and the anode 310 of the light-emitting element EL through vias 206 penetrating the wiring layer 200, respectively. In addition, the gate electrode 102 of the driving transistor Tr1 is electrically connected to an electrode (not shown) of a capacitor C1 and the source or drain of a writing transistor Tr2 described later through a via 206.

[0142] In addition, the capacitor C1 can be provided in the wiring layer 200 stacked on the driving transistor Tr1. Specifically, one electrode (not shown) of the capacitor C1 can be electrically connected to the source or drain of the driving transistor Tr1 described above through a via 206. In addition, the other electrode (not shown) of the capacitor C1 can be electrically connected to the source or drain of the driving transistor Tr1 described above and the source or drain of a writing transistor Tr2 described later through a via 206.

[0143] In addition, the driving transistor Tr1 is separated from other elements by an element isolation portion 106 provided in the semiconductor substrate 100.

[0144] In addition, the source or drain of the driving transistor Tr1 and the source or drain of a light-emitting control transistor Tr3 provided in the semiconductor substrate 100 share the diffusion region 104 provided in the semiconductor substrate 100. That is, the driving transistor Tr1 and the light-emitting control transistor Tr3 have a series gate structure, in which one diffusion region 104 is shared as the source or drain of one transistor and the source or drain of the other transistor. It should be noted that, in the present embodiment, a series gate structure is preferably selected to suppress an increase in the layout area of the driving transistor Tr1 and the light-emitting control transistor Tr3, but the present embodiment is not limited thereto.

[0145] Similar to the driving transistor Tr1, as Figure 4AAs shown, the light emission control transistor Tr3 includes a gate 102, and the gate 102 is provided on a region (third channel formation region) having an n-type conductivity type, and the n-type conductivity type serves as a channel of the light emission control transistor Tr3 provided in the semiconductor substrate 100 via the insulating film 202. In addition, the light emission control transistor Tr3 has a source and a drain including a diffusion region 104, and the diffusion region 104 contains impurities of a P-type conductivity type with a channel formation region interposed therebetween. As described above, in the present embodiment, by providing the light emission control transistor Tr3 on the semiconductor substrate 100, a high breakdown voltage transistor having high driving force while having stable characteristics can be provided. In addition, the light emission control transistor Tr3 is separated from the driving transistor Tr1 by an element isolation portion 106 provided in the semiconductor substrate 100.

[0146] In addition, the source or drain of the light emission control transistor Tr3 is electrically connected to an electrode (not shown) of a capacitor C2 provided in the wiring layer 200 and a wiring 204 connected to a power supply (V DD ) through a via 206. In addition, the gate electrode 102 of the light emission control transistor Tr3 is electrically connected to a signal source of a light emission control signal DS through a via 206.

[0147] In addition, the capacitor C2 may be provided in the wiring layer 200 stacked above the driving transistor Tr1 and the light emission control transistor Tr3. Specifically, one capacitor C2 may be electrically connected to the source and drain shared by the driving transistor Tr1 and the light emission control transistor Tr3 described above through a via 206, and the other of the capacitors C2 may be electrically connected to the wiring 204 connected to a power supply (V DD ) through a via 206.

[0148] In addition, in Figure 4A the structure shown, the write transistor Tr2 and the switch transistor Tr4 are provided in the wiring layer 200 stacked on the semiconductor substrate 100 provided with the driving transistor Tr1 and the light emission control transistor Tr3. In the present embodiment, the driving transistor Tr1 and the light emission control transistor Tr3 included in the driving circuit and expected to have high breakdown voltage are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switch transistor Tr4 are provided in the wiring layer 200. In this way, according to the present embodiment, the layout size of the driving circuit can be reduced while ensuring the high breakdown voltage of a predetermined transistor, and finally, the display device 10 can be miniaturized and downsized. It should be noted that the present embodiment is not limited to this structure, and similar to the driving transistor Tr1 and the light emission control transistor Tr3, the write transistor Tr2 may be provided on the semiconductor substrate 100.

[0149] Specifically, in the present embodiment, as Figure 4AAs shown, the writing transistor Tr2 is configured as a thin film transistor (TFT) provided in the wiring layer 200, and specifically, it can be an N-channel transistor. It should be noted that in this embodiment, the writing transistor Tr2 can be a P-channel transistor. More specifically, the writing transistor Tr2 includes an oxide semiconductor layer 210 provided in the wiring layer 200 stacked on the semiconductor substrate 100, and a gate electrode 212 in contact with the oxide semiconductor layer 210 via an insulating film 202.

[0150] The oxide semiconductor layer 210 can be formed by, for example, an oxide film containing at least one element selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), tin (Sn), and zinc (Zn). More specifically, the oxide semiconductor layer 210 can be indium oxide (In2O3), indium tin oxide (Sn is added to In2O3 as a dopant, such as ITO), indium gallium zinc oxide (In and Ga are added to ZnO4 as dopants, such as IGZO), aluminum-zinc oxide (for example, Al is added to ZnO as a dopant, such as AZO), indium-zinc oxide (for example, In is added to ZnO as a dopant, IZO), indium-tin-zinc oxide (In and Sn are added to ZnO as dopants, such as ITZO), indium-aluminum-zinc oxide (In and Al are added to ZnO as dopants, such as IAZO), etc. In this embodiment, since these oxide semiconductors have extremely small leakage currents, leakage in the writing transistor Tr2 can be suppressed. In this way, according to this embodiment, since a signal can be held for a long time due to low leakage, the frame rate during standby can be reduced and an increase in power consumption of the display device 10 caused by multiple pixels can be suppressed.

[0151] In addition, the writing transistor Tr2 has a top-gate structure in which the gate electrode (second gate electrode) 212 is located above the oxide semiconductor layer 210. However, this embodiment is not limited thereto, and the writing transistor Tr2 can have a bottom-gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210, as described later.

[0152] In addition, the gate electrode 212 of the writing transistor Tr2 has a vertical gate portion (second vertical gate portion) 212a extending along the film thickness direction of the semiconductor substrate 100. The gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 via the insulating film 202. Specifically, the oxide semiconductor layer 210 has a region 210a which is Figure 4AA protruding portion that protrudes downward along the vertical gate portion 212a in the cross section shown. Then, in the oxide semiconductor layer 210, the writing transistor Tr2 has a channel formation region (fourth channel formation region) in the region 210a, which is a protruding portion that contacts the gate electrode 212 and its vertical gate portion 212a via the insulating film 202. Further, in the present embodiment, the source and drain of the writing transistor Tr2 are located in a pair of regions 210b, and the region 210a is interposed therebetween, and the region 210a is a protruding portion in the oxide semiconductor layer 210.

[0153] In the present embodiment, the gate electrode 212 of the writing transistor Tr2 has a vertical gate structure, so that the gate length can be easily increased without increasing the layout area (package size). Further, when forming contacts in the source and drain, hydrogen diffuses into the channel formation region and binds to the dangling bonds in the channel formation region, and the characteristics of the channel formation region may change. On the other hand, in the present embodiment, by extending the vertical gate portion 212a (increasing the aspect ratio), the source and drain can be further separated from the channel formation region of the writing transistor Tr2, so that characteristic fluctuations can be suppressed.

[0154] The gate electrode 212 and the vertical gate portion 212a of the writing transistor Tr2 can be formed of a metal or alloy containing at least one element selected from the group consisting of silicon, aluminum, titanium (Ti), and molybdenum (Mo), for example.

[0155] Further, the source or drain of the writing transistor Tr2 is electrically connected to the wiring 204 (signal voltage Vsig) provided in the wiring layer 200 through a through hole (contact hole) 206. The through hole 206 contacts the upper surface of the region 210b of the oxide semiconductor layer 210. Further, the gate electrode 212 of the writing transistor Tr2 is electrically connected to the wiring 204 connected to the scanning line (WS) through the through hole 206.

[0156] Further, in the present embodiment, as Figure 4A shown, the switching transistor Tr4 is configured as a thin film transistor (TFT) provided in the wiring layer 200, similar to the writing transistor Tr2, and can be, for example, an N-channel transistor. It should be noted that the present embodiment is not limited to such a structure, and the switching transistor Tr4 can be provided on the semiconductor substrate 100 similar to the driving transistor Tr1 and the light emission control transistor Tr3.

[0157] Specifically, the switching transistor Tr4 includes an oxide semiconductor layer 210 provided in the wiring layer 200 and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202. As described above, the oxide semiconductor layer 210 can be formed of, for example, an oxide film containing at least one element selected from the group including aluminum, indium, gallium, tin, and zinc. More specifically, the oxide semiconductor layer 210 can be formed of indium oxide (In2O3), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), and the like. In the present embodiment, since these oxide semiconductors have an extremely small leakage current, leakage in the switching transistor Tr4 can be suppressed. In this way, according to the present embodiment, since the leakage current during transient response is suppressed, black floating is reduced and the contrast is improved. In addition, it is easy to form the switching transistor Tr4 into an N-channel transistor. Therefore, the switching transistor Tr4 as an N-channel transistor can stably control the cathode-anode of the light-emitting element EL to 0V and can prevent current from being supplied to the light-emitting element EL. As a result, according to the present embodiment, a decrease in contrast during black gradation display can be suppressed.

[0158] In addition, the switching transistor Tr4 has a top-gate structure in which the gate electrode (first gate electrode) 212 is located above the oxide semiconductor layer 210. However, the present embodiment is not limited thereto, and as described later, the switching transistor Tr4 can have a bottom-gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.

[0159] In addition, the gate electrode 212 of the switching transistor Tr4 has a vertical gate portion (first vertical gate portion) 212a that extends in the film thickness direction of the semiconductor substrate 100. The gate electrode 212 and its vertical gate portion 212a contact the oxide semiconductor layer 210 via the insulating film 202. Specifically, the oxide semiconductor layer 210 has a region 210a that is a protruding portion that protrudes downward along the vertical gate portion 212a in the cross section shown in Figure 4A the switching transistor Tr4 having a top-gate structure and a vertical gate structure. Then, in the oxide semiconductor layer 210, the switching transistor Tr4 has a channel formation region (second channel formation region) in the region 210a that is the protruding portion that contacts the gate electrode 212 and its vertical gate portion 212a via the insulating film 202. In addition, in the present embodiment, the source and drain of the switching transistor Tr4 are located in a pair of regions 210b, and the region 210a is interposed between the pair of regions 210b, and the region 210a is a protruding portion in the oxide semiconductor layer 210.

[0160] In the present embodiment, since the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, the gate length can be easily increased without increasing the layout area. Further, when forming contacts in the source and drain, hydrogen diffuses into the channel formation region and binds to dangling bonds in the channel formation region, and the characteristics of the channel formation region may change. On the other hand, in the present embodiment, by extending the vertical gate portion 212a, the source and drain can be further separated from the channel formation region of the switching transistor Tr4, so that characteristic fluctuations can be suppressed.

[0161] The gate electrode 212 and the vertical gate portion 212a of the switching transistor Tr4 may be formed of, for example, a metal or alloy containing at least one element selected from the group consisting of silicon, aluminum, titanium (Ti), and molybdenum (Mo).

[0162] Further, the source or drain of the switching transistor Tr4 is electrically connected to the anode 310 of the light-emitting element EL provided on the wiring layer 200 through a via hole 206. The via hole 206 is in contact with the upper surface of the region 210b of the oxide semiconductor layer 210. Further, the gate electrode 212 of the switching transistor Tr4 is electrically connected to the wiring 204 connected to the drive signal source (AZ) through a via hole 206.

[0163] Further, in Figure 4A In the structure shown, the switching transistor Tr4 and the writing transistor Tr2 are provided at the same height, that is, on the same layer in the stacked structure of the pixel 20. However, the present embodiment is not limited thereto, and for example, the switching transistor Tr4 and the writing transistor Tr2 may be provided at different heights, that is, in different layers, and may be stacked on each other in the stacked structure of the pixel 20.

[0164] Further, as Figure 4A shown, the light-emitting unit 300 of the light-emitting element EL is provided on the wiring layer 200. The light-emitting element EL mainly includes an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 stacked on the anode electrode 310 and emitting light, and a cathode electrode 312 stacked on the light-emitting layer 314 and transmitting light from the light-emitting layer 314.

[0165] The anode electrode 310 may also function as a reflection layer, and is preferably formed of a metal film having as high a reflectivity as possible and as large a work function as possible in order to improve the light extraction efficiency. Examples of such a metal film may include a metal film containing at least one of elemental substances or alloys of metal elements such as chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), molybdenum, titanium, tantalum (Ta), aluminum, magnesium (Mg), iron (Fe), tungsten, and silver (Ag).

[0166] In addition, the light-emitting layer 314 provided on the anode electrode 310 is made of an organic material or an inorganic material, and is, for example, a layer capable of emitting white light. Further, the light-emitting layer 314 may include a hole injection layer (not shown) and a hole transport layer (not shown) provided adjacent to the anode electrode 310, and an electron transport layer (not shown) provided adjacent to the cathode electrode 312. In other words, the light-emitting layer 314 may have a structure in which a hole injection layer, a hole transport layer, the light-emitting layer 314, and an electron transport layer (not shown) are stacked from the anode electrode 310 side. Note that the hole injection layer serves as a layer for improving the hole injection efficiency into the light-emitting layer 314, and also serves as a buffer layer for suppressing leakage. The hole transport layer functions as a layer for improving the hole transport efficiency to the light-emitting layer 314. In addition, in the light-emitting layer 314, the generation of an electric field causes recombination of electrons and holes, and light can be generated. The electron transport layer is used as a layer for improving the electron transport efficiency to the light-emitting layer 314. Further, the light-emitting layer 314 may have an electron injection layer (not shown) between the electron transport layer and the cathode electrode 312. The electron injection layer is used as a layer for improving the electron injection efficiency. Note that in the present embodiment, the configuration of the light-emitting layer 314 is not limited to the above configuration, and layers other than the hole injection layer and the light-emitting layer 314 are provided as needed.

[0167] In addition, in the present embodiment, the light-emitting layer 314 is not limited to a layer that emits white light, and may be a layer that emits red light (for example, visible light having a wavelength of about 640 nm to 770 nm), blue light (for example, visible light having a wavelength of about 430 nm to 490 nm), or green light (for example, visible light having a wavelength of about 490 nm to 550 nm).

[0168] In addition, the cathode electrode 312 provided on the light-emitting layer 314 is a transparent electrode that is transparent to the light generated in the light-emitting layer 314, and in the following description, the transparent electrode also includes a semi-transparent electrode. The cathode electrode 312 may be formed of a metal film or an oxide film containing at least one of metal elements such as aluminum, magnesium, calcium (Ca), sodium (Na), silver, indium, and zinc.

[0169] In addition, as Figure 4B shown in the plan view of the writing transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210, the gate electrode 212 (specifically, in Figure 4B it, the vertical gate portion 212a is shown) is provided on the strip-shaped oxide semiconductor layer 210, and a pair of through holes 214 electrically connected to the source and drain of the transistor are provided such that the gate electrode 212 is interposed therebetween. In addition, in the plan view, the center of the gate electrode 212 and the centers of the pair of through holes 214 are arranged on a straight line.

[0170] As described above, according to the present embodiment, it is possible to reduce the layout size of the drive circuit and the power consumption during standby while satisfying the required characteristics of the transistors included in the drive circuit.

[0171] Specifically, in the present embodiment, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided in the semiconductor substrate 100, and the write transistor Tr2 and the switch transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 stacked on the semiconductor substrate 100. In this way, according to the present embodiment, it is possible to reduce the layout size of the drive circuit while ensuring a high breakdown voltage of a predetermined transistor, and ultimately, the display device 10 can be miniaturized and downsized.

[0172] In addition, in the present embodiment, by forming the channel formation regions of the write transistor Tr2 and the switch transistor Tr4, which are thin film transistors (TFTs), using the oxide semiconductor layer 210, leakage of the write transistor Tr2 and the switch transistor Tr4 can be suppressed. Specifically, according to the present embodiment, since leakage in the write transistor Tr2 can be suppressed, a signal can be held for a long time, and thus the frame rate during standby can be reduced and an increase in power consumption of the display device 10 due to a plurality of pixels can be suppressed. In addition, according to the present embodiment, since leakage in the switch transistor Tr4 can be suppressed, black floating is reduced, the contrast is improved, and an increase in power consumption of the display device 10 can be suppressed. In addition, according to the present embodiment, it is easy to form the switch transistor Tr4 as an N-channel transistor. Therefore, the switch transistor Tr4, which is an N-channel transistor, can stably control the cathode-anode of the light emitting element EL to 0V and can prevent current from being supplied to the light emitting element EL. As a result, according to the present embodiment, a decrease in contrast during black gradation display can be suppressed.

[0173] In addition, in the present embodiment, the gate electrodes 212 of the write transistor Tr2 and the switch transistor Tr4 have a vertical gate structure, so that the gate length can be easily increased without increasing the layout area. In addition, since the source and drain can be further separated from the channel formation regions of the write transistor Tr2 and the switch transistor Tr4 by extending the vertical gate portion 212a, when contacts are formed in the source and drain, diffusion of hydrogen from the source and drain to the channel formation region and fluctuations in the characteristics of the channel formation region can be suppressed.

[0174] It should be noted that, in the present embodiment, the pixel 20 is not limited to the configuration shown in Figure 4A and 4B For example, the transistors provided in the semiconductor substrate 100 and the transistors in the oxide semiconductor layer 210 provided in the wiring layer 200 are not limited to Figure 4AThe configurations shown in [figures] can be freely combined as long as at least one transistor is provided in the semiconductor substrate 100 and at least another transistor is provided in the oxide semiconductor layer 210. Further, in the present embodiment, the number of transistors included in the drive circuit of the pixel 20 is not limited to four and is not particularly limited as long as it is two or more.

[0175] <3.2 Variation Example>

[0176] In addition, the present embodiment can also be modified as follows. Therefore, the variation examples of the present embodiment are described with reference to Figure 5 and Figure 6 as follows. Figure 5 and Figure 6 are schematic views showing an example of a cross-sectional configuration of the pixel 20 according to a variation example of the present embodiment, and specifically, show a view corresponding to a cross-section when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100 and the semiconductor substrate 100 is on the lower side. Note that in these figures, the capacitors C1 and C2 are not shown.

[0177] In this variation example, as Figure 5 shown, a conductive layer 220 in contact with the lower surface of the oxide semiconductor layer 210 is provided in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the writing transistor Tr2 and the switching transistor Tr4. In this variation example, by providing the conductive layer 220, when the oxide semiconductor layer 210 is formed, the conductive layer 220 acts like a heat sink to generate a temperature gradient, so that a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.

[0178] The conductive layer 220 can be formed of, for example, a metal or an alloy containing at least one element selected from the group consisting of aluminum, titanium (Ti), tantalum (Ta), and molybdenum (Mo). More specifically, the conductive layer 220 can be formed of aluminum, titanium, tantalum, titanium nitride, tantalum nitride, an aluminum-titanium alloy, a silicon-titanium alloy, molybdenum, or the like.

[0179] In this variation example, as Figure 6As shown, the conductive layer 222 in contact with the upper surface of the oxide semiconductor layer 210 is provided in the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the writing transistor Tr2 and the switching transistor Tr4. In this modification, by providing the conductive layer 222, when the oxide semiconductor layer 210 is formed, the conductive layer 220 serves a role similar to a heat sink to generate a temperature gradient, such that a gradient can be generated in the crystallinity of the oxide semiconductor layer 210. Further, according to this modification, the conductive layer 222 can suppress damage to the oxide semiconductor layer 210 when forming contacts at the source and drain. Further, in the case where hydrogen and oxygen diffuse when forming contacts in the source and drain, they may undergo oxidation-reduction and the carrier concentration may fluctuate, but in this modification, the conductive layer 222 can suppress the diffusion of hydrogen and oxygen when forming contacts.

[0180] Similar to the conductive layer 220, the conductive layer 222 can be formed of, for example, a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum. More specifically, the conductive layer 222 can be formed of aluminum, titanium, tantalum, titanium nitride, tantalum nitride, an aluminum-titanium alloy, a silicon-titanium alloy, molybdenum, or the like.

[0181] It should be noted that in this modification, the pixel 20 is not limited to Figure 5 and Figure 6 the configuration shown in

[0182] <<4. Second Embodiment>>

[0183] <4.1 Detailed Configuration>

[0184] Next, a second embodiment of the present invention will be described with reference to Figure 7 FIGs. Figure 7 FIG. 4 is a schematic diagram showing an example of a cross-sectional configuration of the pixel 20 according to the present embodiment, and specifically, is shown as a cross-section corresponding to when the semiconductor substrate 100 is on the lower side when cutting the stacked structure of the pixel 20 in the film thickness direction of the semiconductor substrate 100. It should be noted that in Figure 7 FIG. 4, the capacitors C1 and C2 are not shown.

[0185] In the present embodiment, as in the first embodiment, the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, but as Figure 7 shown in FIG. 5, the gate electrode 212 of the writing transistor Tr2 has a planar gate electrode structure having a planar gate electrode 232 on the oxide semiconductor layer 230.

[0186] As described above, according to the present embodiment, it is possible to reduce the layout size of the drive circuit and the power consumption during standby while satisfying the required characteristics of the transistors included in the drive circuit. Specifically, in the present embodiment, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided in the semiconductor substrate 100, and the write transistor Tr2 and the switch transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 stacked on the semiconductor substrate 100. In this way, according to the present embodiment, it is possible to reduce the layout size of the drive circuit while ensuring a high breakdown voltage of a predetermined transistor, and finally, the display device 10 can be miniaturized and downsized. Further, also in the present embodiment, by forming the channel formation regions of the write transistor Tr2 and the switch transistor Tr4 as thin film transistors (TFTs) using the oxide semiconductor layer 210, leakage of the write transistor Tr2 and the switch transistor Tr4 can be suppressed.

[0187] Further, in the present embodiment, since the gate electrode 212 of the switch transistor Tr4 has a vertical gate structure, it is possible to easily increase the gate length without increasing the layout area. Further, since the source and drain can be further separated from the channel formation region of the switch transistor Tr4 by extending the vertical gate portion 212a, when forming contacts in the source and drain, diffusion of hydrogen from the source and drain to the channel formation region and fluctuations in the characteristics of the channel formation region can be suppressed.

[0188] Note that, in the present embodiment, the pixel 20 is not limited to the configuration shown in Figure 7 For example, the gate electrode 212 of the write transistor Tr2 may have a vertical gate structure, and the gate electrode 212 of the switch transistor Tr4 may have a flat gate electrode structure.

[0189] <4.2 Modification Example>

[0190] In addition, the present embodiment can also be modified as follows. Therefore, the modification examples of the present embodiment will be described with reference to Figure 8 and Figure 9 FIGs. Figure 8 and Figure 9 are schematic views showing an example of the cross-sectional configuration of the pixel 20 according to a modification example of the present embodiment, and specifically, are shown as a cross-section corresponding to when the semiconductor substrate 100 is on the lower side when cutting the stacked structure of the pixel 20 in the film thickness direction of the semiconductor substrate 100. Note that, in these figures, the capacitors C1 and C2 are not shown.

[0191] Moreover, in the present modification example, as shown in Figure 8As shown, a conductive layer 220 in contact with the lower surface of the oxide semiconductor layer 210 is provided in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the switching transistor Tr4. In this modification, by providing the conductive layer 220, when the oxide semiconductor layer 210 is formed, the conductive layer 220 acts like a heat sink to create a temperature gradient, enabling a gradient to be generated in the crystallinity of the oxide semiconductor layer 210.

[0192] In this modification, as Figure 9 shown, a conductive layer 222 in contact with the upper surface of the oxide semiconductor layer 210 is provided in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the switching transistor Tr4. In this modification, by providing the conductive layer 222, when the oxide semiconductor layer 210 is formed, the conductive layer 220 acts like a heat sink to create a temperature gradient, enabling a gradient to be generated in the crystallinity of the oxide semiconductor layer 210. Further, according to this modification, the conductive layer 222 can suppress damage to the oxide semiconductor layer 210 when forming contacts at the source and drain. Further, according to this modification, the conductive layer 222 can suppress the diffusion of hydrogen and oxygen during contact formation.

[0193] Note that in this modification, the pixel 20 is not limited to Figure 8 and Figure 9 the configurations shown.

[0194] <<5. Third Embodiment>>

[0195] Next, a third embodiment of the present invention will be described with reference to Figure 10 FIG. Figure 10 is a schematic diagram showing an example of the planar configuration of the pixel 20 according to the present embodiment and corresponds to Figure 4B FIG.

[0196] In the first embodiment, in the writing transistor Tr2 and the switching transistor Tr4, the gate electrode 212 is provided on the strip-shaped oxide semiconductor layer 210, and a pair of through holes 214 electrically connected to the source and drain of the transistor are provided such that the gate electrode 212 is interposed therebetween. Further, in a plan view, the center of the gate electrode 212 and the centers of the pair of through holes 214 are arranged on a straight line. However, the embodiments of the present disclosure are not limited to this structure.

[0197] For example, as shown on the left side of Figure 10 FIG., for the writing transistor Tr2 and the switching transistor Tr4, the gate electrode 212 (specifically, in Figure 10In [the figure], it is shown that the vertical gate portion 212a) is provided at the center of the L-shaped oxide semiconductor layer 210. In addition, a pair of through holes (contact holes) 214 electrically connected to the source and drain of the transistor are provided at the ends of the L-shaped oxide semiconductor layer 210. In other words, in the plan view, the center of the gate electrode 212 and the centers of the pair of through holes 214 are arranged in an L shape.

[0198] For example, as Figure 10 shown at the center of [the figure], for the write transistor Tr2 and the switch transistor Tr4, the gate electrode 212 (specifically, in Figure 10 [the figure], it is shown that the vertical gate portion 212a) is provided at the center of the U (the Japanese katakana character "ko") shaped oxide semiconductor layer 210. In addition, a pair of through holes 214 electrically connected to the source and drain of the transistor are provided at the ends of the U-shaped oxide semiconductor layer 210. In other words, in the plan view, the center of the gate electrode 212 and the centers of the pair of through holes 214 are arranged in a U shape.

[0199] In addition, a part of the write transistor Tr2 and the switch transistor Tr4 may have a structure that shares a part of the region with these transistors of the adjacent pixel 20. For example, as Figure 10 shown on the right side of [the figure], the gate electrode 212 of the transistor of one pixel 20 (specifically, in Figure 10 [the figure], it is shown that the vertical gate portion 212a) is provided at the center of the oxide semiconductor layer 210 having a Y (the letter "Y") shape. In addition, a pair of through holes 214 electrically connected to the source and drain of the transistor of one pixel 20 and a through hole 214 electrically connected to the source or drain of the transistor of another pixel 20 are provided at the three ends of the Y-shaped oxide semiconductor layer 210. In other words, in the plan view, the center of the gate electrode 212 of the transistor of one pixel 20, the centers of the pair of through holes 214 of the transistor of one pixel 20, and the center of one of the pair of through holes 214 of the transistor of another pixel 20 are arranged in a Y shape.

[0200] As described above, according to the present embodiment, by differently modifying the planar structures of the write transistor Tr2 and the switch transistor Tr4, the layout size of the driving circuit can be further reduced, and in addition, the display device 10 can be miniaturized and downsized.

[0201] It should be noted that in the present embodiment, the write transistor Tr2 and the switch transistor Tr4 of the pixel 20 are not limited to the configuration shown in Figure 10 [the figure].

[0202] <<6. Fourth Embodiment>>

[0203] Next, a fourth embodiment of the present invention will be described with reference to Figure 11 [the figure]. Figure 11FIG. 0 is a schematic diagram showing an example of a cross-sectional configuration of pixel 20 according to the present embodiment, and specifically, is shown as a cross-section corresponding to when the semiconductor substrate 100 is on the lower side when the stacked structure of pixel 20 is cut along the film thickness direction of semiconductor substrate 100. It should be noted that in Figure 11 capacitors C1 and C2 are not shown.

[0204] In the embodiments described so far, the vias 206 of write transistor Tr2 and switch transistor Tr4 are in contact with the upper surface of region 210b of oxide semiconductor layer 210. However, the present embodiment is not limited thereto, and as Figure 11 shown, the vias 206 of write transistor Tr2 and switch transistor Tr4 may be in contact with the lower surface of region 210b of oxide semiconductor layer 210.

[0205] As described above, in the present embodiment, by deforming the cross-sectional structure of write transistor Tr2 and switch transistor Tr4 (i.e., the structure of the contacts of the source and drain of these transistors), the size of the drive circuit in the film thickness direction of semiconductor substrate 100 can be further reduced. As a result, according to the present embodiment, display device 10 can be miniaturized and downsized.

[0206] It should be noted that in the present embodiment, pixel 20 is not limited to the Figure 11 configuration shown in.

[0207] <<7. Fifth Embodiment>>

[0208] Next, a fifth embodiment of the present invention will be described with reference to Figure 12 FIG. 25. Figure 12 FIG. 25 is a schematic diagram showing an example of a cross-sectional configuration of pixel 20 according to the present embodiment, and specifically, is shown as a cross-section corresponding to when the semiconductor substrate 100 is on the lower side when the stacked structure of pixel 20 is cut along the film thickness direction of semiconductor substrate 100. It should be noted that in Figure 12 capacitors C1 and C2 are not shown.

[0209] In the embodiments described so far, write transistor Tr2 and switch transistor Tr4 have a vertical gate structure having one vertical gate portion 212a, but in the present embodiment, write transistor Tr2 and switch transistor Tr4 may have a vertical gate structure having a plurality of vertical gate portions 212b. For example, in Figure 12 write transistor Tr2 and switch transistor Tr4 have two vertical gate portions 212b. Note that the present embodiment is not limited to having two vertical gate portions 212b, and only needs to have two or more vertical gate portions 212b.

[0210] As described above, in the present embodiment, since the gate electrodes 212 of the writing transistor Tr2 and the switching transistor Tr4 have a plurality of vertical gate portions 212b, the gate length can be further increased without increasing the layout area. Further, in the present embodiment, since the source and drain can be further separated from the channel formation regions of the writing transistor Tr2 and the switching transistor Tr4, when contacts are formed in the source and drain, diffusion of hydrogen from the source and drain to the channel formation region and fluctuations in the characteristics of the channel formation region can be more effectively suppressed.

[0211] It should be noted that, in the present embodiment, the pixel 20 is not limited to the configuration shown in Figure 12 .

[0212] <<8. Sixth Embodiment>>

[0213] Next, a sixth embodiment of the present disclosure will be described with reference to Figure 13 and Figure 14 . Figure 13 and Figure 14 are schematic views showing an example of the cross-sectional configuration of the pixel 20 according to the present embodiment, and specifically, show a cross-section corresponding to when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100, and the semiconductor substrate 100 is located on the lower side. Note that, in these figures, the capacitors C1 and C2 are not shown.

[0214] In the embodiments described so far, the writing transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210. However, the present embodiment is not limited thereto, and the writing transistor Tr2 and the switching transistor Tr4 may have a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.

[0215] Specifically, as shown in Figure 13 , the gate electrodes 212 of the writing transistor Tr2 and the switching transistor Tr4 have vertical gate portions 212a extending in the film thickness direction of the semiconductor substrate 100. The gate electrode 212 and its vertical gate portion 212a are in contact with the lower surface of the oxide semiconductor layer 210 via the insulating film 202. Specifically, the oxide semiconductor layer 210 has a region 210a that is a protruding portion that protrudes upward along the vertical gate portion 212a in the cross-section shown in Figure 13 for the writing transistor Tr2 having a bottom gate structure and a vertical gate structure.

[0216] Further, as shown in Figure 13As shown, the vias 206 of the writing transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.

[0217] Alternatively, in the present embodiment, as Figure 14 shown, as Figure 13 in, the writing transistor Tr2 and the switching transistor Tr4 may have a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210. Further, in Figure 14 the example of, the vias 206 of the writing transistor Tr2 and the switching transistor Tr4 are in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.

[0218] As described above, according to the present embodiment, by deforming the cross-sectional structures of the writing transistor Tr2 and the switching transistor Tr4, the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be further reduced, and ultimately, the display device 10 can be miniaturized and downsized.

[0219] Further, in the present embodiment, the pixel 20 is not limited to Figure 13 and Figure 14 the configurations shown in.

[0220] <<9. Seventh Embodiment>>

[0221] Next, an example of a method for manufacturing the pixel 20 according to the first embodiment described above according to the seventh embodiment of the present disclosure will be described with reference to Figures 15A to 15D FIG.. Figures 15A to 15D is a cross-sectional view for describing a method for manufacturing the pixel (pixel circuit) 20 according to the present embodiment, and specifically corresponds to the cross-section shown in Figure 4A FIG..

[0222] First, as shown on the left side of Figure 15A FIG., the driving transistor Tr1 and the light emission control transistor Tr3 are formed on the semiconductor substrate 100, a part of the wiring layer 200 is formed on the semiconductor substrate 100, and the insulating film 202 is further formed. Then, as shown in the center of Figure 15A FIG., a trench 400 is formed in the insulating film 202 by etching or the like. Further, as shown on the right side of Figure 15A FIG., an oxide semiconductor layer 210 serving as a channel formation region of the writing transistor Tr2 and the switching transistor Tr4 is formed by sputtering or the like to cover the insulating film 202.

[0223] Next, as shown on the left side of Figure 15B FIG., an insulating film 202 serving as a gate insulating film of the writing transistor Tr2 and the switching transistor Tr4 is formed to cover the oxide semiconductor layer 210 and fill the trench 400. Then, as shown in Figure 15BAs shown at the center of [], a trench 402 is formed in a region of the insulating film 202 embedded in the trench 400. Further, as Figure 15B shown on the right side of [], a metal film or the like forming a vertical gate portion 212a of the gate electrode 212 of the write transistor Tr2 and the switch transistor Tr4 is formed to be embedded in the trench 402.

[0224] Next, as Figure 15C shown on the left side of [], the insulating film 202 serving as the gate insulating film of the write transistor Tr2 and the switch transistor Tr4 is formed on the insulating film 202 and the vertical gate portion 212a. Further, the insulating film 202 is planarized by using chemical mechanical polishing (CMP) or the like to expose the upper surface of the vertical gate portion 212a, and the gate electrodes 212 of the write transistor Tr2 and the switch transistor Tr4 are formed on the upper surface of the vertical gate portion 212a.

[0225] Then, as Figure 15C shown on the right side of [], an insulating film 202 serving as an interlayer insulating film is formed to cover the upper surfaces of the gate electrode 212 and the insulating film 202.

[0226] Next, as Figure 15D shown on the left side of [], holes for exposing the upper surface of the region 210b of the oxide semiconductor layer 210, which are parts of the source and drain of the write transistor Tr2 and the switch transistor Tr4, are formed in the insulating film 202, and a metal film serving as a via 214 is formed in the holes in the insulating film 202. Then, as Figure 15D shown on the right side of [], wirings 204 are formed on the upper surfaces of the vias 214.

[0227] That is, the pixel 20 according to the embodiment of the present disclosure can be manufactured by using methods, apparatuses, and conditions for manufacturing ordinary semiconductor devices. That is, the pixel 20 according to the present embodiment can be manufactured by using existing methods for manufacturing semiconductor devices.

[0228] <<10. Eighth Embodiment>>

[0229] <10.1 Background>

[0230] First, before describing the details of the eighth embodiment of the present disclosure, the background that led to the creation of the eighth embodiment of the present disclosure by the present inventors will be described with reference to Figure 16 The background that led to the creation of the eighth embodiment of the present disclosure by the present inventors will be described. Figure 16 is a schematic diagram showing an example of a cross-sectional configuration of a main part of the pixel 20 according to the eighth embodiment of the present disclosure.

[0231] In each embodiment of the present disclosure described so far, leakage of the write transistor Tr2 and the switching transistor Tr4 is suppressed by forming channel formation regions of the write transistor Tr2 and the switching transistor Tr4 in the oxide semiconductor layer 210. Further, in these embodiments, the gate electrode 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure, such that the gate length can be easily increased without increasing the layout area. Further, in these embodiments, since the source and drain can be further separated from the channel formation regions of the write transistor Tr2 and the switching transistor Tr4 by extending the vertical gate portion 212a, when contacts are formed in the source and drain, diffusion of hydrogen from the source and drain to the channel formation region and characteristic fluctuations of the channel formation region are suppressed.

[0232] However, the oxide semiconductor layer 210 made of indium gallium zinc oxide (IGZO) or the like has a property of being easily oxidized and reduced due to the influence of surrounding films. For example, when oxygen diffuses from the insulating film 202 made of a silicon oxide film (SiO2) into the oxide semiconductor layer 210, the oxide semiconductor layer 210 is easily oxidized and its resistance tends to increase.

[0233] In the write transistor Tr2 and the switching transistor Tr4 according to the embodiments of the present disclosure described so far, the region 210a of the oxide semiconductor layer 210 that will become the channel may have a high resistance, but a pair of regions 210b of the oxide semiconductor layer 210 that will become the source and drain need to have a low resistance in order to suppress parasitic resistance generated in the source and drain.

[0234] Thus, it may be considered to form the region 210a of the oxide semiconductor layer 210 as the channel and form a pair of regions 210b of the oxide semiconductor layer 210 as the source and drain. However, forming the region 210a and the region 210b separately is difficult due to the fact that the pixel 20 itself is minute, and further increases the number of manufacturing processes of the display device 10, and thus it is hard to say that this is a preferable option.

[0235] Therefore, in view of this situation, the inventors of the present invention have created an eighth embodiment in which the region 210a of the oxide semiconductor layer 210 that will become the channel and a pair of regions 210b of the oxide semiconductor layer 210 that will become the source and drain can be easily formed separately.

[0236] In the eighth embodiment, as Figure 16As shown, the region 210a of the oxide semiconductor layer 210 that is to become the channel is formed in contact with an insulating film (first insulating layer) 202 composed of an oxide film that acquires electrons from the surroundings, thereby increasing the resistance of the region 210a of the oxide semiconductor layer 210 that is to become the channel. On the other hand, in the present embodiment, a pair of regions 210b of the oxide semiconductor layer 210 that are to become the source and drain are formed in contact with an insulating film (second insulating layer) 450 composed of a reducing film that supplies electrons to the surroundings, thereby reducing the resistance of the region 210b.

[0237] Here, the oxide film that acquires electrons from the surroundings refers to a film that acquires electrons from the surroundings and oxidizes the film. Specifically, the oxide film is a film that can acquire electrons from the region 210a of the oxide semiconductor layer 210 that serves as the channel and oxidize the film. Specifically, the oxide film is an oxygen supply film that supplies oxygen to the region 210a of the oxide semiconductor layer 210 that is to become the channel, and can be, for example, silicon oxide, silicon oxynitride (SiON), aluminum oxide (Al2O3), etc. In addition, the oxygen supply film is preferably silicon oxide (SiOx (x>2)) that overly contains oxygen, etc.

[0238] Here, the reducing film that supplies electrons to the surroundings refers to a film that supplies electrons to the surroundings to reduce the film. Specifically, the reducing film is a film that can supply electrons to a pair of regions 210b of the oxide semiconductor layer 210 that are to become the source and drain to reduce the region. Specifically, the reducing film is a hydrogen supply film that supplies hydrogen to the pair of regions 210b of the oxide semiconductor layer 210 that serve as the source and drain, or a film that can extract oxygen from the pair of regions 210b. For example, the hydrogen supply film can be silicon nitride containing hydrogen, silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxynitride (AlON), etc. In addition, since the hydrogen content of the hydrogen supply film can be adjusted by, for example, film formation conditions, film thickness, etc., the reduction effect on the region 210b can be freely adjusted. In the present embodiment, in order to sufficiently supply hydrogen to the region 210b and prevent oxygen from diffusing from the surroundings (e.g., the insulating film 202) to the region 210b, the film thickness of the hydrogen supply film is preferably equal to or greater than, for example, 20 nm. In addition, in the present embodiment, examples of the film that can extract oxygen may include an insulating film having a compressive stress higher than that of the oxide semiconductor layer 210.

[0239] According to this embodiment, by forming the region 210a of the oxide semiconductor layer 210 as a channel so as to be in contact with the insulating film 202 composed of an oxide film that acquires electrons from the surroundings, the region 210a is oxidized and the resistance value can be increased. On the other hand, according to this embodiment, a pair of regions 210b of the oxide semiconductor layer 210 to be used as source and drain are formed in contact with an insulating film (second insulating layer) 450 composed of a reduction film that supplies electrons to the surroundings, so that the pair of regions 210b are reduced and the resistance value can be decreased. Further, according to this embodiment, the regions 210a and 210b of the oxide semiconductor layer 210 can be easily formed to have desired characteristics respectively. Hereinafter, details of this eighth embodiment of the present disclosure will be described in sequence.

[0240] <10.2 Detailed Configuration>

[0241] Next, with reference to Figure 17 , the eighth embodiment of the present invention will be described. Figure 17 is a schematic diagram showing an example of the cross-sectional configuration of the pixel 20 according to this embodiment, and specifically, shows a cross-section corresponding to when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100, and the semiconductor substrate 100 is located on the lower side. Note that the capacitors C1 and C2 are not shown in these figures.

[0242] Specifically, in this embodiment, as shown in Figure 17 , the writing transistor Tr2 and the switching transistor Tr4 have an oxide semiconductor layer 210 provided in a wiring layer 200 stacked on the semiconductor substrate 100, and a gate electrode 212 in contact with the oxide semiconductor layer 210 via an insulating film 202, as in each of the embodiments described so far. Further, the writing transistor Tr2 and the switching transistor Tr4 have a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210. The film thickness of the oxide semiconductor layer 210 is, for example, equal to or less than 20 nm.

[0243] Further, also in this embodiment, the gate electrodes 212 of the writing transistor Tr2 and the switching transistor Tr4 have a vertical gate portion 212a extending in the film thickness direction of the semiconductor substrate 100. Specifically, according to the writing transistor Tr2 and the switching transistor Tr4 having a top gate structure and a vertical gate structure, the oxide semiconductor layer 210 has a region 210a that is in Figure 17A protruding portion that protrudes downward along the vertical gate portion 212a in the cross section shown. Then, in the oxide semiconductor layer 210, the writing transistor Tr2 and the switching transistor Tr4 have channel formation regions in the region 210a, which is a protruding portion that contacts the gate electrode 212 and its vertical gate portion 212a via the insulating film 202. Further, in the present embodiment, the gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 via the insulating film 202 formed of the above-mentioned oxide film. Further, in the present embodiment, the side of the region 210a, which is a protruding portion serving as a channel formation region, that is opposite to the vertical gate portion 212a also contacts the insulating film 202 formed of the oxide film.

[0244] Further, in the present embodiment, as in each of the embodiments described so far, the source and drain of the writing transistor Tr2 and the switching transistor Tr4 are located in a pair of regions 210b therebetween, and the region 210a is a protruding portion in the oxide semiconductor layer 210. Further, in the present embodiment, different from the embodiments described so far, as Figure 17 shown, the insulating film 450 formed of the above-mentioned reduction film is provided in contact with the lower surfaces of the pair of regions 210b.

[0245] As described above, according to the present embodiment, by forming the region 210a to be a channel in contact with the insulating film 202 formed of an oxide film that acquires electrons from the surroundings, the region 210a is oxidized and the resistance value can be increased. On the other hand, according to the present embodiment, the pair of regions 210b to be the source and drain are formed in contact with the insulating film (second insulating layer) 450 formed of a reduction film that supplies electrons to the surroundings, so that the pair of regions 210b are reduced and the resistance value can be lowered.

[0246] Further, also in the present embodiment, by cutting the pixel 20 along the Figure 17 line A-A' shown in, the cross section obtained may have a form similar to the cross section of the first embodiment shown in Figure 4B . Specifically, in the plan view of the writing transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210, the gate electrode 212 may be provided on the strip-shaped oxide semiconductor layer 210, and a pair of through holes 214 electrically connected to the source and drain of the transistor may be provided such that the gate electrode 212 is therebetween. Further, in the plan view, the center of the gate electrode 212 and the centers of the pair of through holes 214 may be arranged on a straight line.

[0247] Alternatively, also in the present embodiment, the plan view of the writing transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210 may have a form similar to that inFigure 10 a form similar to the third embodiment shown in. Specifically, for the writing transistor Tr2 and the switching transistor Tr4, for example, the gate electrode 212 may be provided at the center of the L-shaped oxide semiconductor layer 210. In addition, a pair of through holes (contact holes) 214 electrically connected to the source and drain of the transistor may be provided at the ends of the L-shaped oxide semiconductor layer 210.

[0248] Alternatively, also in this embodiment, for the writing transistor Tr2 and the switching transistor Tr4, for example, the gate electrode 212 may be provided at the center of the U (the Japanese kana "ko")-shaped oxide semiconductor layer 210. In addition, a pair of through holes 214 electrically connected to the source and drain of the transistor may be provided at the ends of the U-shaped oxide semiconductor layer 210.

[0249] Alternatively, also in this embodiment, a part of the writing transistor Tr2 and the switching transistor Tr4 may have a structure in which a part of the region is shared with these transistors of the adjacent pixel 20. For example, the gate electrode 212 of the transistor of one pixel 20 may be provided at the center of the oxide semiconductor layer 210 having a Y (the letter "Y") shape. In addition, the pair of through holes 214 electrically connected to the source and drain of the transistor of one pixel 20 and the through hole 214 electrically connected to the source or drain of the transistor of another pixel 20 may be provided at the three ends of the Y-shaped oxide semiconductor layer 210.

[0250] Note that in this embodiment, the pixel 20 is not limited to the configuration shown in Figure 17 the figure.

[0251] <10.3 Modification Example 1>

[0252] In addition, this embodiment can also be modified as follows. Therefore, Modification Example 1 of this embodiment will be described with reference to Figures 18A to 18C the figure. Figures 18A to 18C is a schematic diagram showing an example of the cross-sectional configuration of the pixel 20 according to Modification Example 1 of this embodiment, and specifically, shows a cross-section corresponding to when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100, and the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitors C1 and C2 are not shown.

[0253] In Figure 18A the example, the conductive layer 220 in contact with the lower surface of the oxide semiconductor layer 210 is provided in the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the writing transistor Tr2 and the switching transistor Tr4.

[0254] The conductive layer 220 is preferably a reducing film that provides electrons to the surroundings, that is, a conductive film having a high ionization tendency and being easily oxidized. Specifically, the conductive layer 220 is formed of a metal or an alloy containing at least one element selected from the group including aluminum, titanium, and tantalum. More specifically, the conductive layer 220 may be formed of aluminum, titanium, tantalum, titanium nitride, tantalum nitride, or the like.

[0255] As described above, in Figure 18A the example, by providing the conductive layer 220, the region 210b can be further reduced, and oxygen diffusion from the periphery (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modification example, the region 210b serving as the source and drain can be further inhibited from having a high resistance, and thus, parasitic resistance in the source and drain of the transistor Tr2 and the switching transistor Tr4 can be prevented.

[0256] In addition, in Figure 18B the example, the conductive layer 222 in contact with the upper surface of the oxide semiconductor layer 210 is provided in the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the writing transistor Tr2 and the switching transistor Tr4.

[0257] The conductive layer 222 is also preferably a reducing film that provides electrons to the surroundings, that is, a conductive film having a high ionization tendency and being easily oxidized. Specifically, the conductive layer 222 is also formed of a metal or an alloy containing at least one element selected from the group including aluminum, titanium, and tantalum. More specifically, the conductive layer 222 may be formed of aluminum, titanium, tantalum, titanium nitride, tantalum nitride, or the like.

[0258] As described above, also in Figure 18B the example, by providing the conductive layer 222, the region 210b can be further reduced, and oxygen diffusion from the periphery (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modification example, the region 210b serving as the source and drain can be further inhibited from having a high resistance, and thus, parasitic resistance in the source and drain of the transistor Tr2 and the switching transistor Tr4 can be prevented.

[0259] In addition, in Figure 18C the example, the conductive layer 220 in contact with the lower surface of the oxide semiconductor layer 210 and the conductive layer 222 in contact with the upper surface of the oxide semiconductor layer 210 are provided in the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the writing transistor Tr2 and the switching transistor Tr4. That is, in Figure 18C the example, the region 210b of the oxide semiconductor layer 210 serving as the source or drain of the writing transistor Tr2 and the switching transistor Tr4 is interposed between the conductive layer 220 and the conductive layer 222.

[0260] As described above, also in Figure 18C In the example of Figure 18C , by providing the conductive layer 220 and the conductive layer 222, the region 210b can be further reduced, and oxygen diffusion from the periphery (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modification example, having a high resistance in the region 210b used as the source and drain can be further suppressed, and thus, parasitic resistance in the source and drain of the transistor Tr2 and the switching transistor Tr4 can be prevented.

[0261] Note that Figure 18C The configuration shown in Figure 18C can be applied to each of the above-described embodiments and modification examples of the present disclosure. In addition, in the first modification example, the pixel 20 is not limited to the configuration shown in Figures 18A to 18C Figures 18A to 18C .

[0262] <10.4 Modification Example 2>

[0263] Next, a description will be given of a second modification example of the present embodiment with reference to Figures 19A to 19D Figures 19A to 19D . Figures 19A to 19D FIG. Figures 19A to 19D is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to a second modification example of the present embodiment, and specifically, is shown in a manner corresponding to a cross-section when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100 and the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitors C1 and C2 are not shown.

[0264] It can be said that this second modification example is an embodiment in which the second embodiment is applied to the eighth embodiment. That is, as shown in Figure 19A Figure 19A , although the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, the gate electrode 212 of the writing transistor Tr2 has a planar gate electrode structure having a planar gate electrode 232 on the oxide semiconductor layer 230.

[0265] In addition, in this second modification example, as shown in Figures 19B - 19D Figures 19B - 19D , similar to the above-described first modification example, the conductive layer 220 and the conductive layer 222 can be applied to the form shown in Figure 19A Figure 19A .

[0266] Note that in this second modification example, the pixel 20 is not limited to the configuration shown in Figures 19A to 19D Figures 19A to 19D .

[0267] <10.5 Modification Example 3>

[0268] Next, a description will be given of a third modification example of the present embodiment with reference to Figures 20A to 20C Figures 20A to 20C . Figures 20A to 20CFIG. 0 is a schematic diagram showing an example of a cross-sectional configuration of pixel 20 according to Modification 2 of the present embodiment. Specifically, it shows a cross-section corresponding to when the stacked structure of pixel 20 is cut along the film thickness direction of semiconductor substrate 100, and semiconductor substrate 100 is located on the lower side. Note that in these figures, capacitors C1 and C2 are not shown.

[0269] In the eighth embodiment and the modifications described so far, the vias 206 of write transistor Tr2 and switch transistor Tr4 are in contact with the upper surface of region 210b of oxide semiconductor layer 210. However, this modification is not limited to this, as Figure 20A shown, the vias 206 of write transistor Tr2 and switch transistor Tr4 may be in contact with the lower surface of region 210b of oxide semiconductor layer 210.

[0270] As described above, in the Figure 20A example, by deforming the cross-sectional structures of write transistor Tr2 and switch transistor Tr4 (i.e., the structures of the contacts of the source and drain of these transistors), the size of the drive circuit in the film thickness direction of semiconductor substrate 100 can be further reduced. As a result, according to this modification, display device 10 can be made smaller and more compact.

[0271] Furthermore, in the eighth embodiment and the modifications described so far, write transistor Tr2 and switch transistor Tr4 have a top-gate structure in which gate electrode 212 is located above oxide semiconductor layer 210. However, this modification is not limited to this, and as in the sixth embodiment, as Figure 20B shown, write transistor Tr2 and switch transistor Tr4 may have a bottom-gate structure in which gate electrode 212 is located below oxide semiconductor layer 210.

[0272] As described above, in the Figure 20B example, by deforming the cross-sectional structures of write transistor Tr2 and switch transistor Tr4, the size of the drive circuit in the film thickness direction of semiconductor substrate 100 can be further reduced. As a result, according to this modification, display device 10 can be made smaller and more compact.

[0273] Alternatively, in the Figure 20C example shown, as Figure 20B shown, although write transistor Tr2 and switch transistor Tr4 have a bottom-gate structure in which gate electrode 212 is located below oxide semiconductor layer 210, the vias 206 of write transistor Tr2 and switch transistor Tr4 may be in contact with the lower surface of region 210b of oxide semiconductor layer 210.

[0274] As described above, in the Figure 20CIn the example, by deforming the cross-sectional structures of the writing transistor Tr2 and the switching transistor Tr4, the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be further reduced. As a result, according to this modification example, the display device 10 can be miniaturized and downsized.

[0275] It should be noted that in this modification example 3, the pixel 20 is not limited to Figures 20A to 20C the configuration shown in

[0276] <10.6 Modification Example 4>

[0277] Next, with reference to Figure 21A and Figure 21B Modification Example 4 of the present embodiment will be described. Figure 21A and Figure 21B are schematic diagrams showing an example of the cross-sectional configuration of the main part of the pixel 20 according to Modification Example 4 of the present embodiment.

[0278] In this modification example 4, as Figure 21A shown, the writing transistor Tr2 and the switching transistor Tr4 may have a double-gate structure. Specifically, the writing transistor Tr2 and the switching transistor Tr4 have vertical gate portions (first vertical gate portions) 212a and a gate electrode (third gate electrode) 212c facing each other, and the region 210a is a protruding portion of the oxide semiconductor layer 210 and serves as a channel formation region, which is interposed therebetween. In this modification example, the same potential may be applied to the vertical gate portion 212a and the gate electrode 212c, or different potentials may be applied.

[0279] Furthermore, in this modification example 4, as Figure 21B shown, the vertical gate portions of the writing transistor Tr2 and the switching transistor Tr4 may have a structure in which metal is not completely embedded. Specifically, the vertical gate portion 212d may have a tubular structure in which the surface facing the region 210a (which is a protruding portion of the oxide semiconductor layer 210 serving as a channel formation region) is closed and the inside is hollow. That is, since this modification can have a structure in which the vertical gate portion is not completely filled with metal, it can be said that this modification has a structure with high mass productivity.

[0280] It should be noted that Figure 21A and Figure 21B the configurations shown in can be applied to the above-described embodiments and modification examples of the present disclosure. Moreover, in this modification example 4, the writing transistor Tr2 and the switching transistor Tr4 of the pixel 20 are not limited to Figure 21A and Figure 21B the configurations shown in

[0281] <10.7 Modification Example 5>

[0282] Next, with reference toFigure 22 A description will be given of Modification 5 of this embodiment. Figure 22 FIG. is a schematic diagram showing an example of the cross-sectional configuration of the pixel 20 according to Modification 5 of this embodiment, and specifically, shows a cross-section corresponding to when the stacked structure of the pixel 20 is cut in the film thickness direction of the semiconductor substrate 100, and the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitors C1 and C2 are not shown.

[0283] In the eighth embodiment and the modifications described so far, the write transistor Tr2 and the switch transistor Tr4 have a vertical gate structure having one vertical gate portion 212a, but in this modification, they may have a vertical gate structure having a plurality of vertical gate portions 212b. Specifically, in Figure 22 the example of, the write transistor Tr2 and the switch transistor Tr4 have two vertical gate portions 212b. Note that this Modification 5 is not limited to having two vertical gate portions 212b, and only needs to have two or more vertical gate portions 212b.

[0284] As described above, in this Modification 5, the gate electrodes 212 of the write transistor Tr2 and the switch transistor Tr4 have a plurality of vertical gate portions 212b, so that the gate length can be further increased without increasing the layout area. Further, in this Modification 5, since the source and drain can be further separated from the channel formation regions of the write transistor Tr2 and the switch transistor Tr4, when contacts are formed in the source and drain, it is possible to more effectively suppress the diffusion of hydrogen from the source and drain to the channel formation region and the fluctuation of the characteristics of the channel formation region.

[0285] <10.8 Modification 6>

[0286] Next, a description will be given of Modification 6 of this embodiment with reference to Figures 23A to 23E A description will be given of Modification 6 of this embodiment. Figures 23A to 23E FIG. is a schematic diagram showing an example of the planar configuration of the pixel 20 according to Modification 6 of this embodiment.

[0287] As Figure 23A shown, in this modification, in the plan views of the write transistor Tr2 and the switch transistor Tr4, the write transistor Tr2 and the switch transistor Tr4 may be separately provided from each other. Further, as Figure 23B shown, in this modification, in the plan views of the write transistor Tr2 and the switch transistor Tr4, the vertical gate portion 212a of the write transistor Tr2 and the switch transistor Tr4 may be connected, for example, in a U (the Japanese katakana character "ko") shape.

[0288] Further, as Figure 23CAs shown, in this modified example, the writing transistor Tr2 and the switching transistor Tr4 can be arranged vertically side by side in the drawing in the plan view of the writing transistor Tr2 and the switching transistor Tr4. Moreover, as Figure 23C shown, in this modified example, the vertical gate portion 212a of the writing transistor Tr2 and the switching transistor Tr4 can extend vertically in the drawing and be connected to each other.

[0289] As Figure 23D shown, in this modified example, the source and drain can be shared in the plan view of the writing transistor Tr2 and the switching transistor Tr4. In this way, the area occupied by the writing transistor Tr2 and the switching transistor Tr4 can be reduced. In addition, as Figure 23E shown, in this modified example, in the plan view of the writing transistor Tr2 and the switching transistor Tr4, the vertical gate portions 212a of the writing transistor Tr2 and the switching transistor Tr4 can be connected, for example, in a U (the Japanese katakana character "ko") shape.

[0290] As described above, according to this modified example 6, the degree of freedom in layout can be ensured while increasing the gate length without increasing the area occupied by the writing transistor Tr2 and the switching transistor Tr4.

[0291] It should be noted that Figures 23A to 23E the configurations shown in can be applied to each of the above-described embodiments and modified examples of the present disclosure. In addition, in this modified example 6, the writing transistor Tr2 and the switching transistor Tr4 of the pixel 20 are not limited to Figures 23A to 23E the configurations shown in.

[0292] <10.9 Manufacturing Method>

[0293] Next, with reference to Figures 24A to 24B , an example of a method for manufacturing the pixel 20 according to the above-described eighth embodiment will be described. Figure 24A and Figure 24B are cross-sectional views for describing a method for manufacturing the pixel (pixel circuit) 20 according to the present embodiment.

[0294] First, as shown on the left side of Figure 24A , the driving transistor Tr1 and the light emission control transistor Tr3 are formed on the semiconductor substrate 100, a part of the wiring layer 200 is formed on the semiconductor substrate 100, and an insulating film 202 made of an oxide film (for example, silicon oxide) is further formed. In addition, an insulating film 450 made of a reduction film (for example, silicon nitride) is formed on the insulating film 202. Next, as shown in the second from the left on the left side of Figure 24A , trenches 400 are formed in the insulating films 202 and 450 by etching or the like.

[0295] In addition, as Figure 24AAs shown in the third one from the left in [figure reference], an oxide semiconductor layer 210, which serves as a channel formation region of a write transistor Tr2 and a switching transistor Tr4, is formed using a process technology with high coverage characteristics such as atomic layer deposition (ALD) to cover the insulating films 202 and 450.

[0296] Next, as Figure 24A shown in the third line from the left in [figure reference], an insulating film 202 made of, for example, silicon oxide serving as a gate insulating film is formed to cover the oxide semiconductor layer 210. In this case, it is preferable to use a process technology with high coating properties such as ALD. Further, as Figure 24A shown on the right side of [figure reference], an electrode material for a vertical gate portion 212a is embedded in the trench.

[0297] Furthermore, as Figure 24B shown in the upper left portion of [figure reference], the embedded electrode can be processed. Alternatively, as Figure 24B shown in the middle left portion of [figure reference], n-type impurities can be ion-implanted into the oxide semiconductor layer 210 on both sides of the vertical gate portion 212a to form impurity diffusion regions 460. Alternatively, as Figure 24B shown in the lower left portion of [figure reference], after removing the insulating films 202 on both sides of the vertical gate portion 212a, ions can be implanted into the exposed oxide semiconductor layer 210 on both sides of the vertical gate portion 212a to form impurity diffusion regions 460.

[0298] Next, as Figure 24B shown in the second one from the left in [figure reference], the insulating film 202 is stacked. Further, as Figure 24B shown in the third one from the left, a via hole 214 connected to a portion that becomes the source and drain of the oxide semiconductor layer 210 is formed, and as Figure 24B shown on the right side of [figure reference], a wiring 204 is formed on the via hole 214.

[0299] As described above, in the present embodiment, a trench 400 is formed on the stacked insulating films 202 and 450 to form the oxide semiconductor layer 210, and a gate (vertical gate portion 212a) in contact with the oxide semiconductor layer 210 is further formed via the insulating film 202. That is, according to the present embodiment, by using a stack of the insulating film 202 made of an oxide film and the insulating film 450 made of a reduction film, it is possible to easily separate and form a channel region 210a and source and drain regions 210b to have desired characteristics without significantly increasing the number of steps. Further, in the present embodiment, the reduction effect on the region 210b can be freely adjusted by adjusting the film thickness of the insulating film 450 or the like.

[0300] That is, the pixel 20 according to the eighth embodiment of the present disclosure can be manufactured by using the methods, apparatuses, and conditions for manufacturing ordinary semiconductor devices. That is, the pixel 20 according to the present embodiment can be manufactured by using existing methods for manufacturing semiconductor devices.

[0301] Note that examples of the above methods may include physical vapor deposition (PVD) methods, CVD methods, ALD methods, etc. Examples of the PVD method may include vacuum vapor deposition, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, radio frequency direct current (RF-DC) combined with bias sputtering, electron cyclotron resonance (ECR) sputtering, reverse target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer methods. Examples of the CVD method may include plasma CVD methods, thermal CVD methods, metalorganic (MO) CVD methods, and photo-CVD methods. In addition, other methods may include electrolytic plating, electroless plating, and spin coating; dipping; casting methods; microcontact printing; droplet casting; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; stamping; spraying; and various coating methods such as air knife coater, knife coater, rod coater, knife coater, extrusion coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, casting coater, spray coater, slot hole coater, and calender coater. In addition, examples of patterning methods may include chemical etching such as shadow masks, laser transfer, and photolithography, and physical etching using ultraviolet light, lasers, etc. In addition, examples of planarization techniques may include CMP methods, laser planarization methods, reflow methods, etc.

[0302] <<11. Summary>>

[0303] As described above, according to each embodiment of the present disclosure, the layout size of the driving circuit can be reduced and the power consumption during standby can be lowered while satisfying the required characteristics of the transistors included in the driving circuit.

[0304] Specifically, in the present embodiment, the driving transistor Tr1 and the light emission control transistor Tr3 included in the driving circuit are provided in the semiconductor substrate 100, and the writing transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 stacked on the semiconductor substrate 100. In this way, according to the present embodiment, the layout size of the driving circuit can be reduced while ensuring a high breakdown voltage of a predetermined transistor, and ultimately, the display device 10 can be miniaturized and downsized.

[0305] In addition, in the present embodiment, by using the oxide semiconductor layer 210 to form the channel formation regions of the writing transistor Tr2 and the switching transistor Tr4 which are thin film transistors (TFTs), leakage of the writing transistor Tr2 and the switching transistor Tr4 can be suppressed. Specifically, according to the present embodiment, since leakage in the writing transistor Tr2 can be suppressed, a signal can be held for a long time, and thus the frame rate during standby can be reduced and an increase in power consumption of the display device 10 caused by a plurality of pixels can be suppressed. In addition, according to the present embodiment, since leakage in the switching transistor Tr4 can be suppressed, black floating is reduced, contrast is improved, and an increase in power consumption of the display device 10 can be suppressed. In addition, according to the present embodiment, it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4 as an N-channel transistor can stably control the cathode-anode of the light-emitting element EL to 0V and can prevent current from being supplied to the light-emitting element EL. As a result, according to the present embodiment, a decrease in contrast during black gradation display can be suppressed.

[0306] In addition, in the present embodiment, since the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, the gate length can be easily increased without increasing the layout area. In addition, since the source and drain can be further separated from the channel formation region of the switching transistor Tr4 by extending the vertical gate portion 212a, when contacts are formed in the source and drain, diffusion of hydrogen from the source and drain to the channel formation region and fluctuations in the characteristics of the channel formation region can be suppressed.

[0307] It should be noted that the technology of the present disclosure can be applied not only to the display device 10 but also to lighting devices and the like.

[0308] In addition, in the above-described embodiment of the present disclosure, the semiconductor substrate 100 does not have to be a silicon substrate and can be another substrate (for example, a silicon-on-insulator (SOI) substrate, a SiGe substrate, etc.).

[0309] <<12. Application Examples>>

[0310] For example, the technology according to the present disclosure can be applied to display units of various electronic devices and the like. Therefore, examples of electronic devices to which the present technology can be applied will be described below.

[0311] (Specific Example 1)

[0312] Figure 25A is a front view showing an example of the appearance of a digital camera 500, and Figure 25BIt is a rear view showing an example of the appearance of the digital camera 500. The digital still camera 500 is a single-lens reflex type with interchangeable lenses, and includes an interchangeable imaging lens unit (interchangeable lens) 512 substantially at the center of the front of the camera body (camera body) 511, and a grip portion 513 held by the photographer on the left front side.

[0313] The monitor 514 is provided at a position offset to the left from the center of the back surface of the camera body 511. An electronic viewfinder (eyepiece window) 515 is provided above the monitor 514. By observing the electronic viewfinder 515, the photographer can determine the composition by visually recognizing the optical image of the subject guided by the imaging lens unit 512. As the monitor 514 and the electronic viewfinder 515, the display device 10 according to the embodiment of the present disclosure can be used.

[0314] (Specific Example 2)

[0315] Figure 26 It is an external view of the head-mounted display 600. The head-mounted display 600 includes, for example, earhook portions 612 on both sides of the user's head that are worn on the glasses-shaped display unit 611. In the head-mounted display 600, the display device 10 according to the embodiment of the present disclosure can be used as the display unit 611.

[0316] (Specific Example 3)

[0317] Figure 27 It is an external view of the see-through head-mounted display 634. The see-through head-mounted display 634 includes a main body 632, an arm 633, and a lens barrel 631.

[0318] The main body 632 is connected to the arm 643 and the glasses 630. Specifically, the end of the main body 632 in the long side direction is coupled to the arm 633, and one side of the side surface of the main body 632 is coupled to the glasses 630 via a connecting member. Note that the main body 632 can be directly worn on the human head.

[0319] The main body 632 includes a control board for controlling the operation of the see-through head-mounted display 634 and a display unit. The arm 633 connects the main body 632 and the lens barrel 631 and supports the lens barrel 631. Specifically, the arm 633 is connected to the end of the main body 632 and the end of the lens barrel 631, and fixes the lens barrel 631. In addition, the arm 633 contains a signal line for communicating data related to the image provided from the main body 632 to the lens barrel 631.

[0320] The lens barrel 631 projects, via the arm 633, image light provided by the main body 632 through the eyepiece toward the eyes of the user wearing the see-through head-mounted display 634. In the see-through head-mounted display 634, the display device 10 according to an embodiment of the present disclosure can be used for the display unit of the main body 632.

[0321] (Specific Example 4)

[0322] Figure 28 An example of the appearance of the television device 710 is shown. The television device 710 includes, for example, a video display screen unit 711 including a front panel 712 and a filter glass 713, and the video display screen unit 711 includes the display device 10 according to an embodiment of the present disclosure.

[0323] (Specific Example 5)

[0324] Figure 29 An example of the appearance of the smart phone 800 is shown. The smart phone 800 includes a display unit 802 that displays various types of information, an operation unit including buttons that receive operations input by the user, and the like. The display unit 802 can be the display device 10 according to the present embodiment.

[0325] (Specific Example 6)

[0326] Figure 30A and Figure 30B are views showing the interior configuration of an automobile including the display device 10 according to an embodiment of the present disclosure as a display device. Specifically, Figure 30A is a view showing the state of the interior of the automobile from the rear to the front of the automobile, and Figure 30B is a view showing the state of the interior of the automobile from the inclined rear to the inclined front of the automobile.

[0327] Figure 30A and Figure 30B The automobiles shown in and have a center display 911, a console display 912, a head-up display 913, a digital rearview mirror 914, a steering wheel display 915, and a rear-seat entertainment display 916. The display device 10 according to an embodiment of the present disclosure can be applied to some or all of these displays.

[0328] The center display 911 is provided at a position on the center console 907 facing the driver's seat 901 and the passenger seat 902. Figure 30A and Figure 30BAn example of the center display 911 having a horizontally long shape extending from the driver's seat 901 side to the passenger's seat 902 side is shown, but the screen size and arrangement position of the center display 911 are arbitrary. The center display 911 can display information detected by various sensors (not shown). As a specific example, the center display 911 can display a captured image captured by an image sensor, a distance image to an obstacle in front of or on the side of the vehicle measured by a time-of-flight (ToF) sensor, the body temperature of a passenger detected by an infrared sensor, etc. The center display 911 can be used to display at least one of, for example, safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, or entertainment-related information.

[0329] Safety-related information is information such as drowsiness detection, looking-away detection, prank detection of a child riding together, detection of the presence or absence of seat belt wearing, and detection of a passenger's departure, and is information detected by, for example, sensors (not shown) superimposed on the rear side of the center display 911. Operation-related information uses sensors to detect gestures related to the operations of the occupants. The detected postures can include the operations of various devices in the vehicle. For example, the operations of an air conditioning device, a navigation device, an audio / video (AV) device, a lighting device, etc. are detected. Life logs include the life logs of all occupants. For example, life logs include the action records of each occupant in the vehicle. By acquiring and storing the life records, the state of the passengers at the time of an accident can be confirmed. Health-related information uses a temperature sensor to detect the body temperature of an occupant and estimates the health condition of the occupant based on the detected body temperature. Alternatively, the face of the occupant can be imaged using an image sensor, and the health condition of the occupant can be estimated from the imaged facial expression. In addition, a conversation can be automatically carried out with the passenger by voice, and the health condition of the passenger can be estimated based on the content of the passenger's answer. Authentication / identification-related information includes a keyless input function that performs face authentication using sensors, an automatic adjustment function of the sheet height and position in face recognition, etc. Entertainment-related information includes a function for the passenger to detect the operation information of the AV device using sensors, a function for the sensors to identify the face of the passenger and the AV device to provide content suitable for the passenger, etc.

[0330] For example, the console display 912 can be used to display life log information. The console display 912 is arranged near the shift lever 908 of the center console 907 between the driver's seat 901 and the passenger's seat 902. The console display 912 can also display information detected by different sensors (not shown). In addition, the console display 912 can display an image of the vehicle periphery captured by an image sensor, or can display a distance image to an obstacle in the vehicle periphery.

[0331] The head-up display 913 is virtually displayed behind the windshield 904 in front of the driver's seat 901. The head-up display 913 can be used to display at least one of, for example, safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information. In many cases, since the head-up display 913 is virtually set in front of the driver's seat 901, the head-up display is suitable for displaying information directly related to the operation of the vehicle, such as the speed of the vehicle and the remaining amount of fuel (battery).

[0332] The digital rearview mirror 914 can not only display the rear of the vehicle but also display the state of the passengers in the rear seat, and can thus be used to display life log information, for example, by arranging sensors (not shown) to overlap with the back side of the digital rearview mirror 914.

[0333] The steering wheel display 915 is arranged near the center of the steering wheel 906 of the vehicle. The steering wheel display 915 can be used to display at least one of, for example, safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, since the steering wheel display 915 is close to the driver's hand, it is suitable for displaying life log information such as the driver's body temperature, or for displaying information related to the operation of an AV device, an air conditioning device, etc.

[0334] The rear entertainment display 916 is attached to the backs of the driver's seat 901 and the passenger seat 902 and is used for viewing by the passengers in the rear seat. The rear entertainment display 916 can be used to display at least one of, for example, safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information. In particular, since the rear entertainment display 916 is in front of the passengers in the rear seat, it displays information related to the passengers in the rear seat. For example, information about the operation of an AV device or an air conditioning device can be displayed, or the result of measuring the body temperature of the passengers in the rear seat by a temperature sensor (not shown) can be displayed.

[0335] <<13. Supplementary>>

[0336] Although the preferred exemplary embodiments of the present disclosure have been described in detail with reference to the drawings, the technical scope of the present disclosure is not limited to such examples. Obviously, various changes or modifications within the scope of the technical idea described in the claims can be conceived by those of ordinary skill in the art, and it is naturally understood that these changes or modifications also belong to the technical scope of the present disclosure.

[0337] In addition, the effects described in this specification are merely illustrative or exemplary, rather than restrictive. That is, according to the technology of the present disclosure, other effects obvious to those skilled in the art may be exhibited from the description of this specification together with or instead of the above effects.

[0338] It should be noted that the present technology may also have the following configurations.

[0339] (1) A display device, comprising:

[0340] A plurality of pixels two-dimensionally arranged in a matrix form on a semiconductor substrate, wherein,

[0341] Each pixel includes:

[0342] A light-emitting element whose brightness changes according to the provided current; and

[0343] A plurality of transistors electrically connected to the light-emitting element, the plurality of transistors at least including a first transistor and a second transistor,

[0344] The first transistor includes:

[0345] A first channel formation region in the semiconductor substrate, and

[0346] The second transistor includes:

[0347] A first gate electrode including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate; and

[0348] A second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film.

[0349] (2) The display device according to (1), wherein,

[0350] In a cross-section obtained by cutting a pixel along the film thickness direction of the semiconductor substrate,

[0351] When the semiconductor substrate is disposed on the lower side,

[0352] The second transistor is stacked above the first transistor.

[0353] (3) The display device according to (1) or (2), wherein,

[0354] In a cross-section obtained by cutting a pixel along the film thickness direction of the semiconductor substrate,

[0355] When the semiconductor substrate is disposed on the lower side,

[0356] The oxide semiconductor layer has a protruding portion protruding downward along the first vertical gate portion.

[0357] (4)The display device according to (1) or (2), wherein,

[0358] In a cross-section obtained by cutting a pixel along the film thickness direction of a semiconductor substrate,

[0359] When the semiconductor substrate is disposed on the lower side,

[0360] The oxide semiconductor layer has a protruding portion that protrudes upward along the first vertical gate portion.

[0361] (5)The display device according to any one of (1) to (4), wherein the first gate electrode includes a plurality of first vertical gate portions.

[0362] (6)The display device according to any one of (1) to (5), wherein the oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc.

[0363] (7)The display device according to (3) or (4), wherein the second transistor includes a source and a drain, and the protruding portion of the oxide semiconductor layer is interposed between the source and the drain.

[0364] (8)The display device according to (7), wherein the source and the drain of the second transistor include a conductive layer disposed on the oxide semiconductor layer.

[0365] (9)The display device according to (7), wherein the source and the drain of the second transistor include a conductive layer disposed under the oxide semiconductor layer.

[0366] (10)The display device according to (7), wherein the source and the drain of the second transistor are interposed between two conductive layers.

[0367] (11)The display device according to any one of (8) to (10), wherein the conductive layer is composed of a metal or an alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum.

[0368] (12)The display device according to any one of (7) to (11), wherein the second channel formation region is in contact with a first insulating layer composed of an oxide film that acquires electrons from the surroundings.

[0369] (13)The display device according to (12), wherein the oxide film includes an oxygen supply film that supplies oxygen to the second channel formation region.

[0370] (14)The display device according to any one of (7) to (13), wherein the source and the drain of the second transistor are in contact with a second insulating layer composed of a reduction film that gives electrons to the surroundings.

[0371] The display device according to (14), wherein the reduction film includes a hydrogen supply film that supplies hydrogen to the source and drain electrodes.

[0372] The display device according to (14) or (15), wherein the thickness of the reduction film is 20 nm or more.

[0373] The display device according to any one of (1) to (16), wherein the first vertical gate portion has a tubular structure, and in the tubular structure, the surface facing the second channel formation region is closed.

[0374] The display device according to any one of (1) to (17), wherein

[0375] The second transistor further includes a third gate electrode facing the first vertical gate portion, and the second channel formation region is interposed between the third gate electrode and the first vertical gate portion.

[0376] The display device according to (7), wherein

[0377] When the semiconductor substrate is disposed on the lower side of the cross-section,

[0378] The source and drain electrodes of the second transistor include contact holes that contact the upper surface of the oxide semiconductor layer.

[0379] The display device according to (7), wherein

[0380] When the semiconductor substrate is disposed on the lower side of the cross-section,

[0381] The source and drain electrodes of the second transistor include contact holes that contact the lower surface of the oxide semiconductor layer.

[0382] The display device according to (19) or (20), wherein

[0383] In the plan view of the semiconductor substrate when viewed from above,

[0384] A pair of contact holes and the first gate electrode are arranged in a line.

[0385] The display device according to (19) or (20), wherein

[0386] In the plan view of the semiconductor substrate when viewed from above,

[0387] A pair of contact holes and the first gate electrode are arranged in an L shape.

[0388] The display device according to (19) or (20), wherein

[0389] In the plan view of the semiconductor substrate when viewed from above,

[0390] A pair of contact holes and a first gate electrode are arranged in a U shape.

[0391] The display device according to (19) or (20), wherein

[0392] in a plan view of the semiconductor substrate when viewed from above,

[0393] a pair of contact holes of a second transistor of a pixel, a first gate electrode, and one of a pair of contact holes of a second transistor of another pixel adjacent to the pixel are arranged in a Y shape.

[0394] The display device according to any one of (1) to (23), wherein

[0395] the plurality of transistors include a third transistor and a fourth transistor,

[0396] The third transistor includes:

[0397] a third channel formation region in the semiconductor substrate, and

[0398] The fourth transistor includes:

[0399] a fourth channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate.

[0400] The display device according to (25), wherein the fourth transistor includes a second gate electrode, and the second gate electrode includes a second vertical gate portion extending in the film thickness direction of the semiconductor substrate.

[0401] The display device according to (25) or (26), wherein

[0402] the first transistor is a driving transistor electrically connected to a current source and a light-emitting element and supplying a current corresponding to a signal voltage to the light-emitting element,

[0403] the second transistor is a switching transistor electrically connected to the light-emitting element and controlling the light-emitting element not to emit light during a non-light-emitting period,

[0404] the third transistor is a light-emission control transistor electrically connected to the driving transistor and controlling the light-emitting element to emit light, and

[0405] the fourth transistor is a writing transistor electrically connected to the driving transistor and supplying the signal voltage to the driving transistor via a capacitor.

[0406] The display device according to any one of (1) to (27), wherein the light-emitting element is an OLED.

[0407] (29)An electronic device, on which a display device is mounted, wherein,

[0408] The display device includes:

[0409] A plurality of pixels, two-dimensionally arranged in a matrix form on a semiconductor substrate, wherein

[0410] Each pixel includes:

[0411] A light-emitting element, the brightness of which changes according to the provided current; and

[0412] A plurality of transistors, electrically connected to the light-emitting element, the plurality of transistors at least including a first transistor and a second transistor,

[0413] The first transistor includes:

[0414] A first channel formation region in the semiconductor substrate, and

[0415] The second transistor includes:

[0416] A first gate electrode, including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate; and

[0417] A second channel formation region, in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film.

[0418] List of reference numerals

[0419] 10 Display device

[0420] 20, 20a Pixel

[0421] 30 Pixel array unit

[0422] 31 Scan line

[0423] 32, 33 Drive line

[0424] 34 Signal line

[0425] 40 Write scan unit

[0426] 50, 60 Drive scan unit

[0427] 70 Signal output unit

[0428] 80 Display panel

[0429] 100 Semiconductor substrate

[0430] 102, 212, 212c, 232 Gate electrode

[0431] 104 Diffusion region

[0432] 106 Component isolation section

[0433] 200 Wiring layer

[0434] 202, 450 Insulating film

[0435] 204 Wiring

[0436] 206, 214 Through hole

[0437] 212a, 212b, 212d Vertical gate section

[0438] 310, 312 Electrode

[0439] 210, 230 Oxide semiconductor layer

[0440] 210a, 210b Region

[0441] 220, 222 Conductive layer

[0442] 300 Light-emitting unit

[0443] 314 Light-emitting layer

[0444] 400, 402 Groove

[0445] 460 Diffusion region

[0446] 500 Digital camera

[0447] 511 Camera body

[0448] 512 Imaging lens unit

[0449] 513 Grip portion

[0450] 514 Monitor

[0451] 515 Electronic viewfinder

[0452] 600 Head-mounted display

[0453] 611, 802 Display unit

[0454] 612 Ear hook portion

[0455] 630 Glasses

[0456] 631 Lens barrel

[0457] 632 Body

[0458] 633, 643 Arm

[0459] 634 See-through head-mounted display

[0460] 710 TV device

[0461] 711 Video display unit

[0462] 712 Front panel

[0463] 713 Filter glass

[0464] 800 Smart phone

[0465] 901 Driver's seat

[0466] 902 Passenger seat

[0467] 904 Windshield

[0468] 906 Steering wheel

[0469] 907 Center console

[0470] 908 Shift lever

[0471] 911 Center display

[0472] 912 Console display

[0473] 913 Head-up display

[0474] 914 Digital rearview mirror

[0475] 915 Steering wheel display

[0476] 916 Rear entertainment display

[0477] EL light-emitting element

[0478] Tr1, Tr2, Tr3, Tr4 transistors

[0479] C1, C2 capacitors.

Claims

1. A display device, comprising: A plurality of pixels are two-dimensionally arranged in a matrix on a semiconductor substrate, wherein: Each of the pixels comprises: a light emitting element whose brightness varies according to a supplied current; and a plurality of transistors electrically connected to the light emitting element, the plurality of transistors including at least a first transistor and a second transistor, The first transistor comprises: a first channel formation region in the semiconductor substrate, and The second transistor comprises: a first gate electrode including a first vertical gate portion extending in a film thickness direction of the semiconductor substrate; and A second channel formation region is in contact with the first gate electrode via an insulating film in the oxide semiconductor layer stacked over the semiconductor substrate.

2. The display device according to claim 1, wherein: In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate, When the semiconductor substrate is disposed on the lower side, The second transistor is stacked above the first transistor.

3. The display device according to claim 1, wherein: In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate, When the semiconductor substrate is disposed on the lower side, The oxide semiconductor layer has a protruding portion protruding downward along the first vertical gate portion.

4. The display device according to claim 1, wherein: In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate, When the semiconductor substrate is disposed on the lower side, The oxide semiconductor layer has a protruding portion protruding upward along the first vertical gate portion.

5. The display device according to claim 1, wherein: The first gate electrode includes a plurality of the first vertical gate portions.

6. The display device according to claim 1, wherein: The oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc.

7. The display device according to claim 3, wherein: The second transistor includes a source and a drain, and the protruding portion of the oxide semiconductor layer is interposed between the source and the drain.

8. The display device according to claim 7, wherein: A source and a drain of the second transistor include a conductive layer disposed on the oxide semiconductor layer.

9. The display device according to claim 7, wherein: A source and a drain of the second transistor include a conductive layer disposed under the oxide semiconductor layer.

10. The display device according to claim 7, wherein: The source and drain of the second transistor are between two conductive layers.

11. The display device according to claim 8, wherein: The conductive layer is composed of a metal or an alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum.

12. The display device according to claim 7, wherein: The second channel formation region is in contact with a first insulating layer composed of an oxide film that extracts electrons from the surroundings.

13. The display device according to claim 12, wherein: The oxide film includes an oxygen supply film that supplies oxygen to the second channel formation region.

14. The display device according to claim 7, wherein: The source and drain of the second transistor are in contact with a second insulating layer formed of a reducing film that gives out electrons to the surroundings.

15. The display device according to claim 14, wherein: The reducing film includes a hydrogen supply film that supplies hydrogen to the source electrode and the drain electrode.

16. The display device according to claim 14, wherein: The reducing film has a thickness of 20 nm or more.

17. The display device according to claim 1, wherein: The first vertical gate portion has a tubular structure in which a surface facing the second channel formation region is closed.

18. The display device according to claim 1, wherein: The second transistor further includes a third gate electrode facing the first vertical gate portion, and the second channel formation region is interposed between the third gate electrode and the first vertical gate portion.

19. The display device according to claim 7, wherein: When the semiconductor substrate is disposed on the lower side of the cross section, A source and a drain of the second transistor include contact holes contacting an upper surface of the oxide semiconductor layer.

20. The display device according to claim 7, wherein: When the semiconductor substrate is disposed on the lower side of the cross section, A source and a drain of the second transistor include contact holes contacting a lower surface of the oxide semiconductor layer.

21. The display device according to claim 19, wherein: In a plan view of the semiconductor substrate when viewed from above, A pair of the contact holes and the first gate electrode are arranged in a line.

22. The display device according to claim 19, wherein: In a plan view of the semiconductor substrate when viewed from above, A pair of the contact holes and the first gate electrode are arranged in an L shape.

23. The display device according to claim 19, wherein: In a plan view of the semiconductor substrate when viewed from above, A pair of the contact holes and the first gate electrode are arranged in a U shape.

24. The display device according to claim 19, wherein: In a plan view of the semiconductor substrate when viewed from above, The pair of contact holes of the second transistor of the pixel, the first gate electrode, and one of the pair of contact holes of the second transistor of another pixel adjacent to the pixel are arranged in a Y shape.

25. The display device according to claim 1, wherein: The plurality of transistors include a third transistor and a fourth transistor, The third transistor comprises: a third channel formation region in the semiconductor substrate, and The fourth transistor comprises: A fourth channel formation region is stacked in the oxide semiconductor layer over the semiconductor substrate.

26. The display device according to claim 25, wherein: The fourth transistor includes a second gate electrode including a second vertical gate portion extending in a film thickness direction of the semiconductor substrate.

27. The display device according to claim 25, wherein: The first transistor is a driving transistor that is electrically connected to a current source and the light emitting element and supplies a current corresponding to a signal voltage to the light emitting element, The second transistor is a switch transistor electrically connected to the light emitting element and controls the light emitting element not to emit light during a non-light emitting period. The third transistor is a light emission control transistor electrically connected to the driving transistor and controls the light emission of the light emitting element, and The fourth transistor is a write transistor which is electrically connected to the drive transistor and supplies the signal voltage to the drive transistor via a capacitor.

28. The display device according to claim 1, wherein: The light emitting element is an OLED.

29. An electronic device having a display device mounted thereon, wherein: The display device comprises: A plurality of pixels are two-dimensionally arranged in a matrix on a semiconductor substrate, wherein: Each of the pixels comprises: a light emitting element whose brightness varies according to a supplied current; and a plurality of transistors electrically connected to the light emitting element, the plurality of transistors including at least a first transistor and a second transistor, The first transistor comprises: a first channel formation region in the semiconductor substrate, and The second transistor comprises: a first gate electrode including a first vertical gate portion extending in a film thickness direction of the semiconductor substrate; and A second channel formation region is in contact with the first gate electrode via an insulating film in the oxide semiconductor layer stacked over the semiconductor substrate.

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