Pixel circuit, pixel driving circuit and display device

Abstract

The invention provides a pixel circuit, a pixel driving circuit and a display device. The pixel circuit comprises a driving circuit (10), a first light-emitting control circuit (11) and a light-emitting element (E1). The first end of the driving circuit (10) is electrically connected with the second node (N2), the second end of the driving circuit (10) is electrically connected with the first voltage line (V1), and the driving circuit (10) is used for controlling to generate driving current under the control of the potential of the first node (N1); the first light-emitting control circuit (11) is used for controlling the connection or disconnection between the first pole of the light-emitting element (E1) and the second voltage line (V2) under the control of a first light-emitting control signal (EM1); or the first light-emitting control circuit (11) controls the connection or disconnection between the second pole of the light-emitting element (E1) and the second node (N2) under the control of the first light-emitting control signal (EM1). The pixel circuit stabilizes the picture brightness uniformity of the pixel circuit under high and low gray scales by stabilizing the source voltage of a driving transistor included in the driving circuit (10).

Description

Pixel circuit, pixel driving circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving circuit, and a display device. Background Art

[0002] In related technologies, the low-voltage line is routed through the cathode layer. Due to the large cathode resistance, the IR voltage drop of the low-voltage line is large. When the pixel circuit is working, the source voltage of the driving transistor is unstable, causing the display brightness to change.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, comprising a driving circuit, a first light emitting control circuit, and a light emitting element;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the first voltage line, and the driving circuit is used to control the generation of a driving current under the control of the potential of the first node;

[0006] The first pole of the light-emitting element is electrically connected to the second voltage line through the first light-emitting control circuit, and the second pole of the light-emitting element is electrically connected to the second node. The first light-emitting control circuit is used to control the connection or disconnection between the first pole of the light-emitting element and the second voltage line under the control of a first light-emitting control signal provided by the first light-emitting control terminal; or the first pole of the light-emitting element is electrically connected to the second voltage line, and the second pole of the light-emitting element is electrically connected to the second node through the first light-emitting control circuit. The first light-emitting control circuit is used to control the connection or disconnection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal.

[0007] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit;

[0008] The second end of the driving circuit is electrically connected to the first voltage line through the second light emitting control circuit;

[0009] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, and is used to control the connection or disconnection between the second end of the driving circuit and the first voltage line under the control of a second light-emitting control signal provided by the second light-emitting control terminal.

[0010] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit, a second energy storage circuit, a data writing circuit, an on-off control circuit, and a first initialization circuit;

[0011] The second end of the driving circuit is directly electrically connected to the third node;

[0012] A first end of the first energy tank circuit is electrically connected to the third node, a second end of the first energy tank circuit is electrically connected to the fourth node, a first end of the second energy tank circuit is electrically connected to the fourth node, and a second end of the second energy tank circuit is electrically connected to the fifth node, and the first energy tank circuit and the second energy tank circuit are used to store electrical energy;

[0013] The data writing circuit is electrically connected to the scan terminal, the data line and the fifth node respectively, and is used to write the data voltage provided by the data line into the fifth node under the control of the scan signal provided by the scan terminal;

[0014] The on-off control circuit is electrically connected to the second light-emitting control terminal, the first node, and the fifth node, respectively, and is used to control the connection or disconnection between the first node and the fifth node under the control of the second light-emitting control signal;

[0015] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0016] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0017] the second initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the fourth node respectively, and is configured to write the first initial voltage into the fourth node under the control of the first reset control signal; or

[0018] The second initialization circuit is electrically connected to the first reset control terminal, the first node, and the fourth node respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the first reset control signal.

[0019] Optionally, the pixel circuit further includes a third initialization circuit;

[0020] The third initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal.

[0021] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit;

[0022] A first end of the third energy storage circuit is electrically connected to the first voltage line, a second end of the third energy storage circuit is electrically connected to the DC voltage line, and the third energy storage circuit is used to store electrical energy.

[0023] Optionally, the third energy storage circuit includes a third capacitor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0024] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the fourth node;

[0025] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the fifth node;

[0026] A first end of the third capacitor is electrically connected to the first voltage line, and a second end of the third capacitor is electrically connected to the DC voltage line;

[0027] The capacitance value of the third capacitor is smaller than the capacitance value of the first capacitor, and the capacitance value of the third capacitor is smaller than the capacitance value of the second capacitor.

[0028] Optionally, an absolute value of a difference between a voltage value of a second voltage signal provided by the second voltage line and a voltage value of the second initial voltage is smaller than a turn-on voltage of the light-emitting element.

[0029] Optionally, the display cycle of the pixel circuit includes a reset phase and a light emitting phase which are arranged successively; the reset phase includes a setting time period;

[0030] The first light-emitting control circuit is configured to control the connection between the first electrode of the light-emitting element and the second voltage line, or control the connection between the second electrode of the light-emitting element and the second node, under the control of the first light-emitting control signal, during the light-emitting phase;

[0031] The driving circuit is used to control the generation of a driving current in the light-emitting stage to drive the light-emitting element to emit light;

[0032] The third initialization circuit is used to write a second initial voltage into the second node under the control of a second reset control signal during the reset phase.

[0033] The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the set time period.

[0034] Optionally, the display period further includes an initialization phase provided before the reset phase, and a writing phase and a compensation phase provided between the reset phase and the light-emitting phase, wherein the writing phase and the compensation phase are provided successively;

[0035] The first initialization circuit is used to write a first initial voltage into the first node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase, and the compensation phase;

[0036] The on-off control circuit controls the connection between the first node and the fifth node under the control of the second light-emitting control signal during the initialization phase, the reset phase, the writing phase, and the light-emitting phase;

[0037] The data writing circuit is used for writing the data voltage provided by the data line into the fifth node under the control of the scan signal during the writing phase;

[0038] The third initialization circuit is used to write a second initial voltage into the second node under the control of a second reset control signal during the compensation phase.

[0039] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0040] The second initialization circuit is configured to write a first initial voltage into the fourth node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase, and the compensation phase.

[0041] Optionally, the driving circuit includes a driving transistor, and the first light emitting control circuit includes a first light emitting control transistor;

[0042] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the first voltage line;

[0043] The gate of the first light-emitting control transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the first light-emitting control transistor is electrically connected to the second voltage line; or the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first light-emitting control transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first light-emitting control transistor is electrically connected to the second node;

[0044] The first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the data writing circuit includes a writing transistor, the on-off control circuit includes an on-off control transistor, and the first initialization circuit includes a first initialization transistor;

[0045] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the fourth node;

[0046] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the fifth node;

[0047] The gate of the write transistor is electrically connected to the scan end, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the fifth node;

[0048] The gate of the on-off control transistor is electrically connected to the second light emitting control terminal, the first electrode of the on-off control transistor is electrically connected to the first node, and the second electrode of the on-off control transistor is electrically connected to the fifth node;

[0049] A gate of the first initialization transistor is electrically connected to the first reset control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the first node.

[0050] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit, a data writing circuit, and a first initialization circuit;

[0051] The second end of the driving circuit is directly electrically connected to the third node;

[0052] A first end of the first energy storage circuit is electrically connected to the first node, a second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;

[0053] The data writing circuit is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning terminal;

[0054] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0055] Optionally, the pixel circuit further includes a third initialization circuit;

[0056] The third initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal.

[0057] Optionally, the second electrode of the light-emitting element is electrically connected to the second node through the first light-emitting control circuit; the pixel circuit further includes a fourth initialization circuit;

[0058] The fourth initialization circuit is electrically connected to the second reset control terminal, the second electrode of the light-emitting element and the second initial voltage terminal respectively, and is used to write the second initial voltage into the second electrode of the light-emitting element under the control of the second reset control signal.

[0059] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit;

[0060] A first end of the third energy storage circuit is electrically connected to the DC voltage line, a second end of the third energy storage circuit is electrically connected to the third node, and the third energy storage circuit is used to store electrical energy.

[0061] Optionally, the first energy storage circuit includes a first capacitor, and the third energy storage circuit includes a third capacitor;

[0062] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0063] A first end of the third capacitor is electrically connected to the DC voltage line, and a second end of the third capacitor is electrically connected to the third node;

[0064] The capacitance value of the third capacitor is smaller than the capacitance value of the first capacitor.

[0065] Optionally, the first energy storage circuit includes a first capacitor, the data writing circuit includes a writing transistor, and the first initialization circuit includes a first initialization transistor;

[0066] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0067] The gate of the write transistor is electrically connected to the scan end, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the first node;

[0068] A gate of the first initialization transistor is electrically connected to the first reset control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the first node.

[0069] Optionally, an absolute value of a difference between a voltage value of a second voltage signal provided by the second voltage line and a voltage value of the second initial voltage is smaller than a turn-on voltage of the light-emitting element.

[0070] Optionally, the display cycle of the pixel circuit includes a reset phase and a light emitting phase which are arranged successively; the reset phase includes a setting time period;

[0071] The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the reset phase;

[0072] The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the set time period.

[0073] Optionally, the display period further includes an initialization phase provided before the reset phase, and a writing phase and a compensation phase provided between the reset phase and the light-emitting phase, wherein the writing phase and the compensation phase are provided successively;

[0074] The first initialization circuit is used to write a first initial voltage into the first node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase, and the compensation phase;

[0075] The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the compensation phase;

[0076] The data writing circuit is used for writing the data voltage provided by the data line into the first node under the control of the scan signal during the writing phase;

[0077] The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the light-emitting phase.

[0078] In a second aspect, an embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit. The pixel driving method includes:

[0079] The driving circuit controls the generation of a driving current under the control of the potential of the first node;

[0080] The first light-emitting control circuit controls the connection or disconnection between the first pole of the light-emitting element and the second voltage line under the control of the first light-emitting control signal; or, the first light-emitting control circuit controls the connection or disconnection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal.

[0081] In a third aspect, an embodiment of the present disclosure provides a display device comprising a substrate and the above-mentioned pixel circuit disposed on the substrate.

[0082] Optionally, the display device according to at least one embodiment of the present disclosure includes a first voltage line and a plurality of metal layers disposed on the substrate;

[0083] The transistors in the pixel circuit are arranged in the metal layer;

[0084] The first voltage line includes at least a portion formed in the metal layer.

[0085] Optionally, the display device according to at least one embodiment of the present disclosure further includes a first electrode layer, a light-emitting material layer, and a second electrode layer;

[0086] The first electrode layer, the light-emitting material layer, and the second electrode layer are arranged in sequence along a direction in which the metal layer is away from the substrate;

[0087] The first electrode of the light-emitting element is formed on the second electrode layer, and the second electrode of the light-emitting element is formed on the first electrode layer;

[0088] Part of the first voltage line is formed on the first electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] FIG1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure;

[0090] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0092] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0094] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0095] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0096] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0097] FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0098] FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0099] FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0100] FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0101] FIG13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0102] FIG14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0103] FIG15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0104] FIG16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0105] FIG17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0106] FIG18 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG17 ;

[0107] FIG19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0108] FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0109] FIG21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0110] FIG22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0111] FIG23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0112] FIG24 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0113] FIG25 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0114] FIG26 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0115] FIG27 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0116] FIG28 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0117] FIG29 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0118] FIG30 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG29 ;

[0119] FIG31 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0120] FIG32 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0121] FIG33 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0122] FIG34 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0123] FIG35 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0124] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0125] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0126] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0127] The pixel circuit according to the embodiment of the present disclosure includes a driving circuit, a first light emitting control circuit and a light emitting element;

[0128] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the first voltage line, and the driving circuit is used to control the generation of a driving current under the control of the potential of the first node;

[0129] The first pole of the light-emitting element is electrically connected to the second voltage line through the first light-emitting control circuit, and the second pole of the light-emitting element is electrically connected to the second node. The first light-emitting control circuit is used to control the connection or disconnection between the first pole of the light-emitting element and the second voltage line under the control of a first light-emitting control signal provided by the first light-emitting control terminal; or the first pole of the light-emitting element is electrically connected to the second voltage line, and the second pole of the light-emitting element is electrically connected to the second node through the first light-emitting control circuit. The first light-emitting control circuit is used to control the connection or disconnection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal.

[0130] An embodiment of the present disclosure provides a pixel circuit that stabilizes the source voltage of a driving transistor included in the driving circuit to stabilize the brightness uniformity of the pixel circuit at high and low grayscales, thereby improving the brightness unevenness caused by the IR Drop (IR drop) fluctuation of the first voltage line.

[0131] In the embodiment of the present disclosure, the second electrode of the light emitting element is set to be electrically connected to the driving circuit, and the source voltage of the driving transistor is stabilized by inverting the light emitting element.

[0132] Optionally, the first voltage line may be a low voltage line, and the second voltage line may be a high voltage line.

[0133] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 10 , a first light emitting control circuit 11 and a light emitting element E1 ;

[0134] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the first voltage line V1. The driving circuit 10 is configured to control the generation of a driving current under the control of the potential of the first node N1;

[0135] The first electrode of the light-emitting element E1 is electrically connected to the second voltage line V2 through the first light-emitting control circuit 11, and the second electrode of the light-emitting element E1 is electrically connected to the second node N2. The first light-emitting control circuit 11 is also electrically connected to the first light-emitting control terminal EM1. The first light-emitting control circuit 11 is used to control the connection or disconnection between the first electrode of the light-emitting element E1 and the second voltage line V2 under the control of a first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0136] As shown in FIG2 , the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 10 , a first light emitting control circuit 11 and a light emitting element E1 ;

[0137] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the first voltage line V1. The driving circuit 10 is configured to control the generation of a driving current under the control of the potential of the first node N1;

[0138] The first electrode of the light-emitting element E1 is electrically connected to the second voltage line V2, and the second electrode of the light-emitting element E1 is electrically connected to the second node N2 through the first light-emitting control circuit 11. The first light-emitting control circuit 11 is also electrically connected to the first light-emitting control end EM1. The first light-emitting control circuit 11 is used to control the connection or disconnection between the second electrode of the light-emitting element E1 and the second node N2 under the control of the first light-emitting control signal.

[0139] The pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit;

[0140] The second end of the driving circuit is electrically connected to the first voltage line through the second light emitting control circuit;

[0141] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, and is used to control the connection or disconnection between the second end of the driving circuit and the first voltage line under the control of a second light-emitting control signal provided by the second light-emitting control terminal.

[0142] In a specific implementation, the pixel circuit may further include a second light emitting control circuit;

[0143] The second light emitting control circuit controls the connection or disconnection between the second end of the driving circuit and the first voltage line under the control of the second light emitting control signal.

[0144] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit 31 ;

[0145] The second end of the driving circuit 10 is electrically connected to the first voltage line V1 through the second light emitting control circuit 31;

[0146] The second light emitting control circuit 31 is electrically connected to the second light emitting control terminal EM2 and is used to control the connection or disconnection between the second terminal of the driving circuit 10 and the first voltage line V1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2.

[0147] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit 31 ;

[0148] The second end of the driving circuit 10 is electrically connected to the first voltage line V1 through the second light emitting control circuit 31;

[0149] The second light emitting control circuit 31 is electrically connected to the second light emitting control terminal EM2 and is used to control the connection or disconnection between the second terminal of the driving circuit 10 and the first voltage line V1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2.

[0150] The pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit, a second energy storage circuit, a data writing circuit, an on / off control circuit, and a first initialization circuit;

[0151] The second end of the driving circuit is directly electrically connected to the third node;

[0152] A first end of the first energy tank circuit is electrically connected to the third node, a second end of the first energy tank circuit is electrically connected to the fourth node, a first end of the second energy tank circuit is electrically connected to the fourth node, and a second end of the second energy tank circuit is electrically connected to the fifth node, and the first energy tank circuit and the second energy tank circuit are used to store electrical energy;

[0153] The data writing circuit is electrically connected to the scan terminal, the data line and the fifth node respectively, and is used to write the data voltage provided by the data line into the fifth node under the control of the scan signal provided by the scan terminal;

[0154] The on-off control circuit is electrically connected to the second light-emitting control terminal, the first node, and the fifth node, respectively, and is used to control the connection or disconnection between the first node and the fifth node under the control of the second light-emitting control signal;

[0155] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0156] In a specific implementation, the pixel circuit may further include a first energy storage circuit, a second energy storage circuit, a data writing circuit, an on-off control circuit and a first initialization circuit. The data writing circuit writes the data voltage to the fifth node under the control of a scanning signal; the on-off control circuit controls the connection or disconnection between the first node and the fifth node under the control of the second light-emitting control signal; the first initialization circuit writes the first initial voltage to the first node under the control of a first reset control signal to reset the potential of the first node.

[0157] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 51 , a second energy storage circuit 52 , a data writing circuit 53 , an on / off control circuit 54 , and a first initialization circuit 55 ;

[0158] The second end of the driving circuit 10 is directly electrically connected to the third node N3;

[0159] The first end of the first energy storage circuit 51 is electrically connected to the third node N3, and the second end of the first energy storage circuit 51 is electrically connected to the fourth node N4;

[0160] A first end of the second energy storage circuit 52 is electrically connected to the fourth node N4, and a second end of the second energy storage circuit 52 is electrically connected to the fifth node N5;

[0161] The first energy storage circuit 51 and the second energy storage circuit 52 are used to store electrical energy;

[0162] The data writing circuit 53 is electrically connected to the scan terminal G1, the data line DL and the fifth node N5, and is used to write the data voltage Vdata provided by the data line DL into the fifth node N5 under the control of the scan signal provided by the scan terminal G1;

[0163] The on-off control circuit 54 is electrically connected to the second light-emitting control terminal EM2, the first node N1, and the fifth node N5, respectively, and is used to control the connection or disconnection between the first node N1 and the fifth node N5 under the control of the second light-emitting control signal;

[0164] The first initialization circuit 55 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1.

[0165] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG4 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 51 , a second energy storage circuit 52 , a data writing circuit 53 , an on / off control circuit 54 , and a first initialization circuit 55 ;

[0166] The second end of the driving circuit 10 is directly electrically connected to the third node N3;

[0167] A first end of the first energy storage circuit 51 is electrically connected to the third node N3, and a second end of the first energy storage circuit 51 is electrically connected to the fourth node N4;

[0168] A first end of the second energy storage circuit 52 is electrically connected to the fourth node N4, and a second end of the second energy storage circuit 52 is electrically connected to the fifth node N5;

[0169] The first energy storage circuit 51 and the second energy storage circuit 52 are used to store electrical energy;

[0170] The data writing circuit 53 is electrically connected to the scan terminal G1, the data line DL and the fifth node N5, and is used to write the data voltage Vdata provided by the data line DL into the fifth node N5 under the control of the scan signal provided by the scan terminal G1;

[0171] The on-off control circuit 54 is electrically connected to the second light-emitting control terminal EM2, the first node N1, and the fifth node N5, respectively, and is used to control the connection or disconnection between the first node N1 and the fifth node N5 under the control of the second light-emitting control signal;

[0172] The first initialization circuit 55 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1.

[0173] In at least one embodiment of the present disclosure, the pixel circuit further includes a second initialization circuit;

[0174] the second initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the fourth node respectively, and is configured to write the first initial voltage into the fourth node under the control of the first reset control signal; or

[0175] The second initialization circuit is electrically connected to the first reset control terminal, the first node, and the fourth node respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the first reset control signal.

[0176] In a specific implementation, the pixel circuit may further include a second initialization circuit, which, under the control of a first reset control signal, writes a first initial voltage into a fourth node, or controls the connection or disconnection between the first node and the fourth node to reset the potential of the fourth node.

[0177] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 71 ;

[0178] The second initialization circuit 71 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the fourth node N4 respectively, and is configured to write the first initial voltage Vi1 into the fourth node N4 under the control of the first reset control signal.

[0179] As shown in FIG8 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 71 ;

[0180] The second initialization circuit 71 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the fourth node N4 respectively, and is configured to write the first initial voltage Vi1 into the fourth node N4 under the control of the first reset control signal.

[0181] As shown in FIG9 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 71 ;

[0182] The second initialization circuit 71 is electrically connected to the first reset control terminal R1, the first node N1 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal R1.

[0183] As shown in FIG10 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 71 ;

[0184] The second initialization circuit 71 is electrically connected to the first reset control terminal R1, the first node N1 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal R1.

[0185] Optionally, the second node is electrically connected to the first node.

[0186] In a specific implementation, the second node may be electrically connected to the first node, so that the potential of the second node can be reset at the same time as the potential of the first node is reset.

[0187] As shown in FIG11 , based on at least one embodiment of the pixel circuit shown in FIG9 , the second node N2 is electrically connected to the first node N1 .

[0188] As shown in FIG. 12 , based on at least one embodiment of the pixel circuit shown in FIG. 10 , the second node N2 is electrically connected to the first node N1 .

[0189] In at least one embodiment of the present disclosure, the pixel circuit further includes a third initialization circuit;

[0190] The third initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal.

[0191] In a specific implementation, the pixel circuit may further include a third initialization circuit. Under the control of a second reset control signal, the third initialization circuit writes a second initial voltage into the second node to reset the potential of the second node.

[0192] As shown in FIG13 , based on at least one embodiment of the pixel circuit shown in FIG9 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 111 ;

[0193] The third initialization circuit 111 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the second node N2 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the second reset control signal provided by the second reset control terminal R2.

[0194] As shown in FIG14 , based on at least one embodiment of the pixel circuit shown in FIG10 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 111 ;

[0195] The third initialization circuit 111 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the second node N2 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the second reset control signal provided by the second reset control terminal R2.

[0196] The pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit;

[0197] A first end of the third energy storage circuit is electrically connected to the first voltage line, a second end of the third energy storage circuit is electrically connected to the second voltage line, and the third energy storage circuit is used to store electrical energy.

[0198] In a specific implementation, the pixel circuit may further include a third energy storage circuit, which is electrically connected to the first voltage line and the second voltage line respectively, and is used to store electrical energy; the third energy storage circuit can optimize the Data Range (data voltage range) of the pixel circuit to achieve better driving of low grayscale image quality.

[0199] As shown in FIG15 , based on at least one embodiment of the pixel circuit shown in FIG13 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 131 ;

[0200] A first end of the third energy storage circuit 131 is electrically connected to the first voltage line V1 , and a second end of the third energy storage circuit 131 is electrically connected to the second voltage line V2 . The third energy storage circuit 131 is used to store electrical energy.

[0201] As shown in FIG16 , based on at least one embodiment of the pixel circuit shown in FIG14 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 131 ;

[0202] A first end of the third energy storage circuit 131 is electrically connected to the first voltage line V1 , and a second end of the third energy storage circuit 131 is electrically connected to the second voltage line V2 . The third energy storage circuit 131 is used to store electrical energy.

[0203] In at least one embodiment of the present disclosure, the absolute value of the difference between the voltage value of the second voltage signal provided by the second voltage line and the voltage value of the second initial voltage is smaller than the turn-on voltage of the light-emitting element, so that the light-emitting element does not emit light during the set time period.

[0204] Optionally, the third energy storage circuit includes a third capacitor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0205] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the fourth node;

[0206] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the fifth node;

[0207] A first end of the third capacitor is electrically connected to the first voltage line, and a second end of the third capacitor is electrically connected to the DC voltage line;

[0208] The capacitance value of the third capacitor is smaller than the capacitance value of the first capacitor, and the capacitance value of the third capacitor is smaller than the capacitance value of the second capacitor.

[0209] In a specific implementation, the first capacitor and the second capacitor are used to store the threshold voltage of the driving transistor, and the third capacitor is used to optimize the Data Range of the pixel circuit. Therefore, when the space occupied by the pixel circuit is limited, the capacitance value of the first capacitor and the capacitance value of the second capacitor are prioritized. Therefore, the capacitance value of the third capacitor can be set to be smaller than the capacitance value of the first capacitor, and the capacitance value of the third capacitor can be set to be smaller than the capacitance value of the second capacitor.

[0210] In at least one embodiment of the present disclosure, the display cycle of the pixel circuit includes a reset phase and a light-emitting phase arranged successively; the reset phase includes a set time period;

[0211] The first light-emitting control circuit is configured to control the connection between the first electrode of the light-emitting element and the second voltage line, or control the connection between the second electrode of the light-emitting element and the second node, under the control of the first light-emitting control signal, during the light-emitting phase;

[0212] The driving circuit is used to control the generation of a driving current in the light-emitting stage to drive the light-emitting element to emit light;

[0213] The third initialization circuit is used to write a second initial voltage into the second node under the control of a second reset control signal during the reset phase.

[0214] The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the set time period.

[0215] In a specific implementation, during the set time period, the third initialization circuit writes the second initial voltage to the second node under the control of the second reset control signal, and the first light-emitting control circuit controls the connection between the first pole of the light-emitting element and the second voltage line, or controls the connection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal, so as to reset the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element, clear the charge stored in the two poles of the light-emitting element, and during the set time period, control the light-emitting element not to emit light by setting the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element.

[0216] In a specific implementation, the duration of the reset phase may be longer than the duration of the set period, so that the light-emitting element does not emit light during the reset phase.

[0217] In at least one embodiment of the present disclosure, the display period further includes an initialization phase provided before the reset phase, and a writing phase and a compensation phase provided between the reset phase and the light-emitting phase, wherein the writing phase and the compensation phase are provided successively;

[0218] The first initialization circuit is used to write a first initial voltage into the first node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase, and the compensation phase;

[0219] The on-off control circuit controls the connection between the first node and the fifth node under the control of the second light-emitting control signal during the initialization phase, the reset phase, the writing phase, and the light-emitting phase;

[0220] The data writing circuit is used for writing the data voltage provided by the data line into the fifth node under the control of the scan signal during the writing phase;

[0221] The third initialization circuit is used to write a second initial voltage into the second node under the control of a second reset control signal during the compensation phase.

[0222] In at least one embodiment of the present disclosure, the pixel circuit further includes a second initialization circuit;

[0223] The second initialization circuit is configured to write a first initial voltage into the fourth node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase, and the compensation phase.

[0224] In a specific implementation, the display cycle of the pixel circuit may include an initialization phase, a reset phase, a writing phase, a compensation phase and a light emitting phase which are arranged in sequence;

[0225] During the initialization phase, the first initialization circuit writes a first initial voltage to the first node under the control of a first reset control signal, the on-off control circuit controls the connection between the first node and the fifth node under the control of a second light-emitting control signal, and the second initialization circuit writes the first initial voltage to the fourth node under the control of the first reset control signal;

[0226] In the reset phase, the first initialization circuit writes a first initial voltage to the first node under the control of a first reset control signal, the on-off control circuit controls the connection between the first node and the fifth node under the control of a second light-emitting control signal, the second initialization circuit writes the first initial voltage to the fourth node under the control of the first reset control signal, and the third initialization circuit writes the second initial voltage to the second node under the control of the second reset control signal;

[0227] In the write phase, the first initialization circuit writes a first initialization voltage into the first node under the control of the first reset control signal, and the on-off control circuit controls the connection between the first node and the fifth node under the control of the second light-emitting control signal; the data write circuit writes the data voltage provided by the data line into the fifth node under the control of the scan signal; and the second initialization circuit writes the first initialization voltage into the fourth node under the control of the first reset control signal.

[0228] During the compensation phase, the first initialization circuit writes a first initial voltage into the first node under the control of the first reset control signal; the second initialization circuit writes the first initial voltage into the fourth node under the control of the first reset control signal; and the third initialization circuit writes the second initial voltage into the second node under the control of the second reset control signal.

[0229] In the light-emitting stage, the first light-emitting control circuit controls the connection between the first pole of the light-emitting element and the second voltage line, or controls the connection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal; the driving circuit controls the generation of a driving current to drive the light-emitting element to emit light.

[0230] Optionally, the driving circuit includes a driving transistor, and the first light emitting control circuit includes a first light emitting control transistor;

[0231] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the first voltage line;

[0232] The gate of the first light-emitting control transistor is electrically connected to the first light-emitting control end, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the first light-emitting control transistor is electrically connected to the second voltage line; or, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control end, the first electrode of the first light-emitting control transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first light-emitting control transistor is electrically connected to the second node.

[0233] Optionally, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the data writing circuit includes a writing transistor, the on-off control circuit includes an on-off control transistor, and the first initialization circuit includes a first initialization transistor;

[0234] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the fourth node;

[0235] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the fifth node;

[0236] The gate of the write transistor is electrically connected to the scan end, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the fifth node;

[0237] The gate of the on-off control transistor is electrically connected to the second light emitting control terminal, the first electrode of the on-off control transistor is electrically connected to the first node, and the second electrode of the on-off control transistor is electrically connected to the fifth node;

[0238] A gate of the first initialization transistor is electrically connected to the first reset control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the first node.

[0239] As shown in FIG17 , based on at least one embodiment of the pixel circuit shown in FIG13 , the driving circuit includes a driving transistor T3 , the first light emitting control circuit includes a first light emitting control transistor T5 ; the second light emitting control circuit includes a second light emitting control transistor T8 ; and the light emitting element is an organic light emitting diode O1 ;

[0240] The gate of the driving transistor T3 is electrically connected to the first node N1, the drain of the driving transistor T3 is electrically connected to the second node N2, and the source of the driving transistor T3 is electrically connected to the third node N3;

[0241] The gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control terminal EM1, the source of the first light-emitting control transistor T5 is electrically connected to the anode of O1, and the drain of the first light-emitting control transistor T5 is electrically connected to the high voltage line VDD; the cathode of O1 is electrically connected to the second node N2;

[0242] The gate of the second light emitting control transistor T8 is electrically connected to the second light emitting control terminal EM2, the drain of the second light emitting control transistor T8 is electrically connected to the third node N3, and the source of the second light emitting control transistor T8 is electrically connected to the low voltage line VSS;

[0243] The first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, the data writing circuit includes a writing transistor T4, the on-off control circuit includes an on-off control transistor T6, and the first initialization circuit includes a first initialization transistor T2;

[0244] A first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the fourth node N4;

[0245] A first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the fifth node N5;

[0246] The gate of the write transistor T4 is electrically connected to the scan terminal G1, the drain of the write transistor T4 is electrically connected to the data line DL, and the source of the write transistor T4 is electrically connected to the fifth node N5;

[0247] The gate of the on-off control transistor T6 is electrically connected to the second light emitting control terminal EM2, the drain of the on-off control transistor T6 is electrically connected to the first node N1, and the source of the on-off control transistor T6 is electrically connected to the fifth node N5;

[0248] The gate of the first initialization transistor T2 is electrically connected to the first reset control terminal R1, the drain of the first initialization transistor T2 is electrically connected to the first initial voltage terminal I1, and the source of the first initialization transistor T2 is electrically connected to the first node N1;

[0249] The second initialization circuit includes a second initialization transistor T1;

[0250] The gate of the second initialization transistor T1 is electrically connected to the first reset control terminal R1, the drain of the second initialization transistor T1 is electrically connected to the first initial voltage terminal I1, and the source of the second initialization transistor T1 is electrically connected to the fourth node N4;

[0251] The third initialization circuit includes a third initialization transistor T7;

[0252] The gate of the third initialization transistor T7 is electrically connected to the second reset control terminal R2, the drain of the third initialization transistor T7 is electrically connected to the second initial voltage terminal I2, and the source of the third initialization transistor T7 is electrically connected to the second node N2;

[0253] The cathode of O1 is electrically connected to the second node N2.

[0254] In at least one embodiment of the pixel circuit shown in FIG. 17 , all transistors are n-type transistors, and the pixel circuit is an oxide pixel circuit.

[0255] In at least one embodiment of the pixel circuit shown in FIG17 , the voltage value of Vi1 may be greater than or equal to 0V and less than or equal to 6V;

[0256] The absolute value of the difference between the voltage value of the high voltage signal provided by VDD and the voltage value of the second initial voltage Vi2 is smaller than the turn-on voltage of O1 , so that O1 does not emit light during the set period.

[0257] In at least one embodiment of the pixel circuit shown in FIG. 17 , T3 may be a dual-gate transistor, a first gate of T3 is electrically connected to the first node N1 , and a second gate of T3 is electrically connected to the source of T3 .

[0258] In at least one embodiment of the pixel circuit shown in FIG. 17 , the capacitance value of C1 is greater than the capacitance value of C3 , and the capacitance value of C2 is greater than the capacitance value of C3 .

[0259] As shown in FIG18 , when at least one embodiment of the pixel circuit shown in FIG17 of the present disclosure is in operation, a display cycle may include an initialization phase S1, a reset phase S2, a writing phase S3, a compensation phase S4, and a light-emitting phase S5, which are arranged in sequence; the reset phase S2 includes a set time period S21;

[0260] In the initialization phase S1, EM2 provides a high voltage signal, EM1 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a low voltage signal, G1 provides a low voltage signal, T6 and T8 are turned on, and T1 and T2 are turned on to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1, the fourth node N4, and the fifth node N5;

[0261] In the reset phase S2, EM2 provides a high voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, T6 and T8 are turned on, T1 and T2 are turned on, and T7 is turned on, so as to write Vi1 into the first node N1, the fourth node N4, and the fifth node N5, and write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the second node N2;

[0262] In the set period S21, EM1 provides a high voltage signal, T5 is turned on, so as to control the anode of O1 to be electrically connected to the high voltage line VDD, so as to reset the anode potential of O1;

[0263] In the write phase S3, EM2 provides a high voltage signal, EM1 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a low voltage signal, G1 provides a high voltage signal, DL provides a data voltage Vdata, T4 is turned on, T6 is turned on, to write the data voltage Vdata into the fifth node N5; T1 and T2 are turned on; T8 is turned on;

[0264] In the compensation phase S4, EM2 provides a low voltage signal, EM1 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, T8 is disconnected, T2 is turned on, T1 is turned on, T7 is turned on, and Vi2 charges C1 and C2 to control the potential of N3 to become Vi1-Vth for threshold voltage compensation; Vth is the threshold voltage of T3;

[0265] In the light-emitting stage S5, EM2 provides a high voltage signal, EM1 provides a high voltage signal, R1 provides a low voltage signal, R2 provides a low voltage signal, G1 provides a low voltage signal, T5 and T8 are turned on, and T6 is turned on, so that the potential of N1 is Vdata, and the gate-source voltage of T3 is Vdata-Vi1+Vth. Then the current value of the driving current flowing through O1 is K×(Vdata-Vi1) 2 ; K is the current coefficient of T3.

[0266] As shown in Figure 18, when at least one embodiment of the pixel circuit shown in Figure 17 of the present disclosure is in operation, in the set time period S21, T5 is turned on, T7 is turned on, the anode of O1 is connected to VDD, and the cathode of O1 is electrically connected to I2 to clear the residual charge at the two poles of O1, and the absolute value of the difference between the voltage value of the high voltage signal provided by VDD and the voltage value of the second initial voltage Vi2 is set to be less than the turn-on voltage of O1, so that O1 does not emit light during the set time period.

[0267] As shown in FIG. 18 , the duration of the reset phase S2 may be longer than the duration of the set period S21 , so that when the reset phase S2 begins, T5 is not turned on to prevent O1 from emitting light.

[0268] The difference between at least one embodiment of the pixel circuit shown in FIG19 and at least one embodiment of the pixel circuit shown in FIG17 is that:

[0269] The drain of T1 is electrically connected to the first node N1.

[0270] The difference between at least one embodiment of the pixel circuit shown in FIG. 20 and at least one embodiment of the pixel circuit shown in FIG. 19 is that T8 is not included.

[0271] The difference between at least one embodiment of the pixel circuit shown in FIG. 21 and at least one embodiment of the pixel circuit shown in FIG. 17 is that T8 is not included.

[0272] The difference between at least one embodiment of the pixel circuit shown in FIG. 22 and at least one embodiment of the pixel circuit shown in FIG. 21 lies in that T7 is not included; and the first node N1 is electrically connected to the second node N2.

[0273] The difference between at least one embodiment of the pixel circuit shown in FIG23 and at least one embodiment of the pixel circuit shown in FIG21 is that: a third energy storage circuit is further included;

[0274] The third energy storage circuit includes a third capacitor C3;

[0275] A first end of the third capacitor C3 is electrically connected to the low voltage line VSS, and a second end of the third capacitor C3 is electrically connected to the high voltage line VDD.

[0276] The pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit, a data writing circuit and a first initialization circuit;

[0277] The second end of the driving circuit is directly electrically connected to the third node;

[0278] A first end of the first energy storage circuit is electrically connected to the first node, a second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;

[0279] The data writing circuit is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning terminal;

[0280] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0281] In a specific implementation, the pixel circuit may include a first energy storage circuit, a data writing circuit and a first initialization circuit; the data writing circuit writes the data voltage into the first node under the control of a scanning signal; the first initialization circuit writes the first initial voltage into the first node under the control of a first reset control signal to reset the potential of the first node.

[0282] Optionally, the first node is electrically connected to the second node.

[0283] In a specific implementation, the first node may be directly electrically connected to the second node, so that the potential of the second node is reset while the potential of the first node is reset.

[0284] In at least one embodiment of the present disclosure, the pixel circuit further includes a third initialization circuit;

[0285] The third initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal.

[0286] In a specific implementation, the pixel circuit may include a third initialization circuit, and the third initialization circuit writes the second initial voltage into the second node under the control of the second reset control signal.

[0287] Optionally, the second electrode of the light-emitting element is electrically connected to the second node through the first light-emitting control circuit; the pixel circuit further includes a fourth initialization circuit;

[0288] The fourth initialization circuit is electrically connected to the second reset control terminal, the second electrode of the light-emitting element and the second initial voltage terminal respectively, and is used to write the second initial voltage into the second electrode of the light-emitting element under the control of the second reset control signal.

[0289] In a specific implementation, the pixel circuit may further include a fourth initialization circuit, which writes a second initial voltage into the second electrode of the light-emitting element under the control of a second reset control signal.

[0290] The pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit;

[0291] A first end of the third energy storage circuit is electrically connected to the DC voltage line, a second end of the third energy storage circuit is electrically connected to the third node, and the third energy storage circuit is used to store electrical energy.

[0292] In a specific implementation, the pixel circuit may further include a third energy storage circuit, which is electrically connected to the second voltage line and the third node, respectively, and is used to store electrical energy; the third energy storage circuit can optimize the Data Range (data voltage range) of the pixel circuit to achieve better driving of low grayscale image quality.

[0293] Optionally, the DC voltage line may be a second voltage line or a first voltage line, but is not limited thereto. In a specific implementation, the DC voltage line may also be other types of DC voltage lines.

[0294] Optionally, the first energy storage circuit includes a first capacitor, and the third energy storage circuit includes a third capacitor;

[0295] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0296] A first end of the third capacitor is electrically connected to the DC voltage line, and a second end of the third capacitor is electrically connected to the third node;

[0297] The capacitance value of the third capacitor is smaller than the capacitance value of the first capacitor.

[0298] In a specific implementation, the first capacitor is used to store the threshold voltage of the driving transistor, and the third capacitor is used to optimize the Data Range of the pixel circuit. Therefore, when the space occupied by the pixel circuit is limited, the capacitance value of the first capacitor is prioritized, so the capacitance value of the third capacitor can be set to be smaller than the capacitance value of the first capacitor.

[0299] As shown in FIG24 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 51 , a data writing circuit 53 , a first initialization circuit 55 , and a third initialization circuit 56 ;

[0300] The second end of the driving circuit 10 is directly electrically connected to the third node N3;

[0301] A first end of the first energy storage circuit 51 is electrically connected to the first node N1, a second end of the first energy storage circuit 51 is electrically connected to the third node N3, and the first energy storage circuit 51 is used to store electrical energy;

[0302] The data writing circuit 53 is electrically connected to the scan terminal G1, the data line DL and the first node N1 respectively, and is used to write the data voltage Vdata provided by the data line DL into the first node N1 under the control of the scan signal provided by the scan terminal G1;

[0303] The first initialization circuit 55 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1;

[0304] The third initialization circuit 56 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the second node N2, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the second reset control signal provided by the second reset control terminal R2.

[0305] As shown in FIG25 , based on at least one embodiment of the pixel circuit shown in FIG4 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 51 , a data writing circuit 53 , a first initialization circuit 55 , and a third initialization circuit 56 ;

[0306] The second end of the driving circuit 10 is directly electrically connected to the third node N3;

[0307] A first end of the first energy storage circuit 51 is electrically connected to the first node N1, a second end of the first energy storage circuit 51 is electrically connected to the third node N3, and the first energy storage circuit 51 is used to store electrical energy;

[0308] The data writing circuit 53 is electrically connected to the scan terminal G1, the data line DL and the first node N1 respectively, and is used to write the data voltage Vdata provided by the data line DL into the first node N1 under the control of the scan signal provided by the scan terminal G1;

[0309] The first initialization circuit 55 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1;

[0310] The third initialization circuit 56 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the second node N2, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the second reset control signal provided by the second reset control terminal R2.

[0311] As shown in FIG26 , based on at least one embodiment of the pixel circuit shown in FIG25 , the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth initialization circuit 241 ;

[0312] The fourth initialization circuit 241 is electrically connected to the second reset control terminal R2, the second electrode of the light-emitting element E1 and the second initial voltage terminal I2 respectively, and is used to write the second initial voltage Vi2 into the second electrode of the light-emitting element E1 under the control of the second reset control signal.

[0313] The difference between at least one embodiment of the pixel circuit shown in FIG27 and at least one embodiment of the pixel circuit shown in FIG24 is as follows:

[0314] The third initialization circuit 56 is not included;

[0315] The first node N1 is electrically connected to the second node N2.

[0316] As shown in FIG28 , based on at least one embodiment of the pixel circuit shown in FIG26 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 131 ;

[0317] A first end of the third energy storage circuit 131 is electrically connected to the first voltage line V1 , a second end of the third energy storage circuit 131 is electrically connected to the third node N3 , and the third energy storage circuit 131 is used to store electrical energy.

[0318] Optionally, the first energy storage circuit includes a first capacitor, the data writing circuit includes a writing transistor, and the first initialization circuit includes a first initialization transistor;

[0319] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0320] The gate of the write transistor is electrically connected to the scan end, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the first node;

[0321] A gate of the first initialization transistor is electrically connected to the first reset control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the first node.

[0322] In at least one embodiment of the present disclosure, the absolute value of the difference between the voltage value of the second voltage signal provided by the second voltage line and the voltage value of the second initial voltage is smaller than the turn-on voltage of the light-emitting element, so that the light-emitting element does not emit light during the reset phase.

[0323] In at least one embodiment of the present disclosure, the display cycle of the pixel circuit includes a reset phase and a light emitting phase arranged successively; the reset phase includes a set time period;

[0324] The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the reset phase;

[0325] The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the set time period.

[0326] In a specific implementation, during the set time period, the third initialization circuit writes the second initial voltage to the second node under the control of the second reset control signal, and the first light-emitting control circuit controls the connection between the first pole of the light-emitting element and the second voltage line, or controls the connection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal, so as to reset the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element, clear the charge stored in the two poles of the light-emitting element, and during the set time period, by setting the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element, control the light-emitting element not to emit light.

[0327] In at least one embodiment of the present disclosure, the duration of the reset phase is longer than the duration of the set period, so that the light-emitting element does not emit light during the reset phase.

[0328] In at least one embodiment of the present disclosure, the display period further includes an initialization phase provided before the reset phase, and a writing phase and a compensation phase provided between the reset phase and the light-emitting phase, wherein the writing phase and the compensation phase are provided successively;

[0329] The first initialization circuit is used to write a first initial voltage into the first node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase, and the compensation phase;

[0330] The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the compensation phase;

[0331] The data writing circuit is used for writing the data voltage provided by the data line into the first node under the control of the scan signal during the writing phase;

[0332] The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the light-emitting phase.

[0333] As shown in FIG29 , based on at least one embodiment of the pixel circuit shown in FIG24 , the driving circuit includes a driving transistor T3 , the first light emitting control circuit includes a first light emitting control transistor T5 , the second light emitting control circuit includes a second light emitting control transistor T8 , and the light emitting element is an organic light emitting diode O1 ;

[0334] The gate of the driving transistor T3 is electrically connected to the first node N1, the drain of the driving transistor T3 is electrically connected to the second node N2, and the source of the driving transistor T3 is electrically connected to the third node N3;

[0335] The gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control terminal EM1, the source of the first light-emitting control transistor T5 is electrically connected to the anode of O1, and the drain of the first light-emitting control transistor T5 is electrically connected to the high voltage line VDD; the cathode of O1 is electrically connected to the second node N2;

[0336] The gate of the second light emitting control transistor T8 is electrically connected to the second light emitting control terminal EM2, the drain of the second light emitting control transistor T8 is electrically connected to the third node N3, and the source of the second light emitting control transistor T8 is electrically connected to the low voltage line VSS;

[0337] The first energy storage circuit includes a first capacitor C1, the data writing circuit includes a data writing transistor T4, the first initialization circuit includes a first initialization transistor T2, and the third initialization circuit board includes a third initialization transistor T7;

[0338] A first terminal of C1 is electrically connected to a first node N1, and a second terminal of C1 is electrically connected to a third node N3;

[0339] The gate of T4 is electrically connected to the scan terminal G1, the drain of T4 is electrically connected to the data line DL, and the source of T4 is electrically connected to the first node N1;

[0340] The gate of T2 is electrically connected to the first reset control terminal R1, the drain of T2 is electrically connected to the first initial voltage terminal I1, and the source of T2 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0341] The gate of T7 is electrically connected to the second reset control terminal R2, the drain of T7 is electrically connected to the second initial voltage terminal I2, and the source of T7 is electrically connected to the second node N2; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2.

[0342] In at least one embodiment of the pixel circuit shown in FIG. 29 , all transistors are n-type transistors, and the pixel circuit is an oxide pixel circuit.

[0343] In at least one embodiment of the pixel circuit shown in FIG29 , the voltage value of Vi1 may be greater than or equal to 0V and less than or equal to 6V;

[0344] The absolute value of the difference between the voltage value of the high voltage signal provided by VDD and the voltage value of the second initial voltage Vi2 is smaller than the turn-on voltage of O1 , so that O1 does not emit light during the set period.

[0345] In at least one embodiment of the pixel circuit shown in FIG. 29 , T3 may be a dual-gate transistor, a first gate of T3 is electrically connected to the first node N1 , and a second gate of T3 is electrically connected to the source of T3 .

[0346] In at least one embodiment of the pixel circuit shown in FIG. 29 , the capacitance value of C1 is greater than the capacitance value of C3 .

[0347] As shown in FIG30 , when at least one embodiment of the pixel circuit shown in FIG29 of the present disclosure is in operation, a display cycle may include an initialization phase S1, a reset phase S2, a writing phase S3, a compensation phase S4, and a light-emitting phase S5, which are arranged in sequence; the reset phase S2 includes a setting period S21;

[0348] In the initialization phase S1, EM2 provides a low voltage signal, EM1 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a low voltage signal, G1 provides a low voltage signal, and T2 is turned on to write Vi1 into the first node N1;

[0349] In the reset phase S2, EM2 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, T2 is turned on to write Vi1 to the first node N1, and T7 is turned on to write Vi2 to the second node N2;

[0350] In the set period S21, EM1 provides a high voltage signal and T5 is turned on to control the connection between the high voltage line VDD and the anode of O1;

[0351] In the writing phase S3, EM2 provides a low voltage signal, EM1 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a low voltage signal, G1 provides a high voltage signal, T2 is turned on to write Vi1 into the first node N1, T4 is turned on, DL provides a data voltage Vdata, and the data voltage Vdata is written into the first node N1;

[0352] In the compensation phase S4, EM2 provides a low voltage signal, EM1 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, T2 is turned on to write Vi1 into the first node N1, T7 is turned on to charge C1 through Vi2 until the potential of N3 is Vi1-Vth, where Vth is the threshold voltage of T3;

[0353] In the light-emitting stage S5, EM2 provides a high voltage signal, EM1 provides a high voltage signal, R1 provides a low voltage signal, R2 provides a low voltage signal, G1 provides a low voltage signal, T5 and T8 are turned on, T3 drives O1 to emit light, T6 is turned on to write Vdata into the first node N1, the gate-source voltage of T3 is Vdata-Vi1+Vth, and the current value of the driving current flowing through O1 is K×(Vdata-Vi1) 2 ; K is the current coefficient of T3.

[0354] As shown in Figure 30, when at least one embodiment of the pixel circuit shown in Figure 29 of the present disclosure is in operation, in the set time period S21, T5 is turned on, T7 is turned on, the anode of O1 is connected to VDD, and the cathode of O1 is electrically connected to I2 to clear the residual charge at the two poles of O1, and the absolute value of the difference between the voltage value of the high voltage signal provided by VDD and the voltage value of the second initial voltage Vi2 is set to be less than the turn-on voltage of O1, so that O1 does not emit light during the set time period.

[0355] As shown in FIG30 , the duration of the reset phase S2 may be longer than the duration of the set period S21 , so that at the beginning of the reset phase S2 , T5 is not turned on to prevent O1 from emitting light.

[0356] The difference between at least one embodiment of the pixel circuit shown in FIG. 31 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 29 of the present disclosure is that T8 is not included.

[0357] The difference between at least one embodiment of the pixel circuit shown in FIG32 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG29 of the present disclosure is that: a fourth initialization circuit is further included;

[0358] The fourth initialization circuit includes a fourth initialization transistor T0;

[0359] The gate of T0 is electrically connected to the second reset control terminal R2, the drain of T0 is electrically connected to the cathode of O1, and the source of T0 is electrically connected to the second initial voltage terminal I2;

[0360] The second initial voltage terminal I2 is used to provide a second initial voltage Vi2.

[0361] The difference between at least one embodiment of the pixel circuit shown in FIG33 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG31 of the present disclosure is that the first node N1 is electrically connected to the second node N2.

[0362] The difference between at least one embodiment of the pixel circuit shown in FIG34 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG32 of the present disclosure is that: a third energy storage circuit is further included;

[0363] The third energy storage circuit includes a third capacitor C3;

[0364] A first end of the third capacitor C3 is electrically connected to the high voltage line VDD, and a second end of the third capacitor C3 is electrically connected to the third node N3.

[0365] The difference between at least one embodiment of the pixel circuit shown in FIG. 35 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 34 of the present disclosure is that:

[0366] A first end of C3 is electrically connected to the low voltage line VSS, and a second end of C3 is electrically connected to the third node N3.

[0367] The pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the pixel driving method includes:

[0368] The driving circuit controls the generation of a driving current under the control of the potential of the first node;

[0369] The first light-emitting control circuit controls the connection or disconnection between the first pole of the light-emitting element and the second voltage line under the control of the first light-emitting control signal; or, the first light-emitting control circuit controls the connection or disconnection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal.

[0370] The display device described in the embodiment of the present disclosure includes a substrate and the above-mentioned pixel circuit arranged on the substrate.

[0371] The display device according to at least one embodiment of the present disclosure includes a first voltage line and a plurality of metal layers disposed on the substrate;

[0372] The transistors in the pixel circuit are arranged in the metal layer;

[0373] The first voltage line includes at least a portion formed in the metal layer.

[0374] In at least one embodiment of the present disclosure, the first voltage line may be a low voltage line, and the second voltage line may be a high voltage line, but the present invention is not limited thereto.

[0375] In related art, low-voltage lines are routed through the cathode layer. Due to the high cathode resistance, this leads to a large IR drop across the low-voltage line. This can cause instability in the source voltage of the drive transistor during pixel circuit operation, leading to variations in display brightness. In at least one embodiment of the present disclosure, at least a portion of the first voltage line is formed in a metal layer to reduce the resistance of the first voltage line and, therefore, the IR drop across the first voltage line.

[0376] The display device according to at least one embodiment of the present disclosure further includes a first electrode layer, a light-emitting material layer, and a second electrode layer;

[0377] The first electrode layer, the light-emitting material layer, and the second electrode layer are arranged in sequence along a direction in which the metal layer is away from the substrate;

[0378] The first electrode of the light-emitting element is formed on the second electrode layer, and the second electrode of the light-emitting element is formed on the first electrode layer;

[0379] Part of the first voltage line is formed on the first electrode layer.

[0380] In a specific implementation, the display device may include a first electrode layer, a light-emitting material layer, and a second electrode layer, wherein the first electrode layer, the light-emitting material layer, and the second electrode layer are arranged in sequence along the direction in which the metal layer is away from the substrate. In at least one embodiment of the present disclosure, the light-emitting element may be reversed, and the setting position of the first voltage line and the setting position of the second voltage line may be swapped, that is, a portion of the first voltage line is set in the first electrode layer, a portion of the first voltage line may be set in at least one of the gate metal layer, the first source and drain metal layer, and the second metal layer, the second voltage line is set in the second electrode layer, and the first pole of the light-emitting element is set in the second electrode layer, and the second pole of the light-emitting element is set in the first electrode layer. By transposing the pixels, the first voltage line is used for in-plane routing, the voltage fluctuation of the first voltage signal is reduced, and the screen uniformity of the pixel circuit is improved.

[0381] In at least one embodiment of the present disclosure, the first electrode layer may be provided as a whole layer, and the second electrode layer may include a plurality of mutually independent electrode patterns.

[0382] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a first light emitting control circuit and a light emitting element; The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the first voltage line, and the driving circuit is used to control the generation of a driving current under the control of the potential of the first node; The first pole of the light-emitting element is electrically connected to the second voltage line through the first light-emitting control circuit, and the second pole of the light-emitting element is electrically connected to the second node. The first light-emitting control circuit is used to control the connection or disconnection between the first pole of the light-emitting element and the second voltage line under the control of a first light-emitting control signal provided by the first light-emitting control terminal; or, the first pole of the light-emitting element is electrically connected to the second voltage line, and the second pole of the light-emitting element is electrically connected to the second node through the first light-emitting control circuit. The first light-emitting control circuit is used to control the connection or disconnection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal.

2. The pixel circuit according to claim 1, wherein: Also includes a second light emitting control circuit; The second end of the driving circuit is electrically connected to the first voltage line through the second light emitting control circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, and is used to control the connection or disconnection between the second end of the driving circuit and the first voltage line under the control of a second light-emitting control signal provided by the second light-emitting control terminal.

3. The pixel circuit according to claim 1 or 2, wherein: It also includes a first energy storage circuit, a second energy storage circuit, a data writing circuit, an on-off control circuit and a first initialization circuit; The second end of the driving circuit is directly electrically connected to the third node; The first end of the first energy tank circuit is electrically connected to the third node, the second end of the first energy tank circuit is electrically connected to the fourth node, the first end of the second energy tank circuit is electrically connected to the fourth node, the second end of the second energy tank circuit is electrically connected to the fifth node, and the first energy tank circuit and the second energy tank circuit are used to store electrical energy; The data writing circuit is electrically connected to the scanning end, the data line and the fifth node respectively, and is used to write the data voltage provided by the data line into the fifth node under the control of the scanning signal provided by the scanning end; The on-off control circuit is electrically connected to the second light-emitting control terminal, the first node and the fifth node respectively, and is used to control the connection or disconnection between the first node and the fifth node under the control of the second light-emitting control signal; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

4. The pixel circuit according to claim 3, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the fourth node respectively, and is used to write the first initial voltage into the fourth node under the control of the first reset control signal; or, The second initialization circuit is electrically connected to the first reset control terminal, the first node and the fourth node respectively, and is used to control the connection between the first node and the fourth node under the control of the first reset control signal. or disconnect.

5. The pixel circuit according to claim 4, wherein: The pixel circuit further includes a third initialization circuit; The third initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal.

6. The pixel circuit according to claim 4, wherein: Also included is a third tank circuit; A first end of the third energy storage circuit is electrically connected to the first voltage line, a second end of the third energy storage circuit is electrically connected to the second voltage line, and the third energy storage circuit is used to store electrical energy.

7. The pixel circuit according to claim 6, wherein: The third energy tank circuit includes a third capacitor, the first energy tank circuit includes a first capacitor, and the second energy tank circuit includes a second capacitor; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the fourth node; The first end of the second capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the first voltage line, and a second end of the third capacitor is electrically connected to the second voltage line; The capacitance value of the third capacitor is smaller than the capacitance value of the first capacitor, and the capacitance value of the third capacitor is smaller than the capacitance value of the second capacitor.

8. The pixel circuit according to claim 5, wherein: An absolute value of a difference between a voltage value of a second voltage signal provided by the second voltage line and a voltage value of the second initial voltage is smaller than a turn-on voltage of the light emitting element.

9. The pixel circuit according to claim 5, wherein: The display cycle of the pixel circuit includes a reset phase and a light emitting phase which are arranged successively; the reset phase includes a setting time period; The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the light-emitting stage; The driving circuit is used to control the generation of a driving current in the light-emitting stage to drive the light-emitting element to emit light; The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the reset phase. The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the set time period.

10. The pixel circuit according to claim 9, wherein: The display cycle also includes an initialization phase arranged before the reset phase, and a writing phase and a compensation phase arranged between the reset phase and the light-emitting phase, wherein the writing phase and the compensation phase are arranged successively; The first initialization circuit is used for the initialization phase, the reset phase, the write phase and the compensation phase. In the compensation stage, under the control of the first reset control signal, a first initial voltage is written into the first node; The on-off control circuit controls the connection between the first node and the fifth node under the control of the second light-emitting control signal during the initialization stage, the reset stage, the writing stage and the light-emitting stage; The data writing circuit is used for writing the data voltage provided by the data line into the fifth node under the control of the scanning signal during the writing phase; The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the compensation phase.

11. The pixel circuit according to claim 10, further comprising a second initialization circuit; The second initialization circuit is used for writing a first initial voltage into a fourth node under the control of a first reset control signal during the initialization phase, the reset phase, the write phase and the compensation phase.

12. The pixel circuit according to claim 3, wherein: The driving circuit includes a driving transistor, and the first light emitting control circuit includes a first light emitting control transistor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the first voltage line; The gate of the first light-emitting control transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the first light-emitting control transistor is electrically connected to the second voltage line; or, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first light-emitting control transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first light-emitting control transistor is electrically connected to the second node; the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the data writing circuit includes a writing transistor, the on-off control circuit includes an on-off control transistor, and the first initialization circuit includes a first initialization transistor; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the fourth node; The first end of the second capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the fifth node; The gate of the write transistor is electrically connected to the scan end, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the fifth node; The gate of the on-off control transistor is electrically connected to the second light emitting control terminal, the first electrode of the on-off control transistor is electrically connected to the first node, and the second electrode of the on-off control transistor is electrically connected to the fifth node; A gate of the first initialization transistor is electrically connected to the first reset control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the first node.

13. The pixel circuit according to claim 1 or 2, wherein: Also includes a first energy storage circuit, a data writing circuit and a first initialization circuit; The second end of the driving circuit is directly electrically connected to the third node; A first end of the first energy storage circuit is electrically connected to the first node, a second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy; The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

14. The pixel circuit according to claim 13, wherein: The pixel circuit further includes a third initialization circuit; The third initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal.

15. The pixel circuit according to claim 14, wherein: The second electrode of the light emitting element is electrically connected to the second node through the first light emitting control circuit; the pixel circuit further includes a fourth initialization circuit; The fourth initialization circuit is electrically connected to the second reset control terminal, the second electrode of the light emitting element and the second initial voltage terminal respectively, and is used to write the second initial voltage into the second electrode of the light emitting element under the control of the second reset control signal.

16. The pixel circuit according to claim 13, wherein: Also included is a third tank circuit; A first end of the third energy storage circuit is electrically connected to the DC voltage line, a second end of the third energy storage circuit is electrically connected to the third node, and the third energy storage circuit is used to store electrical energy.

17. The pixel circuit according to claim 16, wherein: The first energy storage circuit includes a first capacitor, and the third energy storage circuit includes a third capacitor; The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the third node; A first end of the third capacitor is electrically connected to the DC voltage line, and a second end of the third capacitor is electrically connected to the third node; The capacitance value of the third capacitor is smaller than the capacitance value of the first capacitor.

18. The pixel circuit according to claim 13, wherein: The first energy storage circuit includes a first capacitor, the data writing circuit includes a writing transistor, and the first initialization circuit includes a first initialization transistor; The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the third node; The gate of the write transistor is electrically connected to the scan end, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the first node; A gate of the first initialization transistor is electrically connected to the first reset control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the first node.

19. The pixel circuit according to claim 14, wherein: An absolute value of a difference between a voltage value of a second voltage signal provided by the second voltage line and a voltage value of the second initial voltage is smaller than a turn-on voltage of the light emitting element.

20. The pixel circuit according to claim 14, wherein: The display cycle of the pixel circuit includes a reset phase and a light emitting phase which are arranged successively; the reset phase includes a setting time period; The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the reset phase; The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the set time period.

21. The pixel circuit according to claim 20, wherein: The display cycle also includes an initialization phase arranged before the reset phase, and a writing phase and a compensation phase arranged between the reset phase and the light-emitting phase, wherein the writing phase and the compensation phase are arranged successively; The first initialization circuit is used for writing a first initial voltage into the first node under the control of a first reset control signal during the initialization stage, the reset stage, the write stage and the compensation stage; The third initialization circuit is used for writing a second initial voltage into the second node under the control of a second reset control signal during the compensation phase; The data writing circuit is used for writing the data voltage provided by the data line into the first node under the control of the scanning signal during the writing phase; The first light-emitting control circuit is used to control the connection between the first electrode of the light-emitting element and the second voltage line, or to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal during the light-emitting stage.

22. A pixel driving method, applied to the pixel circuit according to any one of claims 1 to 21, the pixel driving method comprising: The driving circuit controls the generation of a driving current under the control of the potential of the first node; The first light-emitting control circuit controls the connection or disconnection between the first pole of the light-emitting element and the second voltage line under the control of the first light-emitting control signal; or, the first light-emitting control circuit controls the connection or disconnection between the second pole of the light-emitting element and the second node under the control of the first light-emitting control signal.

23. A display device comprising a substrate and the pixel circuit according to any one of claims 1 to 21 arranged on the substrate.

24. The display device according to claim 23, wherein: comprising a first voltage line and a plurality of metal layers disposed on the substrate; The transistor in the pixel circuit is arranged in the metal layer; The first voltage line includes at least a portion formed in the metal layer.

25. The display device according to claim 24, wherein: Also includes a first electrode layer, a light emitting material layer, and a second electrode layer; The first electrode layer, the light-emitting material layer and the second electrode layer are arranged in sequence along a direction in which the metal layer is away from the substrate; A first electrode of the light emitting element is formed on the second electrode layer, and a second electrode of the light emitting element is formed on the first electrode layer; Part of the first voltage line is formed on the first electrode layer.

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