Shift register unit, gate drive circuit and control method

Abstract

A shift register unit (200, 300) and a control method thereof, and a gate drive circuit (400). The shift register unit (200, 300) includes at least one of a first adjustment circuit (250, 350) and a second adjustment circuit (260, 360), an input circuit (210, 310), a first control circuit (220, 320), a second control circuit (230, 330), and an output circuit (240, 340). An input circuit (210, 310) is used to provide a signal to a first pull-down node (QB1) and a first pull-up node (Q1). The first control circuits (220, 320) are used for controlling signals of the first pull-up node (Q1) and the first pull-down node (QB1). The second control circuit (230, 330) is used for controlling signals of the second pull-down node (QB2) and the second pull-up node (Q2). And the output circuit (240, 340) is used for providing a signal of one of the clock signal end (GCK) and the reference signal end (VGL) to the output signal end (GOUT) under the control of the second pull-down node (QB2) and the second pull-up node (Q2). A first adjustment circuit (250, 350) is connected to the first pull-down node (QB1) and the second control circuit (230, 330). A second adjustment circuit (260, 360) is connected to the second pull-down node (QB2) and the output circuit (240, 340).

Description

Shift register unit, gate drive circuit and control method Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit, and a control method for the shift register unit. Background Art

[0002] In the display field, gate drive circuits provide drive signals to sub-pixels, which, under the control of the drive signals, emit light based on data signals, thereby achieving image display. However, in display devices, particularly organic light-emitting diode (OLED) displays, the output signals of the shift registers in the gate drive circuits are often unstable for various reasons, thus affecting the display quality.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides a shift register unit, comprising:

[0005] an input circuit connected to an input signal terminal, a reference signal terminal, a first pull-down node, and a first pull-up node of the shift register unit, for providing a signal from the input signal terminal to the first pull-up node and providing a signal from the reference signal terminal to the first pull-down node;

[0006] a first control circuit connected to the first pull-down node and the first pull-up node, configured to control a signal of the first pull-up node based on the first pull-down node and control a signal of the first pull-down node based on the first pull-up node;

[0007] a second control circuit, connected to the first pull-down node, the first pull-up node, the second pull-down node, and the second pull-up node of the shift register unit, configured to provide a signal of the first pull-down node to the second pull-down node under the control of a reference signal terminal, and to control a signal of the second pull-up node based on the first pull-up node;

[0008] an output circuit connected to the second pull-down node, the second pull-up node, the reference signal terminal, and the clock signal terminal and the output signal terminal of the shift register unit, for providing a signal from one of the clock signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-down node and the second pull-up node; and

[0009] At least one of a first regulating circuit and a second regulating circuit, wherein the first regulating circuit is connected to the first pull-down node and the second control circuit, and the second regulating circuit is connected to the second pull-down node and the output circuit.

[0010] For example, the first adjustment circuit is used to lower the potential of the first pull-down node after the first pull-down node is reset, and the second adjustment circuit is used to lower the potential of the second pull-down node after the second pull-down node is reset.

[0011] For example, the second control circuit includes: a first control sub-circuit, connected to the first pull-down node and the first control signal terminal and the third pull-up node of the shift register unit, for providing the signal of the first control signal terminal to the third pull-up node under the control of the first pull-down node; a second control sub-circuit, connected to the reference signal terminal, the first pull-down node and the second pull-down node, for providing the signal of the first pull-down node to the second pull-down node under the control of the signal of the reference signal terminal; a third control sub-circuit, connected to the first pull-up node, the reference signal terminal and the third pull-up node, for providing the signal of the reference signal terminal to the third pull-up node under the control of the first pull-up node; and a fourth control sub-circuit, connected to the second pull-up node, the third pull-up node and the second control signal terminal of the shift register unit, for providing the signal of the third pull-up node to the second pull-up node under the control of the signals of the first pull-up node and the second control signal terminal.

[0012] For example, the first control subcircuit includes a first transistor, the gate of the first transistor is connected to the first pull-down node, the first electrode of the first transistor is connected to the first control signal terminal, and the second electrode of the first transistor is connected to the third pull-up node; the second control subcircuit includes a second transistor, the gate of the second transistor is connected to the reference signal terminal, the first electrode of the second transistor is connected to the first pull-down node, and the second electrode of the second transistor is connected to the second pull-down node; the third control subcircuit includes a third transistor, the gate of the third transistor is connected to the first pull-up node, the first electrode of the third transistor is connected to the reference signal terminal, and the second electrode of the third transistor is connected to the third pull-up node; the fourth control subcircuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the first pull-up node, the first electrode of the fourth transistor is connected to the third pull-up node, the second electrode of the fourth transistor is connected to the second pull-up node, the gate of the fifth transistor is connected to the second control signal terminal, the first electrode of the fifth transistor is connected to the third pull-up node, and the second electrode of the fifth transistor is connected to the second pull-up node.

[0013] For example, the first adjustment circuit includes a sixth transistor and a first capacitor, the sixth transistor and the first capacitor are connected in series between the first pull-down node and the third pull-up node, wherein the gate of the sixth transistor is connected to the third control signal terminal.

[0014] For example, a first electrode of the sixth transistor is connected to the third pull-up node, a second electrode of the sixth transistor is connected to a first electrode of the first capacitor, and a second electrode of the first capacitor is connected to the first pull-down node.

[0015] For example, a first electrode of the first capacitor is connected to the third pull-up node, a second electrode of the first capacitor is connected to the first electrode of the sixth transistor, and a second electrode of the sixth transistor is connected to the first pull-down node.

[0016] For example, the second adjustment circuit includes a seventh transistor, a second capacitor and a third capacitor, wherein the gate of the seventh transistor is connected to the fourth control signal terminal of the shift register unit, the first electrode of the seventh transistor is connected to the second control signal terminal of the shift register unit, the second electrode of the seventh transistor is connected to the first electrode of the second capacitor, the second electrode of the second capacitor is connected to the second pull-down node, the first electrode of the third capacitor is connected to the reference signal terminal, and the second electrode of the third capacitor is connected to the second electrode of the seventh transistor.

[0017] For example, the second adjustment circuit also includes an eighth transistor and a ninth transistor, the gate of the eighth transistor is connected to the reference signal terminal, the second electrode of the second transistor and the first electrode of the eighth transistor are connected to the intermediate node, the second electrode of the eighth transistor is connected to the second pull-down node, the gate of the ninth transistor is connected to the second pull-down node, the first electrode of the ninth transistor is connected to the reference signal terminal, and the second electrode of the ninth transistor is connected to the intermediate node.

[0018] For example, the reference signal terminal includes a first reference signal terminal and a second reference signal terminal, the potential of the second reference signal terminal is lower than the potential of the first reference signal terminal; the input circuit is connected to the first reference signal terminal or the second reference signal terminal, and the output circuit is connected to the first reference signal terminal.

[0019] For example, the second adjustment circuit includes a seventh transistor, a second capacitor, and a third capacitor, wherein a first electrode of the third capacitor is connected to the first reference signal terminal.

[0020] For example, the second adjustment circuit further includes an eighth transistor and a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second reference signal terminal.

[0021] For example, the input circuit includes: a tenth transistor, the gate of the tenth transistor is connected to the first control signal terminal, the first electrode of the tenth transistor is connected to the first reference signal terminal or the second reference signal terminal, and the second electrode of the tenth transistor is connected to the first pull-down node; an eleventh transistor, the gate of the eleventh transistor is connected to the first control signal terminal, the first electrode of the eleventh transistor is connected to the input signal terminal, and the second electrode of the eleventh transistor is connected to the first pull-up node.

[0022] For example, at least one of the tenth transistor and the second transistor is a low temperature polysilicon transistor.

[0023] For example, the output circuit includes: a twelfth transistor, the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the reference signal terminal, and the second electrode of the twelfth transistor is connected to the output signal terminal; a thirteenth transistor, the gate of the thirteenth transistor is connected to the second pull-up node, the first electrode of the thirteenth transistor is connected to the clock signal terminal, and the second electrode of the thirteenth transistor is connected to the output signal terminal; a fourth capacitor, the first electrode of the fourth capacitor is connected to the second pull-up node, and the second electrode of the fourth capacitor is connected to the output signal terminal.

[0024] For example, the shift register unit also includes: a cascade output circuit, connected to the first pull-down node, the first pull-up node, the power signal terminal, and the second control signal terminal and the cascade output terminal of the shift register unit, for providing a signal from one of the power signal terminal and the second control signal terminal to the cascade output terminal under the control of the first pull-down node and the first pull-up node.

[0025] For example, the cascade output circuit includes a fourteenth transistor, a fifteenth transistor, a fifth capacitor, and a sixth capacitor.

[0026] For example, the cascade output circuit also includes a sixteenth transistor, wherein the gate of the fifteenth transistor is connected to the first pull-up node through the sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the reference signal terminal, the first electrode of the sixteenth transistor is connected to the first pull-up node, and the second electrode of the sixteenth transistor is connected to the gate of the fifteenth transistor.

[0027] For example, the first control circuit includes a seventeenth transistor, an eighteenth transistor and a nineteenth transistor, the gate of the seventeenth transistor is connected to the first pull-up node, the first electrode of the seventeenth transistor is connected to the first control signal terminal, and the second electrode of the seventeenth transistor is connected to the first pull-down node; the gate of the eighteenth transistor is connected to the first pull-down node, the first electrode of the eighteenth transistor is connected to the power signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the nineteenth transistor; the gate of the nineteenth transistor is connected to the second control signal terminal, and the second electrode of the nineteenth transistor is connected to the first pull-up node.

[0028] For example, at least one transistor in the input circuit, the first control circuit, the second control circuit, the first adjustment circuit, the second adjustment circuit, and the output circuit is a P-type transistor.

[0029] An embodiment of the present disclosure provides another shift register unit, comprising:

[0030] an input circuit connected to an input signal terminal, a power signal terminal, a first pull-down node, and a first pull-up node of the shift register unit, for providing a signal from the input signal terminal to the first pull-down node and providing a signal from the power signal terminal to the first pull-up node;

[0031] a first control circuit connected to the first pull-down node and the first pull-up node, configured to control a signal of the first pull-up node based on the first pull-down node and control a signal of the first pull-down node based on the first pull-up node;

[0032] a second control circuit connected to the first pull-down node, the first pull-up node, the second pull-down node, and the second pull-up node of the shift register unit, and configured to control a signal of the second pull-down node based on the first pull-down node, and to control a signal of the second pull-up node based on the first pull-up node;

[0033] an output circuit connected to the second pull-down node, the second pull-up node, the power signal terminal, and the reference signal terminal and the output signal terminal of the shift register unit, for providing a signal from one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-down node and the second pull-up node; and

[0034] at least one of a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is connected to the first pull-down node and the second control circuit, and the second adjustment circuit is connected to the second pull-down node and the output circuit, for increasing the potential of the second pull-down node after the second pull-down node is reset.

[0035] For example, the first adjustment circuit is used to increase the potential of the first pull-down node after the first pull-down node is reset, and the second adjustment circuit is used to increase the potential of the second pull-down node after the second pull-down node is reset.

[0036] For example, the second control circuit includes: a first control subcircuit, connected to the first pull-up node, the first pull-down node, the power supply signal terminal, and the first control signal terminal and the third pull-down node of the shift register unit, for providing a signal of one of the power supply signal terminal and the first control signal terminal to the third pull-up node under the control of the first pull-down node and the first pull-up node; a second control subcircuit, connected to the first pull-up node, the first pull-down node, the reference signal terminal, and the second control signal terminal and the fourth pull-up node of the shift register unit, for providing a signal of one of the reference signal terminal and the second control signal terminal to the fourth pull-up node under the control of the first pull-down node and the first pull-up node; a third control subcircuit, connected to the second pull-up node, the fourth pull-up node, and the second control signal terminal, for providing a signal of the fourth pull-up node to the second pull-up node under the control of a signal of the second control signal terminal; and a fourth control subcircuit, connected to the power supply signal terminal, the first pull-down node, and the second pull-down node, for providing a signal of the first pull-down node to the second pull-down node under the control of a signal of the power supply signal terminal.

[0037] For example, the first control subcircuit includes a first transistor and a second transistor, the gate of the first transistor is connected to the first pull-up node, the first electrode of the first transistor is connected to the power signal terminal, the second electrode of the first transistor is connected to the third pull-up node, the gate of the second transistor is connected to the first pull-down node, the first electrode of the second transistor is connected to the first control signal terminal, and the second electrode of the second transistor is connected to the third pull-up node; the second control subcircuit includes a third transistor, a fourth transistor, a first capacitor and a second capacitor, the gate of the third transistor is connected to the first pull-up node, the first electrode of the third transistor is connected to the second control signal terminal, the second electrode of the third transistor is connected to the fourth pull-up node, the first electrode of the first capacitor is connected to the first pull-up node, and the first capacitor The second electrode is connected to the fourth pull-up node, the gate of the fourth transistor is connected to the first pull-down node, the first electrode of the fourth transistor is connected to the reference signal terminal, the second electrode of the fourth transistor is connected to the fourth pull-up node, the first electrode of the second capacitor is connected to the first pull-down node, and the second electrode of the second capacitor is connected to the reference signal terminal; the third control sub-circuit includes a fifth transistor, the gate of the fifth transistor is connected to the second control signal terminal, the first electrode of the fifth transistor is connected to the fourth pull-up node, and the second electrode of the fifth transistor is connected to the second pull-up node; the fourth control sub-circuit includes a sixth transistor, the gate of the sixth transistor is connected to the power signal terminal, the first electrode of the sixth transistor is connected to the first pull-down node, and the second electrode of the sixth transistor is connected to the second pull-down node.

[0038] For example, the first adjustment circuit includes a seventh transistor and a third capacitor, wherein the seventh transistor and the third capacitor are connected in series between the first pull-down node and the third pull-up node, wherein the gate of the seventh transistor is connected to the third control signal terminal.

[0039] For example, a first electrode of the seventh transistor is connected to the third pull-up node, a second electrode of the seventh transistor is connected to a first electrode of the third capacitor, and a second electrode of the third capacitor is connected to the first pull-down node.

[0040] For example, a first electrode of the third capacitor is connected to the third pull-up node, a second electrode of the third capacitor is connected to the first electrode of the seventh transistor, and a second electrode of the seventh transistor is connected to the first pull-down node.

[0041] For example, the second adjustment circuit includes an eighth transistor, a fourth capacitor and a fifth capacitor, wherein the gate of the eighth transistor is connected to the fourth control signal terminal of the shift register unit, the first electrode of the eighth transistor is connected to the second control signal terminal of the shift register unit, the second electrode of the eighth transistor is connected to the first electrode of the fourth capacitor, the second electrode of the fourth capacitor is connected to the second pull-down node, the first electrode of the fifth capacitor is connected to the power signal terminal, and the second electrode of the fifth capacitor is connected to the second electrode of the eighth transistor.

[0042] For example, the second control circuit further includes: a ninth transistor, a gate of the ninth transistor connected to the first pull-down node, a first electrode of the ninth transistor connected to the reference signal terminal, and a second electrode of the ninth transistor connected to the second pull-up node.

[0043] For example, the input circuit includes: a tenth transistor, the gate of the tenth transistor is connected to the first control signal terminal, the first electrode of the tenth transistor is connected to the power signal terminal, and the second electrode of the tenth transistor is connected to the first pull-up node; an eleventh transistor, the gate of the eleventh transistor is connected to the first control signal terminal, the first electrode of the eleventh transistor is connected to the input signal terminal, and the second electrode of the eleventh transistor is connected to the first pull-down node.

[0044] For example, at least one of the eleventh transistor and the sixth transistor is a low-temperature polysilicon transistor.

[0045] For example, the output circuit includes: a twelfth transistor, the gate of the twelfth transistor is connected to the second pull-up node, the first electrode of the twelfth transistor is connected to the reference signal terminal, and the second electrode of the twelfth transistor is connected to the output signal terminal; a thirteenth transistor, the gate of the thirteenth transistor is connected to the second pull-down node, the first electrode of the thirteenth transistor is connected to the power signal terminal, and the second electrode of the thirteenth transistor is connected to the output signal terminal; a fourth capacitor, the first electrode of the fourth capacitor is connected to the second pull-up node, and the second electrode of the fourth capacitor is connected to the reference signal terminal.

[0046] For example, the output circuit also includes a fourteenth transistor and a fifteenth transistor, the first electrode of the twelfth transistor is connected to the reference signal terminal through the fourteenth transistor, wherein the gate of the fourteenth transistor is connected to the second pull-up node, the first electrode of the fourteenth transistor is connected to the reference signal terminal, and the second electrode of the fourteenth transistor is connected to the first electrode of the twelfth transistor; the gate of the fifteenth transistor is connected to the output signal terminal, the first electrode of the fifteenth transistor is connected to the power supply signal terminal, and the second electrode of the fifteenth transistor is connected to the first electrode of the twelfth transistor.

[0047] For example, the first control circuit includes a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, the gate of the sixteenth transistor is connected to the first pull-down node, the first electrode of the sixteenth transistor is connected to the first control signal terminal, and the second electrode of the sixteenth transistor is connected to the first pull-up node; the gate of the seventeenth transistor is connected to the first pull-up node, the first electrode of the seventeenth transistor is connected to the reference signal terminal, and the second electrode of the seventeenth transistor is connected to the first electrode of the eighteenth transistor; the gate of the eighteenth transistor is connected to the second control signal terminal, and the second electrode of the eighteenth transistor is connected to the first pull-down node.

[0048] For example, at least one transistor in the input circuit, the first control circuit, the second control circuit, the first adjustment circuit, the second adjustment circuit, and the output circuit is an N-type transistor.

[0049] An embodiment of the present disclosure further provides a method for controlling the shift register unit as described above, comprising:

[0050] In the input phase, the input circuit provides a signal at the input signal terminal to the first pull-up node and provides a signal at the reference signal terminal to the first pull-down node;

[0051] In the output phase, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and controls the signal of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node is at a low level and the second pull-down node is at a high level, and the output circuit provides the signal of the clock signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node;

[0052] In a reset phase, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and controls the signal of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node changes from a low level to a high level and the second pull-down node changes from a high level to a low level, and the output circuit provides the signal of the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node;

[0053] In which, in the reset phase, the first adjustment circuit lowers the potential of the first pull-down node after the first pull-down node changes from a high level to a low level, and / or the second adjustment circuit lowers the potential of the second pull-down node after the second pull-down node changes from a high level to a low level.

[0054] For example, the second control circuit is connected to the first control signal terminal and the second control signal terminal, the first adjustment circuit is connected to the third control signal terminal, and the second adjustment circuit is connected to the fourth control signal terminal; wherein, the effective level duration period of the signal at the first control signal terminal partially overlaps with the effective level duration period of the signal at the third control signal terminal, so that in the reset stage, the first adjustment circuit lowers the potential of the first pull-down node after the first pull-down node changes from a high level to a low level under the control of the third control signal terminal; and / or the effective level duration period of the signal at the second control signal terminal partially overlaps with the effective level duration period of the signal at the fourth control signal terminal, so that in the reset stage, the second adjustment circuit lowers the potential of the second pull-down node after the second pull-down node changes from a high level to a low level under the control of the fourth control signal terminal.

[0055] An embodiment of the present disclosure further provides another control method of the shift register unit as described above, comprising:

[0056] In the input phase, the input circuit provides signals from the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node;

[0057] In the output phase, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and controls the signal of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node is at a high level and the second pull-down node is at a low level, and the output circuit provides the signal of the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node;

[0058] In a reset phase, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and controls the signal of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node changes from a high level to a low level and the second pull-down node changes from a low level to a high level, and the output circuit provides the signal of the power signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node;

[0059] In which, in the reset phase, the first adjustment circuit increases the potential of the first pull-down node after the first pull-down node changes from a low level to a high level, and / or the second adjustment circuit increases the potential of the second pull-down node after the second pull-down node changes from a low level to a high level.

[0060] For example, the second control circuit is connected to the first control signal terminal and the second control signal terminal, the first adjustment circuit is connected to the third control signal terminal, and the second adjustment circuit is connected to the fourth control signal terminal; wherein, the effective level duration period of the signal at the first control signal terminal partially overlaps with the effective level duration period of the signal at the third control signal terminal, so that in the reset stage, the first adjustment circuit increases the potential of the first pull-down node after the first pull-down node changes from a low level to a high level under the control of the third control signal terminal; and / or the effective level duration period of the signal at the second control signal terminal partially overlaps with the effective level duration period of the signal at the fourth control signal terminal, so that in the reset stage, the second adjustment circuit increases the potential of the second pull-down node after the second pull-down node changes from a low level to a high level under the control of the fourth control signal terminal.

[0061] An embodiment of the present disclosure further provides a gate driving circuit, comprising a plurality of shift register units connected in cascade, wherein the shift register units are the shift register units described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 shows a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0063] FIG. 2 shows a signal timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0064] FIG3 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0065] 4 to 6 respectively illustrate circuit diagrams of multiple examples of shift register units according to embodiments of the present disclosure.

[0066] FIG7 shows a schematic block diagram of a shift register unit according to another embodiment of the present disclosure.

[0067] 8 to 9 are circuit diagrams respectively showing multiple examples of a shift register unit according to another embodiment of the present disclosure.

[0068] FIG. 10 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure.

[0069] FIG. 11 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure.

[0070] FIG12 shows a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] While the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that one of ordinary skill in the art may modify the disclosure described herein while still achieving the technical benefits of the present disclosure. Therefore, it should be understood that the above description is intended to be a broad disclosure for one of ordinary skill in the art and is not intended to limit the exemplary embodiments described herein.

[0072] In addition, in the following detailed description, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in diagrammatic form to simplify the accompanying drawings.

[0073] FIG1 shows a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0074] As shown in FIG. 1 , the pixel driving circuit 100 includes a driving circuit 110 , an input circuit 120 , a compensation circuit 130 and a light emitting control circuit 140 .

[0075] The driving circuit 110 has a control terminal G, a first terminal D, and a second terminal S, and is configured to generate a driving current from the first terminal D to the second terminal S under the control of a signal from the control terminal G. The driving circuit 110 may include a driving transistor DTFT and a capacitor Cst. The gate, drain, and source of the driving transistor DTFT serve as the control terminal G, the first terminal D, and the second terminal S of the driving circuit, respectively. For ease of description, the gate, drain, and source of the driving transistor DTFT are also represented by G, D, and S, respectively, hereinafter. The first electrode of the capacitor Cst is connected to the gate of the driving transistor DTFT, and the second electrode of the capacitor Cst is connected to the second electrode of the driving transistor DTFT.

[0076] The input circuit 120 is connected to the data signal terminal DATA and the control terminal G of the driving circuit. Under the control of the first gate drive signal Gate1, the input circuit 120 can provide the data signal at the data signal terminal DATA to the control terminal G of the driving circuit 110. The input circuit 120 can include a fourth transistor TP4, wherein the gate of the fourth transistor TP4 is configured to receive the first gate drive signal Gate1, a first electrode of the fourth transistor TP4 is connected to the data signal terminal DATA, and a second electrode of the fourth transistor TP4 is connected to the control terminal G of the driving circuit.

[0077] The compensation circuit 130 is connected to the first voltage terminal Vini, the second voltage terminal Vref, and the control terminal G and the second terminal S of the driving circuit 110. Under the control of the second gate drive signal Gate2, the compensation circuit 130 can provide a reference voltage at the second voltage terminal Vref to the second terminal S of the driving circuit, and under the control of the third gate drive signal Gate3, provide an initial voltage at the first voltage terminal Vini to the control terminal G of the driving circuit. The compensation circuit 130 may include a first transistor TP1 and a second transistor TP2. The gate of the first transistor TP1 is configured to receive the second gate drive signal Gate2, a first electrode of the first transistor TP1 is connected to the second voltage terminal Vref, and a second electrode of the first transistor TP1 is connected to the second terminal S of the driving circuit 110. The gate of the second transistor TP2 is configured to receive the third gate drive signal Gate3, a first electrode of the second transistor TP2 is connected to the first voltage terminal Vini, and a second electrode of the second transistor TP2 is connected to the control terminal G of the driving circuit 110.

[0078] The light emission control circuit 140 is connected between the first terminal D of the driver circuit 110 and the power supply signal terminal ELVDD. The light emission control circuit 140 can connect or disconnect the first terminal D of the driver circuit 110 from the power supply signal terminal ELVDD under the control of a light emission control signal EM. The light emission control circuit 140 may include a third transistor TP3. The gate of the third transistor TP3 is configured to receive the light emission control signal EM, a first electrode of the third transistor TP3 is connected to the power supply signal terminal ELVDD, and a second electrode of the third transistor TP3 is connected to the first terminal D of the driver circuit 110.

[0079] According to an embodiment of the present disclosure, a pixel driving circuit 100 may be included in a sub-pixel to drive the light-emitting element in the sub-pixel to emit light. For example, in FIG1 , the second electrode S of the driving transistor DTFT of the pixel driving circuit 100 may be connected to the first electrode (e.g., anode) of the light-emitting element EL, and the second electrode (e.g., cathode) of the light-emitting element EL may be connected to the reference signal terminal ELVSS. The light-emitting element EL may be an organic light-emitting diode (OLED).

[0080] FIG. 2 shows a signal timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0081] During period t1, the first gate drive signal Gate1 is at a low level, the second gate drive signal Gate2 and the third gate drive signal Gate3 are at a high level, the fourth transistor TP4 is off, and the first transistor TP1 and the second transistor TP2 are on, causing the gate G of the drive transistor DTFT to be reset to the first voltage of the first voltage terminal Vini, and the source S of the drive transistor DTFT to be reset to the second voltage of the second voltage terminal Vref. During this period, the high level of the second gate drive signal Gate2 may arrive later than the high level of the third gate drive signal Gate3, thereby causing the gate G and source S of the drive transistor DTFT to be reset successively. In addition, during this period, the emission control signal EM may be at a high level, causing the drain D of the drive transistor DTFT to be reset to the reference voltage of the reference signal terminal ELVDD. The drive transistor DTFT is reset during this period, and therefore, this period is also referred to as a reset period.

[0082] During period t2, the third gate drive signal Gate3 and the light emitting control signal EM remain at a high level, and the second gate drive signal Gate2 becomes a low level, so that the second transistor TP2 and the third transistor TP3 remain on, while the first transistor TP1 is turned off. At this time, the gate-source voltage Vgs of the driving transistor DTFT is greater than the threshold voltage Vth of the driving transistor DTFT. The presence of the capacitor Cst charges the source electrode S of the driving transistor DTFT until Vgs = Vth, thereby achieving threshold voltage compensation. This period is also called the compensation period. During this period, the light emitting control signal EM can remain at a high level,

[0083] During period t3, the third gate drive signal Gate3 becomes low, and the second transistor TP2 is turned off. Thereafter, the first gate drive signal Gate1 becomes high, and the light-emission control signal EM becomes low, turning on the third transistor TP3 and the fourth transistor TP4. As a result, when the data signal at the data signal terminal DATA arrives, the data signal is written into the gate G of the drive transistor DTFT. In FIG2 , the data signal at the data signal terminal DATA is shown as a high level. However, those skilled in the art should understand that this is merely to indicate the arrival of the data signal. The actual level of the data signal is determined by the image data and is not a fixed level. During this period, the data signal is written into the gate G of the drive transistor DTFT, and therefore this period is also referred to as the data write period.

[0084] During period t4, the emission control signal EM is at a high level, the first gate drive signal Gate1 becomes low, and the third transistor TP3 is turned on. At this time, the first transistor TP1, the second transistor TP2, and the fourth transistor TP4 are all turned off. The driving transistor DTFT generates a driving current from the drain electrode D to the source electrode S under the action of the voltage of the gate G. The generated driving current drives the light-emitting element EL to emit light. In some embodiments, a black insertion period tb can also be provided in period t4. During this black insertion period, the emission control signal EM is at a low level, the third transistor TP3 is turned off, and the driving transistor DTFT stops generating current, and the light-emitting element EL stops emitting light. After the black insertion period tb ends, the emission control signal EM returns to a high level, thereby continuing to drive the light-emitting element EL to emit light. In some embodiments, the emission control signal EM can be a multi-pulse signal to perform low grayscale dimming.

[0085] The pixel driving circuit proposed in the embodiment of the present disclosure can achieve internal compensation by setting up a compensation circuit and a light-emitting control circuit. Compared with using a source driving circuit with an external compensation function to perform compensation through complex calculations, it can reduce costs and calculation complexity.

[0086] An embodiment of the present disclosure provides a shift register unit, comprising an input circuit, a first control circuit, a second control circuit, an output circuit, and at least one of a first adjustment circuit and a second adjustment circuit. The input circuit is connected to an input signal terminal, a reference signal terminal, a first pull-down node, and a first pull-up node of the shift register unit, and is used to provide signals from the input signal terminal and the reference signal terminal to the first pull-down node and the first pull-up node. The first control circuit is connected to the first pull-down node and the first pull-up node, and is used to control the potential of the first pull-up node based on the potential of the first pull-down node and to control the potential of the first pull-down node based on the potential of the first pull-up node. The second control circuit is connected to the first pull-down node, the first pull-up node, the second pull-down node, and the second pull-up node of the shift register unit, and is used to control the potential of the second pull-down node based on the potential of the first pull-down node and to control the potential of the second pull-up node based on the potential of the first pull-up node. an output circuit connected to the second pull-down node, the second pull-up node, the reference signal terminal, and the clock signal terminal and the output signal terminal of the shift register unit, and configured to provide a signal from one of the clock signal terminal and the reference signal terminal to the output signal terminal under control of the second pull-down node and the second pull-up node; and at least one of a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is connected to the first pull-down node and configured to lower the potential of the first pull-down node after the first pull-down node is reset, and the second adjustment circuit is connected to the second pull-down node and configured to lower the potential of the second pull-down node after the second pull-down node is reset.

[0087] This will be described in detail below with reference to FIG. 3 to FIG. 6 .

[0088] Figure 3 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure. The shift register unit according to an embodiment of the present disclosure is capable of generating scan signals required for display driving, such as gate drive signals or light-emitting control signals, and can be applied to pixel drive circuits with internal compensation functions or other circuits requiring scan signals, such as the pixel drive circuits of the above-mentioned embodiments.

[0089] 3 , the shift register unit 200 includes an input circuit 210, a first control circuit 220, a second control circuit 230, an output circuit 240, and at least one of a first adjustment circuit 250 and a second adjustment circuit 260. The shift register unit 200 may have an input signal terminal IN, an output signal terminal GOUT, a reference signal terminal VGL, a clock signal terminal GCK, a first pull-up node Q1, a second pull-up node Q2, a first pull-down node QB1, and a second pull-down node QB2.

[0090] The input circuit 210 is connected to the input signal terminal IN, the reference signal terminal VGL, a first pull-up node Q1, and a first pull-down node QB1. The input circuit 210 can provide a signal from the input signal terminal IN to the first pull-up node Q1 and a signal from the reference signal terminal VGL to the first pull-down node QB1. In some embodiments, the input circuit 210 may include a first input sub-circuit and a second input sub-circuit. One of the first input sub-circuit and the second input sub-circuit is configured to provide a signal from one of the input signal terminal IN and the reference signal terminal VGL to the first pull-up node Q1, and the other of the first input sub-circuit and the second input sub-circuit is configured to provide a signal from the other of the input signal terminal IN and the reference signal terminal VGL to the first pull-down node QB1.

[0091] The first control circuit 220 connects the first pull-up node Q1 and the first pull-down node QB1. The first control circuit 220 can control the signal of the first pull-down node QB1 based on the first pull-up node Q1, and can control the signal of the first pull-up node Q1 based on the first pull-down node QB1. In some embodiments, the first control circuit 220 may include a pull-up node control subcircuit and a pull-down node control subcircuit, one of which is used to control the signal of the first pull-down node QB1 based on the first pull-up node Q1, and the other of which is used to control the signal of the first pull-up node Q1 based on the first pull-down node QB1.

[0092] The second control circuit 230 is connected to the first pull-up node Q1, the first pull-down node QB1, the second pull-up node Q2, and the second pull-down node QB2. The second control circuit 230 can provide the signal of the first pull-down node QB1 to the second pull-down node QB2 under the control of the reference signal terminal VGL, and control the potential of the second pull-up node Q2 based on the first pull-up node Q1. In some embodiments, the second control circuit 230 may include one or more of a first control subcircuit, a second control subcircuit, a third control subcircuit, and a fourth control subcircuit. For example, the second control circuit 230 may include the first control subcircuit and the second control subcircuit, or include the first to third control subcircuits, or include the first to fourth control subcircuits, which will be described in detail below.

[0093] The output circuit 240 is connected to the second pull-up node Q2, the second pull-down node QB2, the clock signal terminal GCK, the reference signal terminal VGL, and the output signal terminal GOUT. The output circuit 240 can provide a signal from one of the clock signal terminal GCK and the reference signal terminal VGL to the output signal terminal GOUT under the control of the second pull-up node Q2 and the second pull-down node QB2.

[0094] The first adjustment circuit 250 is connected to the first pull-down node QB1 and the second control circuit 230. The first adjustment circuit 250 can adjust the potential of the first pull-down node QB1, for example, lower the potential of the first pull-down node QB1 after the first pull-down node QB1 is reset.

[0095] The second adjustment circuit 260 is connected to the second pull-down node QB2 and the output circuit 240. The second adjustment circuit 260 can adjust the potential of the second pull-down node QB2, for example, lower the potential of the second pull-down node QB2 after the second pull-down node QB2 is reset.

[0096] According to an embodiment of the present disclosure, the input circuit 210 , the first control circuit 220 , the second control circuit 230 , the output circuit 240 , the first adjustment circuit 250 , and the second adjustment circuit 260 may each include at least one P-type transistor.

[0097] In this manner, the embodiments of the present disclosure implement a novel shift register unit structure, wherein the input circuit, the first control circuit, the second control circuit, the output circuit, and the first adjustment circuit and / or the second adjustment circuit cooperate to generate the scanning signals required for display driving, such as gate drive signals or light-emitting control signals. By providing at least one of the first adjustment circuit and the second adjustment circuit, leakage at the first pull-down node and / or the second pull-down node can be effectively mitigated.

[0098] Several examples of the shift register unit according to the embodiment of the present disclosure will be described below with reference to FIG. 4 to FIG. 6 .

[0099] FIG4 shows a circuit diagram of a shift register unit 200A according to an embodiment of the present disclosure. The shift register unit 200A includes an input circuit, a first control circuit, a second control circuit, an output circuit, a first adjustment circuit, and a second adjustment circuit. The description of the input circuit, the first control circuit, the second control circuit, the output circuit, and the first adjustment circuit and the second adjustment circuit in the embodiment of FIG3 above also applies to the embodiment of FIG4.

[0100] As shown in FIG4 , the input circuit includes a first input sub-circuit 2101A and a second input sub-circuit 2102A.

[0101] The first input sub-circuit 2101A is connected to the reference signal terminal VGL, the first pull-down node QB1, and the first control signal terminal CKA of the shift register unit. Under the control of the first control signal terminal CKA, the first input sub-circuit 2101A can provide a signal at the reference signal terminal VGL to the first pull-down node QB1. The first input sub-circuit 2101A includes a tenth transistor M10, the gate of which is connected to the first control signal terminal CKA, a first electrode of which is connected to the reference signal terminal VGL, and a second electrode of which is connected to the first pull-down node QB1.

[0102] The second input sub-circuit 2102A is connected to the input signal terminal IN, the first pull-up node Q1, and the first control signal terminal CKA. The second input sub-circuit 2102A can provide the signal at the input signal terminal IN to the first pull-up node Q1 under the control of the first control signal terminal CKA. For example, the second input sub-circuit 2102A includes an eleventh transistor M11, wherein the gate of the eleventh transistor M11 is connected to the first control signal terminal CKA, the first electrode of the eleventh transistor M11 is connected to the input signal terminal IN, and the second electrode of the eleventh transistor M11 is connected to the first pull-up node Q1.

[0103] As shown in FIG4 , the first control circuit includes a pull-up node control subcircuit 2201A and a pull-down node control subcircuit 2202A.

[0104] The pull-up node control subcircuit 2201A is connected to the first pull-up node Q1, the first pull-down node QB1, the power supply signal terminal VGH, and the second control signal terminal CKB of the shift register unit. Under the control of the second control signal terminal CKB and the first pull-down node QB1, the pull-up node control subcircuit 2201A can provide a signal at the power supply signal terminal VGH to the first pull-up node Q1. For example, the pull-up node control subcircuit 2201A may include an eighteenth transistor M18 and a nineteenth transistor M19. The gate of the eighteenth transistor M18 is connected to the first pull-down node QB1, the first electrode of the eighteenth transistor M18 is connected to the power supply signal terminal VGH, and the second electrode of the eighteenth transistor M18 is connected to the first electrode of the nineteenth transistor M19. The gate of the nineteenth transistor M19 is connected to the second control signal terminal CKB, and the second electrode of the nineteenth transistor M19 is connected to the first pull-up node Q1.

[0105] The pull-down node control subcircuit 2202A is connected to the first pull-up node Q1, the first pull-down node QB1, and the first control signal terminal CKA. The pull-down node control subcircuit 2202A can provide a signal at the first control signal terminal CKA to the first pull-down node QB1 under the control of the first pull-up node Q1. For example, the pull-down node control subcircuit 2202A can include a seventeenth transistor M17, wherein a gate of the seventeenth transistor M17 is connected to the first pull-up node Q1, a first electrode of the seventeenth transistor M17 is connected to the first control signal terminal CKA, and a second electrode of the seventeenth transistor M17 is connected to the first pull-down node QB1.

[0106] As shown in FIG4 , the second control circuit includes a first control sub-circuit 2301A, a second control sub-circuit 2302A, a third control sub-circuit 2303A, and a fourth control sub-circuit 2304A.

[0107] The first control subcircuit 2301A is connected to the first pull-down node QB1, the first control signal terminal CKA, and the third pull-up node Q3 of the shift register unit. Under control of the first pull-down node QB1, the first control subcircuit 2301A can provide a signal at the first control signal terminal CKA to the third pull-up node Q3. For example, the first control subcircuit 2301A may include a first transistor M1. The gate of the first transistor M1 is connected to the first pull-down node QB1, the first electrode of the first transistor M1 is connected to the first control signal terminal CKA, and the second electrode of the first transistor M1 is connected to the third pull-up node Q3.

[0108] The second control sub-circuit 2302A is connected to the reference signal terminal VGL, the first pull-down node QB1, and the second pull-down node QB2. The second control sub-circuit 2302A can provide the signal of the first pull-down node QB1 to the second pull-down node QB2 under the control of the signal of the reference signal terminal VGL. For example, the second control sub-circuit 2302A may include a second transistor M2, the gate of the second transistor M2 being connected to the reference signal terminal VGL, the first electrode of the second transistor M2 being connected to the first pull-down node QB1, and the second electrode of the second transistor M2 being connected to the second pull-down node QB2.

[0109] The third control sub-circuit 2303A is connected to the first pull-up node Q1, the reference signal terminal VGL, and the third pull-up node Q3. Under the control of the first pull-up node Q1, the third control sub-circuit 2303A can provide a signal from the reference signal terminal VGL to the third pull-up node Q3. For example, the third control sub-circuit 2303A may include a third transistor M3, wherein a gate of the third transistor M3 is connected to the first pull-up node Q1, a first electrode of the third transistor M3 is connected to the reference signal terminal VGL, and a second electrode of the third transistor M3 is connected to the third pull-up node Q3.

[0110] The fourth control subcircuit 2304A is connected to the first pull-up node Q1 (or the fourth pull-up node Q4), the second pull-up node Q2, the third pull-up node Q3, and the second control signal terminal CKB. The fourth control subcircuit 2304A can provide a signal from the third pull-up node Q3 to the second pull-up node Q2 under the control of signals from the first pull-up node Q1 and the second control signal terminal CKB. The fourth control subcircuit 2304A includes a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is connected to the first pull-up node Q1 (or the fourth pull-up node Q4), the first electrode of the fourth transistor M4 is connected to the third pull-up node Q3, the second electrode of the fourth transistor M4 is connected to the second pull-up node Q2, the gate of the fifth transistor M5 is connected to the second control signal terminal CKB, the first electrode of the fifth transistor M5 is connected to the third pull-up node Q3, and the second electrode of the fifth transistor M5 is connected to the second pull-up node Q2. In some embodiments, the fourth control subcircuit 2304A may include one of the fourth transistor M4 and the fifth transistor M5, as long as it can provide the signal of the third pull-up node Q3 to the second pull-up node Q2 under the control of an appropriate control signal so that the second pull-up node Q2 has a desired waveform.

[0111] As shown in FIG. 4 , the output circuit 240A may include a twelfth transistor M12 , a thirteenth transistor M13 , and a fourth capacitor C4 .

[0112] A gate of the twelfth transistor M12 is connected to the second pull-down node QB2 , a first electrode of the twelfth transistor M12 is connected to the reference signal terminal VGL, and a second electrode of the twelfth transistor M12 is connected to the output signal terminal GOUT.

[0113] A gate of the thirteenth transistor M13 is connected to the second pull-up node Q2 , a first electrode of the thirteenth transistor M13 is connected to the clock signal terminal GCK, and a second electrode of the thirteenth transistor M13 is connected to the output signal terminal GOUT.

[0114] A first electrode of the fourth capacitor C4 is connected to the second pull-up node Q2 , and a second electrode of the fourth capacitor C4 is connected to the output signal terminal GOUT.

[0115] As shown in FIG4 , the first adjustment circuit 250A may include a sixth transistor M6 and a first capacitor C1. The sixth transistor M6 and the first capacitor C1 are connected in series between the first pull-down node QB1 and the third pull-up node Q3. The gate of the sixth transistor M6 is connected to the third control signal terminal CKD of the shift register unit. For example, the first electrode of the sixth transistor M6 is connected to the third pull-up node Q3, the second electrode of the sixth transistor M6 is connected to the first electrode of the first capacitor C1, and the second electrode of the first capacitor C1 is connected to the first pull-down node QB1. In some embodiments, the first adjustment circuit 250A may include the sixth transistor M6 without the first capacitor C1, as long as it can adjust the potential of the first pull-down node QB1 under the control of an appropriate control signal. For example, the first electrode of the sixth transistor M6 is connected to the third pull-up node Q3, the second electrode of the sixth transistor M6 is connected to the first pull-down node QB1, and the gate of the sixth transistor M6 can be connected to an appropriate signal terminal to receive a desired control signal, as long as it can provide the signal from the third pull-up node Q3 to the first pull-down node QB1 at a desired time to stabilize the first pull-down node QB1.

[0116] As shown in FIG4 , the second adjustment circuit 260A may include a seventh transistor M7, a second capacitor C2, and a third capacitor C3. A gate of the seventh transistor M7 is connected to the fourth control signal terminal CKC of the shift register unit, a first electrode of the seventh transistor M7 is connected to the second control signal terminal CKB of the shift register unit, a second electrode of the seventh transistor M7 is connected to the first electrode of the second capacitor C2, a second electrode of the second capacitor C2 is connected to the second pull-down node QB2, a first electrode of the third capacitor C3 is connected to the reference signal terminal VGL, and a second electrode of the third capacitor is connected to the second electrode of the seventh transistor M7.

[0117] In some embodiments, the shift register unit may further include a cascade output circuit in addition to the input circuit, the first control circuit, the second control circuit, the output circuit, the first adjustment circuit, and / or the second adjustment circuit.

[0118] As shown in FIG4 , the shift register unit 200A includes a cascade output circuit 270A. The cascade output circuit 270A is connected to the first pull-down node QB1, the first pull-up node Q1, the power signal terminal VGH, the second control signal terminal CKB, and the cascade output terminal CR of the shift register unit. <n>The cascade output circuit 270A can provide a signal of one of the power signal terminal VGH and the second control signal terminal CKB to the cascade output terminal CR under the control of the first pull-down node QB1 and the first pull-up node Q1. <n>.

[0119] The cascade output circuit 270A may include a fourteenth transistor M14, a fifteenth transistor M15, a fifth capacitor C5, and a sixth capacitor C6. The gate of the fourteenth transistor M14 is connected to the first pull-down node QB1, the first electrode of the fourteenth transistor M14 is connected to the power signal terminal VGH, and the second electrode of the fourteenth transistor M14 is connected to the cascade output terminal CR. <n>The first electrode of the fifth capacitor C5 is connected to the first pull-down node QB1, and the second electrode of the fifth capacitor C5 is connected to the power signal terminal VGH. The gate of the fifteenth transistor M15 is connected to the first pull-up node Q1 (or the fourth pull-up node Q4), the first electrode of the fifteenth transistor M15 is connected to the second control signal terminal CKB, and the second electrode of the fifteenth transistor M15 is connected to the cascade output terminal CR. <n>The first electrode of the sixth capacitor C6 is connected to the first pull-up node Q1 (or the fourth pull-up node Q4), and the second electrode of the sixth capacitor C6 is connected to the cascade output terminal CR <n>.

[0120] As shown in FIG4 , the cascade output circuit 270A may further include a sixteenth transistor M16, wherein the gate of the fifteenth transistor M15 is connected to the first pull-up node Q1 via the sixteenth transistor M16. The gate of the sixteenth transistor M16 is connected to the reference signal terminal VGL, a first electrode of the sixteenth transistor M16 is connected to the first pull-up node Q1, and a second electrode of the sixteenth transistor M16 is connected to the gate of the fifteenth transistor M15.

[0121] At least a portion of the transistors involved in the embodiment described above with reference to FIG4 can be implemented by P-type transistors, for example, by P-type low-temperature polysilicon (LTPS). For example, at least one of transistors M10 and M2 is a P-type LTPS transistor. In some embodiments, all transistors in the shift register unit of FIG4 can be implemented by P-type LTPS transistors. Since the drive signal of the sub-pixel is often a high-level active signal, how to use P-type transistors to output a high-level active pulse waveform becomes a challenge. In addition, the off-state current of the low-temperature polysilicon transistor is too large and is prone to leakage, making the circuit unstable. According to the embodiment described above with reference to FIG4, a shift register unit implemented based on P-type transistors can be provided, which can generate a high-level active output signal and, by providing at least one of a first adjustment circuit and a second adjustment circuit, can effectively alleviate leakage at the first pull-down node and / or the second pull-down node. For example, by reducing the potential at the first pull-down node and / or the second pull-down node, the leakage time of transistors M10 and M2 is prolonged, thereby reducing the leakage rate.

[0122] FIG5 shows a circuit diagram of a shift register unit 200B according to another embodiment of the present disclosure. The shift register unit 200B of FIG5 is similar to the shift register unit 200A of FIG4 , differing at least in the first adjustment circuit and the configuration of the reference signal terminal. For the sake of brevity and clarity, the following will primarily describe the differences in detail.

[0123] As shown in FIG5 , the first adjustment circuit 250B may include a sixth transistor M6 and a first capacitor C1, which are connected in series between the first pull-down node QB1 and the third pull-up node Q3. Unlike FIG4 , the positions of the sixth transistor M6 and the first capacitor C1 are swapped, i.e., the first electrode of the first capacitor C1 is connected to the third pull-up node Q3, the second electrode of the first capacitor C1 is connected to the first electrode of the sixth transistor M6, the second electrode of the sixth transistor M6 is connected to the first pull-down node QB1, and the gate of the sixth transistor M6 is connected to the third control signal terminal CKD.

[0124] In some embodiments, the reference signal terminal VGL may include a first reference signal terminal VGL1 and a second reference signal terminal VGL2 , and a potential of the second reference signal terminal VGL2 is lower than a potential of the first reference signal terminal VGL1 .

[0125] As shown in FIG5 , the first input sub-circuit 2101B is connected to the second reference signal terminal VGL2, and the first electrode of the tenth transistor M10 is connected to the second reference signal terminal VGL2. The output circuit 240B is connected to the first reference signal terminal VGL1, and the first electrode of the twelfth transistor M12 is connected to the first reference signal terminal VGL1. The second adjustment circuit 260B is connected to the first reference signal terminal VGL1, and the first electrode of the third capacitor C3 is connected to the first reference signal terminal VGL1.

[0126] However, the embodiments of the present disclosure are not limited thereto, and the first input sub-circuit may also be connected to the first reference signal terminal VGL1, and the output circuit and the second adjustment circuit may also be connected to the second reference signal terminal VGL2; or, the first input sub-circuit, the output circuit and the second adjustment circuit may all be connected to the second reference signal terminal VGL2; or, the first input sub-circuit, the output circuit and the second adjustment circuit may all be connected to the first reference signal terminal VGL1.

[0127] As shown in FIG5 , the gate of the sixteenth transistor M16 is connected to the first reference signal terminal VGL1, the first electrode of the third transistor M3 is connected to the first reference signal terminal VGL1, and the gate of the second transistor M2 is connected to the first reference signal terminal VGL1. However, the embodiments of the present disclosure are not limited thereto, and these transistors may also be connected to the second reference signal terminal VGL2.

[0128] FIG6 shows a circuit diagram of a shift register unit 200C according to another embodiment of the present disclosure. The shift register unit 200C of FIG6 is similar to the shift register unit 200B of FIG5 , except that the second adjustment circuit is structured and the shift register unit 200C of FIG6 does not include the first adjustment circuit. For the sake of brevity and clarity, the following description will focus on the differences.

[0129] As shown in FIG6 , the second adjustment circuit 260C includes, in addition to the seventh transistor M7, the second capacitor C2, and the third capacitor C3, an eighth transistor M8 and a ninth transistor M9. The gate of the eighth transistor M8 and the gate of the second transistor M2 included in the second control sub-circuit are connected to the first reference signal terminal VGL1, the second electrode of the second transistor M2 and the first electrode of the eighth transistor M8 are connected to the intermediate node, the second electrode of the eighth transistor M8 is connected to the second pull-down node QB2, the gate of the ninth transistor M9 is connected to the second pull-down node QB2, the first electrode of the ninth transistor is connected to the second reference signal terminal VGL2, and the second electrode of the ninth transistor M9 is connected to the intermediate node.

[0130] In some embodiments, the gate of the eighth transistor M8 and the gate of the second transistor M2 included in the second control sub-circuit may also be connected to the second reference signal terminal VGL2, and the first electrode of the ninth transistor may also be connected to the first reference signal terminal VGL1. Alternatively, the gate of the eighth transistor M8, the gate of the second transistor M2 included in the second control sub-circuit, and the first electrode of the ninth transistor may all be connected to the first reference signal terminal VGL1. Alternatively, the gate of the eighth transistor M8, the gate of the second transistor M2 included in the second control sub-circuit, and the first electrode of the ninth transistor may all be connected to the second reference signal terminal VGL2.

[0131] In some embodiments, the shift register unit may include, in addition to the second adjustment circuit 260C shown in FIG. 6 , the first adjustment circuit 250A shown in FIG. 4 or the first adjustment circuit 250B shown in FIG. 5 .

[0132] In some embodiments, at least one of the tenth transistor M10 and the second transistor M2 is a low-temperature polysilicon transistor. However, the embodiments of the present disclosure are not limited thereto. In any embodiment of the shift register unit described above, at least one transistor may be a low-temperature polysilicon transistor. In some embodiments, the transistors M1 to M19 described above may all be low-temperature polysilicon transistors.

[0133] An embodiment of the present disclosure further provides another shift register unit, comprising: an input circuit connected to an input signal terminal, a power signal terminal, a first pull-down node, and a first pull-up node of the shift register unit, for providing signals from the input signal terminal and the power signal terminal to the first pull-down node and the first pull-up node; a first control circuit connected to the first pull-down node and the first pull-up node, for controlling the potential of the first pull-up node based on the potential of the first pull-down node and for controlling the potential of the first pull-down node based on the potential of the first pull-up node; a second control circuit connected to the first pull-down node, the first pull-up node, the second pull-down node, and the second pull-up node of the shift register unit, for controlling the potential of the second pull-down node based on the potential of the first pull-down node. The present invention relates to a first pull-down node, a second pull-up node, a second pull-up node, a power supply signal terminal, a reference signal terminal and an output signal terminal of the shift register unit, and a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is connected to the first pull-down node, and is used to increase the potential of the first pull-down node after the first pull-down node is reset, and the second adjustment circuit is connected to the second pull-down node, and is used to increase the potential of the second pull-down node after the second pull-down node is reset.

[0134] This will be described in detail below with reference to FIG. 7 to FIG. 9 .

[0135] Figure 7 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure. The shift register unit according to an embodiment of the present disclosure can generate scanning signals required for display driving, such as gate drive signals or light-emitting control signals, and can be applied to pixel drive circuits with internal compensation functions or other circuits requiring scanning signals, such as the pixel drive circuits in the above-mentioned embodiments.

[0136] 7 , the shift register unit 300 includes an input circuit 310, a first control circuit 320, a second control circuit 330, an output circuit 340, and at least one of a first adjustment circuit 350 and a second adjustment circuit 360. The shift register unit 300 may have an input signal terminal IN, an output signal terminal GOUT, a reference signal terminal VGL, a power signal terminal VGH, a first pull-up node Q1, a second pull-up node Q2, a first pull-down node QB1, and a second pull-down node QB2.

[0137] The input circuit 310 is connected to the input signal terminal IN, the power signal terminal VGH, a first pull-up node Q1, and a first pull-down node QB1. The input circuit 310 can provide a signal from the power signal terminal VGH to the first pull-up node Q1 and a signal from the input signal terminal IN to the first pull-down node QB1. In some embodiments, the input circuit 310 may include a first input sub-circuit and a second input sub-circuit. One of the first input sub-circuit and the second input sub-circuit is configured to provide a signal from either the input signal terminal IN or the power signal terminal VGH to the first pull-up node Q1, and the other of the first input sub-circuit and the second input sub-circuit is configured to provide a signal from the other of the input signal terminal IN and the power signal terminal VGH to the first pull-down node QB1.

[0138] The first control circuit 320 connects the first pull-up node Q1 and the first pull-down node QB1. The first control circuit 320 can control the signal of the first pull-down node QB1 based on the first pull-up node Q1 and control the signal of the first pull-up node Q1 based on the first pull-down node QB1. In some embodiments, the first control circuit 320 may include a pull-up node control subcircuit and a pull-down node control subcircuit, one of which is configured to control the potential of the first pull-down node QB1 based on the potential of the first pull-up node Q1, and the other of which is configured to control the potential of the first pull-up node Q1 based on the potential of the first pull-down node QB1.

[0139] The second control circuit 330 is connected to the first pull-up node Q1, the first pull-down node QB1, the second pull-up node Q2, and the second pull-down node QB2. The second control circuit 330 can control the signal of the second pull-down node QB2 based on the first pull-down node QB1, and provide the signal of the first pull-up node Q1 to the second pull-up node Q2 under the control of the power supply signal terminal VGH. In some embodiments, the second control circuit 330 may include one or more of a first control subcircuit, a second control subcircuit, a third control subcircuit, and a fourth control subcircuit. For example, the second control circuit 330 may include the first control subcircuit and the second control subcircuit, or include the first to third control subcircuits, or include the first to fourth control subcircuits, which will be described in detail below.

[0140] The output circuit 340 is connected to the second pull-up node Q2, the second pull-down node QB2, the power signal terminal VGH, the reference signal terminal VGL, and the output signal terminal GOUT. The output circuit 340 can provide a signal from one of the power signal terminal VGH and the reference signal terminal VGL to the output signal terminal GOUT under the control of the second pull-up node Q2 and the second pull-down node QB2.

[0141] The first adjustment circuit 350 is connected to the first pull-down node QB1 and is configured to increase the potential of the first pull-down node QB1 after the first pull-down node QB1 is reset.

[0142] The second adjustment circuit 360 is connected to the second pull-down node QB2 and is configured to increase the potential of the second pull-down node QB2 after the second pull-down node QB2 is reset.

[0143] According to an embodiment of the present disclosure, the input circuit 310 , the first control circuit 320 , the second control circuit 330 , the output circuit 340 , the first adjustment circuit 350 , and the second adjustment circuit 360 may each include at least one N-type transistor.

[0144] In this manner, the disclosed embodiments implement a novel shift register unit structure, wherein the input circuit, the first control circuit, the second control circuit, the output circuit, and the first adjustment circuit and / or the second adjustment circuit cooperate to generate the scanning signals required for display driving, such as gate drive signals or light-emitting control signals. By providing at least one of the first adjustment circuit and the second adjustment circuit, leakage at the first pull-down node and / or the second pull-down node can be effectively mitigated.

[0145] FIG8 shows a circuit diagram of a shift register unit 300A according to an embodiment of the present disclosure. The shift register unit 300A includes an input circuit, a first control circuit, a second control circuit, an output circuit, a first adjustment circuit, and a second adjustment circuit. The above description of the input circuit, the first control circuit, the second control circuit, the output circuit, and the first adjustment circuit and the second adjustment circuit in the embodiment of FIG7 is also applicable to the embodiment of FIG8.

[0146] As shown in FIG8 , the input circuit includes a first input sub-circuit 3101A and a second input sub-circuit 3102A.

[0147] The first input sub-circuit 3101A is connected to the power supply signal terminal VGH, the first pull-up node Q1, and the first control signal terminal CKA of the shift register unit. Under the control of the first control signal terminal CKA, the first input sub-circuit 3101A can provide a signal at the power supply signal terminal VGH to the first pull-up node Q1. The first input sub-circuit 3101A can include a tenth transistor T10, wherein a gate of the tenth transistor T10 is connected to the first control signal terminal CKA, a first electrode of the tenth transistor T10 is connected to the power supply signal terminal VGH, and a second electrode of the tenth transistor T10 is connected to the first pull-up node Q1.

[0148] The second input sub-circuit 3102A is connected to the input signal terminal IN, the first pull-down node QB1, and the first control signal terminal CKA. The second input sub-circuit 3102A can provide the signal at the input signal terminal IN to the first pull-down node QB1 under the control of the first control signal terminal CKA. For example, the second input sub-circuit 3102A includes an eleventh transistor T11, wherein the gate of the eleventh transistor T11 is connected to the first control signal terminal CKA, the first electrode of the eleventh transistor T11 is connected to the input signal terminal IN, and the second electrode of the eleventh transistor T11 is connected to the first pull-down node QB1.

[0149] As shown in FIG8 , the first control circuit includes a pull-up node control sub-circuit 3201A and a pull-down node control sub-circuit 3202A.

[0150] The pull-up node control subcircuit 3201A is connected to the first pull-up node Q1, the first pull-down node QB1, and the first control signal terminal CKA. The pull-up node control subcircuit 3201A can provide a signal at the first control signal terminal CKA to the first pull-up node Q1 under the control of the first pull-down node QB1. For example, the pull-up node control subcircuit 3201A may include a sixteenth transistor T16. The gate of the sixteenth transistor T16 is connected to the first pull-down node QB1, the first electrode of the sixteenth transistor T16 is connected to the first control signal terminal CKA, and the second electrode of the sixteenth transistor T16 is connected to the first pull-up node Q1.

[0151] The pull-down node control subcircuit 3202A is connected to the first pull-up node Q1, the first pull-down node QB1, the reference signal terminal VGL, and the second control signal terminal CKB of the shift register unit. The pull-down node control subcircuit 3202A can provide a signal at the reference signal terminal VGL to the first pull-down node QB1 under the control of the first pull-up node Q1 and the second control signal terminal CKB. For example, the pull-down node control subcircuit 3202A may include a seventeenth transistor T17 and an eighteenth transistor T18, wherein the gate of the seventeenth transistor T17 is connected to the first pull-up node Q1, the first electrode of the seventeenth transistor T17 is connected to the reference signal terminal VGL, the second electrode of the seventeenth transistor T17 is connected to the first electrode of the eighteenth transistor T18, the gate of the eighteenth transistor T18 is connected to the second control signal terminal CKB, and the second electrode of the eighteenth transistor T18 is connected to the first pull-down node QB1.

[0152] As shown in FIG8 , the second control circuit includes a first control sub-circuit 3301A, a second control sub-circuit 3302A, a third control sub-circuit 3303A, and a fourth control sub-circuit 3304A.

[0153] The first control sub-circuit 3301A is connected to a first pull-up node Q1, a first pull-down node QB1, a power supply signal terminal VGH, a first control signal terminal CKA, and a third pull-up node Q3 of the shift register unit. Under control of the first pull-down node QB1 and the first pull-up node Q1, the first control sub-circuit 3301A can provide a signal from either the power supply signal terminal VGH or the first control signal terminal CKA to the third pull-up node Q3. For example, the first control sub-circuit 3301A includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the first pull-up node Q1, the first electrode of the first transistor T1 is connected to the power supply signal terminal VGH, the second electrode of the first transistor T1 is connected to the third pull-up node Q3, the gate of the second transistor T2 is connected to the first pull-down node QB1, the first electrode of the second transistor T2 is connected to the first control signal terminal CKA, and the second electrode of the second transistor T2 is connected to the third pull-up node Q3.

[0154] The second control sub-circuit 3302A is connected to the first pull-up node Q1, the first pull-down node QB1, the reference signal terminal VGL, the second control signal terminal CKB of the shift register unit, and the fourth pull-up node Q4. Under the control of the first pull-down node QB1 and the first pull-up node Q1, the second control sub-circuit 3302A can provide a signal from one of the reference signal terminal VGL and the second control signal terminal CKB to the fourth pull-up node Q4. For example, the second control sub-circuit 3302A may include a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2. A gate of the third transistor T3 is connected to the first pull-up node Q1, a first electrode of the third transistor T3 is connected to the second control signal terminal CKB, a second electrode of the third transistor T3 is connected to the fourth pull-up node Q4, a first electrode of the first capacitor C1 is connected to the first pull-up node Q1, a second electrode of the first capacitor C1 is connected to the fourth pull-up node Q4, a gate of the fourth transistor T4 is connected to the first pull-down node QB1, a first electrode of the fourth transistor T4 is connected to the reference signal terminal VGL, a second electrode of the fourth transistor T4 is connected to the fourth pull-up node Q4, a first electrode of the second capacitor C2 is connected to the first pull-down node QB1, and a second electrode of the second capacitor C2 is connected to the reference signal terminal VGL.

[0155] The third control subcircuit 3303A is connected to the second pull-up node Q2, the fourth pull-up node Q4, and the second control signal terminal CKB. The third control subcircuit 3303A can provide a signal from the fourth pull-up node Q4 to the second pull-up node Q2 under the control of a signal from the second control signal terminal CKB. For example, the third control subcircuit 3303A includes a fifth transistor T5, wherein the gate of the fifth transistor T5 is connected to the second control signal terminal CKB, the first electrode of the fifth transistor T5 is connected to the fourth pull-up node Q4, and the second electrode of the fifth transistor T5 is connected to the second pull-up node Q2.

[0156] The fourth control sub-circuit 3304A is connected to the power supply signal terminal VGH, a first pull-down node QB1, and a second pull-down node QB2. Under control of the signal at the power supply signal terminal VGH, the fourth control sub-circuit 3304A can provide a signal from the first pull-down node QB1 to the second pull-down node QB2. The fourth control sub-circuit 3304A may include a sixth transistor T6, having a gate connected to the power supply signal terminal VGH, a first electrode connected to the first pull-down node QB1, and a second electrode connected to the second pull-down node QB2.

[0157] As shown in FIG8 , the second control circuit further includes a ninth transistor T9 , a gate of which is connected to the first pull-down node QB1 , a first electrode of which is connected to the reference signal terminal VGL, and a second electrode of which is connected to the second pull-up node Q2 .

[0158] As shown in FIG. 8 , the output circuit 340A may include a twelfth transistor T12 , a thirteenth transistor T13 , and a fourth capacitor C4 .

[0159] A gate of the twelfth transistor T12 is connected to the second pull-up node Q2 , a first electrode of the twelfth transistor T12 is connected to the reference signal terminal VGL, and a second electrode of the twelfth transistor T12 is connected to the output signal terminal GOUT.

[0160] A gate of the thirteenth transistor T13 is connected to the second pull-down node QB2 , a first electrode of the thirteenth transistor M13 is connected to the power signal terminal VGH, and a second electrode of the thirteenth transistor T13 is connected to the output signal terminal GOUT.

[0161] A first electrode of the fourth capacitor C4 is connected to the second pull-up node Q2 , and a second electrode of the fourth capacitor C4 is connected to the reference signal terminal VGL.

[0162] As shown in FIG8 , the output circuit 340A further includes a fourteenth transistor T14 and a fifteenth transistor T15. The first electrode of the twelfth transistor T12 is connected to the reference signal terminal VGL via the fourteenth transistor T14. The gate of the fourteenth transistor T14 is connected to the second pull-up node Q2. The first electrode of the fourteenth transistor T14 is connected to the reference signal terminal VGL, and the second electrode of the fourteenth transistor T14 is connected to the first electrode of the twelfth transistor T12. The gate of the fifteenth transistor T15 is connected to the output signal terminal GOUT. The first electrode of the fifteenth transistor T15 is connected to the power supply signal terminal VGH, and the second electrode of the fifteenth transistor T15 is connected to the first electrode of the twelfth transistor T12. The presence of the fourteenth transistor T14 and the fifteenth transistor T15 can prevent leakage in the twelfth transistor T12. For example, when the second pull-up node Q2 is low and the output signal terminal GOUT is high, the twelfth transistor T12 is in the off state. Without the fourteenth transistor T14 and the fifteenth transistor T15, the first electrode and the second electrode of the twelfth transistor T12 would be high and low, respectively, resulting in an excessive voltage difference between the two electrodes and leakage. By providing the fourteenth transistor T14 and the fifteenth transistor T15, a high level at the output signal terminal GOUT turns on the fifteenth transistor T15, thereby placing both the first and second electrodes of the twelfth transistor at high levels, reducing the voltage difference therebetween. A low level at the second pull-up node Q2 turns off the fourteenth transistor T14, thereby isolating the first electrode of the twelfth transistor T12 from the reference signal terminal VGL. This prevents leakage.

[0163] As shown in Figure 8, the first adjustment circuit 350A may include a seventh transistor T7 and a third capacitor C3, and the seventh transistor T7 and the third capacitor C3 are connected in series between the first pull-down node QB1 and the third pull-up node Q3, wherein the first electrode of the third capacitor C3 is connected to the third pull-up node Q3, the second electrode of the third capacitor C3 is connected to the first electrode of the seventh transistor T7, the gate of the seventh transistor T7 is connected to the third control signal terminal CKD of the shift register unit, and the second electrode of the seventh transistor T7 is connected to the first pull-down node QB1.

[0164] As shown in FIG8 , the second adjustment circuit 360A may include an eighth transistor T8, a fourth capacitor C4, and a fifth capacitor C5. The gate of the eighth transistor T8 is connected to the fourth control signal terminal CKC of the shift register unit, the first electrode of the eighth transistor T8 is connected to the second control signal terminal CKB of the shift register unit, the second electrode of the eighth transistor T8 is connected to the first electrode of the fourth capacitor C4, the second electrode of the fourth capacitor C4 is connected to the second pull-down node QB2, the first electrode of the fifth capacitor C5 is connected to the power signal terminal VGH, and the second electrode of the fifth capacitor C5 is connected to the second electrode of the eighth transistor T8.

[0165] In some embodiments, at least one of the sixth transistor T6 and the eleventh transistor T11 is a low-temperature polysilicon transistor. However, the embodiments of the present disclosure are not limited thereto. In any embodiment of the shift register unit described above, at least one transistor may be a low-temperature polysilicon transistor. In some embodiments, the transistors T1 to T18 described above may all be low-temperature polysilicon transistors.

[0166] At least a portion of the transistors involved in the embodiment described above with reference to FIG8 can be implemented using N-type transistors, such as N-type low-temperature polysilicon (LTPS). For example, at least one of transistors T6 and T11 is an N-type LTPS transistor. In some embodiments, all transistors in the shift register unit of FIG8 can be implemented using N-type LTPS transistors. Since the drive signal of the sub-pixel is often an active-low signal, how to use N-type transistors to output an active-low pulse waveform becomes a challenge. In addition, the off-state current of the low-temperature polysilicon transistor is too large and is prone to leakage, making the circuit unstable. According to the embodiment described above with reference to FIG8, a shift register unit implemented based on N-type transistors can be provided, which can generate an active-low output signal and, by providing at least one of a first adjustment circuit and a second adjustment circuit, can effectively alleviate leakage at the first pull-down node and / or the second pull-down node. For example, by increasing the potential at the first pull-down node and / or the second pull-down node, the leakage time of transistors T6 and T11 is prolonged, thereby reducing the leakage rate.

[0167] FIG9 shows a circuit diagram of a shift register unit 300B according to another embodiment of the present disclosure. The shift register unit 300B of FIG9 is similar to the shift register unit 300A of FIG8 , differing at least in that the first adjustment circuit is different. For the sake of brevity and clarity, the following will focus on the differences.

[0168] As shown in FIG9 , the first adjustment circuit 350B may include a seventh transistor T7 and a third capacitor C3, which are connected in series between the first pull-down node QB1 and the third pull-up node Q3. Unlike FIG8 , the positions of the seventh transistor T7 and the third capacitor C3 are swapped. That is, the first electrode of the seventh transistor T7 is connected to the third pull-up node Q3, the second electrode of the seventh transistor T7 is connected to the first electrode of the third capacitor C3, the second electrode of the third capacitor C3 is connected to the first pull-down node QB1, and the gate of the seventh transistor T7 is connected to the third control signal terminal CKD.

[0169] Embodiments of the present disclosure also provide a method for controlling a shift register unit. During an input phase, an input circuit provides signals from an input signal terminal and a reference signal terminal to a first pull-up node and a first pull-down node. During an output phase, a first control circuit controls the potential of the first pull-up node based on the potential of the first pull-down node and controls the potential of the first pull-down node based on the potential of the first pull-up node. A second control circuit provides the signal from the first pull-up node to a second pull-up node and provides the signal from the first pull-down node to a second pull-down node, such that the second pull-up node is at a low level and the second pull-down node is at a high level. Under the control of the second pull-up node and the second pull-down node, the output circuit provides the signal from the clock signal terminal to the output signal terminal. During the reset phase, the first control circuit controls the potential of the first pull-up node based on the potential of the first pull-down node, and controls the potential of the first pull-down node based on the potential of the first pull-up node. The second control circuit provides the signal of the first pull-up node to the second pull-up node and the signal of the first pull-down node to the second pull-down node, causing the second pull-up node to change from a low level to a high level and the second pull-down node to change from a high level to a low level. The output circuit, under the control of the second pull-up node and the second pull-down node, provides the signal of the reference signal terminal to the output signal terminal. During the reset phase, the first adjustment circuit lowers the potential of the first pull-down node after the first pull-down node changes from a high level to a low level, and / or the second adjustment circuit lowers the potential of the second pull-down node after the second pull-down node changes from a high level to a low level. This will be explained in detail below with reference to the signal timing of Figure 10.

[0170] Figure 10 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure. This timing diagram can be applied to an embodiment of the shift register unit implemented based on a P-type transistor of the present disclosure, so that it generates a gate drive signal or a light-emitting control signal. For ease of explanation, the shift register unit of Figure 4 will be used as an example for explanation below. The control method may include an input stage, an output stage, and a reset stage. In Figure 10, the input stage includes period P1, the output stage includes periods P2 to P4, and the reset stage includes P5 and P6.

[0171] During period P1, the input signal terminal IN and the first control signal terminal CKA are at a low level. The tenth transistor M10 and the eleventh transistor M11 are turned on, thereby providing the low level of the reference signal terminal VGL to the first pull-down node QB1 and the low level of the input signal terminal IN to the first pull-up node Q1. The low level of the first pull-up node Q1 turns on the third transistor M3. Since the sixteenth transistor M16 is in the on state, the low level of the input signal terminal IN is written to the third pull-up node Q3. The low levels of the first pull-up node Q1 and the fourth pull-up node Q4 turn on the fourth transistor M4, thereby writing the low level to the second pull-up node Q2. The low level of the second pull-up node Q2 turns on the thirteenth transistor M13, thereby providing the low level of the clock signal terminal GCK to the output signal terminal GOUT. Since the second transistor M2 is in the on state, the low level of the reference signal terminal VGL is written to the second pull-down node QB2. The low level of the second pull-down node QB2 turns on the twelfth transistor M12 , thereby providing the low level of the reference signal terminal VGL to the output signal terminal GOUT, and the output signal terminal GOUT maintains a low level.

[0172] During period P2, the input signal terminal IN remains at a low level, the first control signal terminal CKA becomes high, and the tenth transistor M10 and the eleventh transistor M11 are disconnected. At this time, the low level of the first pull-up node Q1 turns on the seventeenth transistor M17, thereby providing the high level of the first control signal terminal CKA to the first pull-down node QB1 and the second pull-down node QB2. The low level of the first pull-up node Q1 keeps the third transistor M3 turned on. The turned-on third transistor M3 and fourth transistor M4 keep the third pull-up node Q3 and the second pull-up node Q2 at a low level, thereby keeping the thirteenth transistor M13 in the on state. Since the clock signal terminal GCK jumps from a low level to a high level during period P2, the output signal terminal GOUT also jumps from a low level to a high level following the waveform of the clock signal terminal GCK.

[0173] In period P3, the first pull-up node Q1 and the second pull-up node Q2 are still maintained at a low level, the first pull-down node QB1 and the second pull-down node QB2 are still maintained at a high level, and the turned-on thirteenth transistor M13 continues to provide the high level of the clock signal terminal GCK to the output signal terminal GOUT, so that the output signal terminal GOUT continues to output a high level. The turned-on fifteenth transistor M15 provides the low level of the second control signal terminal CKB to the cascade output terminal CR, so that the output signal CR of the cascade output terminal CR is <n>is low level.

[0174] In period P4, the first pull-up node Q1 and the second pull-up node Q2 are still maintained at a low level, the first pull-down node QB1 and the second pull-down node QB2 are still maintained at a high level, and the turned-on thirteenth transistor M13 provides the low level of the clock signal terminal GCK to the output signal terminal GOUT, so that the output signal terminal GOUT outputs a low level.

[0175] During period P5, the first control signal terminal CKA is at a low level. While the first control signal terminal CKA is at a low level, the tenth transistor M10 and the eleventh transistor M11 are turned on. The turned-on tenth transistor M10 provides the low level of the reference signal terminal VGL to the first pull-down node QB1, which is then transmitted to the second pull-down node QB2 via the turned-on transistor M2. The turned-on eleventh transistor M11 provides the high level of the input signal terminal IN to the first pull-up node Q1, which is then transmitted to the fourth pull-up node Q4 via the turned-on sixteenth transistor M16. The potentials of the first pull-up node Q1 and the fourth pull-up node Q4 cause the third transistor M3 and the fourth transistor M4 to turn off, thereby maintaining the second pull-up node Q2 at a low level. The low level of the second pull-up node Q2 turns off the thirteenth transistor M13, and the low level of the second pull-down node QB2 turns on the twelfth transistor M12, thereby providing the low level of the reference signal terminal VGL to the output signal terminal GOUT.

[0176] During period P6, the first control signal terminal CKA is at a high level, the tenth transistor M10 and the eleventh transistor M11 are both turned off, the first pull-down node QB1 and the second pull-down node QB2 remain at a low level, and the first pull-up node Q1 and the fourth pull-up node Q4 remain at a high level. The low level of the first pull-down node QB1 turns on the first transistor M1, thereby providing the high level of the first control signal terminal CKA to the third pull-down node Q3. The second control signal terminal CKB is at a low level, turning on the fifth transistor M5, thereby providing the high level of the third pull-up node Q3 to the second pull-down node Q2.

[0177] At this point, the shift register unit completes signal output.

[0178] As shown in FIG10 , the active level duration of the signal at the first control signal terminal CKA does not overlap with the active level duration of the signal at the second control signal terminal CKB. In some embodiments, the active level duration of the signal at the first control signal terminal CKA partially overlaps with the active level duration of the signal at the third control signal terminal CKD. This allows the first adjustment circuit, under the control of the third control signal terminal CKD, to lower the potential of the first pull-down node QB1 after the first pull-down node QB1 transitions from a high level to a low level during the reset phase. For example, during the transition from period P4 to period P5 (which can be defined as the period between the falling edge of the signal at the third control signal terminal CKA falling into period P4 and the rising edge falling into period P5), the active level duration of the signal at the third control signal terminal CKD partially overlaps with the active level duration of the signal at the first control signal terminal CKA, causing the first control signal terminal CKA to transition from a high level to a low level while the third control signal terminal CKD remains at a low level. The level transition at the first control signal terminal CKA causes the tenth transistor M10 to turn on and then off, thereby providing the low level of the reference signal terminal VGL to the first pull-down node QB1. The low level of the first pull-down node QB1 turns on the first transistor M1, thereby providing the signal of the first control signal terminal CKA to the third pull-up node Q3, thereby causing the third pull-up node Q3 to also transition from a high level to a low level. Since the third control signal terminal CKD remains at a low level during this transition phase, the transition from a high level to a low level of the third pull-up node Q3 is transmitted to the first electrode of the first capacitor C1, causing the first electrode of the first capacitor to transition from a high level to a low level. The bootstrap effect of the first capacitor C1 further reduces the potential of the second electrode of the first capacitor, thereby further reducing the potential of the first pull-down node QB1, that is, to a level lower than the level at the reference signal terminal VGL. After the transition phase ends (i.e., after the third control signal terminal CKD becomes high), the sixth transistor M6 remains off, so that the potential of the first pull-down node QB1 is no longer affected by the level change of the third pull-up node Q3.

[0179] In some embodiments, the active level duration of the second control signal terminal CKB partially overlaps with the active level duration of the fourth control signal terminal CKC, such that during the reset phase, the second adjustment circuit, under the control of the fourth control signal terminal CKC, lowers the potential of the second pull-down node QB2 after the second pull-down node QB2 changes from a high level to a low level. For example, during the transition from period P5 to period P6 (which can be defined as the period between the falling edge of the fourth control signal terminal CKC falling into period P5 and the rising edge of the fourth control signal terminal CKC falling into period P6), the second control signal terminal CKB transitions from a high level to a low level, the fourth control signal terminal CKC remains at a low level, and the seventh transistor M7 is turned on, thereby transmitting the transition of the second control signal terminal CKB from a high level to a low level to the first electrode of the second capacitor C2. The voltage at the second pull-down node QB2 is further pulled down by the bootstrapping effect of the second capacitor C2, i.e., to a level lower than the voltage at the reference signal terminal VGL. After the transition phase ends, ie, after the fourth control signal terminal CKC becomes high, the seventh transistor M7 remains turned off, so that the potential of the second pull-down node QB2 is no longer affected by the level change of the second control signal terminal CKB.

[0180] In some embodiments, the gate of the seventh transistor M7 may also be connected to the third control signal terminal CKD, and the first electrode of the seventh transistor M7 may also be connected to the first control signal terminal CKA. In this case, the second pull-down node QB2, like the first pull-down node QB1, will be further pulled down to a level lower than the level at the reference signal terminal VGL during the P5 phase.

[0181] In an embodiment of the present disclosure, at least one of the tenth transistor M10 and the second transistor M2 may be a low-temperature polysilicon (LTPS) transistor. When the second transistor M2 and the tenth transistor M10 are in a positive drift or operating at a low frequency, leakage occurs in the off state due to the inherent characteristics of low-temperature polysilicon (LTPS). This creates a leakage path during the reset phase, namely, "second pull-down node QB2 - first transistor M1 - first pull-down node QB1 - tenth transistor M10 - reference signal terminal VGL." In this case, the second pull-down node QB2 is pulled to the potential of the reference signal terminal VGL. However, the threshold voltage of the twelfth transistor M12 in the output circuit is negative, so the twelfth transistor M12 cannot output the full potential of VGL (Vgs - Vth > 0, where Vgs represents the gate-source voltage of the twelfth transistor and Vth represents the threshold voltage of the twelfth transistor M12). Consequently, the output signal terminal GOUT is in a floating state, making the output susceptible to interference from external signals or other AC signals, resulting in output anomalies and circuit failure.

[0182] In an embodiment of the present disclosure, by providing at least one of the first adjustment circuit and the second adjustment circuit, at least one of the first pull-down node QB1 and the second pull-down node QB2 can be pulled down to a lower potential during the reset phase, thereby extending the leakage time of the tenth transistor M10 and / or the second transistor M2, thereby achieving an anti-leakage effect.

[0183] In some embodiments, such as the shift register unit 200B shown in FIG. 5 , the first electrode of the tenth transistor M10 is connected to the second reference signal terminal VGL2, while the twelfth transistor M12 is connected to the first reference signal terminal VGL1. Because the potential of the second reference signal terminal VGL2 is lower than the potential of the first reference signal terminal VGL1, compared to the case where the tenth transistor M10 is connected to the first reference signal terminal VGL1, the original leakage path "second pull-down node QB2-first transistor M1-first pull-down node QB1-tenth transistor M10-reference signal terminal VGL1" becomes "second pull-down node QB2-first transistor M1-first pull-down node QB1-tenth transistor M10-second reference signal terminal VGL2." In other words, compared to the case where the tenth transistor M10 is connected to the first reference signal terminal VGL1, the tenth transistor M10 connected to the second reference signal terminal VGL2 can provide a lower potential to the second pull-down node QB2. At the same time, the presence of the first and second adjustment circuits can further lower the first and second pull-down nodes QB1 and QB2, reducing the Vds (Vds represents the source-drain voltage of the transistor) of the tenth transistor M10 and the second transistor M2, and significantly reducing the leakage rate. In this way, the twelfth transistor M12 is ensured to satisfy Vgs-Vth<0, the output signal terminal GOUT will not enter a floating state, and the output can be further stabilized.

[0184] Embodiments of the present disclosure also provide a method for controlling a shift register unit. During an input phase, an input circuit provides signals from an input signal terminal and a power signal terminal to a first pull-up node and a first pull-down node. During an output phase, a first control circuit controls the potential of the first pull-up node based on the potential of the first pull-down node and controls the potential of the first pull-down node based on the potential of the first pull-up node. A second control circuit provides the signal from the first pull-up node to a second pull-up node and provides the signal from the first pull-down node to a second pull-down node, such that the second pull-up node is at a high level and the second pull-down node is at a low level. Under the control of the second pull-up node and the second pull-down node, the output circuit provides the signal from the reference signal terminal to the output signal terminal. During the reset phase, the first control circuit controls the potential of the first pull-up node based on the potential of the first pull-down node and controls the potential of the first pull-down node based on the potential of the first pull-up node. The second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node changes from a high level to a low level and the second pull-down node changes from a low level to a high level. The output circuit provides the signal of the power supply signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node. During the reset phase, the first adjustment circuit increases the potential of the first pull-down node after the first pull-down node changes from a low level to a high level, and / or the second adjustment circuit increases the potential of the second pull-down node after the second pull-down node changes from a low level to a high level. This will be explained in detail below with reference to FIG.

[0185] FIG11 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure. This timing diagram can be applied to a shift register unit implemented based on N-type transistors in the present disclosure to generate a gate drive signal or a light-emitting control signal. For ease of explanation, the shift register unit of FIG8 will be used as an example for explanation.

[0186] In Figure 11 , the method also includes an input phase, an output phase, and a reset phase. The input phase includes a period P1, the output phase includes periods P2 to P5, and the reset phase includes periods P6 to P8.

[0187] In period P1, the input signal terminal IN is at a low level, the first control signal terminal CKA is at a high level, the tenth transistor T10, the twelfth transistor T12, the first transistor T1 and the eleventh transistor T11 are turned on, thereby providing the high level of the power supply signal terminal VGH to the first pull-up node Q1, and providing the low level of the input signal terminal IN to the first pull-down node QB1 and the second pull-down node QB2.

[0188] During period P2, the input signal terminal IN remains at a low level, the first control signal terminal CKA changes from a high level to a low level, the tenth transistor T10 and the eleventh transistor T11 are turned off, the first pull-up node Q1 remains at a high level, the first transistor T1 remains on, and the third pull-up node Q3 remains at a high level.

[0189] During period P3, the input signal terminal IN remains at a low level, the first control signal terminal CKA remains at a low level, and the second control signal terminal CKB changes from a low level to a high level. Since the first pull-up node Q1 remains at a high level, the third transistor T3 is in an on state, thereby writing the high level of the second control signal terminal CKB to the fourth pull-up node Q4. The high level of the second control signal terminal CKB turns on the fifth transistor T5, thereby writing the high level to the second pull-up node Q2. The high level of the second pull-up node Q2 turns on the twelfth transistor T12 and the fourteenth transistor T14, thereby providing the low level of the reference signal terminal VGL to the output signal terminal GOUT.

[0190] In period P4, the input signal terminal IN is maintained at a low level, the first pull-up node Q1 and the second pull-up node Q2 are maintained at a high level, the first pull-down node QB1 and the second pull-down node QB2 are maintained at a low level, the twelfth transistor T12 is turned on, and the thirteenth transistor T13 is turned off, so that the output signal terminal GOUT is maintained at a low level.

[0191] In period P5, the input signal terminal IN changes from a low level to a high level, the first control signal terminal CKA remains at a low level, the tenth transistor M10 and the eleventh transistor M11 are in the off state, so the first pull-up node Q1 and the second pull-up node Q2 still maintain a high level, the first pull-down node QB1 and the second pull-down node QB2 still maintain a low level, the twelfth transistor T12 is turned on, and the thirteenth transistor T13 is turned off, so that the output signal terminal GOUT still maintains a low level.

[0192] During period P6, the first control signal terminal CKA goes high, turning on both the tenth transistor T10 and the eleventh transistor T11. This provides the high level of the power supply signal terminal VGH to the first pull-up node Q1, and the high level of the input signal terminal IN to the first pull-down node QB1, and then to the second pull-down node QB2. The low level of the second control signal terminal CKB turns off the fifth transistor T5, and the high level of the first pull-down node QB1 turns on the ninth transistor T9, thereby providing the low level of the reference signal terminal to the second pull-up node Q2. The high levels of the first pull-up node Q1 and the first pull-down node QB1 respectively turn on the third transistor T3 and the fourth transistor T4, causing the fourth pull-up node Q4 to be at a low level. The low level of the second pull-up node Q2 turns off both the twelfth transistor and the fourteenth transistor T14. The high level of the second pull-down node QB2 turns on the thirteenth transistor, resulting in a high level output at the output signal terminal GOUT.

[0193] In period P7, the first control signal terminal CKA becomes a low level, the tenth transistor T10 and the eleventh transistor T11 are both turned off, and the high level of the first pull-down node QB1 turns on the sixteenth transistor T16, thereby providing the low level of the first control signal terminal CKA to the first pull-up node Q1, thereby completing the reset.

[0194] In some embodiments, the active level duration of the signal at the first control signal terminal CKA partially overlaps with the active level duration of the signal at the third control signal terminal CKD, such that during a reset phase, the first adjustment circuit, under the control of the third control signal terminal CKD, increases the potential of the first pull-down node QB1 after the first pull-down node QB1 transitions from a low level to a high level. For example, during the transition from period P5 to period P6 (which can be defined as the period between the rising edge of the signal at the third control signal terminal falling within period P5 and the falling edge of the signal at the third control signal terminal falling within period P6), the first control signal terminal CKA transitions from a low level to a high level, the third control signal terminal CKD remains at a high level, and the eleventh transistor T11 and the second transistor T2 are turned on, thereby providing the signal at the first control signal terminal CKA to the third pull-up node Q3. Due to the transition of the first control signal terminal CKA from a low level to a high level, the third pull-up node Q3 also transitions from a low level to a high level. During this stage, since the third control signal terminal CKD maintains a high level, the seventh transistor T7 is in the on state, thereby transmitting the jump of the third pull-up node Q3 from a low level to a high level to the first electrode of the third capacitor C3, so that the potential of the first pull-down node QB1 is further pulled up under the bootstrap effect of the third capacitor C3.

[0195] In some embodiments, the active level duration of the second control signal terminal CKB partially overlaps with the active level duration of the fourth control signal terminal CKC. This allows the second adjustment circuit, under the control of the fourth control signal terminal CKC, to increase the potential of the second pull-down node QB2 after the second pull-down node QB2 transitions from a low level to a high level during the reset phase. For example, during the transition from period P7 to period P8 (defined as the period between the rising edge of the fourth control signal terminal CKC falling within period P7 and the falling edge of period P8), the input signal terminal IN remains at a high level, the second control signal terminal CKB transitions from a low level to a high level, and the fourth control signal terminal CKC remains at a high level. The low level of the fourth control signal terminal CKC turns on the eighth transistor T8, thereby transmitting the transition of the second control signal terminal CKB from a low level to a high level to the second pull-down node QB2, causing the potential of the second pull-down node QB2 to be further increased by the bootstrap effect of the fourth capacitor C4. The presence of the fifth capacitor C5 can prevent the node between the eighth transistor T8 and the fourth capacitor C1 from floating, thereby further stabilizing the potential of the second pull-down node QB.

[0196] According to an embodiment of the present disclosure, by providing at least one of the first adjustment circuit and the second adjustment circuit, the potential of the first pull-down node and the second pull-down node can be further increased after being reset (i.e., after being reset to a high level), thereby extending the leakage time of the eleventh transistor T11 and / or the sixth transistor T6, thereby playing a role in preventing leakage.

[0197] FIG12 shows a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure.

[0198] As shown in FIG12 , the gate driving circuit 400 may include a plurality of shift register units GOA connected in cascade. <1> , GOA <2> , GOA <3> , GOA <4> , .... At least one of these shift register units can be implemented by the shift register unit of any of the above embodiments.

[0199] In FIG12 , the output signal terminal of each stage shift register unit is connected to the input signal terminal of the next stage shift register unit. For example, the first stage shift register unit GOA <1> The output signal terminal GOUT is connected to the second stage shift register unit GOA <2> The input signal terminal IN, the second stage shift register unit GOA <2> The output signal terminal GOUT is connected to the third-stage shift register unit GOA <3> The output signal terminal of the nth stage shift register unit can be connected to the input signal terminal of the n+ith stage shift register unit, where i can be set as needed, and the embodiment of the present disclosure does not limit this. The first stage shift register unit GOA <1> The input signal terminal IN receives the start signal STU. The waveform of the start signal determines the waveform of the output signal at the output signal terminal GOUT. That is to say, by adjusting the pulse width of the start signal, the pulse width of the output signal can be adjusted, thereby realizing pulse width modulation output.

[0200] As shown in FIG12 , the odd-numbered shift register units (eg GOA <1> , GOA <3> , ...) is connected to receive the first control signal Cka, the second control signal terminal CKB is connected to receive the second control signal Ckb, the third control signal terminal CKD is connected to receive the third control signal Ckd, and the fourth control signal terminal CKC is connected to receive the fourth control signal Ckc. In contrast, the even-numbered shift register units (e.g., GOA <2> , GOA <3> , ...) is connected to receive the second control signal Ckb, the second clock signal terminal CKB is connected to receive the first control signal Cka, the third control signal terminal CKD is connected to receive the fourth control signal Ckc, and the fourth control signal terminal CKC is connected to receive the third control signal Ckd. However, the embodiments of the present disclosure are not limited thereto, and the clock connection methods of the odd-numbered stages and the even-numbered stages can be interchanged, which will not be further described here.

[0201] In FIG12 , the output signal terminal GOUT of each shift register unit is used to connect to other shift registers in cascade connection, and is also used to provide scanning signals to the sub-pixels in the display area. However, the embodiments of the present disclosure are not limited to this. In the case where a separate control output terminal CR is provided in the shift register unit, the control output terminal CR can be used for cascade connection, while the output signal terminal GOUT is used to provide scanning signals to the sub-pixels in the display area.

[0202] Those skilled in the art will appreciate that the embodiments described above are exemplary and can be improved upon by those skilled in the art. The structures described in various embodiments can be freely combined without causing any conflicts in structure or principle.

[0203] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art will clearly understand that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and that the present disclosure is not limited to the exemplary embodiments described in the specification.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register unit, comprising: An input circuit connected to an input signal terminal, a reference signal terminal, a first pull-down node and a first pull-up node of the shift register unit, and configured to provide a signal of the input signal terminal to the first pull-up node and a signal of the reference signal terminal to the first pull-down node; a first control circuit, connected to the first pull-down node and the first pull-up node, for controlling a signal of the first pull-up node based on the first pull-down node and controlling a signal of the first pull-down node based on the first pull-up node; a second control circuit connected to the first pull-down node, the first pull-up node, the second pull-down node, and the second pull-up node of the shift register unit, and configured to provide a signal of the first pull-down node to the second pull-down node under the control of a reference signal terminal, and to control a signal of the second pull-up node based on the first pull-up node; an output circuit connected to the second pull-down node, the second pull-up node, the reference signal terminal, and the clock signal terminal and the output signal terminal of the shift register unit, and configured to provide a signal of one of the clock signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-down node and the second pull-up node; as well as At least one of a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is connected to the first pull-down node and the second control circuit, and the second adjustment circuit is connected to the second pull-down node and the output circuit.

2. The shift register unit according to claim 1, wherein: The first adjustment circuit is used to reduce the potential of the first pull-down node after the first pull-down node is reset, and the second adjustment circuit is used to reduce the potential of the second pull-down node after the second pull-down node is reset.

3. The shift register unit according to claim 1 or 2, wherein: The second control circuit comprises: A first control subcircuit, connected to the first pull-down node and the first control signal terminal and the third pull-up node of the shift register unit, for providing a signal of the first control signal terminal to the third pull-up node under the control of the first pull-down node; a second control subcircuit, connected to the reference signal terminal, the first pull-down node and the second pull-down node, for providing a signal of the first pull-down node to the second pull-down node under the control of a signal of the reference signal terminal; A third control subcircuit is connected to the first pull-up node, the reference signal terminal and the third pull-up node a point for providing the signal of the reference signal terminal to the third pull-up node under the control of the first pull-up node; and A fourth control subcircuit is connected to the second pull-up node, the third pull-up node and the second control signal terminal of the shift register unit, and is used to provide the signal of the third pull-up node to the second pull-up node under the control of the signals of the first pull-up node and the second control signal terminal.

4. The shift register unit according to claim 3, wherein: The first control subcircuit comprises a first transistor, a gate of the first transistor is connected to the first pull-down node, a first electrode of the first transistor is connected to the first control signal terminal, and a second electrode of the first transistor is connected to the third pull-up node; The second control subcircuit comprises a second transistor, a gate of the second transistor is connected to the reference signal terminal, a first electrode of the second transistor is connected to the first pull-down node, and a second electrode of the second transistor is connected to the second pull-down node; The third control subcircuit comprises a third transistor, a gate of the third transistor is connected to the first pull-up node, a first electrode of the third transistor is connected to the reference signal terminal, and a second electrode of the third transistor is connected to the third pull-up node; The fourth control subcircuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the first pull-up node, the first electrode of the fourth transistor is connected to the third pull-up node, the second electrode of the fourth transistor is connected to the second pull-up node, the gate of the fifth transistor is connected to the second control signal terminal, the first electrode of the fifth transistor is connected to the third pull-up node, and the second electrode of the fifth transistor is connected to the second pull-up node.

5. The shift register unit according to claim 3 or 4, wherein the first adjustment circuit comprises a sixth transistor and a first capacitor, wherein the sixth transistor and the first capacitor are connected in series between the first pull-down node and the third pull-up node, wherein the gate of the sixth transistor is connected to a third control signal terminal.

6. The shift register unit according to claim 5, wherein: A first electrode of the sixth transistor is connected to the third pull-up node, a second electrode of the sixth transistor is connected to a first electrode of the first capacitor, and a second electrode of the first capacitor is connected to the first pull-down node.

7. The shift register unit according to claim 5, wherein: A first electrode of the first capacitor is connected to the third pull-up node, a second electrode of the first capacitor is connected to a first electrode of the sixth transistor, and a second electrode of the sixth transistor is connected to the first pull-down node.

8. The shift register unit according to any one of claims 1 to 7, wherein: The second adjustment circuit includes a seventh transistor, a second capacitor and a third capacitor. Among them, the gate of the seventh transistor is connected to the fourth control signal terminal of the shift register unit, the first electrode of the seventh transistor is connected to the second control signal terminal of the shift register unit, the second electrode of the seventh transistor is connected to the first electrode of the second capacitor, the second electrode of the second capacitor is connected to the second pull-down node, the first electrode of the third capacitor is connected to the reference signal terminal, and the second electrode of the third capacitor is connected to the second electrode of the seventh transistor.

9. The shift register unit according to claim 8, wherein: The second adjustment circuit further includes an eighth transistor and a ninth transistor, The gate of the eighth transistor is connected to the reference signal terminal, the second electrode of the second transistor and the first electrode of the eighth transistor are connected to an intermediate node, the second electrode of the eighth transistor is connected to the second pull-down node, the gate of the ninth transistor is connected to the second pull-down node, the first electrode of the ninth transistor is connected to the reference signal terminal, and the second electrode of the ninth transistor is connected to the intermediate node.

10. The shift register unit according to any one of claims 1 to 9, wherein: The reference signal terminal includes a first reference signal terminal and a second reference signal terminal, and the potential of the second reference signal terminal is lower than the potential of the first reference signal terminal; The input circuit is connected to the first reference signal terminal or the second reference signal terminal, and the output circuit is connected to the first reference signal terminal.

11. The shift register unit according to claim 10, wherein: The second adjustment circuit includes a seventh transistor, a second capacitor and a third capacitor, wherein a first electrode of the third capacitor is connected to the first reference signal terminal.

12. The shift register unit according to claim 11, wherein: The second adjustment circuit further includes an eighth transistor and a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second reference signal terminal.

13. The shift register unit according to any one of claims 10 to 12, wherein: The input circuit comprises: a tenth transistor, wherein a gate of the tenth transistor is connected to the first control signal terminal, a first electrode of the tenth transistor is connected to the first reference signal terminal or the second reference signal terminal, and a second electrode of the tenth transistor is connected to the first pull-down node; An eleventh transistor, wherein a gate of the eleventh transistor is connected to the first control signal terminal, a first electrode of the eleventh transistor is connected to the input signal terminal, and a second electrode of the eleventh transistor is connected to the first pull-up node.

14. The method according to claim 13, wherein: At least one of the tenth transistor and the second transistor is a low temperature polysilicon transistor.

15. The shift register unit according to any one of claims 1 to 14, wherein: The output circuit comprises: a twelfth transistor, wherein a gate of the twelfth transistor is connected to the second pull-down node, a first electrode of the twelfth transistor is connected to the reference signal terminal, and a second electrode of the twelfth transistor is connected to the output signal terminal; a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the second pull-up node, a first electrode of the thirteenth transistor is connected to the clock signal terminal, and a second electrode of the thirteenth transistor is connected to the output signal terminal; A fourth capacitor, wherein a first electrode of the fourth capacitor is connected to the second pull-up node, and a second electrode of the fourth capacitor is connected to the output signal terminal.

16. The shift register unit according to any one of claims 1 to 15, further comprising: A cascade output circuit is connected to the first pull-down node, the first pull-up node, the power signal terminal, the second control signal terminal of the shift register unit, and the cascade output terminal, and is used to provide a signal from one of the power signal terminal and the second control signal terminal to the cascade output terminal under the control of the first pull-down node and the first pull-up node.

17. The shift register unit according to claim 16, wherein: The cascade output circuit includes a fourteenth transistor, a fifteenth transistor, a fifth capacitor and a sixth capacitor.

18. The shift register unit according to claim 17, wherein: The cascade output circuit also includes a sixteenth transistor, wherein the gate of the fifteenth transistor is connected to the first pull-up node through the sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the reference signal terminal, the first electrode of the sixteenth transistor is connected to the first pull-up node, and the second electrode of the sixteenth transistor is connected to the gate of the fifteenth transistor.

19. The shift register unit according to any one of claims 1 to 18, wherein: The first control circuit includes a seventeenth transistor, an eighteenth transistor and a nineteenth transistor, The gate of the seventeenth transistor is connected to the first pull-up node, the first electrode of the seventeenth transistor is connected to the first control signal terminal, and the second electrode of the seventeenth transistor is connected to the first pull-down node; The gate of the eighteenth transistor is connected to the first pull-down node, the first electrode of the eighteenth transistor is connected to the power signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the nineteenth transistor; A gate electrode of the nineteenth transistor is connected to the second control signal terminal, and a second electrode of the nineteenth transistor is connected to the first pull-up node.

20. The shift register unit according to any one of claims 1 to 19, wherein: At least one transistor in the input circuit, the first control circuit, the second control circuit, the first adjustment circuit, the second adjustment circuit, and the output circuit is a P-type transistor.

21. A shift register unit, comprising: An input circuit connected to an input signal terminal, a power signal terminal, a first pull-down node and a first pull-up node of the shift register unit, and configured to provide a signal of the input signal terminal to the first pull-down node and a signal of the power signal terminal to the first pull-up node; a first control circuit, connected to the first pull-down node and the first pull-up node, for controlling a signal of the first pull-up node based on the first pull-down node and controlling a signal of the first pull-down node based on the first pull-up node; a second control circuit connected to the first pull-down node, the first pull-up node, the second pull-down node, and the second pull-up node of the shift register unit, for controlling a signal of the second pull-down node based on the first pull-down node, and providing the signal of the first pull-up node to the second pull-up node under the control of the power signal terminal; an output circuit connected to the second pull-down node, the second pull-up node, the power signal terminal, and the reference signal terminal and the output signal terminal of the shift register unit, and configured to provide a signal of one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-down node and the second pull-up node; as well as At least one of a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is connected to the first pull-down node and the second control circuit, and the second adjustment circuit is connected to the second pull-down node and the output circuit.

22. The shift register unit according to claim 21, wherein: The first adjustment circuit is used to increase the potential of the first pull-down node after the first pull-down node is reset, and the second adjustment circuit is used to increase the potential of the second pull-down node after the second pull-down node is reset.

23. The shift register unit according to claim 21 or 22, wherein: The second control circuit comprises: a first control subcircuit, connected to the first pull-up node, the first pull-down node, the power signal terminal, and the first control signal terminal and the third pull-down node of the shift register unit, and configured to provide a signal of one of the power signal terminal and the first control signal terminal to the third pull-up node under the control of the first pull-down node and the first pull-up node; a second control subcircuit connected to the first pull-up node, the first pull-down node, the reference signal terminal, the second control signal terminal of the shift register unit, and a fourth pull-up node, and configured to, under the control of the first pull-down node and the first pull-up node, shift the reference signal terminal and the second control signal terminal to the reference signal terminal; A signal is provided to the fourth pull-up node; a third control subcircuit, connected to the second pull-up node, the fourth pull-up node and the second control signal terminal, for providing the signal of the fourth pull-up node to the second pull-up node under the control of the signal of the second control signal terminal; A fourth control subcircuit is connected to the power signal terminal, the first pull-down node and the second pull-down node, and is used to provide the signal of the first pull-down node to the second pull-down node under the control of the signal of the power signal terminal.

24. The shift register unit according to claim 23, wherein: The first control subcircuit includes a first transistor and a second transistor, the gate of the first transistor is connected to the first pull-up node, the first electrode of the first transistor is connected to the power signal terminal, the second electrode of the first transistor is connected to the third pull-up node, the gate of the second transistor is connected to the first pull-down node, the first electrode of the second transistor is connected to the first control signal terminal, and the second electrode of the second transistor is connected to the third pull-up node; The second control subcircuit comprises a third transistor, a fourth transistor, a first capacitor and a second capacitor, the gate of the third transistor is connected to the first pull-up node, the first electrode of the third transistor is connected to the second control signal terminal, the second electrode of the third transistor is connected to the fourth pull-up node, the first electrode of the first capacitor is connected to the first pull-up node, the second electrode of the first capacitor is connected to the fourth pull-up node, the gate of the fourth transistor is connected to the first pull-down node, the first electrode of the fourth transistor is connected to the reference signal terminal, the second electrode of the fourth transistor is connected to the fourth pull-up node, the first electrode of the second capacitor is connected to the first pull-down node, and the second electrode of the second capacitor is connected to the reference signal terminal; The third control subcircuit comprises a fifth transistor, a gate of the fifth transistor is connected to the second control signal terminal, a first electrode of the fifth transistor is connected to the fourth pull-up node, and a second electrode of the fifth transistor is connected to the second pull-up node; The fourth control subcircuit includes a sixth transistor, a gate of the sixth transistor is connected to the power signal terminal, a first electrode of the sixth transistor is connected to the first pull-down node, and a second electrode of the sixth transistor is connected to the second pull-down node.

25. According to the shift register unit according to claim 23 or 24, the first adjustment circuit comprises a seventh transistor and a third capacitor, the seventh transistor and the third capacitor are connected in series between the first pull-down node and the third pull-up node, and the gate of the seventh transistor is connected to the third control signal terminal.

26. The shift register unit according to claim 25, wherein: A first electrode of the seventh transistor is connected to the third pull-up node, a second electrode of the seventh transistor is connected to a first electrode of the third capacitor, and a second electrode of the third capacitor is connected to the first pull-down node.

27. The shift register unit according to claim 25, wherein: A first electrode of the third capacitor is connected to the third pull-up node, a second electrode of the third capacitor is connected to a first electrode of the seventh transistor, and a second electrode of the seventh transistor is connected to the first pull-down node.

28. The shift register unit according to any one of claims 21 to 27, wherein: The second adjustment circuit includes an eighth transistor, a fourth capacitor and a fifth capacitor, Among them, the gate of the eighth transistor is connected to the fourth control signal end of the shift register unit, the first electrode of the eighth transistor is connected to the second control signal end of the shift register unit, the second electrode of the eighth transistor is connected to the first electrode of the fourth capacitor, the second electrode of the fourth capacitor is connected to the second pull-down node, the first electrode of the fifth capacitor is connected to the power signal end, and the second electrode of the fifth capacitor is connected to the second electrode of the eighth transistor.

29. The shift register unit according to any one of claims 23 to 28, wherein: The second control circuit further includes: a ninth transistor, a gate of the ninth transistor is connected to the first pull-down node, a first electrode of the ninth transistor is connected to the reference signal terminal, and a second electrode of the ninth transistor is connected to the second pull-up node.

30. The shift register unit according to any one of claims 21 to 29, wherein: The input circuit comprises: a tenth transistor, wherein a gate of the tenth transistor is connected to the first control signal terminal, a first electrode of the tenth transistor is connected to the power signal terminal, and a second electrode of the tenth transistor is connected to the first pull-up node; An eleventh transistor, wherein a gate of the eleventh transistor is connected to the first control signal terminal, a first electrode of the eleventh transistor is connected to the input signal terminal, and a second electrode of the eleventh transistor is connected to the first pull-down node.

31. The method according to any one of claims 30, wherein: At least one of the eleventh transistor and the sixth transistor is a low temperature polysilicon transistor.

32. The shift register unit according to any one of claims 21 to 31, wherein: The output circuit comprises: a twelfth transistor, wherein a gate of the twelfth transistor is connected to the second pull-up node, a first electrode of the twelfth transistor is connected to the reference signal terminal, and a second electrode of the twelfth transistor is connected to the output signal terminal; a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the second pull-down node, and the thirteenth transistor The first electrode of the body tube is connected to the power signal terminal, and the second electrode of the thirteenth transistor is connected to the output signal terminal; A fourth capacitor, wherein a first electrode of the fourth capacitor is connected to the second pull-up node, and a second electrode of the fourth capacitor is connected to the reference signal terminal.

33. The shift register unit according to claim 32, wherein: The output circuit further includes a fourteenth transistor and a fifteenth transistor, wherein a first electrode of the twelfth transistor is connected to the reference signal terminal through the fourteenth transistor, wherein a gate of the fourteenth transistor is connected to the second pull-up node, a first electrode of the fourteenth transistor is connected to the reference signal terminal, and a second electrode of the fourteenth transistor is connected to the first electrode of the twelfth transistor; The gate of the fifteenth transistor is connected to the output signal terminal, the first electrode of the fifteenth transistor is connected to the power signal terminal, and the second electrode of the fifteenth transistor is connected to the first electrode of the twelfth transistor.

34. The shift register unit according to any one of claims 21 to 33, wherein: The first control circuit includes a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, A gate of a sixteenth transistor is connected to the first pull-down node, a first electrode of the sixteenth transistor is connected to the first control signal terminal, and a second electrode of the sixteenth transistor is connected to the first pull-up node; A gate of the seventeenth transistor is connected to the first pull-up node, a first electrode of the seventeenth transistor is connected to the reference signal terminal, and a second electrode of the seventeenth transistor is connected to the first electrode of the eighteenth transistor; A gate electrode of the eighteenth transistor is connected to the second control signal terminal, and a second electrode of the eighteenth transistor is connected to the first pull-down node.

35. The shift register unit according to any one of claims 21 to 34, wherein at least one transistor in the input circuit, the first control circuit, the second control circuit, the first adjustment circuit, the second adjustment circuit and the output circuit is an N-type transistor.

36. A method for controlling a shift register unit according to any one of claims 1 to 20, comprising: In the input stage, the input circuit provides a signal at the input signal terminal to the first pull-up node and provides a signal at the reference signal terminal to the first pull-down node; In the output stage, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and controls the signal of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node is at a low level and the second pull-down node is at a high level, and the output circuit provides the signal of the clock signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node; In the reset phase, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and The first pull-up node is used to control the signal of the first pull-down node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node changes from a low level to a high level and the second pull-down node changes from a high level to a low level, and the output circuit provides the signal of the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node; In which, in the reset stage, the first adjustment circuit reduces the potential of the first pull-down node after the first pull-down node changes from a high level to a low level, and / or the second adjustment circuit reduces the potential of the second pull-down node after the second pull-down node changes from a high level to a low level.

37. The method of claim 36, wherein: The second control circuit is connected to the first control signal terminal and the second control signal terminal, the first adjustment circuit is connected to the third control signal terminal, and the second adjustment circuit is connected to the fourth control signal terminal; Among them, the effective level duration period of the signal at the first control signal terminal partially overlaps with the effective level duration period of the signal at the third control signal terminal, so that in the reset stage, the first adjustment circuit reduces the potential of the first pull-down node after the first pull-down node changes from a high level to a low level under the control of the third control signal terminal; and / or the effective level duration period of the signal at the second control signal terminal partially overlaps with the effective level duration period of the signal at the fourth control signal terminal, so that in the reset stage, the second adjustment circuit reduces the potential of the second pull-down node after the second pull-down node changes from a high level to a low level under the control of the fourth control signal terminal.

38. A method for controlling a shift register unit according to any one of claims 21 to 35, comprising: In the input stage, the input circuit provides signals from the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node; In the output stage, the first control circuit controls the potential of the first pull-up node based on the first pull-down node and controls the potential of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node is at a high level and the second pull-down node is at a low level, and the output circuit provides the signal of the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node; In the reset phase, the first control circuit controls the signal of the first pull-up node based on the first pull-down node and controls the signal of the first pull-down node based on the first pull-up node, the second control circuit provides the signal of the first pull-up node to the second pull-up node and provides the signal of the first pull-down node to the second pull-down node, so that the second pull-up node changes from a high level to a low level and the second pull-down node changes from a low level to a high level, and the output circuit provides the signal of the power supply signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node; In which, in the reset stage, the first adjustment circuit increases the potential of the first pull-down node after the first pull-down node changes from a low level to a high level, and / or the second adjustment circuit increases the potential of the second pull-down node after the second pull-down node changes from a low level to a high level.

39. The method of claim 38, wherein: The second control circuit is connected to the first control signal terminal and the second control signal terminal, the first adjustment circuit is connected to the third control signal terminal, and the second adjustment circuit is connected to the fourth control signal terminal; Among them, the effective level duration period of the signal at the first control signal terminal partially overlaps with the effective level duration period of the signal at the third control signal terminal, so that in the reset stage, the first adjustment circuit increases the potential of the first pull-down node after the first pull-down node changes from a low level to a high level under the control of the third control signal terminal; and / or the effective level duration period of the signal at the second control signal terminal partially overlaps with the effective level duration period of the signal at the fourth control signal terminal, so that in the reset stage, the second adjustment circuit increases the potential of the second pull-down node after the second pull-down node changes from a low level to a high level under the control of the fourth control signal terminal.

40. A gate driving circuit, comprising a plurality of shift register units connected in cascade, wherein the shift register unit is the shift register unit according to any one of claims 1 to 37.

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