Vertical semiconductor device

Abstract

A semiconductor device is provided with a semiconductor substrate (10) having a cell region (1) in which a semiconductor element is formed and an outer peripheral region (2) surrounding the cell region (1), the cell region (1) being a region in which an impurity layer (14) is formed, a trench gate structure extending from the cell region (1) to the outer peripheral region (2), and a base layer (13) extending from the cell region (1) to the outer peripheral region (2). The contact hole (20a) extends from the cell region (1) to the outer peripheral region (2), and the upper electrode (21) is also connected to the base layer (13) via the contact hole (20a) in the outer peripheral region (2).

Description

[0001] Cross-reference to related applications

[0002] This application is based on Japanese Patent Application No. 2022-176618 filed on November 2, 2022, the contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a vertical semiconductor device having a trench gate structure. Background art

[0004] Conventionally, a vertical semiconductor device having a trench gate structure has been proposed (for example, refer to Patent Document 1). Specifically, a MOSFET (metal Oxide semiconductor field effect transistor) element is formed to constitute the vertical semiconductor device. More specifically, in the vertical semiconductor device, an n + -type drain region is formed with an n - -type drift layer, and a p-type base layer is formed on the drift layer. An n + -type source layer is formed on the surface portion of the base layer, and the trench gate structure is formed to penetrate the source layer and the base layer and reach the drift layer.

[0005] Prior art documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2013-84905 Summary of the invention

[0008] Such a vertical semiconductor device generally includes a cell region in which a MOSFET element is formed and an outer peripheral region that surrounds and disposes the cell region. In addition, the trench gate structure may extend from the cell region to the outer peripheral region so as to achieve electric field relaxation in the outer peripheral region.

[0009] However, in the vertical semiconductor device as described above, a parasitic bipolar transistor is formed by the drift layer, the base layer, and the source layer. And according to the research of the present inventors, it has been confirmed that when the trench gate structure is extended to the outer peripheral region, the parasitic bipolar transistor is likely to operate around the trench gate structure disposed in the outer peripheral region. Therefore, it is desired to improve the avalanche withstand voltage in such a manner that the parasitic bipolar transistor does not easily operate.

[0010] An object of the present disclosure is to provide a vertical semiconductor device capable of improving the avalanche withstand voltage.

[0011] According to one aspect of the present disclosure, a vertical semiconductor device is provided. A semiconductor element having a trench gate structure is formed. The semiconductor device includes a semiconductor substrate having a cell region where the semiconductor element is formed and a peripheral region surrounding the cell region. The cell region includes a drift layer of a first conductivity type; a base layer of a second conductivity type formed on the drift layer; an impurity layer of the first conductivity type formed on the surface portion of the base layer, the impurity concentration of which is higher than that of the drift layer; a trench gate structure in which a gate electrode is disposed in a trench with a gate insulating film interposed therebetween, the trench penetrating through the impurity layer and the base layer to reach the drift layer and extending along the plane direction of the semiconductor substrate; a high-concentration layer of the first conductivity type or the second conductivity type formed on the opposite side of the base layer across the drift layer, the impurity concentration of which is higher than that of the drift layer; an interlayer insulating film formed on one surface of the semiconductor substrate, and contact holes are formed to expose the base layer and the impurity layer; a first electrode electrically connected to the impurity layer and the base layer via the contact holes; and a second electrode electrically connected to the high-concentration layer. The region where the impurity layer is formed is set as the cell region, the trench gate structure extends from the cell region to the peripheral region, the base layer extends from the cell region to the peripheral region, the contact holes extend from the cell region to the peripheral region, and the first electrode is also connected to the base layer via the contact holes in the peripheral region.

[0012] Thus, when the vertical semiconductor device performs an avalanche operation, carriers (e.g., holes) are easily extracted from the first electrode through the base layer in the peripheral region. Therefore, an improvement in avalanche withstand voltage can be achieved, and the operation of the parasitic bipolar transistor can be suppressed.

[0013] In addition, the reference numerals in parentheses attached to each component etc. represent an example of the correspondence relationship between the component etc. and the specific components etc. described in the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view of the vertical semiconductor device according to the first embodiment.

[0015] Figure 2 is along Figure 1 sectional view taken along line II-II in

[0016] Figure 3 is along Figure 1 sectional view taken along line III-III in

[0017] Figure 4 is a schematic diagram showing Figure 1 the circuit structure of the vertical semiconductor device shown in

[0018] Figure 5 is a graph showing the relationship between the adjustment distance and the avalanche withstand voltage.

[0019] Figure 6 This is a cross-sectional view of the vertical semiconductor device of the second embodiment. Detailed Embodiment

[0020] Hereinafter, embodiments of the present disclosure will be described based on the drawings. In addition, in the following embodiments, the same or equivalent parts are denoted by the same reference numerals for description.

[0021] (First Embodiment)

[0022] The first embodiment will be described with reference to the drawings. In addition, the vertical semiconductor device of the present embodiment is mounted on a vehicle such as an automobile, and is preferably applied as a device for driving various in-vehicle electronic devices.

[0023] As Figure 1 shown, the vertical semiconductor device of the present embodiment has a cell region 1 and a peripheral region 2. In addition, although it will be described in detail later, the vertical semiconductor device of the present embodiment is configured to form an n-channel MOSFET element having a source layer 14 as a semiconductor element. And, in the present embodiment, the cell region 1 and the peripheral region 2 are divided according to whether the source layer 14 is formed, and the portion where the source layer 14 is formed is set as the cell region 1. In other words, the portion that actually functions as a MOSFET element is set as the cell region 1, and the portion that does not function as a MOSFET element is set as the peripheral region 2. In addition, in Figure 1 , the interlayer insulating film 20 and the upper electrode 21 described later are omitted. In addition, Figure 1 Although it is not a cross-sectional view, for easy understanding, the gate insulating film 17 and the gate electrode 18 described later are shaded.

[0024] As Figure 2 and Figure 3 shown, the vertical semiconductor device of the present embodiment is formed using a semiconductor substrate 10 having a substrate 11 made of an n + -type silicon substrate or the like with a high impurity concentration. On the surface of the substrate 11, an n - -type drift layer 12 having an impurity concentration lower than that of the substrate 11 is formed. In addition, in the present embodiment, the substrate 11 functions as a drain region and corresponds to a high-concentration layer.

[0025] In the surface portion of the drift layer 12, a p-type base layer 13 with a relatively low impurity concentration is formed. The base layer 13 is formed, for example, by ion-implanting p-type impurities into the drift layer 12 and functions as a channel layer for forming a channel region. In the present embodiment, the base layer 13 includes a base region 13a and a base contact region 13b. The base region 13a is located on the side of the drift layer 12, and the base contact region 13b has a higher impurity concentration than the base region 13a and is formed on the base region 13a. Moreover, the base layer 13 of the present embodiment extends from the unit region 1 to the peripheral region 2.

[0026] In addition, in the surface portion of the base layer 13, an n + -type source layer 14 with an impurity concentration higher than that of the drift layer 12 is formed. The source layer 14 is formed between the plurality of trenches 16 described later in a manner that abuts against the side surfaces of the trenches 16. Further, the base contact region 13b is formed on the opposite side of the trench 16 described later with the source layer 14 interposed therebetween.

[0027] In the present embodiment, the region where the source layer 14 is formed is defined as the unit region 1. In addition, in the longitudinal direction (i.e., the extending direction) of the trench 16 described later, the base contact region 13b may be formed to coincide with the source layer 14 or may be formed to slightly protrude from the unit region 1 toward the peripheral region 2. In the present embodiment, the source layer 14 corresponds to an impurity layer. Regarding the semiconductor substrate 10, the side of the substrate 11 is defined as the other surface 10b, and the side of the base layer 13 and the source layer 14 is defined as the one surface 10a.

[0028] In the semiconductor substrate 10, a plurality of trenches 16 are formed so as to penetrate the base layer 13 and the source layer 14 from the one surface 10a side and reach the drift layer 12. The plurality of trenches 16 are formed to be arranged along a direction intersecting with one direction in the plane direction of the semiconductor substrate 10 with one direction in the plane direction of the semiconductor substrate 10 as the longitudinal direction. More specifically, the plurality of trenches 16 are arranged in parallel at equal intervals to form a strip-shaped layout. In addition, in Figure 1 the trenches 16 extend in the left-right direction of the paper surface as the longitudinal direction and are arranged in the up-down direction of the paper surface. Further, each trench 16 is formed such that both end portions in the longitudinal direction protrude from the unit region 1 toward the peripheral region 2.

[0029] The inner wall surface of the trench 16 is covered with a gate insulating film 17. In the trench 16, a gate electrode 18 made of doped polysilicon is disposed with the gate insulating film 17 interposed therebetween.

[0030] On the one surface 10a side of the semiconductor substrate 10, an interlayer insulating film 20 made of an oxide film or the like is formed so as to cover the gate electrode 18. In the interlayer insulating film 20, contact holes 20a for exposing the source layer 14 and the base layer 13 are formed.

[0031] Here, the contact hole 20a of the present embodiment is formed to protrude from the source layer 14 in the longitudinal direction of the trench 16. In other words, the contact hole 20a is formed to expose the base layer 13 located in the outer peripheral region 2. However, the contact hole 20a is formed to terminate at a position closer to the unit region 1 side than the end portion in the longitudinal direction of the trench 16. In addition, in Figure 1 , the contact hole 20a is indicated by a dashed line. That is, in Figure 1 , the region surrounded by the dashed line becomes the region exposed from the interlayer insulating film 20.

[0032] And, an upper electrode 21 corresponding to the source electrode is formed on the interlayer insulating film 20. Specifically, the upper electrode 21 is formed in the unit region 1 to be connected to the source layer 14 and the base contact region 13b (i.e., the base layer 13) through the contact hole 20a. In addition, the upper electrode 21 is formed in the outer peripheral region 2 to be connected to the base layer 13 through the contact hole 20a. In addition, in the present embodiment, the upper electrode 21 corresponds to the first electrode.

[0033] On the other side 10b side of the substrate 11, a lower electrode 22 corresponding to the drain electrode is formed. In addition, in the present embodiment, the lower electrode 22 corresponds to the second electrode.

[0034] The above is the structure of the vertical semiconductor device of the present embodiment. In addition, in the present embodiment, n - -type, n-type, n + -type corresponds to the first conductivity type, and p-type, p + -type corresponds to the second conductivity type. In addition, in the present embodiment, as described above, the semiconductor substrate 10 is constituted by including the substrate 11, the drift layer 12, the base layer 13, the source layer 14, etc.

[0035] Next, the operation and effects of the above vertical semiconductor device will be described. First, in the vertical semiconductor device as described above, by applying a voltage equal to or higher than the threshold voltage of the insulated gate structure to the gate electrode 18, a channel region is formed in the portion of the base layer 13 in contact with the trench 16, and a current flows between the source and the drain to become a conductive state. In addition, if the voltage applied to the gate electrode 18 becomes less than the threshold voltage, the channel region formed in the base layer 13 disappears, and the current is cut off to become an off state.

[0036] And, the vertical semiconductor device as described above becomes Figure 4A circuit structure as shown. That is, the vertical semiconductor device of the present embodiment has a circuit structure including a MOS transistor MTr, a parasitic bipolar transistor PTr formed by a drift layer 12, a base layer 13, and a source layer 14, a depletion capacitance DC, and an internal resistance R of the base layer 13. And, in the vertical semiconductor device as described above, when changing from the on state to the off state, avalanche breakdown may occur and an excessive current may flow between the source and the drain.

[0037] Therefore, in the present embodiment, the contact hole 20a extends to the peripheral region 2, and the base layer 13 is electrically connected to the upper electrode 21 in the peripheral region 2. Thus, when the vertical semiconductor device performs an avalanche operation, holes can be easily extracted from the upper electrode 21 through the base layer 13 in the peripheral region 2. That is, the area where the internal resistance R of the base layer 13 becomes smaller increases. Therefore, the avalanche tolerance can be improved, and the operation of the parasitic bipolar transistor PTr can be suppressed.

[0038] Here, as Figure 4 shown, the length of the contact hole 20a protruding from the cell region 1 to the peripheral region 2 is set as the adjustment distance d. That is, the length of the contact hole 20a protruding from the source layer 14 toward the peripheral region 2 is set as the adjustment distance d. In other words, the length of the base layer 13 connected to the upper electrode 21 in the peripheral region 2 along the length direction of the trench 16 is set as the adjustment distance d. In this case, the longer the adjustment distance d is, the easier it is to extract holes from the upper electrode 21. However, according to the research of the present inventors, as Figure 5 shown, it is confirmed that the avalanche tolerance hardly changes when the adjustment distance d is 0.1 μm or more. Therefore, in the present embodiment, the adjustment distance d is set to 0.1 μm or more.

[0039] In addition, Figure 5 shows the result of setting the substrate 11 to 1×10 18 to 1×10 20 cm -3 in each impurity concentration, setting the drift layer 12 to 1×10 16 to 1×10 18 cm -3 , setting the base region 13a to 1×10 13 cm -3 , setting the base contact region 13b to 1×10 15 to 1×10 16 cm -3 or so, and setting the source layer 14 to 1×10 13 cm -3 or so.

[0040] As described above, in the present embodiment, the contact hole 20a extends from the unit region 1 to the peripheral region 2, and the upper electrode 21 is also connected to the base layer 13 in the peripheral region 2. Therefore, when the vertical semiconductor device performs an avalanche operation, holes are easily extracted from the upper electrode 21 through the base layer 13 in the peripheral region 2. Therefore, an improvement in avalanche withstand voltage can be achieved, and the operation of the parasitic bipolar transistor PTr can be suppressed.

[0041] (1) In the present embodiment, the adjustment distance is set to 0.1 μm or more. Therefore, the avalanche withstand voltage can be sufficiently increased.

[0042] (Second Embodiment)

[0043] The second embodiment will be described. In this embodiment, a trench contact is formed with respect to the first embodiment. The others are the same as those in the first embodiment, so the description is omitted here.

[0044] In the present embodiment, as Figure 6 shown, a contact trench 23 is formed in the semiconductor substrate 10 so as to communicate with the contact hole 20a formed in the interlayer insulating film 20. More specifically, the contact trench 23 is formed to be aligned with the contact hole 20a in the normal direction of one surface 10a of the semiconductor substrate 10. That is, like the contact hole 20a, the adjustment distance d from the unit region 1 of the contact trench 23 is 0.1 μm or more.

[0045] Further, the source layer 14 in the present embodiment is configured to have a source region 14a and a source contact region 14b. The source region 14a is located on the side of the gate insulating film 17, and the source contact region 14b is formed to have a higher impurity concentration than the source layer 14 and to be in contact with the side surface of the contact trench 23. In addition, the base contact region 13b is formed so as to be in contact with the bottom surface of the contact trench 23.

[0046] According to the present embodiment described above, the contact hole 20a extends from the unit region 1 to the peripheral region 2, and the upper electrode 21 is also connected to the base layer 13 in the peripheral region 2. Therefore, the same effect as that of the first embodiment described above can be obtained.

[0047] Here, for example, a structure may be considered in which the contact hole 20a and the contact trench 23 are not extended to the peripheral region 2, but other contact holes are formed in the peripheral region 2 and the upper electrode 21 is connected to the base layer 13 in the peripheral region 2. However, in this structure, the processes of forming the contact trench 23 and the contact hole 20a and the process of forming other contact holes need to be performed separately, and the manufacturing process increases. That is, the vertical semiconductor device of the present embodiment can suppress an increase in the manufacturing process and obtain the same effect as that of the first embodiment described above.

[0048] (1) In this embodiment, a contact trench 23 is formed in the semiconductor substrate 10, and the source contact region 14b and the base contact region 13b are formed in contact with the contact trench 23. Therefore, it is possible to easily ensure the connection area with the upper electrode 21, and the length between adjacent trenches 16 can be shortened. Therefore, it is possible to reduce the on-resistance and miniaturize the vertical semiconductor device.

[0049] (Other embodiments)

[0050] Although the present disclosure has been described based on embodiments, it should be understood that the present disclosure is not limited to these embodiments and configurations. The present disclosure also includes various modifications and variations within an equivalent range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more than one, or less than one of them, also fall within the scope and spirit of the present disclosure.

[0051] For example, in the above embodiments, an n-channel trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the vertical semiconductor device may also be configured to form a p-channel trench gate structure MOSFET in which the conductivity types of the respective components are inverted with respect to the n-channel type. Furthermore, in addition to the MOSFET, the vertical semiconductor device may also be configured to form an IGBT having the same structure. In the case of an IGBT, in addition to changing the n-type substrate 11 in the above embodiments to a p-type collector layer, it is the same as the vertical MOSFET described in the first embodiment above. + type substrate 11 to a p + type collector layer, it is the same as the vertical MOSFET described in the first embodiment above.

[0052] In addition, in the above embodiments, an example in which the semiconductor substrate 10 is composed of a silicon substrate has been described. However, the semiconductor substrate 10 may also be a silicon carbide substrate or a gallium nitride substrate.

[0053] Moreover, in the above embodiments, the base contact region 13b may not be formed, and the base layer 13 may be directly connected to the upper electrode 21. In addition, in the first embodiment above, the source contact region 14b may be formed in contact with the upper electrode 21, and in the second embodiment above, the source contact region 14b may not be formed.

Claims

1. A vertical semiconductor device having a semiconductor element having a trench gate structure, characterized in that: A semiconductor substrate (10) is provided, the semiconductor substrate having a cell region (1) in which the semiconductor element is formed and a peripheral region (2) surrounding the cell region, The unit area has: A drift layer (12) of a first conductivity type; A base layer (13) of a second conductivity type, formed on the drift layer; An impurity layer (14) of a first conductivity type is formed on a surface portion of the base layer and has a higher impurity concentration than the drift layer; The trench gate structure has a gate electrode (18) disposed in a trench (16) via a gate insulating film (17), the trench penetrates the impurity layer and the base layer to reach the drift layer, and is extended along the surface direction of the semiconductor substrate; A high-concentration layer (11) of the first conductivity type or the second conductivity type is formed on the opposite side of the base layer via the drift layer and has a higher impurity concentration than the drift layer; An interlayer insulating film (20) is formed on one side (10a) of the semiconductor substrate and has a contact hole (20a) for exposing the base layer and the impurity layer; a first electrode (21) electrically connected to the impurity layer and the base layer via the contact hole; and a second electrode (22) electrically connected to the high concentration layer, The region where the impurity layer is formed is set as the cell region, The trench gate structure extends from the cell region to the peripheral region. The base layer is extended from the cell region to the peripheral region, The contact hole is extended from the cell area to the peripheral area. The first electrode is also connected to the base layer through the contact hole in the peripheral region.

2. The vertical semiconductor device according to claim 1, wherein: When the length of the contact hole in the peripheral region along the extending direction of the trench is defined as an adjustment distance (d), the adjustment distance is equal to or greater than 0.1 μm.

3. The vertical semiconductor device according to claim 1 or 2, characterized in that, A contact groove (23) communicating with the contact hole is formed in the semiconductor substrate, The impurity layer is formed in contact with the side surface of the contact trench. The base layer is formed in contact with a bottom surface of the contact trench.

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