Data reading method and device and data storage method and device

Abstract

The invention discloses a data reading method and device and a data storage method and device. The method comprises the steps that a first storage address of target data to be read is sent to N memory controllers, the target data are data belonging to a target type, and the target data are stored in N memory modules in a scattered mode, each memory controller obtains partial data of the target data from the memory modules based on the first storage address, the sum of bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1; and receiving data fed back by the N memory controllers, and obtaining target data based on the data fed back by the N memory controllers. According to the method and the device, the technical problem of low access efficiency when a specific type of data is accessed to a memory in related technologies is solved.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular, to a data reading method and device, and a data storage method and device. Background Art

[0002] During the use of a chip, it is necessary to continuously access the memory for data interaction (such as reading data, storing data, etc.) to execute related operations. The standard memory controller integrated in the chip will have a set of buffering and arbitration logics. After optimizing the memory address sent by, for example, a processor core, according to the algorithm logic of the optimal effective bandwidth (or first come, first served), the address data is sent to the memory chip, and then the memory data is obtained. Using a standard memory controller is relatively easy to implement a memory interface, but the latency of the returned data is unpredictable. At this time (i.e., when waiting for the data to return), the control unit that initiates the memory access (such as a processor, pipeline, data cache module, etc.) can only be in a waiting state, wasting the computing power of the computing unit. Therefore, efficient memory access efficiency becomes particularly important.

[0003] In some application scenarios, a chip needs to frequently access a specific type of data (such as session entries) in the memory. However, in the related art, a single memory controller is usually used to manage the data access of the entire memory module, resulting in a problem of low access efficiency.

[0004] In view of the above problems, no effective solution has been proposed yet. Summary of the Invention

[0005] Embodiments of the present invention provide a data reading method and device, and a data storage method and device, so as to at least solve the technical problem of low access efficiency in the related art when accessing a specific type of data in the memory.

[0006] According to an aspect of an embodiment of the present invention, a data reading method is provided, which is applied to a target processing unit in a target chip, and includes: sending a first storage address of target data to be read to N memory controllers, where the target data is data belonging to a target type, the target data is dispersedly stored in N memory modules, each memory controller obtains partial data of the target data from the memory module based on the first storage address, the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1; receiving the data fed back by the N memory controllers, and obtaining the target data based on the data fed back by the N memory controllers.

[0007] Further, the target chip is a chip in a network device, and the target data is a session entry.

[0008] Further, the data reading method further includes: sending a synchronization signal to N memory controllers to control the processing time points of the N memory controllers for processing the first storage address based on the synchronization signal.

[0009] Further, at least a priority control signal is included in the synchronization signal. Wherein, the data reading method further includes: during the process of sending the first storage address to the N memory controllers, setting the signal value in the priority control signal to a target value, where the priority corresponding to the target value is higher than a preset priority. When the memory controller receives the target value, it adjusts the order of the first storage address matching the target value among the storage addresses to be processed, and the processing time point is determined based on the order.

[0010] Further, the data reading method further includes: determining the target value from the range of available values of the priority control signal according to the data information of the target data. Different signal values correspond to different priorities. The data information includes at least one of the following: a priority identifier associated with the target data, a service type matched by the target data; and setting the signal value in the priority control signal to the target value.

[0011] Further, the data reading method further includes: before sending the first storage address of the target data to be read to the N memory controllers, determining the number of storage addresses to be processed by each of the N memory controllers; determining the time point for sending the first storage address to the N memory controllers based on the number of storage addresses to be processed, so as to control the processing time points of the N memory controllers for processing the first storage address.

[0012] Further, the data reading method further includes: determining the data size of the target data; determining the target bit width required to obtain the target data through a single burst read based on the data size of the target data and the expected consecutive read times for a single burst read of the memory module; and determining the sum of the bit widths required for the N memory modules based on the target bit width.

[0013] According to another aspect of the embodiments of the present invention, there is also provided a data storage method, which is applied to a target processing unit in a target chip and includes: obtaining target data to be dispersedly stored in N memory modules, and dividing the target data into N data, where the target data is data belonging to a target type; sending a single data among the N data and the first storage address of the target data to each of the N memory controllers to dispersedly store the target data, where each memory controller writes data into the memory module based on the first storage address, and the sum of the bit widths required for the N memory modules is determined based on the size of the target data.

[0014] According to another aspect of the embodiments of the present invention, there is also provided a data reading device, which is applied to a target processing unit in a target chip, and includes: a first sending module, configured to send a first storage address of target data to be read to N memory controllers, where the target data is data belonging to a target type, the target data is dispersedly stored in N memory modules, each memory controller obtains partial data of the target data from the memory module based on the first storage address, and the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1; a receiving module, configured to receive the data fed back by the N memory controllers, and obtain the target data based on the data fed back by the N memory controllers.

[0015] According to another aspect of the embodiments of the present invention, there is also provided a data storage device, which is applied to a target processing unit in a target chip, and includes: an obtaining module, configured to obtain target data to be dispersedly stored in N memory modules, and divide the target data into N pieces of data, where the target data is data belonging to a target type; a second sending module, configured to send a single piece of data among the N pieces of data and the first storage address of the target data to each of the N memory controllers to dispersedly store the target data, where each memory controller writes the data into the memory module based on the first storage address, and the sum of the bit widths required by the N memory modules is determined based on the size of the target data.

[0016] According to another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium, in which a computer program is stored, where the computer program is configured to execute the above-mentioned data reading method or data storage method when running.

[0017] According to another aspect of the embodiments of the present invention, there is also provided an electronic device, which includes one or more processors; a memory, configured to store one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement running the program, where the program is configured to execute the above-mentioned data reading method or data storage method when running.

[0018] According to another aspect of the embodiments of the present invention, there is also provided a computer program product, including a computer program / instructions, where the computer program / instructions implement the above-mentioned data reading method or data storage method when executed by a processor.

[0019] In an embodiment of the present invention, a method of dispersedly storing target data and parallelly reading the target data from multiple memory modules during reading is adopted. By sending the first storage address of the target data to be read to N memory controllers, receiving the data fed back by the N memory controllers, and obtaining the target data based on the data fed back by the N memory controllers. Wherein, the target data is data belonging to a target type, the target data is dispersedly stored in N memory modules, each memory controller obtains a partial data of the target data from the memory module based on the first storage address, the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1.

[0020] In the above process, by sending the first storage address of the target data to be read to N memory controllers to parallelly read the partial data of the target data based on the N memory controllers, the unified use of multiple memory controllers is realized, and the problem of excessive read operations caused by insufficient bit width of a single memory module when using a single memory controller to manage data access of memory modules is avoided, thereby improving the data read speed, that is, improving the memory access efficiency. By setting the sum of the bit widths required by the N memory modules to be determined based on the size of the target data, the waste of resources caused by over-configuring memory modules is avoided, and the effective control of costs is realized. By receiving the data fed back by the N memory controllers and obtaining the target data based on the data fed back by the N memory controllers, the effective restoration of the dispersedly stored target data is realized, that is, the effective acquisition of the target data is realized.

[0021] It can be seen that the solution provided by this application achieves the purpose of dispersedly storing the target data and parallelly reading the target data from multiple memory modules during reading, thereby realizing the technical effect of improving the memory access efficiency, and further solving the technical problem of low access efficiency in related technologies when accessing specific types of data in memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, and the schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0023] Figure 1 is a schematic diagram of an optional data reading method in related technologies;

[0024] Figure 2 is a schematic diagram of an optional data reading method according to an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of an optional interaction between a target processing unit and a memory controller according to an embodiment of the present invention;

[0026] Figure 4 It is a schematic diagram of an optional data storage method according to an embodiment of the present invention;

[0027] Figure 5 It is a schematic diagram of an optional data reading device according to an embodiment of the present invention;

[0028] Figure 6 It is a schematic diagram of an optional data storage device according to an embodiment of the present invention;

[0029] Figure 7 It is a schematic diagram of an optional electronic device according to an embodiment of the present invention. Detailed implementation manners

[0030] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant regions, and corresponding operation entrances are provided for the user to choose to authorize or refuse.

[0033] Embodiment 1

[0034] According to an embodiment of the present invention, an embodiment of a data reading method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0035] In some application scenarios, a chip needs to frequently access specific types of data (such as session entries) from memory. However, in the related art, a single memory controller is usually used to manage the data access of the entire memory module, resulting in a problem of low access efficiency.

[0036] For example, taking the application scenario of a firewall chip reading session entries as an example, the foregoing problem will be explained. When a firewall chip (such as an ASIC (Application Specific Integrated Circuit) chip) implements the fast-forwarding function, it needs to maintain a large-sized session table. When a packet in the network is received by the firewall chip, the firewall chip will extract the five-tuple in the packet, and then look up the session entry in the session table according to the address calculated from the five-tuple. Since the size of the session table is very large (calculated in GBytes) and needs to be stored in memory, the speed of obtaining session entries from memory will greatly affect the latency performance and throughput performance of the firewall chip.

[0037] The cacheline of mainstream CPUs on the market is 64 bytes. Therefore, each most efficient burst read (i.e., burst read) in the DDR (3 / 4 / 5) specification for a standard DIMM (Dual In-line Memory Module) is 64 bytes. Among them, DDR (Double Data Rate) represents double data rate, and DDR (3 / 4 / 5) are different versions of this memory technology of dynamic random access memory with double data transfer rate.

[0038] However, the length of the firewall session entry is not exactly an integer multiple of 64 bytes, and reading a session entry will generate multiple BL8 or BC4 (Burst Chop 4, read continuously 4 times). This will affect performance and latency. For example, Figure 1 is a schematic diagram of an optional data reading method in the related art, such as Figure 1As shown, reading a session entry uses BL8 twice and BC4 once. Among them, BL refers to burst length, that is, the number of times data can be continuously read in a single burst read operation. BL8 means that data is continuously read 8 times in a single burst read operation. BC refers to Burst Chop, that is, burst segmentation. BC4 means that in a single burst operation, only half of the burst length is transmitted.

[0039] If, in order to improve the reading performance, the session entries are aligned in 64-byte units when storing, a large amount of memory will be wasted.

[0040] For example, the size of a session entry is 129 bytes. When reading, 3 BL8s are required (read BL8 3 times, affecting latency). BC4 takes 2 fewer clock cycles than BL8, slightly shortening the time, saving about 10% of the time compared to a full BL8, but still affecting the reading speed; when storing, it needs to occupy 64x3 = 192 bytes, wasting 32% of the space.

[0041] Therefore, there is a problem of low memory access efficiency in the related art. To solve this problem, the present application proposes a data reading method.

[0042] Figure 2 is a schematic diagram of an optional data reading method according to an embodiment of the present invention. As Figure 2 shown, this method is applied to a target processing unit in a target chip, and includes the following steps:

[0043] Step S201, send the first storage address of the target data to be read to N memory controllers. Among them, the target data is data belonging to the target type, and the target data is scattered and stored in N memory modules. Each memory controller obtains partial data of the target data from the memory module based on the first storage address. The sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1.

[0044] The method provided by the present application is applicable to scenarios where the target chip needs to frequently (for example, the number of reads per day is greater than a preset number, or the proportion of the number of reads per day is greater than a preset proportion) access a certain specific type of data in the memory, so as to improve the access efficiency of this type of data. According to different actual application scenarios, the device to which the target chip belongs and the type of target data are also different. In this embodiment, taking the target chip as a chip in a network device (such as a firewall, etc.) and the target data as a session entry as an example, the method provided by the present application is exemplarily described.

[0045] Optionally, the target chip can be an ASIC or other integrated circuit chips with processing capabilities. The target processing unit in the target chip interacts with the memory controller in the target chip, which can be a memory synchronization controller. The memory controller used in this embodiment can be a standard memory controller, which can support data bit widths of 8 bits, 16 bits, 32 bits, and 64 bits. The target chip includes N memory controllers, and the N memory controllers respectively manage the read and write operations of different memory modules, that is, the N memory controllers correspond one-to-one with the N memory modules. The memory module can be a memory strip or a memory chip.

[0046] In some embodiments, the target type is a session type, that is, the target data is a session entry. The target data is dispersedly stored in N memory modules. For example, for each session entry, the session entry is split and stored in multiple memory modules, and each memory module stores a part of the data in a single session entry.

[0047] When the target processing unit receives a packet to be processed, in order to implement the fast-forwarding function of the packet, the target processing unit extracts the five-tuple information (source IP address, destination IP address, source port, destination port, protocol number) of the packet from the packet, and then calculates the storage address of the corresponding session entry according to the five-tuple, so as to find the session entry from the memory according to the storage address of the session entry, thereby implementing the fast-forwarding of the packet according to the session entry. Optionally, the target data to be read is equivalent to the session entry corresponding to the aforementioned packet to be processed, and the storage address is the first storage address of the session entry, and the first storage address represents the storage address where the target data is dispersedly stored in N memory modules.

[0048] Optionally, in order to optimize the reading efficiency, a single session entry is strategically divided into N data segments, and these segments are stored in parallel in N different memory modules, and they are placed at the same relative address position within their respective memory modules. For example, in a system composed of three memory modules, when the session entry is split, each segment will be stored at the address "5" of its corresponding memory module, and the address "5" here represents the starting storage position of the segment of the session entry within each memory module.

[0049] For example, Figure 3 is an optional interaction schematic diagram of the target processing unit and the memory controller according to an embodiment of the present invention, as Figure 3As shown, the target processing unit can send the same first storage address to these memory controllers based on the standard control memory signal, so as to trigger them to read partial data of the target data from the memory modules they manage according to the first storage address. After receiving the first storage address sent by the target processing unit, each memory controller independently reads the corresponding part of the target data from the memory module it is responsible for in parallel. By accessing multiple memory modules simultaneously, the total time required to read the complete target data can be significantly reduced. Among them, the aforementioned standard control memory signal at least includes an address signal for transmitting the first storage address, and the standard control memory signal may also include a clock signal, a command signal (carrying instructions for operating on the memory, such as reading, writing, etc.), a data signal (for transmitting actual data), etc.

[0050] In some embodiments, the sum of the bit widths required for N memory modules is determined based on the size of the target data. That is, in this embodiment, the selection of memory modules depends on the size of the target data. For example, assume the size of the target data is 129 bytes. The bit width of a single memory module is not sufficient to obtain the entire data in one read operation. Therefore, according to the size of 129 bytes, N memory modules are allocated so that the sum of their bit widths (i.e., the total data throughput) is sufficient to cover the entire 129 - byte data size to ensure that the complete target data can be obtained in one go or in as few read cycles as possible.

[0051] For example, if it is desired to complete data reading with a single BL8 (i.e., single - burst read), the total bit width of the memory controllers is: the session size (in units of "bytes", e.g., 129 bytes) divided by 8 to get the quotient A1 (16), and the ideal bit width A2 = A1 x 8 + 8 (136 bits), that is, 2 64 - bit memory sticks and 1 8 - bit memory chip are required. If it is desired to reduce costs and the number of memory controllers, and use 2 BL8s to complete data reading, then 1 64 - bit memory stick and 1 8 - bit memory chip are required.

[0052] For example, as Figure 3 shown, using multiple memory sticks / chips with different bit widths to (logically) form a memory with a large bit width, and the overall bit width matches the session entry size, where Figure 3 the bit width of the memory stick in the standard DIMM is 64 bits.

[0053] Step S202: Receive the data fed back by N memory controllers, and obtain the target data based on the data fed back by N memory controllers.

[0054] Optionally, the target processing unit can receive the data fed back by N memory controllers in parallel and combine the received scattered partial data into complete target data. For example, during storage, the first data segment of the target data is stored in the first memory module, the second data segment is stored in the second memory module, and so on for all data segments of the target data, so that after the data segments are read from the memory modules, the data segments are combined according to the order of the corresponding memory modules to accurately obtain the target data.

[0055] Based on the solutions defined in the above steps S201 to S202, it can be known that in the embodiments of the present invention, the target data is stored in a scattered manner, and when reading, the target data is obtained by reading in parallel from multiple memory modules. By sending the first storage address of the target data to be read to N memory controllers, receiving the data fed back by the N memory controllers, and obtaining the target data based on the data fed back by the N memory controllers. Among them, the target data is data belonging to the target type, the target data is scattered and stored in N memory modules, each memory controller obtains partial data of the target data from the memory module based on the first storage address, the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1.

[0056] It is easy to notice that in the above process, by sending the first storage address of the target data to be read to N memory controllers to read the partial data of the target data in parallel based on the N memory controllers, the unified use of multiple memory controllers is realized, avoiding the excessive number of read operations caused by the insufficient bit width of a single memory module when using a single memory controller to manage the data access of the memory module, thereby improving the data read speed, that is, improving the memory access efficiency. By setting the sum of the bit widths required by the N memory modules to be determined based on the size of the target data, the waste of resources caused by over-configuring the memory module is avoided, and the effective control of the cost is realized. By receiving the data fed back by the N memory controllers and obtaining the target data based on the data fed back by the N memory controllers, the effective restoration of the scattered target data is realized, that is, the effective acquisition of the target data is realized.

[0057] It can be seen that the solution provided by this application achieves the purpose of storing the target data in a scattered manner and obtaining the target data by reading in parallel from multiple memory modules when reading, thereby realizing the technical effect of improving the memory access efficiency, and further solving the technical problem of low access efficiency in the related art when accessing specific types of data in the memory.

[0058] In an optional embodiment, the target chip is a chip in a network device, and the target data is a session entry.

[0059] Optionally, the network device includes, but is not limited to, a firewall, a router, a switch, etc. The target chip refers to the integrated circuit chip used for data processing inside these devices. A session entry is a data structure used in a network device to record and manage the network session state, containing key information such as source IP address, destination IP address, source port, destination port, and protocol type. In network communication, the quick reading of session entries is crucial for timely processing of data packets, state detection, and implementation of security policies.

[0060] It should be noted that through the above method, the access efficiency of the network device when accessing session entries in memory can be effectively improved, thereby improving the efficiency of the network device in processing packets.

[0061] In an optional embodiment, the data reading method further includes: sending a synchronization signal to N memory controllers to control the processing time points of the N memory controllers for processing the first storage address based on the synchronization signal.

[0062] When a memory controller receives a memory address sent by an upper control module (such as a target processing unit, a data controller, or other hardware units), since it may be completing other previously entered data requests, the memory controller will not immediately initiate a memory operation. That is, for address requests sent synchronously to multiple memory controllers (such as sending the first storage address to N memory controllers simultaneously), the time for these multiple memory controllers to return data may not be the same, and may even vary widely. And the data reading delay is usually calculated based on the return time of the last data content. Therefore, it is necessary to make the N memory controllers complete the feedback of data segments of the target data (i.e., partial data of the target data) within a relatively short time difference as much as possible.

[0063] Therefore, in this embodiment, an external trigger method can be adopted to send a synchronization signal to N memory controllers to control the processing time points of the N memory controllers for processing the first storage address to be within a preset time range. As Figure 3 shown, when the target processing unit sends a standard memory controller signal to the memory controller, it can also send a controller synchronization signal or a group of controller synchronization signals to the memory controller.

[0064] For example, the address information of the first storage address (such as address identifier, address content, etc.) and a target identifier are transmitted through the synchronization signal. The target identifier is used to mark the storage address to be preferentially processed. Thus, the memory controller determines the storage address to be preferentially processed based on the synchronization signal, and then when receiving a storage address that matches the address information through the standard memory controller signal, adjusts this storage address to a relatively forward position (such as the first position) in the storage addresses to be processed to preferentially process this storage address.

[0065] For another example, the controller synchronization signal may include a priority control signal, and the signal value in the priority control signal may be 0 or 1. For example, when the target processing unit sends a storage address other than the data of the target type to the memory controller, the synchronization sets the signal value to 0, so that the memory controller operates in an asynchronous mode. In this case, the memory controller sends the address data to the memory module according to the algorithm logic of the optimal effective bandwidth (or first-come, first-served), and then obtains the memory data, that is, the memory controller determines the order of the storage address in the storage addresses to be processed by the memory controller based on the original logic. When the target processing unit sends the first storage address of the target data to the memory controller, the synchronization can set the signal value to 1, so that the memory controller operates in a synchronous mode. In this case, the memory controller preferentially sends the first storage address to the memory module, and then obtains the memory data, that is, the memory controller determines that the priority of the first storage address is higher, and adjusts the first storage address to a relatively forward position (e.g., the first position) in the storage addresses to be processed, so as to process this storage address preferentially.

[0066] In some embodiments, the synchronization signal may further include a sequential count marker signal, which is used to mark the sequence number of the storage address sent by the target processing unit to the memory controller, so as to help the memory controller identify which addresses are requested first and which are requested later, to facilitate the design of caches and pipelines, avoid errors caused by old data overwriting new data, or improper data update order, and improve the reliability of memory access.

[0067] It should be noted that by setting the synchronization signal, the target processing unit can effectively control the read start time of N memory controllers, ensure that the parallel reading of data is as synchronous as possible, and thus can further improve the memory access efficiency.

[0068] In an alternative embodiment, the synchronization signal at least includes a priority control signal. Among them, in the process of controlling the processing time points of N memory controllers to process the first storage address based on the synchronization signal, the target processing unit can set the signal value in the priority control signal to a target value during the process of sending the first storage address to the N memory controllers, where the priority corresponding to the target value is higher than the preset priority. When the memory controller receives the target value, it adjusts the order of the first storage address matching the target value in the storage addresses to be processed based on the target value, and the processing time point is determined based on the order.

[0069] Optionally, the priority control signal is used to adjust the priority of the memory controller when processing the storage address. The priority control signal carries a signal value, and the signal value represents the priority level of the read request. Among them, the memory controller processes the storage address, which means performing a data read operation or a data write operation based on the storage address.

[0070] Optionally, the priority corresponding to the target value is higher than the preset priority. Generally speaking, the target value corresponds to a high priority level, which is higher than the default or normal priority preset in the system. By setting the signal value of the priority control signal to the target value, the target processing unit can clearly instruct the memory controller to place the storage address in the read request of the current session entry at a higher position in its processing queue for priority processing. For example, assuming that the value of the priority control signal is 0 or 1, and the priority increases as the number increases, the aforementioned target value can be 1, and 0 is used to represent the preset priority. Another example, assuming that the value of the priority control signal is 0, 1, 2, 3, 4, 5, the aforementioned target value can be any one of "1, 2, 3, 4, 5", and 0 is used to represent the preset priority. In some embodiments, based on different actual application scenarios, the target processing unit can also set a higher priority for data of types other than the target type. In this embodiment, the priority setting of data of types other than the target type by the target processing unit is not specifically limited.

[0071] Optionally, when the memory controller receives the target value based on the synchronization signal, it adjusts the processing order of the first storage address that is synchronously sent with the target value in the standard memory controller signal, ensuring that the first storage address is in a priority position in the memory controller's queue to be processed, so as to be processed in a timely manner. And it should be emphasized that the higher the priority of the storage address, the relatively more forward position it occupies in the queue to be processed.

[0072] For example, assume there are five memory controllers, and the target processing unit needs to immediately read a session entry. When sending the first storage address of this session entry to all memory controllers, the target processing unit sets the signal value in the priority control signal to the value representing "the highest priority" and synchronously sends it to each memory controller. When the memory controller receives the first storage address, it will synchronously receive the signal value representing "the highest priority" in the synchronization signal. In this case, the memory controller immediately adjusts the first storage address to the front end of the queue to be processed (that is, the queue used to record the storage addresses to be processed), ensuring to start reading at the next available time point, so as to achieve relatively synchronous reading of the session entry by the 5 memory controllers. Among them, the memory controller processes the storage addresses based on the arrangement order of the storage addresses to be processed, and the storage address with a more forward sort is processed first.

[0073] Optionally, if the storage addresses previously marked with the same priority signal value are included in the queue to be processed, the newly obtained first storage address is arranged after the storage addresses previously marked with the same priority signal value and before all the storage addresses marked with the target low-priority signal value, where the target low-priority signal value refers to the signal value associated with the priority lower than that of the first storage address. For example, assuming that the signal values are 0, 1, and 2, if the currently newly obtained first storage address is marked with "1" and the currently to-be-processed storage addresses include the storage addresses previously marked with the signal values "1" and "2", the newly obtained first storage address is arranged after the storage addresses previously marked with the signal values "1" and "2" and before all the storage addresses marked with the signal value "0".

[0074] It should be noted that by introducing the priority control signal, the read operation of the target data can be preferentially performed, so that the time for each memory controller to feedback data can be effectively controlled to be basically the same or within a certain time range, improving the access efficiency and reducing the delay of data processing, thereby improving the response speed and overall performance, and facilitating the timing design of other modules inside the target chip.

[0075] In an optional embodiment, during the process of setting the signal value in the priority control signal to the target value, the target processing unit may determine the target value from the range of available values of the priority control signal according to the data information of the target data, where different signal values correspond to different priorities, and the data information includes at least one of the following: the priority identifier associated with the target data, the service type matched by the target data; and set the signal value in the priority control signal to the target value.

[0076] For example, the values of the priority control signal may be 0, 1, 2, 3, 4, 5, and the priority increases as the number increases.

[0077] Optionally, the target processing unit may determine the data information of the target data according to the message information of the message associated with the target data. When the target data is a session entry, the priority identifier associated with the target data is the same as the priority identifier of the message used to trigger the read of the target data, and the service type matched by the target data is the same as the service type of the message used to trigger the read of the target data. The message used to trigger the read of the target data is the message associated with the target data. For example, when the target processing unit receives a message and calculates the first storage address of a certain target data to be read based on the five-tuple of the message, the priority identifier of the received message is determined as the priority identifier associated with the target data, and the service type of the received message is determined as the service type matched by the target data.

[0078] Optionally, the target processing unit may store the matching relationship between the data information and the target value. After determining the data information of the target data, the target value can be determined based on this matching relationship and the data information. For example, when the data information is the service type matched by the target data, a session entry related to a security audit message may have a "high priority", while a session entry related to ordinary message transmission may be marked as "ordinary priority", so as to determine the target value based on this service type.

[0079] After determining the target value, the target processing unit may set the signal value in the priority control signal to the target value for indicating the memory controller.

[0080] It should be noted that by dynamically determining the signal value of the priority control signal according to the data information of the target data, the intelligent control of the read priority of the target data is realized, thereby optimizing the allocation of system resources and improving the flexibility of memory access.

[0081] In an optional embodiment, before sending the first storage address of the target data to be read to N memory controllers, the target processing unit may determine the number of storage addresses to be processed by each of the N memory controllers; determine the time point for sending the first storage address to the N memory controllers based on the number of storage addresses to be processed, so as to control the processing time points of the N memory controllers for the first storage address.

[0082] At the same time point, the number of storage addresses to be processed by each of the N memory controllers may be different, that is, the length of the queue to be processed may be different. For example, at a certain time point, the No. 1 memory controller has 100 storage addresses to be processed, the No. 2 memory controller has 81 storage addresses to be processed, and the No. 3 memory controller has 90 storage addresses to be processed. In this case, if the first storage address is sent to the N memory controllers at the same time point, the first storage address will be ranked at the 101st, 82nd, and 91st positions of the No. 1, No. 2, and No. 3 memory controllers respectively, resulting in a relatively large difference in the time points for the N memory controllers to return the data segments of the target data, making it difficult to achieve the effect of synchronous return, and further affecting the memory access efficiency.

[0083] Therefore, in some embodiments, the target processing unit may adopt a logical synchronization method to enable the N memory controllers to complete the feedback of the data segments of the target data within a short time difference. That is, the target processing unit arranges the order of sending the first storage address to the N memory controllers to achieve the effect of approximate synchronous return of data.

[0084] Optionally, before sending the first storage address to the memory controller, the target processing unit may first determine the number of storage addresses to be processed by each of the N memory controllers, that is, determine the length of the queue to be processed by each of the N memory processors.

[0085] Optionally, after determining the number of storage addresses to be processed by each memory controller, the target processing unit may determine the time point for sending the first storage address to the N memory controllers based on the number of storage addresses to be processed, so as to control the processing time points of the N memory controllers for processing the first storage address to be within a preset time range. For example, determine the memory controller with the largest number of storage addresses to be processed among the N memory controllers, and determine it as the target memory controller, and record the number of storage addresses to be processed by the target memory controller at this time to obtain the first quantity. For each memory controller other than the target memory controller, calculate the difference between the number of storage addresses to be processed by this memory controller and the first quantity to obtain the second quantity. Then directly send the first storage address to the target memory controller, and for each memory controller other than the target memory controller, after sending the second quantity of storage addresses to this memory controller, then send the first storage address to this memory controller.

[0086] For example, at a certain time point, the No. 1 memory controller has 100 storage addresses to be processed, the No. 2 memory controller has 81 storage addresses to be processed, and the No. 3 memory controller has 90 storage addresses to be processed. In this case, the target processing unit may directly send the first storage address to the No. 1 memory controller, and then after sending 19 storage addresses to the No. 2 memory controller, send the first storage address to the No. 2 memory controller, and after sending 10 storage addresses to the No. 3 memory controller, send the first storage address to the No. 3 memory controller. That is, in the time dimension, the No. 1 memory controller receives the first storage address first, then the No. 3 memory controller receives the first storage address, and finally the No. 2 memory controller receives the first storage address. In the queue to be processed dimension, the position of the first storage address in the queues to be processed of the No. 1, No. 2, and No. 3 memory controllers remains the same or similar. Optionally, the more storage addresses a memory controller has to process, the relatively later it receives the first storage address.

[0087] It should be noted that through the above method, each memory controller can still process the first storage address within a close time even when the lengths of the queues to be processed are different, thereby effectively improving the access efficiency when accessing specific types of data in the memory.

[0088] In an alternative embodiment, the sum of the bit widths required for N memory modules is determined as follows: Determine the data size of the target data; Based on the data size of the target data and the desired consecutive read count for a single burst read of the memory module, determine the target bit width required to obtain the target data through a single burst read; Based on the target bit width, determine the sum of the bit widths required for N memory modules.

[0089] In some embodiments, the data length of data of a target type is fixed. For example, the data size of a session entry is fixed at 129 bytes.

[0090] Optionally, after determining the data size of the target data, the target processing unit may calculate the minimum bit width (i.e., the target bit width) required to obtain the target data through a single burst read operation based on the data size and the desired consecutive read count for a single burst read, and thus determine this bit width as the sum of the bit widths required for N memory modules. Or, multiply this bit width by a preset ratio (such as 1 / 2, 1 / 3, etc.) to obtain a first bit width, and determine the first bit width as the sum of the bit widths required for N memory modules. The desired consecutive read count for a single burst read refers to the number of times the system expects to continuously read data in a single burst read operation.

[0091] Optionally, after determining the sum of the bit widths required for N memory modules, N memory modules may be selected based on this sum of bit widths for subsequent storage of the target data in the N memory modules.

[0092] For example, assume the system needs to read a target data with a data size of 128 bytes. The system also sets that, in order to reduce the number of reads, it hopes to continuously read at most 4 times in a single burst read, and each time reads 32 bytes of data. Based on this information, the system calculates that the target bit width required to read the entire 128 - byte target data in a single burst read is 128 bits (4 times * 32 bits). Next, if the data of the target data is scattered and stored in N memory modules, the system will ensure that the sum of the bit widths of these memory modules is at least 128 bits. In this way, in a single burst read operation, 32 - bit data is read from each module, and a total of 4 times are read, so as to completely read the entire 128 - byte target data. This strategy avoids redundant operations of multiple reads, significantly reduces the read latency, and improves the speed and efficiency of data reading.

[0093] Another example, if it is desired to complete the data reading of a session entry through a BL8 burst read, the total bit width of the memory controller is: the session size (in units of "bytes", for example, 129 bytes) divided by 8 to obtain a quotient A1 (16), and the ideal bit width (i.e., the target bit width) A2 = A1 x 8 + 8 (136 bits). Therefore, 2 64 - bit memory sticks and 1 8 - bit memory chip are required.

[0094] For another example, if it is desired to reduce costs and the number of memory controllers, and data reading is completed using 2 BL8s (i.e., two burst reads), then one 64-bit memory module and one 8-bit memory die are required.

[0095] It should be noted that through the above method, it is convenient to accurately determine the memory module for storing the target data, so that the target data can be effectively obtained in a single burst read, improving the memory access efficiency, and effectively avoiding the occupation of additional memory space and reducing resource waste.

[0096] It can be seen that the solution provided by this application achieves the purpose of dispersedly storing the target data and reading the target data from multiple memory modules in parallel during reading, thereby achieving the technical effect of improving the memory access efficiency, and further solving the technical problem of low access efficiency in the related art when accessing specific types of data in the memory.

[0097] Embodiment 2

[0098] According to an embodiment of the present invention, an embodiment of a data storage method is provided, wherein Figure 4 is a schematic diagram of an optional data storage method according to an embodiment of the present invention, as Figure 4 shown, this method is applied to a target processing unit in a target chip, and includes the following steps:

[0099] Step S401, obtain target data to be dispersedly stored in N memory modules, and divide the target data into N data, where the target data is data belonging to the target type.

[0100] Optionally, during the process of dividing the target data, the data can be divided according to the bit widths of the N memory modules respectively. A memory module with a larger bit width means that it can process more data in a single operation. Therefore, the target processing unit can divide larger data segments of the target data to these memory modules with larger bit widths, while the memory modules with smaller bit widths are divided into smaller data segments.

[0101] For example, assume that the size of the target data is 129 bytes and it needs to be dispersedly stored in 3 memory modules, where the bit widths of two of the modules are 64 bits and the other is 8 bits. The target processing unit can divide the target data into two data segments of 64 bytes and one data segment of 1 byte.

[0102] Step S402: Send a single data among the N data and the first storage address of the target data to each of the N memory controllers to disperse and store the target data. Each memory controller writes the data to the memory module based on the first storage address. The sum of the bit widths required by the N memory modules is determined based on the size of the target data.

[0103] In some embodiments, the amount of data read in a single burst by the N memory modules is the same.

[0104] After dividing the target data into N data, the target processing unit can determine the data segments sent to the memory controllers according to the bit widths of the memory modules corresponding to the memory controllers. For example, send a 64-byte data segment to the memory controller corresponding to the memory module with a bit width of 64, and send a 1-byte data segment to the memory controller corresponding to the memory module with a bit width of 8. Such a division strategy makes full use of the bit width advantages of each memory module, reduces the number of storage and read operations, and improves the overall performance. Among them, the N data are placed at the same relative address positions within their respective memory modules.

[0105] Optionally, after receiving the first storage address and the data segment, the memory controller stores the data segment at the corresponding position of the memory module according to the first storage address, thereby realizing the effective storage of the data segment.

[0106] Based on the solution defined in the above Step S401 to Step S402, it can be known that in the embodiment of the present invention, a method of dispersing and storing the target data is adopted. By obtaining the target data to be dispersed and stored in the N memory modules and dividing the target data into N data, a single data among the N data and the first storage address of the target data are sent to each of the N memory controllers to disperse and store the target data.

[0107] It is easy to note that in the above process, by sending the data in the target data and the first storage address to the N memory controllers to parallelly store partial data of the target data based on the N memory controllers, the unified use of multiple memory controllers is realized, avoiding excessive write operations caused by insufficient bit width of a single memory module when using a single memory controller to manage data access to the memory module. Thus, the data write speed can be increased, that is, the memory access efficiency can be improved. By setting the sum of the bit widths required by the N memory modules to be determined based on the size of the target data, resource waste caused by over-configuring the memory modules is avoided, and effective control of the cost is realized.

[0108] It can be seen that the solution provided by this application achieves the purpose of dispersedly storing target data, thereby realizing the technical effect of improving memory access efficiency, and further solving the technical problem of low access efficiency in the related art when accessing specific types of data in memory.

[0109] In an optional embodiment, the processing manner of the first storage address by the target processing unit during the data storage process is the same as that during the data reading process, so it will not be elaborated here.

[0110] Embodiment 3

[0111] According to an embodiment of the present invention, an embodiment of a data reading device is provided, wherein, Figure 5 is a schematic diagram of an optional data reading device according to an embodiment of the present invention, as Figure 5 shown, this device is applied to a target processing unit in a target chip, and includes:

[0112] A first sending module 501, configured to send a first storage address of target data to be read to N memory controllers, wherein the target data is data belonging to a target type, the target data is dispersedly stored in N memory modules, each memory controller obtains partial data of the target data from the memory module based on the first storage address, the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1;

[0113] A receiving module 502, configured to receive the data fed back by the N memory controllers, and obtain the target data based on the data fed back by the N memory controllers.

[0114] It should be noted that the above-mentioned first sending module 501 and receiving module 502 correspond to steps S201 to S202 in the above embodiment, and the examples and application scenarios implemented by the two modules and the corresponding steps are the same, but are not limited to the content disclosed in the above embodiment 1.

[0115] Optionally, the target chip is a chip in a network device, and the target data is a session entry.

[0116] Optionally, the data reading device further includes: a third sending module, configured to send a synchronization signal to the N memory controllers to control the processing time points of the N memory controllers for processing the first storage address based on the synchronization signal.

[0117] Optionally, the synchronization signal at least includes a priority control signal. The third sending module further includes: a processing sub-module, configured to set the signal value in the priority control signal to a target value during the process of sending the first storage address to N memory controllers, where the priority corresponding to the target value is higher than a preset priority. When receiving the target value, the memory controller adjusts the order of the first storage address matching the target value in the storage addresses to be processed, and the processing time point is determined based on the order.

[0118] Optionally, the processing sub-module further includes: a determining unit, configured to determine the target value from the range of available values of the priority control signal according to the data information of the target data, where different signal values correspond to different priorities, and the data information includes at least one of the following: a priority identifier associated with the target data, a service type matched by the target data; a processing unit, configured to set the signal value in the priority control signal to the target value.

[0119] Optionally, the data reading device further includes: a first determining module, configured to determine the number of storage addresses to be processed by each of the N memory controllers; a fourth sending module, configured to determine the time point for sending the first storage address to the N memory controllers based on the number of storage addresses to be processed, so as to control the processing time points of the N memory controllers for processing the first storage address.

[0120] Optionally, the data reading device further includes: a second determining module, configured to determine the data size of the target data; a third determining module, configured to determine the target bit width required to obtain the target data through a single burst read based on the data size of the target data and the expected consecutive read times for a single burst read of the memory module; a fourth determining module, configured to determine the sum of the bit widths required for the N memory modules based on the target bit width.

[0121] Embodiment 4

[0122] According to an embodiment of the present invention, an embodiment of a data storage device is provided, where Figure 6 is a schematic diagram of an optional data storage device according to an embodiment of the present invention, as Figure 6 shown. The device is applied to a target processing unit in a target chip and includes:

[0123] An obtaining module 601, configured to obtain target data to be dispersedly stored in N memory modules, and divide the target data into N data, where the target data is data belonging to a target type;

[0124] A second sending module 602, configured to send a single piece of data among N pieces of data and a first storage address of target data to each of the N memory controllers, so as to disperse and store the target data, where each memory controller writes data into a memory module based on the first storage address, and the sum of bit widths required by the N memory modules is determined based on the size of the target data.

[0125] It should be noted that the above-mentioned obtaining module 601 and second sending module 602 correspond to steps S401 to S402 in the above-mentioned embodiment. The examples and application scenarios implemented by the two modules and the corresponding steps are the same, but are not limited to the content disclosed in the above-mentioned embodiment 2.

[0126] Embodiment 5

[0127] On the other hand, according to an embodiment of the present invention, there is also provided a computer-readable storage medium, in which a computer program is stored, where the computer program is configured to execute the above-mentioned data reading method or data storage method when running.

[0128] Embodiment 6

[0129] On the other hand, according to an embodiment of the present invention, there is also provided an electronic device, where Figure 7 is a schematic diagram of an optional electronic device according to an embodiment of the present invention, as Figure 7 shown, the electronic device includes one or more processors; a memory for storing one or more programs, when the one or more programs are executed by the one or more processors, enabling the one or more processors to implement a program for running, where the program is configured to execute the above-mentioned data reading method or data storage method when running.

[0130] Embodiment 7

[0131] On the other hand, according to an embodiment of the present invention, there is also provided a computer program product, including computer program / instructions, and when the computer program / instructions are executed by a processor, the above-mentioned data reading method or data storage method is implemented.

[0132] The serial numbers of the above-mentioned embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0133] In the above-mentioned embodiments of the present invention, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0134] The embodiments or examples of the present disclosure are not exhaustive. They are only illustrations of some embodiments or examples and do not constitute specific limitations on the protection scope of the present disclosure. Without conflict, each step in an embodiment or example can be implemented as an independent example, and the steps can be combined arbitrarily. For example, a solution obtained by removing some steps in an embodiment or example can also be implemented as an independent example, and the order of the steps in an embodiment or example can be exchanged arbitrarily. Additionally, the optional modes or optional examples in an embodiment or example can be combined arbitrarily; moreover, the embodiments or examples can be combined arbitrarily. For example, some or all of the steps of different embodiments or examples can be combined arbitrarily, and an embodiment or example can be combined arbitrarily with the optional modes or optional examples of other embodiments or examples.

[0135] In several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are merely illustrative. For example, the division of units can be a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of units or modules can be in electrical or other forms.

[0136] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0138] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs.

[0139] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A data reading method, characterized in that, Applied to a target processing unit in a target chip, the method includes: Sending a first storage address of target data to be read to N memory controllers, where the target data is data belonging to a target type, the target data is dispersedly stored in N memory modules, each memory controller obtains partial data of the target data from the memory module based on the first storage address, and the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1; Receiving the data fed back by the N memory controllers and obtaining the target data based on the data fed back by the N memory controllers.

2. The method according to claim 1, wherein The target chip is a chip in a network device, and the target data is a session entry.

3. The method according to claim 1 or 2, characterized in that, The method further includes: Sending a synchronization signal to the N memory controllers to control the processing time points of the N memory controllers for processing the first storage address based on the synchronization signal.

4. The method according to claim 3, wherein At least a priority control signal is included in the synchronization signal, where controlling the processing time points of the N memory controllers for processing the first storage address based on the synchronization signal includes: During the process of sending the first storage address to the N memory controllers, setting the signal value in the priority control signal to a target value, where the priority corresponding to the target value is higher than a preset priority, and when the memory controller receives the target value, adjusting the order of the first storage address matching the target value in the storage addresses to be processed based on the target value, and the processing time point is determined based on the order.

5. The method according to claim 4, wherein Setting the signal value in the priority control signal to the target value includes: Determining a target value from the range of available values of the priority control signal according to the data information of the target data, where different signal values correspond to different priorities, and the data information includes at least one of the following: a priority identifier associated with the target data, a service type matched by the target data; Setting the signal value in the priority control signal to the target value.

6. The method according to claim 1 or 2, characterized in that, Before sending the first storage address of the target data to be read to the N memory controllers, the method further includes: Determining the number of storage addresses to be processed by each of the N memory controllers; Determining the time point for sending the first storage address to the N memory controllers based on the number of storage addresses to be processed to control the processing time points of the N memory controllers for processing the first storage address.

7. The method according to claim 1 or 2, characterized in that, The sum of the bit widths required by the N memory modules is determined by the following method: Determining the data size of the target data; Based on the data size of the target data and the expected consecutive reading times for a single burst read of the memory module, determining the target bit width required to obtain the target data through a single burst read; Determining the sum of the bit widths required by the N memory modules based on the target bit width.

8. A data storage method, characterized in that, Applied to a target processing unit in a target chip, the method includes: Obtaining target data to be dispersedly stored in N memory modules and dividing the target data into N data, where the target data is data belonging to a target type; Send a single one of the N data and the first storage address of the target data to each of the N memory controllers to store the target data dispersedly, where each memory controller writes the data into the memory module based on the first storage address, and the sum of the bit widths required by the N memory modules is determined based on the size of the target data.

9. A data reading device, characterized in that, Applied to a target processing unit in a target chip, including: A first sending module, configured to send the first storage address of target data to be read to N memory controllers, where the target data is data belonging to a target type, the target data is dispersedly stored in N memory modules, each memory controller obtains partial data of the target data from the memory module based on the first storage address, the sum of the bit widths required by the N memory modules is determined based on the size of the target data, and N is a positive integer greater than 1; A receiving module, configured to receive the data fed back by the N memory controllers and obtain the target data based on the data fed back by the N memory controllers.

10. A data storage device, characterized in that, Applied to a target processing unit in a target chip, including: An obtaining module, configured to obtain target data to be dispersedly stored in N memory modules and divide the target data into N data, where the target data is data belonging to a target type; A second sending module, configured to send a single one of the N data and the first storage address of the target data to each of the N memory controllers to store the target data dispersedly, where each memory controller writes the data into the memory module based on the first storage address, and the sum of the bit widths required by the N memory modules is determined based on the size of the target data.

11. An electronic device, characterized in that, The electronic device includes one or more processors; A memory, configured to store one or more programs, and when the one or more programs are executed by the one or more processors, cause the one or more processors to implement a program for running, where the program is set to execute the data reading method in any one of claims 1 to 7 or the data storage method in claim 8 when running.

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