Register renaming method and processor

Abstract

The embodiment of the invention provides a register renaming method and a processor. The method comprises the steps of obtaining a to-be-processed target instruction; if the target instruction is a first instruction for writing a flag bit, distributing a corresponding first target physical register for a first target logic register of the first instruction according to a renaming mechanism; renaming a flag bit physical register corresponding to a first flag bit of the first instruction as the first target physical register; and according to the first destination physical register, updating table entries corresponding to the first destination logical register and the first flag bit in a renaming table. According to the embodiment of the invention, the design complexity of the flag bit related instruction in the micro-architecture is reduced, and the execution efficiency of the processor on the flag bit related instruction is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a register renaming method and a processor. Background Art

[0002] The design of the processor microarchitecture is one of the key technologies in the field of computers. It determines the current software-hardware interface and initial performance, and is one of the core research hotspots in the computer architecture in recent years. The flag bit is one of the key points to be considered in the design of the processor microarchitecture. There are mainly two purposes for the existence of the flag bit in the hardware: 1) Instruction operation acceleration, including the requirements of encryption and decryption instructions and conditional transfer instructions. 2) The need to be compatible with other software. In RISC machines, an instruction set software with flag bits is simulated, and binary translation is representative. Currently, the mainstream RISC instruction sets do not support flag registers, which makes them have certain limitations in terms of efficiency and compatibility. Exploring how to efficiently implement flag bits in RISC machines is a key technology among them. Summary of the Invention

[0003] Embodiments of the present invention provide a register renaming method and a processor, which can efficiently implement flag bits in a RISC machine.

[0004] On the one hand, embodiments of the present invention disclose a register renaming method, and the method includes:

[0005] Obtain a target instruction to be processed;

[0006] If the target instruction is a first instruction for writing a flag bit, allocate a corresponding first destination physical register for a first destination logical register of the first instruction according to a renaming mechanism;

[0007] Rename a flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register;

[0008] Update entries in a renaming table corresponding to the first destination logical register and the first flag bit according to the first destination physical register.

[0009] Optionally, the first instruction includes a logical operation instruction; the method further includes:

[0010] Execute the first instruction to perform a calculation according to values in source physical registers corresponding to source logical registers of the first instruction, and obtain an operation result and a first value of the first flag bit;

[0011] Write the operation result and the first value into the first destination physical register.

[0012] Optionally, the method further includes:

[0013] Determine whether the third physical register to be released is the first destination physical register corresponding to the first flag bit described in the rename table;

[0014] If the third physical register is not the first destination physical register, release the third physical register;

[0015] If the third physical register is the first destination physical register, release the target flag bit physical register, and set the first destination physical register as the flag bit physical register to be released; the target flag bit physical register is the flag bit physical register to be released saved before releasing the third physical register.

[0016] Optionally, the method further includes:

[0017] If the target instruction is the second instruction for reading the flag bit, query the second destination physical register corresponding to the second destination operand of the second instruction according to the rename table;

[0018] If the second destination physical register is valid, determine that the flag bit physical register corresponding to the second instruction is valid;

[0019] If the second destination physical register is invalid, determine that the flag bit physical register corresponding to the second instruction is invalid.

[0020] Optionally, the method further includes:

[0021] Read the value of the second flag bit from the second destination physical register;

[0022] Perform a logical operation according to the value of the second flag bit.

[0023] On the other hand, an embodiment of the present invention discloses a processor, the processor includes:

[0024] Logical register;

[0025] Physical register;

[0026] Rename table;

[0027] An instruction fetching and decoding unit, configured to obtain a target instruction to be processed and decode it;

[0028] An execution unit, configured to execute an instruction;

[0029] Renaming logic, for the case where the target instruction is the first instruction for writing a flag bit, allocating a corresponding first destination physical register for the first destination logical register of the first instruction according to the renaming mechanism; renaming the flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register; updating the entries in the renaming table corresponding to the first destination logical register and the first flag bit according to the first destination physical register.

[0030] Optionally, the first instruction includes a logical operation instruction; the processing unit is further configured to:

[0031] Execute the first instruction to perform a calculation according to the values in the source physical registers corresponding to the source logical registers of the first instruction, obtaining an operation result and a first value of the first flag bit;

[0032] Write the operation result and the first value into the first destination physical register.

[0033] Optionally, the renaming logic is further configured to:

[0034] Determine whether the third physical register to be released is the first destination physical register corresponding to the first flag bit in the renaming table;

[0035] Release the third physical register if the third physical register is not the first destination physical register;

[0036] Release the target flag bit physical register and set the first destination physical register as the flag bit physical register to be released if the third physical register is the first destination physical register; the target flag bit physical register is the flag bit physical register to be released saved before releasing the third physical register.

[0037] Optionally, the renaming logic is further configured to:

[0038] If the target instruction is the second instruction for reading a flag bit, query the second destination physical register corresponding to the second destination operand of the second instruction according to the renaming table;

[0039] Determine that the flag bit physical register corresponding to the second instruction is valid if the second destination physical register is valid;

[0040] Determine that the flag bit physical register corresponding to the second instruction is invalid if the second destination physical register is invalid.

[0041] Optionally, the processing unit is further configured to:

[0042] Read the value of the second flag bit from the second destination physical register;

[0043] Perform a logical operation according to the value of the second flag bit.

[0044] In another aspect, an embodiment of the present invention also discloses an electronic device, which includes a memory and one or more programs, wherein one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the foregoing register renaming method.

[0045] An embodiment of the present invention also discloses a readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can perform the foregoing register renaming method.

[0046] The embodiments of the present invention have the following advantages:

[0047] The embodiment of the present invention provides a register renaming method. When the target instruction to be processed is a first instruction for writing a flag bit, first allocate a first destination physical register for the first destination logical register of the first instruction according to the renaming mechanism, then rename the flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register, and update the entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register, so as to update the physical register recorded in the entries corresponding to the first destination logical register and the first flag bit in the renaming table to the first destination physical register. When renaming the register of the first flag bit of the first instruction, the embodiment of the present invention reuses the first destination physical register allocated for the first destination logical register of the first instruction. Therefore, an instruction for writing a flag bit only needs to write one physical register, that is, the first destination physical register, which reduces the design complexity of the flag bit-related instructions in the microarchitecture and is beneficial to improving the execution efficiency of the processor for the flag bit-related instructions. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 is a flowchart of the steps of an embodiment of a register renaming method of the present invention;

[0050] Figure 2 is a schematic diagram of the processing flow of a flag bit register of the present invention;

[0051] Figure 3 is a schematic diagram of a renaming mechanism of the present invention;

[0052] Figure 4 is a schematic diagram of the structure of a processor of the present invention. Detailed implementation manners

[0053] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0054] Method embodiment

[0055] Referring to Figure 1 , a flowchart of the steps of an embodiment of a register renaming method of the present invention is shown. The method may specifically include the following steps:

[0056] Step 101, obtain a target instruction to be processed;

[0057] Step 102, if the target instruction is a first instruction for writing a flag bit, then allocate a corresponding first destination physical register for the first destination logical register of the first instruction according to the renaming mechanism;

[0058] Step 103, rename the flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register;

[0059] Step 104, update the entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register.

[0060] The register renaming method provided by the embodiment of the present invention can be applied to a processor for implementing renaming of a flag bit register.

[0061] It should be noted that the flag bit register is a special register defined by the instruction set, which stores the flag bits of the calculation results. For example, EFLAGS (CF / PF / AF / ZF / SF / OF) in x86, APSR (ZF / CF / NF / VF) in AArch64, which represent the result status of the operation, carry, parity check, adjustment, zero and sign flag and other information. For example, if the operation result is 0, ZF is 1, and if the operation result is 1, ZF is 0; while SF flags the sign bit of the result.

[0062] The flag bits have multiple uses, which may specifically include at least one of the following:

[0063] 1. Used as the source operand of a jump instruction, and the jump instruction can determine whether to jump according to the value of the FLAGS register

[0064] 2. The conditional transfer instruction can determine whether to transfer data according to the value of the flag bit register.

[0065] 3. Further operations. For example, the ADC (ADD with Carry) instruction adds the CF to the operand to perform an addition operation.

[0066] Good design of the flag bits can accelerate the running of the program to a certain extent; while the RISC instruction set lacks the support of flag bits and is relatively poor in some fields, such as the field of encryption and decryption.

[0067] In an out-of-order processor architecture, instructions will go through stages such as decoding, renaming, dispatching, issuing, executing, writing back, and committing in sequence. The calculation of flag bits mainly involves the processing logic in the renaming, issuing, and writing-back stages in the processor. As Figure 2 shown, a schematic diagram of the processing flow of the flag bit register in a superscalar processor pipeline is shown. As Figure 2 shown, after the multi-way decoder decodes the instruction, it enters the renaming stage. The processor renames the registers of the instruction by reading the renaming table (including the renaming table of general-purpose registers and the renaming table of flag bit registers). After renaming, it enters the dispatching stage, and the instruction is sent to the instruction reorder queue, and then sent to the issue queue in the issuing stage. After that, in the execution stage, the instructions in the issue queue are sequentially sent into the execution unit for execution. Among them, in the issuing stage, it involves the dependency judgment logic, register reading logic, and forwarding logic for each register. After the execution unit executes an instruction, in the writing-back stage, the register resources are updated, specifically involving the register writing logic and the physical register release logic.

[0068] In the renaming stage, the logical registers in an instruction are renamed to physical registers. Specifically, the processor will obtain the corresponding physical register number for the source logical register number (source operand) of the instruction, and update the entry corresponding to the destination logical register in the renaming table according to the destination logical register number and physical register number of the instruction. Among them, the renaming table is used to record the mapping relationship between the logical register number and the physical register number. The physical register corresponding to the source logical register (source operand) of the instruction can be obtained by reading the renaming table.

[0069] If an instruction needs to write to a logical register, then during the renaming stage, the processor fetches the number of an idle physical register from the list of physical registers in the space and uses this number of the idle physical register to update the entry corresponding to the destination logical register (destination operand) in the renaming table.

[0070] As an example, for the following code D1, which contains write-after-write dependencies, where "r" represents a logical register and "pr" represents a physical register:

[0071] add r1,r2,r3

[0072] or r3,r1,r4

[0073] Assume that the corresponding renaming table at this time is:

[0074] r1→pr91

[0075] r2→pr92

[0076] r3→pr93

[0077] r4→pr94

[0078] After the above code D1 is renamed, it becomes:

[0079] add pr101,pr92,pr93

[0080] or pr102,pr101,pr94

[0081] After renaming, the renaming table is updated to:

[0082] r1→pr101

[0083] r2→pr92

[0084] r3→pr102

[0085] r4→pr94

[0086] It should be noted that the code D1 represents the execution of the logical operations "r1 = r2 + r3" and "r3 = r1 | r4". The calculation result of "r2 + r3" is written into the logical register r1, and the result of the OR operation between r1 and r4 is written into the logical register r3.

[0087] Since the above operations will cause the parameter value corresponding to r1 to be updated, during the renaming stage, the processor will newly allocate an idle physical register for the logical register r1. Therefore, the physical register pr91 corresponding to the logical register r1 in the renaming table will be updated to pr101. Similarly, since the parameter value corresponding to the logical register r3 will be updated, during the renaming stage, the processor will newly allocate an idle physical register for the logical register r3. Therefore, the physical register pr91 corresponding to the logical register r3 in the renaming table will be updated to pr102.

[0088] It should be noted that multiple instructions may be renamed within one cycle. Therefore, for an instruction that is not the first one to be renamed, the physical register corresponding to its source logical register needs to be determined in combination with the physical register number of the destination logical register that was renamed earlier in this cycle.

[0089] The renaming mechanism can avoid false dependencies in the program and improve the concurrency of the processor.

[0090] Instructions that generate and use flag bits can be divided into two types:

[0091] Type1: add.f, an addition instruction that calculates the addition result and the flag bit result;

[0092] Type2: branch.cc.f, a branch instruction that determines whether to jump based on the flag bit.

[0093] The renaming of flag bits can adopt a method similar to that of the GPR register renaming.

[0094] Exemplarily, for the following code D2, which contains instructions that generate and use flag bits, where "r" represents the logical register, "pr" represents the physical register, and "pfr" represents the physical register of the flag bit:

[0095] add.f r1,r2,r3

[0096] or r3,r1,r4

[0097] branch.cc.f 0x234

[0098] Assume that the corresponding renaming table at this time is:

[0099] r1→pr101

[0100] r2→pr102

[0101] r3→pr93

[0102] r4→pr104

[0103] After the above code D2 is renamed, it becomes:

[0104] add.f pr100,pr102,pr93,write pfr5

[0105] or pr105,pr100,pr104,

[0106] branch.cc.f read pfr5 0x234

[0107] After renaming, the rename table is updated to:

[0108] r1 → pr100

[0109] r2 → pr102

[0110] r3 → pr105

[0111] r4 → pr104

[0112] It should be noted that the code D2 represents the execution of logical operations of "r1 = r2 + r3" and "r3 = r1 | r4". The calculation result of "r2 + r3" is written into the logical register r1, the result of the OR operation of "r1 | r4" is written into the logical register r3, and the flag bit is written into the register pfr5. Then, the flag bit recorded in the register pfr5 is read, and a jump judgment is made according to the read result. The target offset of the jump is "0x234".

[0113] Since the above operations will cause the parameter value corresponding to r1 to be updated, during the renaming stage, the processor will allocate a new free physical register for the logical register r1. Therefore, the physical register pr101 corresponding to the logical register r1 in the rename table will be updated to pr100. Similarly, since the parameter value corresponding to the logical register r3 will be updated, during the renaming stage, the processor will allocate a new free physical register for the logical register r3. Therefore, the physical register pr93 corresponding to the logical register r3 in the rename table will be updated to pr105.

[0114] During the process of renaming the above code D2, an add.f instruction needs to write two physical registers with different addresses (write physical registers pr100 and pfr5, or write physical registers pr105 and pfr5), which increases the design complexity of the add.f instruction in the microarchitecture and affects the execution efficiency of the add.f instruction by the processor.

[0115] If the register renaming method provided by the embodiment of the present invention is adopted, when the target instruction of the to-be-processed processor is the first instruction for writing a flag bit, first allocate a first destination physical register for the first destination logical register of the first instruction according to the renaming mechanism. Specifically, allocate an idle physical register as the first destination physical register for the first destination logical register. For example, in the example of the above code D2, allocate the destination physical register pr100 for the destination logical register r1 of the add.f instruction.

[0116] Then, rename the flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register. In other words, when renaming the register of the first flag bit of the first instruction, reuse the first destination physical register allocated for the first destination logical register of the first instruction. Exemplarily, in the example of the above code D2, if the register renaming method provided by the embodiment of the present invention is adopted, then write the flag bit into the register pr100. In other words, the register pr100 is renamed to the register "prf100" that can write the flag bit.

[0117] Finally, update the entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register, so as to update the physical register recorded in the entries corresponding to the first destination logical register and the first flag bit in the renaming table to the first destination physical register.

[0118] The renaming logic in the embodiment of the present invention can be expressed as:

[0119] if is_read_pfr:

[0120] pr_src1 = cur_flag

[0121] if is_write_pfr:

[0122] write_pfr = pr_dst

[0123] cur_flag = pr_dst

[0124] Wherein, is_read_pfr represents whether the current instruction reads a flag bit, and is_write_pfr represents whether the current instruction writes a flag bit; is_write_pfr and is_read_pfr are the results after instruction decoding and are supplied for renaming emission and execution. pr_src1 represents the physical register corresponding to the logical register src1 after renaming, cur_flag is the physical register position of the current flag bit saved in the renaming table; pr_dst is the physical register of the logical register dst after renaming, and write_pfr represents the physical register for writing the flag bit after renaming.

[0125] For an instruction that reads a flag bit, the physical register address (pr_src1) for reading the flag bit is set to the physical register address (cur_flag) where the current flag bit is located.

[0126] For an instruction that writes a flag bit, the physical register address (write_pfr) after renaming for writing the flag bit is the general register renaming address (pr_dst) for writing the GPR by this instruction. At the same time, the physical register address (cur_flag) of the current flag bit is set to the general register renaming address (pr_dst).

[0127] As an example, for code D2:

[0128] add.f r1,r2,r3

[0129] or r3,r1,r4

[0130] branch.cc.f 0x234

[0131] After renaming code D2 using the register renaming method provided by the embodiment of the present invention, the following results are obtained:

[0132] add.f pr100,pr102,pr93,write pfr100

[0133] or pr105,pr100,pr104,

[0134] branch.cc.f read pfr1000x234

[0135] Among them, the physical register address for the instruction add.f to write the flag bit is the renaming address prf100 of the general register for writing the GPR by this instruction, and the corresponding flag bit physical register is renamed to general register 100.

[0136] As can be seen from the above example, in the embodiment of the present invention, an instruction for writing a flag bit only needs to write one physical register, that is, the first destination physical register. For example, in the above example, write physical register prf100. The embodiment of the present invention simplifies the design complexity of flag bit-related instructions in the microarchitecture and is beneficial to improving the execution efficiency of the processor for flag bit-related instructions.

[0137] As another example, referring to Figure 3 , a schematic diagram of a renaming mechanism provided by the embodiment of the present invention is shown. As Figure 3 shown, for code D3:

[0138] add.f r1,r2,r3

[0139] or r3,r1,r4

[0140] branch.cc.f 0x100

[0141] Assume the renaming table before renaming is as follows:

[0142] r1→pr91

[0143] r2→pr92

[0144] r3→pr93

[0145] r4→pr94

[0146] r5→pr95

[0147] flag→prf50

[0148] After renaming the code D3 using the register renaming method provided by the embodiment of the present invention, the following results are obtained:

[0149] add.f pr101,pr92,pr93,write pfr101

[0150] or pr102,pr101,pr94,

[0151] branch.cc.f read pfr101 0x100

[0152] After renaming, the renaming table is updated to:

[0153] r1→pr101

[0154] r2→pr92

[0155] r3→pr102

[0156] r4→pr94

[0157] r5→pr95

[0158] flag→prf101

[0159] In the above example, the instruction add.f for writing the flag bit only needs to write one physical register, for example, write the general physical register 101; the physical register address for reading the flag bit of the instruction branch.cc.f is the physical register address where the currently written flag bit is located, that is, pfr101.

[0160] It can be understood that in Figure 3In the renamed table shown, although the physical register bank of GPR and the physical register bank of flag bits are recorded separately, the addresses of the general physical register and the flag bit physical register with the same number are the same. In other words, the general physical register and the flag bit physical register with the same number, such as pr101 and pfr101, are actually the same physical register.

[0161] Furthermore, in the embodiment of the present invention, the number of physical registers of GPR is equal to the number of physical registers of flag bits.

[0162] In an alternative embodiment of the present invention, the first instruction includes a logical operation instruction; the method further includes:

[0163] Step S11: Execute the first instruction to calculate according to the value in the source physical register corresponding to the source logical register of the first instruction, and obtain an operation result and a first value of the first flag bit;

[0164] Step S12: Write the operation result and the first value into the first destination physical register.

[0165] In the embodiment of the present invention, the first instruction for writing flag bits may include a logical operation instruction, such as the addition instruction add.f. After renaming the first instruction according to the method provided by the embodiment of the present invention, the first instruction is executed in the execution stage, that is, calculate according to the value in the source physical register corresponding to the source logical register of the first instruction, obtain an operation result and a first value of the first flag bit, and then write both the operation result and the first value into the first destination physical register.

[0166] As an example, the flag bit writing logic in the embodiment of the present invention can be expressed as:

[0167] if is_write_pfr

[0168] PFR[pr_dst]:=alu_flags_out

[0169] where is_read_pfr indicates whether the current instruction writes flag bits, PFR[] represents the physical register bank of flag bits, pr_dst represents the physical register of the logical register dst after renaming, and alu_flags_out represents the flag bit result after the current instruction is calculated by the arithmetic unit alu.

[0170] If a logical operation instruction for writing a flag bit is executed, the flag bit result (alu_flags_out) obtained by the arithmetic unit after calculation is written into the physical register with the address pr_dst. This physical register is the renamed physical register for the flag bit, that is, the first destination physical register in the embodiments of the present invention.

[0171] Exemplarily, for instruction A1:

[0172] add.f r1,r2,r3

[0173] After renaming instruction A1 using the register renaming method provided by the embodiments of the present invention, the following instruction is obtained:

[0174] add.f pr100,pr102,pr93,write pfr100

[0175] Execute instruction A1, that is, perform the operation of "pr102 + pr93", write the operation result into pr100, and write the value of the flag bit obtained by the operation into pfr100. Among them, "pr100" and "pfr100" refer to the same physical register, that is, the physical register numbered "100". Before renaming the physical register corresponding to the flag bit of instruction A1, physical register 100 is an ordinary physical register. After renaming the physical register corresponding to the flag bit of instruction A1 (that is, renaming the flag bit physical register corresponding to the flag bit to physical register 100), physical register 100 is a physical register that can write the flag bit.

[0176] In the embodiments of the present invention, the operation result and the value of the flag bit obtained by executing the logical operation instruction are both written into the same physical register. In other words, only one physical register needs to be written when executing a logical operation instruction, thereby improving the execution efficiency of the logical operation instruction.

[0177] Optionally, the method further includes:

[0178] Step S21: Determine whether the third physical register to be released is the first destination physical register corresponding to the first flag bit in the renaming table;

[0179] Step S22: Release the third physical register when the third physical register is not the first destination physical register.

[0180] Step S23: When the third physical register is the first destination physical register, release the target flag bit physical register, and set the first destination physical register as the physical register with the flag bit to be released; the target flag bit physical register is the physical register with the flag bit to be released saved before releasing the third physical register.

[0181] When releasing the physical register of the general-purpose register (GPR), the flag bit physical register also needs to be released. Specifically, if the third physical register to be released is not the flag bit physical register (such as the first destination physical register in the embodiments of the present invention), the third physical register can be directly released. If the third physical register to be released is the physical register where the current flag bit is saved in the rename table, such as the first destination physical register, since the first destination physical register is still in use at this time and cannot be directly released, the physical register with the flag bit to be released saved before, that is, the target flag bit physical register, can be released first, and then the first destination physical register is set as the physical register with the flag bit to be released, waiting for the next release.

[0182] Exemplarily, the physical register release logic in the embodiments of the present invention can be expressed as:

[0183] if free_pr == cur_flag:

[0184] PGPR_FREE[next_free_pr]: = 0

[0185] next_free_pr: = free_pr

[0186] else

[0187] PGPR_FREE[free_pr]: = 0

[0188] Among them, free_pr represents the third physical register to be released, cur_flag represents the physical register where the current flag bit is saved in the rename table, and next_free_pr represents the physical register to be released, that is, the physical register to be released next time.

[0189] If the third physical register to be released, free_pr, is equal to the physical register cur_flag that stores the current flag bit in the rename table, such as the first destination physical register, then first release the previously saved physical register to be released, next_free_pr, that is, the physical register of the target flag bit, and set the third physical register to be released, free_pr, as the physical register of the flag bit to be released, waiting for the next release. If the third physical register to be released, free_pr, is not equal to cur_flag, then the third physical register free_pr can be directly released.

[0190] The embodiments of the present invention define the release logic of the physical registers and the physical registers of the flag bits of the GPR, improve the register renaming operation, avoid the instruction execution error caused by the inappropriate release of the physical registers of the flag bits, and are beneficial to improving the overall performance of the processor.

[0191] Optionally, the method further includes:

[0192] Step S31: If the target instruction is the second instruction for reading the flag bit, query the second destination physical register corresponding to the second destination operand of the second instruction according to the rename table;

[0193] Step S32: If the second destination physical register is valid, determine that the physical register of the flag bit corresponding to the second instruction is valid;

[0194] Step S33: If the second destination physical register is invalid, determine that the physical register of the flag bit corresponding to the second instruction is invalid.

[0195] In the embodiments of the present invention, for the second instruction for reading the flag bit, such as the branch.cc.f instruction, the dependency judgment logic is as follows: first query the second destination physical register corresponding to the second destination operand of the second instruction according to the rename table. If the second destination physical register is valid, then the physical register of the flag bit corresponding to the second flag bit of the second instruction is valid; conversely, if the second destination physical register is invalid, then the physical register of the flag bit corresponding to the second flag bit of the second instruction is also invalid.

[0196] Exemplarily, the dependency judgment logic in the embodiments of the present invention can be expressed as:

[0197] if is_read_pfr

[0198] if pr_src1 ready

[0199] FLAGS ready

[0200] else

[0201] FLAGS not ready

[0202] Among them, is_read_pfr indicates whether the current instruction reads the flag bit, pr_src1 represents the physical register after the logical register src1 is renamed, and FLAGS represents the physical register of the flag bit corresponding to the current instruction.

[0203] If the current instruction is an instruction to read the flag bit, for example, an instruction to read the physical register of the flag bit pr_src1, if the pr_src1 register of the GPR is valid, then the physical register of the flag bit of this instruction is valid; conversely, if the pr_src1 register of the GPR is invalid, then the physical register of the flag bit of this instruction is invalid.

[0204] It can be understood that for the second instruction to read the flag bit, its destination operand (that is, the second destination operand in the embodiment of the present invention) indicates the logical register to be read. By querying the renaming table, the corresponding second destination physical register is determined. According to the dependency judgment logic of the embodiment of the present invention, it is only necessary to query whether the second destination physical register of the GPR is valid, and there is no need to query whether the physical register of the flag bit with the same address as the second destination physical register is valid, thereby reducing the dependency judgment logic and being beneficial to improving the operation efficiency of the processor.

[0205] Optionally, the method further includes:

[0206] Step S41: Read the value of the second flag bit from the second destination physical register;

[0207] Step S42: Perform a logical operation according to the value of the second flag bit.

[0208] In the embodiment of the present invention, for the operation of reading the physical register of the flag bit, the flag bit input of its operation unit comes from the result of reading the GPR physical register with the same address as the flag bit register. For example, for the second instruction to read the flag bit, the value of the second flag bit of the second instruction can be read from the second destination physical register corresponding to the second destination operand of this instruction, and then a logical operation is performed according to the read value of the second flag bit.

[0209] Exemplarily, the flag bit reading logic in the embodiment of the present invention can be expressed as:

[0210] if is_read_pfr

[0211] alu_flags_in:=PFR[pr_src1]

[0212] Among them, is_read_pfr indicates whether the current instruction reads the flag bit, pr_src1 represents the physical register after the logical register src1 is renamed, PFR[] represents the physical register file of the flag bits, and alu_flags_in is the input of the physical register of the flag bits after the current instruction enters the arithmetic unit alu for calculation.

[0213] In the embodiment of the present invention, when writing the flag bit, the physical register of the flag bit multiplexes the physical register of the GPR. When reading the address of the flag bit in the instruction for reading the flag bit, the read address of the GPR (such as pr_src1) can be directly multiplexed, thereby reducing the address information carried in the second instruction and reducing the design complexity of the instruction for reading the flag bit in the microarchitecture.

[0214] In addition, in the embodiment of the present invention, in the pipeline forwarding process of the processor, the data forwarded by the flag bit comes from the flag bit output of the arithmetic unit. Exemplarily, the forwarding logic in the embodiment of the present invention can be expressed as:

[0215] if src1 ready:

[0216] alu_flags_in := alu_flags_out

[0217] Among them, src1 is a logical register, alu_flags_in is the input of the physical register of the flag bits after the instruction enters the alu for calculation, and alu_flags_out is the result of the flag bits after the instruction passes through the alu for calculation. During the forwarding process, for a certain instruction, the input of the physical register of the flag bits when it enters the arithmetic unit alu for calculation comes from the result of the flag bits after the previous arithmetic unit alu calculation.

[0218] It should be noted that the pipeline forwarding technology refers to directly using the operation result of the previous instruction as the input of the subsequent instruction through a multiplexer at the place where the source operand of the instruction is read in the pipeline.

[0219] After adopting the above forwarding logic, the processor can directly obtain the flag bit result from the output end of the arithmetic unit without reading the physical register of the flag bit again, thereby improving the processing efficiency of the processor.

[0220] In summary, the embodiment of the present invention provides a register renaming method. When the target instruction to be processed is the first instruction for writing a flag bit, the method first allocates a first destination physical register for the first destination logical register of the first instruction according to the renaming mechanism, and then renames the flag bit physical register corresponding to the first flag bit of the first instruction as the first destination physical register, and updates the entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register, so as to update the physical registers recorded in the entries corresponding to the first destination logical register and the first flag bit in the renaming table as the first destination physical register. When the register of the first flag bit of the first instruction is renamed in the embodiment of the present invention, the first destination physical register allocated for the first destination logical register of the first instruction is reused. Therefore, an instruction for writing a flag bit only needs to write one physical register, that is, the first destination physical register, which reduces the design complexity of the flag bit-related instructions in the microarchitecture and is beneficial to improving the execution efficiency of the processor for the flag bit-related instructions.

[0221] It should be noted that, for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequences, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0222] Device embodiment

[0223] Referring to Figure 4 , a schematic structural diagram of a processor according to the present invention is shown. As Figure 4 shown, the processor 400 includes logical registers, physical registers, a renaming table, an execution unit, an instruction fetching and decoding unit, and renaming logic.

[0224] Among them, the instruction fetching and decoding unit is used to fetch and decode the target instruction to be processed; after decoding, it can determine whether the instruction writes or reads a flag bit.

[0225] The renaming logic is used to, when the target instruction is the first instruction for writing a flag bit, allocate a corresponding first destination physical register for the first destination logical register of the first instruction according to the renaming mechanism; rename the flag bit physical register corresponding to the first flag bit of the first instruction as the first destination physical register; and update the entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register.

[0226] Optionally, the first instruction includes a logical operation instruction; the execution unit is further used for:

[0227] Execute the first instruction to perform a calculation based on the value in the source physical register corresponding to the source logical register of the first instruction, to obtain an operation result and a first value of the first flag bit;

[0228] Write the operation result and the first value into the first destination physical register.

[0229] Optionally, the renaming logic is further configured to:

[0230] Determine whether the third physical register to be released is the first destination physical register corresponding to the first flag bit in the renaming table;

[0231] Release the third physical register if the third physical register is not the first destination physical register;

[0232] Release the target flag bit physical register and set the first destination physical register as the flag bit physical register to be released if the third physical register is the first destination physical register; the target flag bit physical register is the flag bit physical register to be released saved before releasing the third physical register.

[0233] Optionally, the renaming logic is further configured to:

[0234] If the target instruction is a second instruction for reading a flag bit, query the second destination physical register corresponding to the second destination operand of the second instruction according to the renaming table;

[0235] Determine that the flag bit physical register corresponding to the second instruction is valid if the second destination physical register is valid;

[0236] Determine that the flag bit physical register corresponding to the second instruction is invalid if the second destination physical register is invalid.

[0237] Optionally, the execution unit is further configured to:

[0238] Read the value of the second flag bit from the second destination physical register;

[0239] Perform a logical operation according to the value of the second flag bit.

[0240] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0241] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

[0242] The above has introduced in detail a register renaming method and a processor provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A register renaming method, characterized in that, The method includes: Obtaining a target instruction to be processed; If the target instruction is a first instruction for writing a flag bit, allocating a corresponding first destination physical register for a first destination logical register of the first instruction according to a renaming mechanism; Renaming a flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register; Updating entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register.

2. The method according to claim 1, characterized in that, The first instruction includes a logical operation instruction; the method further includes: Executing the first instruction to perform a calculation based on values in source physical registers corresponding to source logical registers of the first instruction, obtaining an operation result and a first value of the first flag bit; Writing the operation result and the first value into the first destination physical register.

3. The method according to claim 1, characterized in that The method further includes: Determining whether a third physical register to be released is the first destination physical register corresponding to the first flag bit in the renaming table; Releasing the third physical register when the third physical register is not the first destination physical register; Releasing a target flag bit physical register and setting the first destination physical register as a flag bit physical register to be released when the third physical register is the first destination physical register; the target flag bit physical register is a flag bit physical register to be released saved before releasing the third physical register.

4. The method according to claim 1, wherein The method further includes: If the target instruction is a second instruction for reading a flag bit, querying a second destination physical register corresponding to a second destination operand of the second instruction according to the renaming table; Determining that a flag bit physical register corresponding to the second instruction is valid if the second destination physical register is valid; Determining that a flag bit physical register corresponding to the second instruction is invalid if the second destination physical register is invalid.

5. The method according to claim 4, wherein The method further includes: Reading a value of the second flag bit from the second destination physical register; Performing a logical operation according to the value of the second flag bit.

6. A processor, characterized in that, The processor includes: Logical registers; Physical registers; Renaming table; An instruction fetching and decoding unit for obtaining a target instruction to be processed and decoding it; An execution unit for executing instructions; A renaming logic for, when the target instruction is a first instruction for writing a flag bit, allocating a corresponding first destination physical register for a first destination logical register of the first instruction according to a renaming mechanism; renaming a flag bit physical register corresponding to the first flag bit of the first instruction to the first destination physical register; updating entries corresponding to the first destination logical register and the first flag bit in the renaming table according to the first destination physical register.

7. The processor according to claim 6, wherein The first instruction includes a logical operation instruction; the execution unit is used for: Executing the first instruction to perform a calculation based on values in source physical registers corresponding to source logical registers of the first instruction, obtaining an operation result and a first value of the first flag bit; Writing the operation result and the first value into the first destination physical register.

8. The processor according to claim 6, characterized in that, The renaming logic is further used for: determining whether a third physical register to be released is a first destination physical register corresponding to the first flag bit described in the renaming table; releasing the third physical register when the third physical register is not the first destination physical register; releasing a target flag bit physical register and setting the first destination physical register as a flag bit physical register to be released when the third physical register is the first destination physical register; the target flag bit physical register is the flag bit physical register to be released saved before releasing the third physical register.

9. The processor according to claim 6, wherein The renaming logic is further used for: if the target instruction is a second instruction for reading a flag bit, querying a second destination physical register corresponding to a second destination operand of the second instruction according to the renaming table; determining that the flag bit physical register corresponding to the second instruction is valid if the second destination physical register is valid; determining that the flag bit physical register corresponding to the second instruction is invalid if the second destination physical register is invalid.

10. The processor according to claim 9, wherein The execution unit is further used for: reading the value of the second flag bit from the second destination physical register; performing a logical operation according to the value of the second flag bit.

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