Non-volatile memory switch with host isolation

Abstract

The embodiment of the invention relates to a non-volatile memory switch with host isolation. The NVM switch has been designed to allow multiple hosts to access a single port NVM device simultaneously and independently. While this active-active multi-host usage configuration allows for various uses of low-cost single-port NVM devices, a problem of one of the hosts may delay or block transactions between other hosts and the NVM device. Although logic of the switch is shared across hosts, the NVM switch includes logic that isolates activity of multiple hosts. When the switch detects a problem of one host ("wrong host"), the switch clears the operating command of the wrong host and flushes the data of the wrong host. Likewise, the NVM switch ensures correct communication of error reports from the attached NVM device to the plurality of hosts.

Description

[0001] Division Application Instructions

[0002] This application is a divisional application of a Chinese patent application with an application date of August 7, 2019, an application number of 201910727578.X, and a title of "Non-Volatile Memory Switch with Host Isolation".

[0003] Cross-reference to Related Applications

[0004] This disclosure claims the benefit of the priority of U.S. Provisional Application Serial No. 62 / 715,713, filed on August 7, 2018, with the title "NVMe Protocol Switch Host Isolation in Active-Active Configuration", the content of which is incorporated herein by reference in its entirety. BACKGROUND OF THE DISCLOSURE

[0005] This disclosure generally relates to the field of computer architectures and, more particularly, to input / output devices and operations.

[0006] High-performance computing environments are increasingly using non-volatile memory (NVM), such as flash memory, for storage solutions. In addition to traditional storage device interfaces optimized for rotating media technology, host controller interfaces optimized for NVM are also used. The Non-Volatile Memory Express (NVMe) specification is a scalable host controller interface specification for NVM that utilizes the Peripheral Component Interconnect-Express architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure can be better understood by referring to the accompanying drawings.

[0008] Figure 1 A block diagram of an example system is depicted that includes an NVM switch having logic and program code for multi-host to single-port host isolation.

[0009] Figure 2 is an example diagram of NVM switch logic to isolate hosts in an active-active configuration with a single-port NVM device.

[0010] Figure 3 is a flowchart of an example operation for isolating error completion status detected in a host response.

[0011] Figure 4 is a flowchart of an example operation for an NVM switch to isolate host data errors detected by the switch.

[0012] Figure 5It is a flowchart of an example operation for isolating data errors detected in read completion packets by an NVM switch.

[0013] Figure 6 It is a flowchart of an example operation for isolating a link disconnection event by an NVM switch from one of multiple hosts.

[0014] Figure 7 It is a flowchart of an example operation for isolating a reset by an NVM switch from one of multiple connected hosts.

[0015] Figure 8 It is a flowchart of an example operation for propagating error reports across hosts by an NVM switch. Detailed implementation

[0016] The following description includes example systems, methods, techniques, and program flows that embody aspects of the present disclosure. However, it should be understood that the present disclosure may be practiced without these specific details. For example, the present disclosure relates to PCIe in illustrative examples. Aspects of the present disclosure may also be applied to another similar interconnect architecture or specification for highly scalable high-speed communication with non-volatile memories or solid-state devices. In other cases, well-known instruction instances, protocols, structures, and techniques are not shown in detail so as not to obscure the description.

[0017] Overview

[0018] Dual-port NVM devices (e.g., solid-state drives (SSDs)) allow multiple hosts to access flash memory at a cost. NVM switches have been designed to allow multiple hosts to simultaneously and independently access a single-port NVM device. Although this active-active multi-host usage configuration allows various uses of low-cost single-port NVM devices (e.g., storage virtualization, redundant array of independent disks (RAID) functions, etc.), a problem in one of the hosts (e.g., failure, loss of reference clock, etc.) can delay or prevent transactions between other hosts and the NVM device. Although the logic of the switch is shared among the hosts, the NVM switch includes logic for isolating the activities of multiple hosts. When the switch detects a problem with one host (“error host”), the switch clears the running commands of the error host and flushes the data of the error host. Similarly, the NVM switch can ensure the correct communication of error reports from the connected NVM device to multiple hosts.

[0019] Example Illustrations

[0020] Figure 1Depicts a block diagram of an example system that includes an NVM switch having logic and program code for multi-host to single-port host isolation. The example system (e.g., a server rack) includes a backplane interconnect 117. A plurality of hosts including host 119 and host 121 are connected to the backplane interconnect 117. The NVM package 102 is also connected to the backplane interconnect. Hosts 119, 121, and the NVM package 102 are all connected to the backplane interconnect 117 via PCIe connectors.

[0021] The NVM package 102 includes an NVM switch 101, a single-port NVM device 120, and another single-port NVM device 122. The NVM devices can be solid-state devices having various configurations. In Figure 1 it, the NVM device 120 is depicted as having an NVM controller 103, addressing logic 107, and flash memories 109A to 109D.

[0022] The NVM switch 101 simultaneously and independently facilitates hosts 119, 121 using the NVM devices 120, 122. Hosts 119, 121 maintain command queues and completion queues in their local memories. Hosts 119, 121 transmit messages and requests (e.g., doorbell messages) to the NVM devices 120, 122 via the NVM switch. The NVM controller 103 retrieves commands from the command queues of hosts 119, 121 via the NVM switch 101. In response to messages from hosts 119, 121. The NVM controller 103 writes completion packets to the completion queues of hosts 119, 121 via the NVM switch 101. Since each of the NVM devices 120, 122 is a single-port, the NVM switch 101 presents a single requester to each of the NVM devices 120, 122. The NVM switch 101 includes logic for properly routing packets to hosts 119, 121 and isolating errors between the connected hosts.

[0023] Figure 2An example diagram of the NVM switch logic to isolate hosts in an active-active configuration with single-port NVM devices. The NVM switch 200 includes an interconnect interface 207 and a non-volatile memory device interface 215. These interfaces can be the same but can also be different. For example, interface 207 can be a PCIe interface with a larger number of lanes than interface 215. This example diagram assumes that the host (root complex from the perspective of switch 200) is linked via the interconnect interface 207 and the NVM memory device is attached to switch 200 through interface 215. The switch 200 includes switch configuration and management logic 203, transaction management logic 201, and direct data path logic 205. The term "logic" refers to the circuit arrangement for implementing a task or function. For example, the logic to determine whether values match can be a circuit arrangement that uses exclusive NOR gates and AND gates for equality comparison. The configuration and management logic 203 directs management and configuration commands to the attached NVM devices. The direct data path logic 205 allows read-completed writes to traverse the switch 200 with little or no latency. The transaction management logic 201 prevents hosts from interfering with each other. This includes at least isolating the performance of an affected event to the transaction of the host where the event occurred ("faulty host"), propagating error reports according to host-specific error reporting settings, and monitoring for errors in the direct data path logic 205.

[0024] Transaction management logic 201 includes registers and logic to facilitate functions for preventing events from one host from affecting transactions of another host. The transaction management logic includes queue 202, timing source 231, host identifier logic 209, reservation logic 211, error isolation logic 213, queue 204, and queue 206. Queues 202, 204, 206 can be 32-bit registers, 64-bit registers, or different types of memory elements suitable for the physical space available for switch 200. Queue 202 stores incoming packets from the host. Examples of incoming data packets include doorbell messages, read commands from host memory, and completion responses. Since switch 200 accommodates multiple hosts, reservation logic 211 reserves different areas of the attached memory or backend device for the hosts to prevent the hosts from overwriting each other. When a host establishes a connection with a backend device via switch 200, reservation logic 211 creates and maintains a mapping to the reserved storage space for each host. Reservation logic 211 can implement reservation by utilizing available private namespace functionality. Another responsibility of switch 200 is to present a single host to the backend device, as the backend device is single-port. This hides the multiple hosts on the other end of switch 200 from the backend device. Host identifier logic 209 and queues 204, 206 are used to ensure the consistency of communication between the backend device and the hosts, even though the backend device is presented as a single host. Host identifier logic 209 associates a first host identifier with queue 204 and a second host identifier with queue 206. Implementations can add additional queues based on the number of hosts connected to the backend device via the NVM switch. Host identifier logic 209 copies the subfield values from the header of an incoming read-type packet into one of queues 204, 206 corresponding to the detected host identifier (e.g., requester identifier or node identifier). These copied values will be used to determine which host is the correct requester. Utilizing the reserved space, host identifier logic 209 can copy the length, address, and ordering tag fields to match the subsequent read completion packet that writes data in response to the read-type packet. Then, host identifier logic 209 resets the host identifier in the input packet to conform to the expected host identifier of the backend device (e.g., root complex 0) before allowing the input packet to flow to the backend device.

[0025] When the backend device returns a read completion packet, the backend device writes the completion packet to the requester via the switch. The read completion packet will have the host identifier reset by switch 200. When the backend device writes the completion packet to the completion write queue 221 of the direct data path logic 205, host identifier 209 determines which of queues 204, 206 has an entry that at least matches the stored fields (e.g., length, ordering tag, address).

[0026] By retaining the host / requester at the switch, the error isolation logic 213 can prevent host events from affecting each other. The error isolation logic 213 can cause appropriate packets to be cleared from the queue 202 based on detecting a problem event for one of the hosts in the host. The error isolation logic 213 can also clear completion packets from the direct data path logic 205 corresponding to a failed or disconnected host. Additionally, the error isolation logic 213 can convert the NVM switch 200 to use the internal timing source 231 in response to detecting a loss of clock reference for one of the adapters in the adapter. The switch 200 switches to the timing source 231 for processing and communicating packets from the adapter that has lost its reference clock.

[0027] Although Figure 2 depicts discrete logic blocks, the different blocks are not necessarily the physical boundaries of the microchip. For example, the NVM switch can include a processor that is logically part of multiple ones of the depicted logic blocks.

[0028] Figures 3 to 8 The flowchart in depicts example operations related to processing error conditions to maintain host isolation. The description refers to the switch as performing the example operations. The switch performs at least some of the operations in accordance with program instructions (e.g., firmware) stored on the NVM switch.

[0029] Figure 3 is a flowchart of example operations for isolating error completion status detected in a host response. After a backend device requests to read data from a host memory, the host provides a packet with the read completion data to the backend device. The packet includes a field for a completion status that can indicate an error. The NVM switch reads the data packet before delivering the completion data to the backend device.

[0030] In block 301, the switch detects an error code in the completion status of the host response to the read from the backend device. The error code can indicate an error based on the completion, a poisoned payload notification, and an internal parity error or error correction code error. The switch can compare the bit at the position corresponding to the completion status with a predefined error code or look up the completion status value in a completion status table.

[0031] In block 303, the switch determines whether the completion status indicates an error based on the completion. Examples of errors based on the completion can be a completer abort (CA), an unsupported request (UR), and a completion timeout.

[0032] If the error code in the completion status field is completion-based, the switch modifies the completion status in the host response at box 305. The switch changes the error code in the completion status to indicate a completion with a completer abort (CA) before allowing the host response to be sent to the backend device identified in the host response.

[0033] At box 307, the switch determines whether the completion status field indicates a poisoned payload. If the completion status field indicates a poisoned payload, the control flow goes to box 311. At box 311, the switch forwards the host response with the poisoned payload indication to the backend device. Otherwise, the control flow goes to box 309.

[0034] If the completion status indicates that an internal parity error or an ECC error has been detected at the host, then at box 309, the switch discards the corrupted data and triggers a data path data integrity error mode in the switch. In this mode, all requests from the backend device to a particular host are dropped, and the read requests are completed and an error is displayed. For example, the switch can set a value in a register associated with the port of the backend device. When the switch receives a request from the backend device, the switch determines the corresponding host identifier. If the host identifier matches the value associated with the port of the backend device for the determined host, the request is dropped.

[0035] Figure 4 Is a flowchart of an example operation in which the NVM switch isolates host data errors detected by the switch. When attempting to avoid inserting latency into the NVM transaction path, the switch also supports data integrity. If the data integrity error mode is activated, the switch evaluates the data parity of the read packets and traverses the read completion packets of the switch.

[0036] At box 401, the switch detects a data parity error in the completion data of the host response. This detection can be the detection of bits set by the data link layer component.

[0037] At box 403, the switch modifies the read packet host response to indicate a poisoned payload in the completion status field. The switch can use the stored poisoned payload code to propagate this parity error detection.

[0038] At box 405, the switch forwards the modified host response to the backend device.

[0039] Figure 5 Is a flowchart of an example operation for the NVM switch to isolate data errors detected in write transactions. The direct data path logic of the NVM switch can be set to check for parity or ECC errors in the data of write transactions from the backend device.

[0040] At block 501, the switch detects a parity error or an uncorrectable ECC error in the write data from the backend device. The switch can examine the data link layer bits to detect an internal parity error or an uncorrectable ECC error.

[0041] At block 503, the switch discards the write data. The discarding of the write data discards the entire write transaction issued by the backend device.

[0042] At block 505, the switch triggers the data path data integrity error mode. In this mode, all requests from the backend device to a specific host are deleted, and read requests are completed and an error is shown.

[0043] Figure 6 Is a flowchart of an example operation for an NVM switch to isolate a link disconnection event from one of multiple hosts. At block 601, the switch detects a link disconnection of a host previously linked to the switch. A component of the data link layer component or the PCIe core detects the link disconnection. The link disconnection indication includes the identifier of the corresponding host. At block 603, the switch triggers a transaction flush of all in-flight transactions targeted at the host with the link disconnection from the NVM device attached to the switch. At block 604, the switch stops traffic to the link-disconnected port. To pause the traffic to the link-disconnected port, the switch aborts all outstanding commands associated with the host pending in the NVM device. At block 605, the switch initiates a reset of the components corresponding to the host with the link disconnection. At block 607, the switch re-establishes or attempts to re-establish a link with the host.

[0044] Figure 7 Is a flowchart of an example operation for an NVM switch to isolate a reset from one of multiple connected hosts. The switch processes reset events per link. The reset event can be a warm reset (PERST), a hot reset, a link disable, and a function level reset (FLR). At block 701, the switch detects a reset command from the host to the endpoint (EP) core implementing a lower layer protocol (e.g., data link layer, physical layer). The switch detects the reset because the reset signal or command generates an interrupt to the switch. At block 703, the switch discards the outstanding submission queue entries received via the EP core. At block 705, the switch aborts the issued but uncompleted commands associated with the EP core. The switch determines the in-flight read commands missing the corresponding read completion in the write queue sent to the host. Then, the switch sends an abort command for each of these uncompleted transactions to the corresponding backend device. At block 707, the switch triggers a transaction flush of the EP core. The switch asserts a signal to cause the EP core to clear the data packets traversing the EP core. At block 709, the switch deletes the queue associated with the EP core being reset. At block 711, the switch initiates a reset of the EP core.

[0045] Figure 8 It is a flowchart of an example operation for cross-host propagation of error reports in an NVM switch. The error report settings include basic error report settings and advanced error reporting (AER) settings set in the registers of the backend device. At block 801, the switch detects the error report settings from the host during enumeration and configuration operations. At block 803, the switch determines whether the error report settings are different between hosts. If the error report settings are the same between hosts, the switch transmits an instance of the error report settings to the attached backend device at block 804. If the error report settings are different, the switch stores an instance of each error report setting. At block 805, the host associates the corresponding host identifier with each instance of the error report settings. This is used to ensure host-specific compliance of error reports from the backend device. At block 807, the switch transmits the instance of the error report settings provided by the host and additional settings to the attached backend device.

[0046] At a later time, the switch can detect an error report from the backend device at block 809. At block 810, the switch determines whether there is a stored instance of an error report setting for which the error report does not conform. For example, the stored instance of the error report settings can indicate that the error report should be a completion status, while the detected error report is an error message. At block 813, the switch transmits the error report to all hosts because the error report conforms to the instance of the error report settings. If an inconsistency is detected for an instance of the error report settings, at block 811 the switch transmits the error report to the host associated with the instance of the error report settings, and the error report is consistent with the error report settings. At block 815, the switch derives and conveys the error report for other instances of the error report settings. The switch extracts information from the detected error report and generates an error report with that information based on the instance of the error report settings.

[0047] The flowchart is provided to assist in understanding the description and is not intended to limit the scope of the claims. The flowchart depicts example operations that can vary within the scope of the claims. Additional operations can be performed; fewer operations can be performed; operations can be performed in parallel; and operations can be performed in a different order. It will be understood that each block of the flowchart illustration and / or block diagram, and combinations of blocks in the flowchart illustration and / or block diagram, can be implemented by program code. The program code can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable machine or device.

[0048] As will be appreciated, aspects of the present disclosure may be embodied as a system, method, or program code / instructions stored on one or more machine-readable media. Accordingly, aspects may take the form of hardware, software (including firmware, resident software, microcode, etc.), or a combination of software and hardware aspects, which may generally be referred to herein as "circuitry", "module", or "system". The functionality presented as a single module / unit in the example illustrations may be organized differently depending on any one of the platform (operating system and / or hardware), application ecosystem, interface, programmer preference, programming language, administrator preference, etc.

[0049] Any combination of one or more machine-readable media may be utilized. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable storage medium may be, for example but not limited to, a system, apparatus, or device that employs any one or a combination of the following technologies to store program code: electronic, magnetic, optical, electromagnetic, infrared, or semiconductor. More specific examples (a non-exhaustive list) of the machine-readable storage medium would include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a machine-readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable storage medium is not a machine-readable signal medium.

[0050] A machine-readable signal medium may include a propagated data signal in which machine-readable program code is embodied, for example, in a baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A machine-readable signal medium may be any machine-readable medium that is not a machine-readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0051] The program code / instructions may also be stored in a machine-readable medium that can direct a machine to operate in a particular manner, such that the instructions stored in the machine-readable medium produce an article of manufacture that includes instructions for implementing the functions / actions specified in the flowchart and / or block diagram block or blocks.

[0052] Multiple instances may be provided for the components, operations, or structures described herein as a single instance. Finally, the boundaries between the various components, operations, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of a particular illustrative configuration. Other functional allocations are envisioned and may fall within the scope of the present disclosure. In general, structures and functions that are presented as separate components in an example configuration may be implemented as a combined structure or component. Similarly, structures and functions that are presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements may fall within the scope of the present disclosure.

[0053] Terms

[0054] As used herein, the term "or" is inclusive unless explicitly stated otherwise. Thus, the phrase "at least one of A, B, or C" is satisfied by any element or any combination from the set {A, B, C}, including multiples of any element.

Claims

1. A method for facilitating access to one or more single-port non-volatile memory devices by a plurality of host computers, the method comprising: Receiving, at the non-volatile memory switch, memory transaction messages from different root complexes corresponding to the plurality of host computers, each of at least some of the memory transaction messages including a host identifier that identifies the root complex from which the memory transaction is received; Generating, at the non-volatile memory switch, modified memory transaction messages by changing, at least, the host identifier within at least some of the memory transaction messages to a common value indicating a single root complex, to present the different root complexes as the single root complex to the one or more single-port non-volatile memory devices; Maintaining, at the non-volatile memory switch, an association between the memory transaction messages and the corresponding root complexes among the different root complexes; And Sending, by the non-volatile memory switch, the modified memory transaction messages to the one or more single-port non-volatile memory devices.

2. The method according to claim 1, wherein generating the modified memory transaction messages and changing the host identifier to the common value indicating the single root complex hides from the one or more single-port non-volatile memory devices that the memory transaction messages are from different root complexes.

3. The method according to claim 1, further comprising: Determining, by the non-volatile memory switch, among the different root complexes, the root complex corresponding to a completion message received by the non-volatile memory switch from the one or more single-port non-volatile memory devices, using the association between the memory transaction messages and the corresponding root complexes among the different root complexes.

4. The method according to claim 3, wherein maintaining the association between the memory transaction messages and the corresponding root complexes among the different root complexes comprises: Associating, at the non-volatile memory switch, a first queue in the non-volatile memory switch with a first root complex among the plurality of root complexes; Associating, at the non-volatile memory switch, a second queue in the non-volatile memory switch with a second root complex among the plurality of root complexes; Storing, for each of at least some of the memory transaction messages having a host identifier identifying the first root complex, header information from the header of the memory transaction message into the first queue for use in identifying a corresponding completion message received from the one or more single-port non-volatile memory devices; And Storing, for each of at least some of the memory transaction messages having a host identifier identifying the second root complex, header information from the header of the memory transaction message into the second queue for use in identifying a corresponding completion message received from the one or more single-port non-volatile memory devices.

5. The method according to claim 1, wherein maintaining the association of the memory transaction message with the corresponding root complex in the different root complexes includes: When receiving a memory transaction message from a specific root complex, storing, by the non-volatile memory switch, information from the header of the memory transaction message into a queue corresponding to the host identifier detected in the memory transaction message, and the information from the header stored in the queue is for subsequent use by the non-volatile memory switch when determining the corresponding host identifier for the memory transaction message.

6. The method according to claim 1, further comprising: Reserving, at the non-volatile memory switch, a corresponding memory space region in the one or more single-port non-volatile memory devices for the corresponding root complex to prevent one root complex from overwriting data written by another root complex.

7. The method according to claim 1, further comprising: Receiving, at the one or more single-port non-volatile memory devices, the modified memory transaction message from the non-volatile memory switch via a first interconnect.

8. The method according to claim 7, wherein receiving the modified memory transaction message from the non-volatile memory switch includes: Via Peripheral Component Interconnect Express The interconnect receives the modified memory transaction message from the non-volatile memory switch.

9. The method according to claim 7, further comprising: Generating, at the plurality of host computers, the memory transaction message; and Sending, by the plurality of host computers, the memory transaction message to the non-volatile memory switch via the first interconnect.

10. The method according to any one of claims 1 to 9, further comprising: Selecting, by the non-volatile memory switch, a memory transaction message in the non-volatile memory switch associated with the specific root complex based on the detection of an error condition corresponding to the specific root complex; and Clearing, by the non-volatile memory switch, the selected memory transaction message from the non-volatile memory switch.

11. A non-volatile memory switch for facilitating access by a plurality of host computers to one or more single-port non-volatile memory devices, the non-volatile memory switch comprising: A first communication interface configured to receive memory transaction messages from different root complexes corresponding to the plurality of host computers, each of at least some of the memory transaction messages including a host identifier that identifies the root complex from which the memory transaction is received; A circuit coupled to the first communication interface and configured to: Generate a modified memory transaction message at least by changing the host identifier within at least some of the memory transaction messages to a common value indicating a single root complex, so as to present the different root complexes as the single root complex to the one or more single-port non-volatile memory devices, and Maintain the association of the memory transaction message with the corresponding root complex in the different root complexes; And A second communication interface, the second communication interface being coupled to the circuit, the second communication interface being configured to send the modified memory transaction message to the one or more single-port non-volatile memory devices.

12. The non-volatile memory switch according to claim 11, wherein the circuit is configured to: Generate the modified memory transaction message and change the host identifier to indicate the common value of the single root complex to hide from the one or more single-port non-volatile memory devices that the memory transaction message comes from different root complexes.

13. The non-volatile memory switch according to claim 11, wherein the circuit is configured to: Use the association of the memory transaction message with the corresponding root complex in the different root complexes to determine, among the different root complexes, the root complex corresponding to the completion message received by the non-volatile memory switch from the one or more single-port non-volatile memory devices.

14. The non-volatile memory switch according to claim 13, further comprising: A memory for storing a plurality of queues, the plurality of queues including a first queue and a second queue; Wherein the circuit is configured to: Associate the first queue with a first root complex among the plurality of root complexes; Associate the second queue with a second root complex among the plurality of root complexes; For each memory transaction message in at least some of the memory transaction messages having a host identifier identifying the first root complex, store header information from the header of the memory transaction message into the first queue for use in identifying the corresponding completion message received from the one or more single-port non-volatile memory devices; And For each memory transaction message in at least some of the memory transaction messages having a host identifier identifying the second root complex, store header information from the header of the memory transaction message into the second queue for use in identifying the corresponding completion message received from the one or more single-port non-volatile memory devices.

15. The non-volatile memory switch according to claim 11, further comprising: A memory for storing a plurality of queues corresponding to respective host identifiers; Wherein the circuit is configured to: When receiving a memory transaction message from a specific root complex, store information from the header of the memory transaction message into the queue among the plurality of queues corresponding to the host identifier detected in the memory transaction message, and the information from the header stored in the queue is for subsequent use by the circuit in determining the corresponding host identifier for the memory transaction message.

16. The non-volatile memory switch according to claim 11, wherein the circuit is further configured to: Reserve a corresponding memory space area in the one or more single-port non-volatile memory devices for the corresponding root complex to prevent one root complex from overwriting data written by another root complex.

17. The non-volatile memory switch according to claim 11, wherein the circuit comprises: a processor; and a memory coupled to the processor, the memory storing machine-readable instructions that, when executed by the processor, cause the processor to: generate the modified memory transaction message; and maintain the association of the memory transaction message with the corresponding root complex in the different root complexes.

18. A system comprising: the non-volatile memory switch according to claim 11; the one or more single-port non-volatile memory devices; and a first interconnect that communicatively couples the one or more single-port non-volatile memory devices to the non-volatile memory switch.

19. The system according to claim 18, wherein the first interconnect comprises a Peripheral Component Interconnect Express interconnect.

20. The system according to claim 18, further comprising: the plurality of host computers; and a second interconnect that communicatively couples the plurality of host computers to the non-volatile memory switch.

21. The non-volatile memory switch according to any one of claims 1 to 20, wherein the circuit is further configured to: select a memory transaction message in the non-volatile memory switch associated with the specific root complex based on detection of an error condition corresponding to the specific root complex; and clear the selected memory transaction message from the non-volatile memory switch by the non-volatile memory switch.

22. A method implemented by a non-volatile memory (NVM) switch configured to communicate with a plurality of host devices and a plurality of solid-state drives (SSDs), the method comprising: detecting, at the NVM switch, that a communication link between the NVM switch and a first host device among the plurality of host devices has been disconnected; and in response to detecting that the communication link between the NVM switch and the first host device has been disconnected, flushing, by the NVM switch, in-flight memory access messages between the first host device and the plurality of SSDs while continuing to transfer memory access messages between: i) one or more other host devices among the plurality of host devices, and ii) the plurality of SSDs.

23. The method according to claim 22, wherein detecting that the communication link between the NVM switch and the first host device has been disconnected comprises: detecting, by a peripheral component interconnect express (PCIe) circuit of the NVM switch, that a PCIe communication link between the NVM switch and the first host device has been disconnected.

24. The method according to claim 22, further comprising: In further response to detecting that the communication link between the NVM switch and the first host device has been disconnected, the NVM switch resets one or more components of the NVM switch corresponding to the communication link between the NVM switch and the first host device, while continuing to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

25. The method according to any one of claims 22 to 24, further comprising: In further response to detecting that the communication link between the NVM switch and the first host device has been disconnected, the NVM switch attempts to re - establish the communication link between the NVM switch and the first host device, while continuing to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

26. The method according to any one of claims 22 to 24, further comprising: In further response to detecting that the communication link between the NVM switch and the first host device has been disconnected, the NVM switch prompts one or more of the plurality of SSDs to stop sending data destined for the first host device to the NVM switch, while continuing to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

27. The method according to claim 26, wherein prompting the one or more SSDs to stop sending data destined for the first host device comprises: The NVM switch issues an abort to the one or more SSDs, the abort corresponding to an outstanding command associated with the first host.

28. A non - volatile memory NVM switch for facilitating access by a plurality of host devices to a plurality of solid - state drives SSDs, the NVM switch comprising: A first communication interface configured to transfer memory access messages between the NVM switch and the plurality of host devices; A second communication interface configured to transfer memory access messages between the NVM switch and the plurality of SSDs; And A control circuit configured to: Determine that a communication link between the NVM switch and a first host device among the plurality of host devices has been disconnected, and In response to determining that the communication link between the NVM switch and the first host device has been disconnected, flush in - flight memory access messages between the first host device and the plurality of SSDs, while the NVM switch continues to transfer memory access messages between: i) one or more other host devices among the plurality of host devices, and ii) the plurality of SSDs.

29. The NVM switch according to claim 28, wherein: The first communication interface includes one or more components corresponding to the communication link between the NVM switch and the first host device; and The control circuit is further configured to, in further response to determining that the communication link between the NVM switch and the first host device has been disconnected, reset the one or more components while the NVM switch continues to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

30. The NVM switch according to claim 28, wherein the control circuit is further configured to: In further response to determining that the communication link between the NVM switch and the first host device has been disconnected, control the first communication interface to attempt to re - establish the communication link between the NVM switch and the first host device while the NVM switch continues to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

31. The NVM switch according to claim 28, wherein the control circuit is further configured to: In further response to determining that the communication link between the NVM switch and the first host device has been disconnected, prompt one or more of the plurality of SSDs to stop sending data destined for the first host device to the NVM switch while the NVM switch continues to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

32. The NVM switch according to claim 31, wherein the control circuit is further configured to prompt the one or more SSDs to stop sending data destined for the first host device at least by: Issuing an abort to the one or more SSDs, the abort corresponding to an outstanding command associated with the first host.

33. The NVM switch according to claim 28, wherein: The first communication interface includes a Peripheral Component Interconnect Express (PCIe) circuit, the Peripheral Component Interconnect Express (PCIe) circuit being configured to notify the control circuit when the PCIe communication link between the NVM switch and the first host device has been disconnected.

34. The NVM switch according to claim 28, wherein the control circuit includes: A processor; And A memory coupled to the processor, the memory storing machine - readable instructions that, when executed by the processor, cause the processor to: Determine that the communication link between the NVM switch and the first host device has been disconnected, and In response to determining that the communication link between the NVM switch and the first host device has been disconnected, flush the in - flight memory access messages between the first host device and the plurality of SSDs while the NVM switch continues to transfer memory access messages between: i) one or more of the plurality of host devices, and ii) the plurality of SSDs.

35. A system comprising the NVM switch according to claim 28, the system further comprising: The plurality of SSDs communicatively coupled to the second communication interface.

36. The system of claim 35, further comprising a Peripheral Component Interconnect Express (PCIe) interconnect communicatively coupling the plurality of SSDs and the second communication interface.

37. The system of claim 35, further comprising: The plurality of host devices communicatively coupled to the first communication interface.

38. The system of claim 37, further comprising a Peripheral Component Interconnect Express (PCIe) interconnect communicatively coupling the plurality of host devices and the first communication interface.

39. A non-transitory computer-readable memory storing machine-readable instructions that, when executed by a processor of a Non-Volatile Memory (NVM) switch, cause the processor to: Determine that a communication link between the NVM switch and a first host device among a plurality of host devices communicatively coupled to the NVM switch has been disconnected; and In response to determining that the communication link between the NVM switch and the first host device has been disconnected, control the NVM switch to flush in-flight memory access messages between the first host device and a plurality of SSDs while the NVM switch continues to transfer memory access messages between: i) one or more other host devices among the plurality of host devices, and ii) the plurality of SSDs.

40. The non-transitory computer-readable memory of claim 39, further storing machine-readable instructions that, when executed by the processor, cause the processor to: Further in response to detecting that the communication link between the NVM switch and the first host device has been disconnected, control the NVM switch to reset one or more components of the NVM switch corresponding to the communication link between the NVM switch and the first host device while continuing to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

41. The non-transitory computer-readable memory of claim 39, further storing machine-readable instructions that, when executed by the processor, cause the processor to: Further in response to detecting that the communication link between the NVM switch and the first host device has been disconnected, control the NVM switch to attempt to re-establish the communication link between the NVM switch and the first host device while continuing to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

42. The non-transitory computer-readable memory of claim 39, further storing machine-readable instructions that, when executed by the processor, cause the processor to: In further response to detecting that the communication link between the NVM switch and the first host device has been disconnected, prompt one or more of the plurality of SSDs to stop sending data destined for the first host device to the NVM switch, while continuing to transfer memory access messages between: i) the one or more other host devices, and ii) the plurality of SSDs.

43. The non-transitory computer-readable memory of claim 42, further storing machine-readable instructions that, when executed by the processor, cause the processor to: Prompt the one or more SSDs to stop sending data destined for the first host device, at least by sending an abort to the one or more SSDs, the abort corresponding to an outstanding command associated with the first host.

Images