Circuit entering chip debugging mode after power-on

Abstract

The invention relates to a circuit entering a chip debugging mode after power-on. The circuit comprises a power-on detection module, an input state latch module, an input module, a data clock separation module, a shift register and an efuse module, the power-on detection module is used for detecting the access condition of a power supply, and the output end of the power-on detection module is electrically connected to the first input end of the input state latch module through the delay module; a chip pin PIN1 is electrically connected to the input ends of the data clock separation module and the input module; a first output end and a second output end of the data clock separation module are electrically connected with the input state latch module and the shift register; the input state latch module is electrically connected with the shift register, the output end of the shift register is electrically connected to the input end of the efuse module, and the efuse module is electrically connected with the input state latch module and the internal circuit module. The method has the effect that the register in the chip is operated only by sharing one pin of the chip.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and in particular, to a circuit that enters the chip debugging mode after power-on. Background Art

[0002] The processing and manufacturing of chips is a complex process with many uncontrollable factors. Therefore, generally, the actually produced chips will have a certain deviation from the ideal design parameters. In order to debug the packaged chips, some debugging circuits are usually designed inside the chips to be able to receive external data and adjust the circuit parameters.

[0003] The I2C communication scheme is commonly used in the industry to operate the internal registers of the chip, and then read the register values through the efuse module and burn them fixed. However, the I2C communication adds at least one clock pin CLK and one data pin SDA in the chip. In some special cases, the chip port resources are limited and two additional pins cannot be added for I2C communication, so this scheme cannot be used. Summary of the Invention

[0004] In order to be able to operate the internal registers of the chip and complete the function of the chip debugging mode by sharing only one pin of the chip itself without adding pins, this application provides a circuit that enters the chip debugging mode after power-on.

[0005] A circuit that enters the chip debugging mode after power-on provided by this application adopts the following technical solution: A circuit that enters the chip debugging mode after power-on includes a power-on detection module, a delay module, an input status latch module, an input module, a data clock separation module, a shift register, and an efuse module; the power-on detection module is used to detect the access situation of the power supply, and the output end of the power-on detection module is electrically connected to the first input end of the input status latch module through the delay module; the chip pin PIN1 is electrically connected to the input end of the data clock separation module and the input end of the input module; the first output end of the data clock separation module is electrically connected to the second input end of the input status latch module and the first input end of the shift register; the second output end of the data clock separation module is electrically connected to the third input end of the input status latch module and the second input end of the shift register; the output end of the input status latch module is electrically connected to the third input end of the shift register, and the output end of the shift register is electrically connected to the input end of the efuse module, the first output end of the efuse module is electrically connected to the fourth input end of the input status latch module, and the second output end of the efuse module is electrically connected to the internal circuit module.

[0006] By adopting the above technical solution, the power-on detection module is used to detect the power supply access and provide a trigger signal for subsequent operations; the input module and the data clock separation module process the input signal from chip pin PIN1 and separate it into different data and clock signals; the shift register shifts and stores the input serial data as parallel data for subsequent processing; the efuse module stores key information, and its output terminals are respectively connected to the input status latch module and the internal circuit module to achieve data feedback and control of the internal circuit. Through the interconnection between these modules, the detection of the power supply access situation is realized, and the input signal is processed, latched, shifted and stored, and data interaction with the efuse module is completed through a pin of the chip, providing a complete circuit basis for the chip to enter the debug mode.

[0007] Preferably, the data clock separation module includes a first comparator comp1 and a second comparator comp2. The voltage output terminal of the power supply VDD is grounded in sequence through resistor R1, resistor R2, resistor R3 and resistor R4, and the resistor values of resistor R1, resistor R2, resistor R3 and resistor R4 are the same; the pin Pin1 is electrically connected to the non-inverting input terminal of the first comparator comp1, the connection point between resistor R1 and resistor R2 is electrically connected to the inverting input terminal of the first comparator comp1, and the output terminal of the first comparator comp1 is set as the first output terminal sda of the data clock separation module; the pin Pin1 is electrically connected to the non-inverting input terminal of the second comparator comp2, the connection point between resistor R3 and resistor R4 is electrically connected to the inverting input terminal of the second comparator comp2, and the output terminal of the second comparator comp2 is set as the second output terminal sdl of the data clock separation module.

[0008] By adopting the above technical solution, through multiple resistors and two comparators, the comparison between the voltage signal of pin Pin1 and the reference voltage set by the voltage divider is realized, and the input signal is separated into the signal output from the first output terminal sda and the signal output from the second output terminal sdl.

[0009] Preferably, the power-on detection module includes a first NMOS transistor N1, a second NMOS transistor N2, and an inverter inv1; the voltage output terminal of the power supply VDD is electrically connected to the drain of the second NMOS transistor N2 through a resistor R5, the source of the second NMOS transistor N2 is electrically connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is grounded; the gate of the second NMOS transistor N2 is electrically connected to the gate of the first NMOS transistor N1, and the gate of the first NMOS transistor N1 is electrically connected to the voltage output terminal of the power supply VDD; the drain of the second NMOS transistor N2 is electrically connected to the input terminal of the inverter inv1, and the output terminal of the inverter inv1 is set as the output terminal Pwr_on of the power-on detection module.

[0010] By adopting the above technical solution, the power-on situation of the power supply VDD is detected by connecting the power supply VDD to the drain of the second NMOS transistor N2 through the resistor R5, the connection between the NMOS transistors, and the inverter inv1, and the detection result is output through the inverter inv1 to form a power-on detection signal.

[0011] Preferably, the power-on detection module further includes an inverter inv2 and an inverter inv3. The output terminal of the inverter inv1 is electrically connected to the input terminal of the inverter inv2, the output terminal of the inverter inv2 is electrically connected to the input terminal of the inverter inv3, and the output terminal of the inverter inv3 is set as the output terminal Pwr_on of the power-on detection module.

[0012] By adopting the above technical solution, by sequentially passing the output of the inverter inv1 through inv2 and inv3, the output power-on detection signal can be buffered and shaped to ensure the quality of the output signal, avoid signal jitter and glitches, improve the stability and reliability of the signal, and enable the subsequent circuit to receive a more stable power-on trigger signal.

[0013] Preferably, the delay module includes a plurality of buffers electrically connected in sequence. The output terminal of the power-on detection module sequentially passes through the plurality of buffers, and the output terminal of the last buffer is set as the output terminal Pwr_on1 of the delay module.

[0014] By adopting the above technical solution, using the delay characteristic of the buffer to delay the signal, after receiving the output signal of the power-on detection module, the signal can be output after a certain time delay, realizing the time coordination between different operations in the circuit, ensuring that each module operates in a predetermined time sequence, and avoiding signal conflicts.

[0015] Preferably, the input state latch module includes a first D flip-flop FF1, a second D flip-flop FF2, an inverter inv4, and a NOR gate; a first output terminal of the data clock separation module is electrically connected to a pin D of the first D flip-flop FF1, and a second output terminal sdl of the data clock separation module is electrically connected to a pin D of the second D flip-flop FF2; an output terminal of the delay module is electrically connected to a pin CLK of the first D flip-flop FF1 and a pin CLK of the second D flip-flop FF2, and a second output terminal Efuse_ready of the efuse module is electrically connected to a pin Reset of the first D flip-flop FF1 and a pin Reset of the second D flip-flop FF2; a pin Q of the first D flip-flop FF1 is electrically connected to a first input terminal of the NOR gate, a pin Q of the second D flip-flop FF2 is electrically connected to an input terminal of the inverter inv4, an output terminal of the inverter inv4 is electrically connected to a second input terminal of the NOR gate, and an output terminal of the NOR gate is set as an output terminal Testmode_on of the input state latch module.

[0016] By adopting the above technical solution, the output signal of the data clock separation module is used as the input of the D flip-flop, the output of the delay module is used as the clock signal, and the output of the efuse module is used as the reset signal. The input state is latched by the D flip-flop and processed by the inverter and the NOR gate, and finally the test mode enable signal Testmode_on is output. This module can latch the input state under appropriate clock and reset signals, providing a stable test mode control signal for subsequent circuit operations.

[0017] Preferably, the shift register includes D flip-flops FF3, FF4, FF5, FF6, and an inverter Inv5; an output terminal Testmode_en of the input state latch module is electrically connected to an input terminal of the inverter Inv5, and an output terminal of the inverter Inv5 is electrically connected to pins Reset of the D flip-flops FF3, FF4, FF5, and FF6; an output terminal scl of the data clock separation module is electrically connected to pins clk of the flip-flops FF3, FF4, FF5, and FF6; an output terminal sda of the data clock separation module is electrically connected to a pin D of the D flip-flop FF3, a pin Q of the D flip-flop FF3 is electrically connected to a pin D of the D flip-flop FF4, a pin Q of the D flip-flop FF4 is electrically connected to a pin D of the D flip-flop FF5, and a pin Q of the D flip-flop FF5 is electrically connected to a D of the D flip-flop FF6; pins Q of the D flip-flops FF3, FF4, FF5, and FF6 are all electrically connected to an input terminal of the efuse module.

[0018] By adopting the above technical solution, the output of the input state latch module resets the trigger through the inverter Inv5, and the output of the data clock separation module is used as the clock signal and data signal, and the data shift storage is realized through multiple D flip-flops. The input serial data is shifted and stored in multiple D flip-flops in sequence, and finally parallel data is output to the efuse module, completing the conversion from serial data to parallel data, which facilitates the efuse module to store and process data.

[0019] Preferably, the power is turned on at time t0, the output voltage value of the power supply VDD starts to rise, and the output voltage value of the power supply VDD outputs a high level stably after t1; the pin Pin1 outputs a voltage of VDD / 2 at time t0; the power-on detection module detects that the VDD power supply is successfully powered on at time t1, and the output end of the power-on detection module outputs a high level at this time, and the data clock separation module detects the output voltage of pin Pin1 at this time, and the first output end of the data clock separation module outputs a high level and the second output end outputs a low level at this time; at time t1, the delay module receives the output signal of the power-on detection module and starts timing, and when it reaches time t2, the delay module outputs a high level; at time t2, the input state latch module receives the rising edge output of the delay module, and internally records the states of the first output end and the second output end of the data clock separation module at this time, and outputs a high level at the same time, at this time the input module is closed, the shift register module is turned on, and the efuse module is turned on; after time t2, the shift register module receives the output signals of the first output end and the second output end of the data clock separation module, and shifts the serial data into the register to form parallel data.

[0020] By adopting the above technical solution, when the power is turned on at time t0, the voltage of the power supply and pin Pin1 changes, and the signal changes and operation sequences of the subsequent modules at times t1, t2, etc. The working sequence of each module is clarified, such as the power-on detection is successful at time t1, and the data clock separation module starts to work; at time t2, the delay module outputs a high level, the input state latch module records the state, and the shift register starts to receive data, etc., which provides a clear time sequence basis for circuit debugging and performance analysis, and helps to understand the circuit workflow and troubleshooting.

[0021] In summary, the present application includes at least one of the following beneficial technical effects: by using only one pin PIN1 to realize the operation and debugging of the internal register of the chip, the problem of port resource shortage caused by adding additional pins in the prior art is effectively solved; by using the power-on detection module and the delay module to work together, precise timing control is achieved, ensuring that the chip can reliably enter the debugging mode after power-on, thereby improving the success rate and stability of debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is the principle block diagram of an embodiment of the present application; Figure 2 is the simulation diagram of an embodiment of the present application; Figure 3 is the circuit diagram of the data clock separation module in an embodiment of the present application; Figure 4 is the circuit diagram of the power-on detection module in an embodiment of the present application; Figure 5 is the circuit diagram of the delay module in an embodiment of the present application; Figure 6 is the circuit diagram of the input state latch module in an embodiment of the present application; Figure 7 is the circuit diagram of the shift register module in an embodiment of the present application. Detailed implementation manners

[0023] The following Figures 1-7 further describes the present application in detail with reference to the attached

[0024] An embodiment of the present application discloses a circuit that enters the chip debugging mode after power-on.

[0025] Referring to Figure 1 , a circuit that enters the chip debugging mode after power-on includes a power-on detection module, a delay module, an input state latch module, an input module, a data clock separation module, and a shift register. The power-on detection module is used to detect the access situation of the power supply, and the output terminal Pwr_on of the power-on detection module is electrically connected to the first input terminal of the input state latch module through the delay module. The chip pin PIN1 is electrically connected to the input terminal of the data clock separation module and the input terminal of the input module. The first output terminal sda of the data clock separation module is electrically connected to the second input terminal of the input state latch module and the first input terminal of the shift register; the second output terminal sdl of the data clock separation module is electrically connected to the third input terminal of the input state latch module and the second input terminal of the shift register. The output terminal Testmode_on of the input state latch module is electrically connected to the third input terminal of the shift register, and the output terminal of the shift register is electrically connected to the input terminal of the efuse module. The first output terminal of the efuse module is electrically connected to the fourth input terminal of the input state latch module, and the second output terminal of the efuse module is electrically connected to the internal circuit module.

[0026] Referring to Figure 2, The embodiments of the present application include two working modes. The period from t0 to t2 is the trimming test mode after power-on, and after t2 is the register data writing mode. Power is applied at t0. At this time, the output voltage value of the power supply VDD starts to rise and stably outputs a high level after t1. The voltage value of the voltage output at the pin Pin1 is VDD / 2 at t0. The power-on detection module detects the successful power-on of the VDD power supply at t1. At this time, the output terminal Pwr_on of the power-on detection module outputs a high level. At the same time, the data clock separation module detects the output voltage of the pin Pin1, and the first output terminal sda outputs a high level, and the second output terminal sdl outputs a low level.

[0027] Referring to Figure 3 , The data clock separation module includes a first comparator comp1 and a second comparator comp2. The voltage output terminal of the power supply VDD is grounded in sequence through a resistor R1, a resistor R2, a resistor R3, and a resistor R4. In this embodiment, the resistance values of the resistor R1, the resistor R2, the resistor R3, and the resistor R4 are the same. The pin Pin1 is electrically connected to the non-inverting input terminal of the first comparator comp1, and the connection point between the resistor R1 and the resistor R2 is electrically connected to the inverting input terminal of the first comparator comp1. The output terminal of the first comparator comp1 is set as the first output terminal sda of the data clock separation module. The pin Pin1 is electrically connected to the non-inverting input terminal of the second comparator comp2, and the connection point between the resistor R3 and the resistor R4 is electrically connected to the inverting input terminal of the second comparator comp2. The output terminal of the second comparator comp2 is set as the second output terminal sdl of the data clock separation module.

[0028] The voltage value of the inverting input terminal of the first comparator comp1 is VDD / 4, and the voltage value of the inverting input terminal of the second comparator comp2 is 3*VDD / 4. When the output voltage of the pin Pin1 reaches VDD / 2, at this time, the output terminal sda of the first comparator comp1 outputs a high level, and the output terminal sdl of the second comparator comp2 outputs a low level. By controlling the output voltage value of the pin Pin1, it is possible to control the output terminal sda to output a high level / low level, and the output terminal sdl to output a low level / high level.

[0029] Reference Figure 4, the power-on detection module includes a first NMOS transistor N1, a second NMOS transistor N2, an inverter inv1, an inverter inv2, and an inverter inv3. The voltage output terminal of the power supply VDD is electrically connected to the drain of the second NMOS transistor N2 through a resistor R5. The source of the second NMOS transistor N2 is electrically connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is grounded. The gate of the second NMOS transistor N2 is electrically connected to the gate of the first NMOS transistor N1, and the gate of the first NMOS transistor N1 is electrically connected to the voltage output terminal of the power supply VDD. The drain of the second NMOS transistor N2 is electrically connected to the input terminal of the inverter inv1. The output terminal of the inverter inv1 is electrically connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2 is electrically connected to the input terminal of the inverter inv3. The output terminal of the inverter inv3 is set as the output terminal Pwr_on of the power-on detection module.

[0030] When the power supply VDD is powered on, the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are pulled high, so that both the first NMOS transistor N1 and the second NMOS transistor N2 are in the conducting state. As a result, the voltage at the input terminal of the inverter inv1 is pulled low through the first NMOS transistor N1 and the second NMOS transistor N2, and then the output terminal of the inverter inv1 outputs a high level, the output terminal of the inverter inv2 outputs a level, and the output terminal of the inverter inv3 outputs a high level. That is, when the power supply VDD is powered on, the output terminal Pwr_on of the power-on detection module outputs a high level at this time.

[0031] Reference Figure 5 , the delay module includes a plurality of buffers electrically connected in sequence. The output terminal Pwr_on of the power-on detection module passes through the plurality of buffers in sequence, and the output terminal of the last buffer is set as the output terminal Pwr_on1 of the delay module. When a plurality of buffers are connected in series, the signal needs to pass through each buffer in sequence, and each buffer will generate a certain propagation delay, and these delays will accumulate, so as to realize the delay of the signal.

[0032] At time t1, when the delay module receives a high level output from the output terminal Pwr_on of the power-on detection module, it starts timing. By time t2, the output terminal Pwr_on1 of the delay module outputs a high level.

[0033] Reference Figure 6, the input status latch module includes a first D flip-flop FF1, a second D flip-flop FF2, an inverter inv4, and a NOR gate. The first output terminal sda of the data clock separation module is electrically connected to the pin D of the first D flip-flop FF1, and the second output terminal sdl of the data clock separation module is electrically connected to the pin D of the second D flip-flop FF2. The output terminal Pwr_on1 of the delay module is electrically connected to the pin CLK of the first D flip-flop FF1 and the pin CLK of the second D flip-flop FF2, and the second output terminal Efuse_ready of the efuse module is electrically connected to the pin Reset of the first D flip-flop FF1 and the pin Reset of the second D flip-flop FF2. The pin Q of the first D flip-flop FF1 is electrically connected to the first input terminal of the NOR gate, the pin Q of the second D flip-flop FF2 is electrically connected to the input terminal of the inverter inv4, the output terminal of the inverter inv4 is electrically connected to the second input terminal of the NOR gate, and the output terminal of the NOR gate is set as the output terminal Testmode_on of the input status latch module.

[0034] At time t2, the output voltage value of the output terminal Pwr_on of the delay module is at the rising edge, and the pin D of the first D flip-flop FF1 receives a low level, and the pin D of the second D flip-flop FF2 receives a high level; at this time, the pin Q of the first D flip-flop FF1 outputs a low level, and the pin Q of the second D flip-flop FF2 outputs a high level, so that the first input terminal of the NOR gate receives a low level, and the second input terminal of the NOR gate receives a low level, and then the NOR gate outputs a high level.

[0035] When the output terminal Testmode_en of the input status latch module outputs a high level, the input module is turned off, the shift register module is turned on, and the efuse module is turned on.

[0036] Reference Figure 7, the shift register includes D flip - flop FF3, D flip - flop FF4, D flip - flop FF5, D flip - flop FF6, and inverter Inv5. The output terminal Testmode_en of the input state latch module is electrically connected to the input terminal of inverter Inv5, and the output terminal of inverter Inv5 is electrically connected to the Reset pins of D flip - flop FF3, D flip - flop FF4, D flip - flop FF5, and D flip - flop FF6. The output terminal scl of the data clock separation module is electrically connected to the clk pins of flip - flop FF3, D flip - flop FF4, D flip - flop FF5, and D flip - flop FF6. The output terminal sda of the data clock separation module is electrically connected to the D pin of D flip - flop FF3, the Q pin of D flip - flop FF3 is electrically connected to the D pin of D flip - flop FF4, the Q pin of D flip - flop FF4 is electrically connected to the D pin of D flip - flop FF5, and the Q pin of D flip - flop FF5 is electrically connected to the D of D flip - flop FF6. The Q pins of D flip - flop FF3, D flip - flop FF4, D flip - flop FF5, and D flip - flop FF6 are all electrically connected to the input terminal of the efuse module. When the output terminal Testmode_en outputs a high level, the shift register starts to work, shifting the serial data into the register to form parallel data.

[0037] The implementation principle of the circuit for entering the chip debugging mode after power - on in an embodiment of this application is as follows: At time t0, power is applied, and the output voltage value of power supply VDD starts to rise. The voltage value output by pin Pin1 at time t0 is VDD / 2. The power - on detection module detects the successful power - on of the VDD power supply at time t1, and at this time, the output terminal Pwr_on of the power - on detection module outputs a high level. At the same time, the data clock separation module detects the output voltage of pin Pin1, and at this time, the first output terminal sda of the data clock separation module outputs a high level, and the second output terminal scl outputs a low level. At time t1, the delay module receives the output signal of the power - on detection module and starts timing. By the time of t2, the output terminal Pwr_on1 of the delay module outputs a high level. At time t2, the input state latch module receives the rising edge output by the delay module, internally records the output states of the first output terminal sda and the second output terminal scl of the data clock separation module at this time, and outputs a high level at the same time. At this time, the input module is turned off, the shift register module is turned on, and the efuse module is turned on. After time t2, the shift register module receives the output signal of the data clock separation module, shifting the serial data into the register to form parallel data. By using only one pin PIN1 to implement the operation and debugging of the internal registers of the chip, it effectively solves the problem of port resource tension caused by adding extra pins in the prior art.

[0038] The above are all the preferred embodiments of this application. Without limiting the protection scope of this application accordingly, therefore: All equivalent changes made according to the structure, shape, and principle of this application should be covered within the protection scope of this application.

Claims

1. A circuit that enters the chip debugging mode after power-on, characterized in that: It includes a power-on detection module, a delay module, an input status latch module, an input module, a data clock separation module, a shift register, and an efuse module; the power-on detection module is used to detect the access situation of the power supply, and the output end of the power-on detection module is electrically connected to the first input end of the input status latch module through the delay module; the chip pin PIN1 is electrically connected to the input end of the data clock separation module and the input end of the input module; the first output end of the data clock separation module is electrically connected to the second input end of the input status latch module and the first input end of the shift register; the second output end of the data clock separation module is electrically connected to the third input end of the input status latch module and the second input end of the shift register; the output end of the input status latch module is electrically connected to the third input end of the shift register, and the output end of the shift register is electrically connected to the input end of the efuse module, the first output end of the efuse module is electrically connected to the fourth input end of the input status latch module, and the second output end of the efuse module is electrically connected to the internal circuit module.

2. The circuit for entering the chip debugging mode after power-on according to claim 1, wherein: The data clock separation module includes a first comparator comp1 and a second comparator comp2. The voltage output end of the power supply VDD is grounded in sequence through a resistor R1, a resistor R2, a resistor R3, and a resistor R4, and the resistance values of the resistor R1, the resistor R2, the resistor R3, and the resistor R4 are the same; the pin Pin1 is electrically connected to the non-inverting input end of the first comparator comp1, the connection point between the resistor R1 and the resistor R2 is electrically connected to the inverting input end of the first comparator comp1, and the output end of the first comparator comp1 is set as the first output end sda of the data clock separation module; the pin Pin1 is electrically connected to the non-inverting input end of the second comparator comp2, the connection point between the resistor R3 and the resistor R4 is electrically connected to the inverting input end of the second comparator comp2, and the output end of the second comparator comp2 is set as the second output end sdl of the data clock separation module.

3. The circuit for entering the chip debugging mode after power-on according to claim 1, wherein: The power-on detection module includes a first NMOS transistor N1, a second NMOS transistor N2, and an inverter inv1; the voltage output end of the power supply VDD is electrically connected to the drain of the second NMOS transistor N2 through a resistor R5, the source of the second NMOS transistor N2 is electrically connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is grounded; the gate of the second NMOS transistor N2 is electrically connected to the gate of the first NMOS transistor N1, and the gate of the first NMOS transistor N1 is electrically connected to the voltage output end of the power supply VDD; the drain of the second NMOS transistor N2 is electrically connected to the input end of the inverter inv1, and the output end of the inverter inv1 is set as the output end Pwr_on of the power-on detection module.

4. The circuit for entering the chip debugging mode after power-on according to claim 3, wherein: The power-on detection module further includes an inverter inv2 and an inverter inv3. The output terminal of the inverter inv1 is electrically connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2 is electrically connected to the input terminal of the inverter inv3. The output terminal of the inverter inv3 is set as the output terminal Pwr_on of the power-on detection module.

5. A circuit for entering the chip debugging mode after power-on according to claim 1, characterized in that: The delay module includes a plurality of buffers electrically connected in sequence. The output terminal of the power-on detection module sequentially passes through a plurality of the buffers, and the output terminal of the last buffer is set as the output terminal Pwr_on1 of the delay module.

6. The circuit for entering the chip debugging mode after power-on according to claim 1, wherein: The input status latch module includes a first D flip-flop FF1, a second D flip-flop FF2, an inverter inv4, and a NOR gate. The first output terminal of the data clock separation module is electrically connected to the pin D of the first D flip-flop FF1. The second output terminal sdl of the data clock separation module is electrically connected to the pin D of the second D flip-flop FF2. The output terminal of the delay module is electrically connected to the pin CLK of the first D flip-flop FF1 and the pin CLK of the second D flip-flop FF2. The second output terminal Efuse_ready of the efuse module is electrically connected to the pin Reset of the first D flip-flop FF1 and the pin Reset of the second D flip-flop FF2. The pin Q of the first D flip-flop FF1 is electrically connected to the first input terminal of the NOR gate. The pin Q of the second D flip-flop FF2 is electrically connected to the input terminal of the inverter inv4. The output terminal of the inverter inv4 is electrically connected to the second input terminal of the NOR gate. The output terminal of the NOR gate is set as the output terminal Testmode_on of the input status latch module.

7. A circuit that enters the chip debugging mode after power-on according to claim 1, characterized in that: The shift register includes a D flip-flop FF3, a D flip-flop FF4, a D flip-flop FF5, a D flip-flop FF6, and an inverter Inv5. The output terminal Testmode_en of the input status latch module is electrically connected to the input terminal of the inverter Inv5. The output terminal of the inverter Inv5 is electrically connected to the pins Reset of the D flip-flop FF3, the D flip-flop FF4, the D flip-flop FF5, and the D flip-flop FF6. The output terminal scl of the data clock separation module is electrically connected to the pins clk of the flip-flop FF3, the D flip-flop FF4, the D flip-flop FF5, and the D flip-flop FF6. The output terminal sda of the data clock separation module is electrically connected to the pin D of the D flip-flop FF3. The pin Q of the D flip-flop FF3 is electrically connected to the pin D of the D flip-flop FF4. The pin Q of the D flip-flop FF4 is electrically connected to the pin D of the D flip-flop FF5. The pin Q of the D flip-flop FF5 is electrically connected to the D of the D flip-flop FF6. The pins Q of the D flip-flop FF3, the D flip-flop FF4, the D flip-flop FF5, and the D flip-flop FF6 are all electrically connected to the input terminal of the efuse module.

8. The circuit for entering the chip debugging mode after power-on according to claim 1, wherein: Power on at time t0, the output voltage value of the power supply VDD starts to rise, and the output voltage value of the power supply VDD stably outputs a high level after t1; the voltage of the pin Pin1 at time t0 is VDD / 2; the power-on detection module detects that the VDD power supply is successfully powered on at time t1, and at this time the output end of the power-on detection module outputs a high level. At the same time, the data clock separation module detects the output voltage of the pin Pin1, and at this time the first output end of the data clock separation module outputs a high level and the second output end outputs a low level; at time t1, the delay module receives the output signal of the power-on detection module and starts timing. Wait until time t2, the delay module outputs a high level; at time t2, the input state latch module receives the rising edge output by the delay module, and internally records the states of the first output end and the second output end of the data clock separation module at this time, and at the same time outputs a high level. At this time, the input module is closed, the shift register module is opened, and the efuse module is opened; after time t2, the shift register module receives the output signals of the first output end and the second output end of the data clock separation module, and shifts the serial data into the register to form parallel data.

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