Signal processing system, electronic device, storage medium and program product

Abstract

The present application discloses a signal processing system, electronic device, storage medium and program product, which relate to the field of computer technology. The system includes a baseboard management controller (BMC) that can first determine first data in a first memory when delayed data reception is required. The first data can be an alternating bit sequence. The first data is read according to multiple first delays to obtain multiple read second data. The second delay for data reception is determined based on the first data, the multiple read second data and the multiple first delays, and the second delay is stored in a second memory. In this way, by traversing the first delays to read the first data of the alternating bit sequence and determine the second delay for data reception, the probability of conflict in the BMC receiving signals is reduced, thereby improving the success rate of the BMC receiving signals.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a signal processing system, electronic equipment, storage medium, and program product. Background Art

[0002] By embedding a baseboard management controller on the server's motherboard, users can remotely monitor and manage the hardware status.

[0003] In complex systems, when a baseboard management controller (BMC) receives data from multiple devices simultaneously, signal interference and conflicts may occur. Related technologies can reduce signal interference by controlling the BMC to delay signal reception. However, in these methods, the delay duration is determined by randomly selecting data, resulting in poor results. Summary of the Invention

[0004] The present application provides a signal processing system, an electronic device, a storage medium, and a program product to at least solve the problem of poor effect of delayed reception time.

[0005] The present application provides a signal processing system, comprising:

[0006] The baseboard management controller determines first data and stores the first data in a first memory, where the first data is an alternating bit sequence;

[0007] The baseboard management controller reads the first data in the first memory according to the plurality of first delays to obtain a plurality of second data;

[0008] The baseboard management controller determines a second delay according to the first data, the plurality of second data and the plurality of first delays, where the second delay is a delay for the baseboard management controller to receive data;

[0009] The baseboard management controller stores the second delay in the second memory.

[0010] The present application also provides a data processing device, comprising: a first determining module, a reading module, and a second determining module, wherein:

[0011] a first determining module, configured to determine first data and store the first data in a first memory, wherein the first data is an alternating bit sequence;

[0012] a reading module, configured to read the first data in the first memory according to the plurality of first delays to obtain a plurality of second data;

[0013] The second determining module is used to determine a second delay according to the first data, multiple second data and multiple first delays, where the second delay is a delay for the baseboard management controller to receive data, and the baseboard management controller stores the second delay in the second memory.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing any of the above-mentioned signal processing systems when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned signal processing systems is implemented.

[0016] The present application also provides a computer program product, comprising a computer program, which implements any of the above-mentioned signal processing systems when executed by a processor.

[0017] Through the present application, when delayed reception of data is required, the baseboard management controller can first determine the first data in the first memory. The first data can be an alternating bit sequence. The first data is read according to multiple first delays to obtain multiple read second data. The second delay for data reception is determined based on the first data, the multiple read second data, and the multiple first delays, and the second delay is stored in the second memory. In the above process, the first data of the alternating bit sequence is read by traversing the first delay to determine the optimal second delay for data reception. Since the first data is an alternating bit sequence, the diversity of the training samples is improved, and the reliability of the second delay is improved, thereby improving the success rate of the baseboard management controller in receiving signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1a A schematic diagram of the system architecture provided in an embodiment of the present application;

[0020] Figure 1b A schematic diagram of the system architecture provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a data processing flow of a signal processing system provided in an embodiment of the present application;

[0022] Figure 3A schematic diagram of the internal clock signal of the baseboard management controller;

[0023] Figure 4 A schematic diagram of a process in which a signal processing system according to an embodiment of the present application receives data according to a second delay;

[0024] Figure 5 A schematic diagram of a first daughter card and a second daughter card provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of the structure of another data processing device provided in an embodiment of the present application;

[0027] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] First, let’s explain the terms involved in this application:

[0031] Baseboard Management Controller (BMC): A BMC is an embedded controller commonly used in servers and other enterprise-class hardware, providing remote management and monitoring capabilities. The BMC runs independently of the main operating system, allowing it to maintain management operations even if the operating system crashes or the server is shut down. A key component of modern data centers and enterprise-class servers, BMCs can be used for remote power control, hardware monitoring, remote console access, firmware updates, and remote management.

[0032] In complex systems, when a baseboard management controller (BMC) receives data from multiple devices simultaneously, signal interference and conflicts may occur. Related technologies can reduce signal interference by controlling the BMC to delay signal reception. However, in these methods, the delay duration is determined by randomly selecting data, resulting in poor results.

[0033] To address the above issues, in an embodiment of the present application, in a signal processing system, when data needs to be processed, the baseboard management controller can first determine first data in a first memory. The first data can be an alternating bit sequence. The first data can be read according to multiple first delays to obtain multiple read second data. Based on the first data, the multiple read second data, and the multiple first delays, a second delay for data reception is determined, and the second delay is stored in the second memory. In this way, by traversing the first delays to read the first data of the alternating bit sequence and determine the second delay for data reception, the probability of conflict in the baseboard management controller receiving signals is reduced, thereby improving the success rate of the baseboard management controller receiving signals.

[0034] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the signal processing system depends, the specific application environment architecture or specific hardware architecture is described here. Figure 1a and Figure 1b . Figure 1a This is a schematic diagram of the system architecture provided by the embodiment of this application. Figure 1a, including a board, which includes a baseboard management controller (BMC), a first memory, a second memory, a central processing unit (CPU), a multiplexer, and a level converter. The BMC can be used to receive status information sent by components within the board and remotely monitor the components. The first memory can be used to store data, such as firmware storage and a file system. The second memory can be used to store data, such as configuration parameters, user settings, and other data that requires frequent updates. The storage capacity of the first memory can be larger than that of the second memory. The CPU can be used to execute instructions, process data, and coordinate the operation of other hardware in the system. The multiplexer can be used to route signals. The level converter can be used to convert signal levels between different voltage domains to ensure that devices with different voltages can communicate safely. The CPU can be connected to and communicate with the multiplexer, the level converter can be used to convert levels between the BMC and the multiplexer, the BMC can be connected to the second memory, the BMC can read and receive data from the second memory, and the multiplexer can be connected to the first memory for data transmission.

[0036] Figure 1b This is another system architecture diagram provided by the embodiment of this application. Figure 1b , including a first daughter board and a second daughter board, wherein the first daughter board includes a second memory and a baseboard control manager, the second daughter board includes a first memory, a second memory, a central processing unit, a level converter and a multiplexer, and the first daughter board and the second daughter board are connected via a connector. The baseboard control manager is connected to the second memory of the first daughter board and the second memory of the second daughter board, the baseboard management controller can read and receive data from the second memory, the baseboard control manager is connected to the level converter of the second daughter board, the level converter can be used to perform level conversion between the baseboard management controller and the multiplexer, the central processing unit can be connected to the multiplexer for communication, and the multiplexer can be connected to the first memory for data transmission.

[0037] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0038] Figure 2 A schematic diagram of a flow chart of data processing by a signal processing system provided in an embodiment of the present application, such as Figure 2 As shown below:

[0039] S201: A baseboard management controller determines first data and stores the first data in a first memory.

[0040] The execution subject of the embodiment of the present application can be a baseboard management controller, or a data processing device provided in the baseboard management controller. The data processing device can be implemented by software or by a combination of software and hardware.

[0041] The first data is an alternating bit sequence stored in a first memory corresponding to the board, that is, the first data is a discontinuous binary number, which may refer to 0 and 1.

[0042] Illustratively, the first data may be 010101010101010, or 1010101010, etc.

[0043] The board may refer to a board of a server or a board of a computer terminal device. The board may be provided with a baseboard management controller and a first memory, the first memory may be used to store data, and the first memory may be a flash memory module.

[0044] The first data may be determined in the following manner: generating the first data, where the first data is an alternating bit sequence, and the data size corresponding to the first data is a preset size, which may be a value preset by a user.

[0045] Optionally, the first data can also be determined in the following manner: traverse the data stored in the first memory to determine multiple pre-selected data, where the pre-selected data is an alternating bit sequence; determine the data size corresponding to each pre-selected data, and determine the target data within each pre-selected data, where the target data has the largest data size; and determine the target data as the first data.

[0046] S202: The baseboard management controller reads the first data in the first memory according to the multiple first delays to obtain multiple second data.

[0047] The first delay may refer to a delay duration for delaying the reception of data, for example, the first delay may be 30ns, 100ns, etc. The multiple first delays may be multiple delay durations preset by the user, and the multiple first delays are different from each other.

[0048] For any first delay, the baseboard management controller may read the first data from the first memory after delaying the first delay at the falling edge of the internal clock signal according to the internal clock signal.

[0049] For example, assuming that the first delay is 50 ns, the baseboard management controller reads the first data after a delay of 50 ns at the falling edge of the internal clock signal.

[0050] The second data may refer to the first data read by the baseboard management controller according to the first delay. There is a one-to-one correspondence between the multiple first delays and the multiple second data read according to the multiple first delays.

[0051] Next, combine Figure 3 , the first delay is explained in detail through specific examples.

[0052] Figure 3 This is a schematic diagram of the baseboard management controller's internal clock signal. Figure 3 The clock signal may include multiple falling edges according to a preset clock cycle, and the baseboard management controller delays the falling edge by a first delay before receiving the data.

[0053] S203: The baseboard management controller determines a second delay according to the first data, the plurality of second data, and the plurality of first delays.

[0054] The second delay is a delay in data reception by the baseboard management controller.

[0055] The second delay may be determined in the following manner: determining target data from the plurality of second data according to the first data and the plurality of second data; determining a first delay corresponding to the target data; and determining the second delay according to the first delay corresponding to the target data.

[0056] The similarity between the target data and the first data is greater than or equal to a preset threshold value, and the target data may be one or more; the preset threshold value may be a value preset by the user in advance.

[0057] The target data may be determined in the following manner: performing comparison processing on the first data and the plurality of second data; determining the similarity between the first data and the plurality of second data; and determining the target data from the plurality of second data based on the similarity, wherein the similarity of the target data is greater than or equal to a preset threshold.

[0058] For example, assuming that there are first data, second data A, second data B, second data C, and second data D, the preset threshold is 0.8, the similarity between the first data and the second data A is 0.96, the similarity between the first data and the second data B is 0.89, the similarity between the first data and the second data C is 0.58, and the similarity between the first data and the second data D is 0.75, then the similarity between the first data and the second data A and the similarity between the first data and the second data B are greater than or equal to the preset threshold, that is, the target data is the second data A and the second data B.

[0059] Optionally, the second delay can be determined based on the first delay corresponding to the target data in the following manner: among the first delays corresponding to the target data, sort the first delay corresponding to at least one target data in order from large to small, and determine the largest first delay and the smallest first delay based on the sorting; determine the delay interval based on the largest first delay and the smallest first delay, the minimum value of the delay interval is the smallest first delay, and the maximum value of the delay interval is the largest first delay; determine the second delay based on the delay interval, and the second delay is the median value of the delay interval.

[0060] For example, assuming that the first delay corresponding to target data A is 10, the first delay corresponding to target data B is 38, the first delay corresponding to target data C is 30, and the first delay corresponding to target data D is 6, then the first delays corresponding to the target data are sorted in descending order, and the order obtained is the first delay corresponding to target data B, the first delay corresponding to target data C, the first delay corresponding to target data A, and the first delay corresponding to target data D. That is, the largest first delay is 38 and the smallest first delay is 6. In this way, the delay interval can be determined to be (6, 38), and the median value of the delay interval (6, 38) is 22, so the second delay can be determined to be 22.

[0061] Optionally, the second delay can be determined based on the first delay corresponding to the target data in the following manner: among the first delays corresponding to the target data, the first delay corresponding to at least one target data is sorted in descending order; if the number of target data is an even number, the two target data in the middle of the sorting position are selected, the average of the first delays corresponding to the two target data is calculated, and the average is determined as the second delay; if the number of target data is an odd number, the target data in the middle of the sorting position is selected, and the target data is determined as the second delay.

[0062] For example, assuming that the number of target data is an even number, the first delay corresponding to target data A is 10, the first delay corresponding to target data B is 38, the first delay corresponding to target data C is 30, and the first delay corresponding to target data D is 6. Then the first delays corresponding to the target data are sorted in descending order, and the order obtained is the first delay corresponding to target data B, the first delay corresponding to target data C, the first delay corresponding to target data A, and the first delay corresponding to target data D. The average of the first delay corresponding to target data A and the first delay corresponding to target data C is 20, that is, the second delay is 20.

[0063] Assuming that the number of target data is an odd number, the first delay corresponding to target data A is 10, the first delay corresponding to target data B is 30, and the first delay corresponding to target data C is 15. Then the first delays corresponding to the target data are sorted in descending order, and the order is: the first delay corresponding to target data B is 30, the first delay corresponding to target data C is 15, and the first delay corresponding to target data A is 10. Then the second delay is the first delay corresponding to target data C, that is, the second delay is 15.

[0064] S204: The baseboard management controller stores the second delay in the second memory.

[0065] The board also includes a second memory, which can be used to store data and can be a programmable memory.

[0066] In an embodiment of the present application, when a baseboard management controller needs to delay receiving data, it can first determine first data in a first memory, where the first data is an alternating bit sequence. Based on multiple first delays, the first data in the first memory can be read to obtain multiple second data, with the multiple first delays corresponding to the multiple second data read according to the multiple first delays. Based on the first data, the multiple second data read, and the corresponding multiple first delays, a second delay can be determined and stored in the second memory. At least one target data can be determined based on the multiple first delays, and the interval of the first delay corresponding to the at least one target data can be determined as the delay interval. The second delay can be the median of the delay interval. In this way, by traversing the first delays to read the first data and thereby determining the optimal second delay for data reception, the probability of conflict in the baseboard management controller receiving signals can be reduced, thereby improving the success rate of the baseboard management controller receiving signals. Furthermore, since the first data is an alternating bit sequence, there are no consecutive binary numbers, such as consecutive 0s or consecutive 1s, in the first data, which can increase the diversity of the first data and thus improve the accuracy of determining the second delay.

[0067] Based on any of the above embodiments, Figure 4 , a process of the signal processing system receiving data according to the second delay is described in detail.

[0068] Figure 4 Schematic diagram of the process of data reception by the signal processing system according to the second delay provided in the embodiment of the present application. Figure 4 , the method may include:

[0069] S401: In response to a startup instruction for a board, a baseboard management controller obtains board information, a second delay, and a first check code from a second memory.

[0070] The startup instruction for the board may refer to an instruction sent by the board to the baseboard management controller when the board receives power from the power supply.

[0071] The second memory may be a programmable memory, and the programmable memory may be provided on a board.

[0072] The board information may include the serial number of the board, for example, AB1234567890.

[0073] The first verification code may be a verification code generated based on the second delay and the board information after the second delay is determined. The first verification code may be used to indicate whether the second delay has been tampered with.

[0074] The first verification code can be determined in the following manner: obtaining the second delay and board information, performing verification processing on the second delay and board information to obtain the first verification code, wherein the verification processing can refer to hash verification processing; after determining the first verification code, it also includes storing the first verification code and the second delay in a second memory.

[0075] Before obtaining the board information, the second delay, and the first check code from the second memory, the method further includes: obtaining a target parameter of a target area of ​​the second memory, where the target area is an area storing the second delay, and the target parameter is used to indicate whether valid data has been stored in the target area; and determining the first data when all the target parameters are preset values, where the preset values ​​may be 0.

[0076] It can be understood that when all the target parameters are preset values, it means that the baseboard management controller has not generated the second delay; when any value in the target parameters is not the preset value, it indicates that data has been written to the target area, that is, the second delay has been generated, and then the board information, the second delay and the first check code are obtained from the second memory.

[0077] S402: The baseboard management controller verifies the board information and the second delay to obtain a second verification code.

[0078] The board information obtained from the second memory and the second delay are verified to obtain a second verification code.

[0079] The second check code may be used to indicate whether the second delay stored in the second memory has been tampered with.

[0080] S403: The baseboard management controller determines whether the first verification code and the second verification code are the same.

[0081] If so, execute S404.

[0082] If not, execute S405.

[0083] S404: The baseboard management controller determines that the second delay has not been tampered with during the storage process, and receives data according to the second delay.

[0084] The second delay not being tampered with during the storage process may mean that the second delay obtained from the second memory is the same as the second delay stored in the second memory.

[0085] S405: The baseboard management controller determines that the second delay has been tampered with during the storage process.

[0086] The second delay having been tampered with during the storage process may mean that the second delay obtained from the second memory is different from the second delay stored in the second memory.

[0087] S406 : The baseboard management controller re-reads the first data according to the multiple first delays to obtain multiple third data.

[0088] S407: The baseboard management controller re-determines the target data according to the first data and the plurality of third data.

[0089] S408: The baseboard management controller re-determines the second delay according to the first delay corresponding to the re-determined target data.

[0090] It should be noted that the execution process of the above steps S406-S408 can be referred to S202-S203, and will not be repeated here.

[0091] S409: The baseboard management controller receives data according to the re-determined second delay.

[0092] exist Figure 4In the illustrated embodiment, the baseboard management controller can obtain a second delay from the second memory in response to a startup instruction for the board card to delay receiving data. In order to prevent the second delay stored in the second memory from being tampered with, thereby causing a received data conflict, the board card information, the second delay and the first check code can be first obtained from the second memory, and then a check is performed based on the board card information and the second delay obtained from the second memory to obtain a second check code. The second check code can be used to indicate whether the second delay after being stored in the second memory has been tampered with; determine whether the first check code and the second check code are the same. If they are the same, it can be determined that the second delay has not been tampered with during the storage process, and data is received according to the second delay; if they are different, it can be determined that the second delay has been tampered with during the storage process, and the second delay needs to be re-determined. Specifically, the first data is re-read based on multiple first delays to obtain multiple third data, and then the target data is re-determined based on the first data and the multiple third data. The second delay is re-determined based on the first delay corresponding to the re-determined target data, and data is received based on the re-determined second delay. In this way, when the second delay is generated for the first time, a first verification code is generated, and each time the second delay is obtained, a second verification code is generated based on the obtained second delay. By comparing whether the first verification code and the second verification code are the same, it can be determined whether the second delay stored in the second memory has been tampered with, thereby improving the accuracy of the second delay and improving the reliability of data reception.

[0093] Based on any of the above embodiments, Figure 5 , a process for determining the second delay by the signal processing system when the board in the signal processing system includes a first daughter board and a second daughter board, that is, the first memory and the second memory are located on different boards is described in detail.

[0094] Figure 5 For a schematic diagram of the first daughter card and the second daughter card provided in the embodiment of the present application, please refer to Figure 5 , including a first daughter card and a second daughter card. The first daughter card and the second daughter card are connected via a connector. The first daughter card may include a first memory and a second memory, the second daughter card may include a baseboard management controller, wherein the second daughter card may further include a third memory, which may be a programmable memory corresponding to the second daughter card.

[0095] The second memory stores first daughter card information corresponding to the first daughter card and the second delay of the first daughter card. The third memory stores second daughter card information corresponding to the second daughter card and the second delay of the second daughter card.

[0096] The baseboard management controller can obtain the second delay of the first daughter board and the second delay of the second daughter board, and determine whether the second delay of the first daughter board and the second daughter board are the same. If they are the same, the baseboard management controller reads the data according to the second delay; if they are different, the baseboard management controller will re-determine the second delay and receive data according to the re-determined second delay.

[0097] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0098] Based on any of the above embodiments, the method for performing data processing by the signal processing system can also be implemented based on a data processing device. Figure 6 , the structure of the data processing device is described in detail.

[0099] Figure 6 This is a schematic diagram of the structure of the data processing device provided in the embodiment of the present application. Figure 6 As shown, an embodiment of the present application further provides a data processing device 10, comprising: a first determining module 11, a reading module 12, and a second determining module 13, wherein:

[0100] The first determining module 11 is used to determine the first data and store the first data in the first memory as an alternating bit sequence stored in the first memory corresponding to the board;

[0101] The reading module 12 is configured to read the first data in the first memory according to a plurality of first delays to obtain a plurality of second data;

[0102] The second determining module 13 is configured to determine a second delay according to the first data, the plurality of second data and the plurality of first delays, and store the second delay in the second memory, where the second delay is a delay for the board to receive data.

[0103] A data processing device provided in an embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0104] In one possible design, the second determining module 13 is specifically configured to:

[0105] Determining target data from the plurality of second data according to the first data and the plurality of second data, wherein a similarity between the target data and the first data is greater than or equal to a preset threshold;

[0106] determining a first delay corresponding to the target data;

[0107] The second delay is determined according to the first delay corresponding to the target data.

[0108] In one possible design, the second determining module 13 is specifically configured to:

[0109] Determining a maximum first delay and a minimum first delay among the first delays corresponding to the target data;

[0110] The second delay is determined according to the maximum first delay and the minimum first delay.

[0111] In one possible design, the second determining module 13 is specifically configured to:

[0112] performing comparison processing on the first data and the plurality of second data;

[0113] determining a similarity between the first data and the plurality of second data;

[0114] According to the similarity, target data is determined from the plurality of second data, and the similarity of the target data is greater than or equal to a preset threshold.

[0115] A data processing device provided in an embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0116] Figure 7 This is a structural diagram of another data processing device provided in an embodiment of the present application. Figure 6 Based on the examples shown, see Figure 7 The data processing device 10 further includes: a verification module 14 and a third determination module 15, wherein:

[0117] The verification module 14 is used to determine the board information of the board, wherein the board information includes the serial number of the board;

[0118] Performing verification processing on the board information and the second delay to obtain a first verification code;

[0119] The board information, the second delay and the first check code are stored in a second memory corresponding to the board.

[0120] In one possible design, the verification module 14 is further configured to:

[0121] In response to a startup instruction for the board, acquiring the board information, the second delay, and the first check code from the second memory;

[0122] Performing verification processing on the board information and the second delay to obtain a second verification code;

[0123] determining whether the first verification code and the second verification code are the same;

[0124] When the first verification code and the second verification code are the same, determining that the second delay has not been tampered with during the storage process;

[0125] receiving data according to the second delay;

[0126] When the first verification code and the second verification code are different, determining that the second delay has been tampered with during the storage process;

[0127] re-reading the first data according to the multiple first delays to obtain multiple third data;

[0128] re-determining target data based on the first data and the plurality of third data;

[0129] re-determining the second delay according to the first delay corresponding to the re-determined target data;

[0130] Data reception is performed according to the re-determined second delay.

[0131] The third determining module 15 is configured to obtain a target parameter of a target area of ​​the second memory, where the target area is an area storing the second delay, and the target parameter is used to indicate whether valid data has been stored in the target area;

[0132] When the target parameters are all preset values, the first data is determined.

[0133] A data processing device provided in an embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0134] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 8 As shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected via a bus.

[0135] During the specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502 , so that the at least one processor 501 executes the above-mentioned embodiment of the method for managing a server cluster.

[0136] The specific implementation process of the processor 501 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0137] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0138] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0139] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0140] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute a signal processing system when run.

[0141] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0142] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the signal processing system is implemented.

[0143] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned signal processing system is implemented.

[0144] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0145] The above is a detailed introduction to a signal processing system, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A signal processing system, characterized in that: The signal processing system includes: a board, the board including a baseboard management controller, a first memory and a second memory, wherein: The baseboard management controller determines first data and stores the first data in the first memory, where the first data is an alternating bit sequence; The baseboard management controller reads the first data in the first memory according to the plurality of first delays to obtain a plurality of second data; The baseboard management controller determines a second delay according to the first data, the plurality of second data, and the plurality of first delays, where the second delay is a delay for the baseboard management controller to receive data; The baseboard management controller stores the second delay in the second memory; The baseboard management controller determines the second delay according to the first data, the plurality of second data, and the plurality of first delays, including: The baseboard management controller determines target data from the plurality of second data according to the first data and the plurality of second data, wherein a similarity between the target data and the first data is greater than or equal to a preset threshold; The baseboard management controller determines a first delay corresponding to the target data, determines a maximum first delay and a minimum first delay among the first delays corresponding to the target data, and determines a delay interval based on the maximum first delay and the minimum first delay; and determines a second delay based on the delay interval, where the second delay is a median value of the delay interval.

2. The signal processing system according to claim 1, wherein The baseboard management controller determines target data from the plurality of second data according to the first data and the plurality of second data, including: The baseboard management controller compares the first data with the plurality of second data, and determines a similarity between the first data and the plurality of second data; The baseboard management controller determines target data from the plurality of second data according to the similarity, and the similarity of the target data is greater than or equal to a preset threshold.

3. The signal processing system according to any one of claims 1 to 2, characterized in that: The baseboard management controller determines the board information of the board, wherein the board information includes the serial number of the board; The baseboard management controller performs verification processing on the board information and the second delay to obtain a first verification code; The baseboard management controller stores the board information, the second delay, and the first check code in the second memory.

4. The signal processing system according to any one of claims 1 to 2, characterized in that: The baseboard management controller obtains the stored board information, the second delay and the first check code from the second memory in response to a startup instruction for the board; The baseboard management controller verifies the board information and the second delay to obtain a second verification code; Determining, by the baseboard management controller, whether the first verification code and the second verification code are the same; When the first verification code and the second verification code are the same, the baseboard management controller determines that the second delay has not been tampered with in the second memory; The baseboard management controller receives data according to the second delay; When the first verification code and the second verification code are different, the baseboard management controller determines that the second delay has been tampered with in the second memory; The baseboard management controller re-reads the first data in the first memory according to the multiple first delays to obtain multiple third data; The baseboard management controller re-determines target data according to the first data and the plurality of third data; The baseboard management controller re-determines the second delay according to the first delay corresponding to the re-determined target data; The baseboard management controller receives data according to the re-determined second delay.

5. The signal processing system according to claim 1, wherein: The baseboard management controller obtains a target parameter of a target area of ​​the second memory, where the target area is an area storing the second delay, and the target parameter is used to indicate whether valid data has been stored in the target area; When the target parameter indicates that the target area has not stored valid data, the baseboard management controller determines the first data.

6. The signal processing system according to claim 1, wherein: The board includes a first daughter board and a second daughter board, the first daughter board and the second daughter board are connected via a connector, the first daughter board includes the baseboard management controller and the second memory, and the second daughter board includes the first memory.

7. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the signal processing system according to any one of claims 1 to 6 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the signal processing system according to any one of claims 1 to 6.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the signal processing system according to any one of claims 1 to 6 is implemented.

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