FPGA chip configuration method, device, program product, medium and electronic device

Abstract

The present application belongs to the field of chip configuration technology and proposes a configuration method, device, program product, medium and electronic device for an FPGA chip. The method includes: obtaining an operational index of each converter module in a deep learning model, wherein the operational index is used to characterize the amount of computation performed by the converter module; obtaining the total amount of programmable hardware resources in an FPGA chip, wherein the FPGA chip is used to perform computational tasks on the deep learning model; and configuring multiple processing units in the FPGA chip based on the operational index of each converter module and the total amount of hardware resources, wherein the processing units adapt to the amount of computation performed by the converter module. The technical solution provided by the present application can efficiently provide a deep learning model with hardware resources that can dynamically adapt to its computational needs.

Description

Technical Field

[0001] The present application belongs to the field of chip configuration technology, and in particular relates to a configuration method, device, program product, medium and electronic device for an FPGA chip. Background Art

[0002] With the rapid development of deep learning technology, the complexity and computational demands of deep learning models are increasing, and the requirements for supporting hardware are also becoming increasingly stringent. As the primary computational acceleration hardware in the deep learning field, GPUs (graphics processing units) have become the preferred platform for training and inference of large-scale neural network models due to their powerful parallel computing capabilities and high-bandwidth memory access. However, once a GPU is designed or manufactured, its hardware architecture is fixed. Different deep learning models have different architectures and require significantly different hardware resources. Therefore, when faced with diverse deep learning tasks, GPUs with fixed architectures may not achieve optimal resource utilization and may even lead to problems such as wasted computing power or bottlenecks. Therefore, how to efficiently provide deep learning models with hardware resources that can dynamically adapt to their computational demands has become a pressing technical challenge. Summary of the Invention

[0003] The embodiments of the present application provide a configuration method, device, computer program product, computer-readable storage medium and electronic device for an FPGA chip, thereby efficiently providing hardware resources for deep learning models that can dynamically adapt to their computing needs.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0005] According to a first aspect of an embodiment of the present application, a method for configuring an FPGA chip is provided, the method comprising: obtaining an operation index of each converter module in a deep learning model, the operation index being used to characterize the amount of operation of the converter module; obtaining the total amount of programmable hardware resources in the FPGA chip, the FPGA chip being used to execute operation tasks on the deep learning model; and configuring a plurality of processing units in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources, the processing units being adapted to the amount of operation of the converter module.

[0006] In some embodiments of the present application, based on the aforementioned scheme, multiple processing units are configured in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources, including: allocating hardware resources to each converter module according to the operation index of each converter module and the total amount of hardware resources, wherein the hardware resource allocation amount of each converter module is positively correlated with the operation index of each converter module, and the sum of the hardware resource allocation amounts of each converter module is less than or equal to the total amount of hardware resources; based on the hardware resources allocated to each converter module, multiple processing units are configured in the FPGA chip.

[0007] In some embodiments of the present application, based on the aforementioned scheme, hardware resources are allocated to each converter module according to the operation index of each converter module and the total amount of hardware resources, including: determining the sum of the operation indexes of the each converter module, and determining the first proportion of the operation index of each converter module to the sum of the operation indexes; allocating hardware resources to each converter module based on the first proportion corresponding to each converter module, wherein the absolute value of the difference between the second proportion of the hardware resource allocation amount of each converter module to the total amount of hardware resources and the first proportion is less than the preset proportion.

[0008] In some embodiments of the present application, based on the aforementioned scheme, multiple processing units are configured in the FPGA chip based on the hardware resources allocated to each converter module, including: generating a first chip configuration file based on the hardware resources allocated to each converter module, the first chip configuration file being used to describe the status and connections of the hardware resources inside the FPGA chip; loading the first chip configuration file into the FPGA chip to configure multiple processing units in the FPGA chip.

[0009] In some embodiments of the present application, based on the aforementioned scheme, each converter module includes multiple network modules. After configuring multiple processing units in the FPGA chip, the method further includes: configuring a processing sub-unit corresponding one-to-one to the network module in each converter module in the processing unit corresponding to each converter module, and the processing sub-unit is used to perform computing tasks on the network module.

[0010] In some embodiments of the present application, based on the aforementioned scheme, multiple processing units are configured in the FPGA chip based on the hardware resources allocated to each converter module, and processing sub-units corresponding one-to-one to the network modules in each converter module are configured in the processing unit corresponding to each converter module, including: respectively determining the number of network modules contained in each converter module; generating a second chip configuration file based on the hardware resources allocated to each converter module and the number of network modules contained in each converter module, the second chip configuration file being used to describe the status and connections of the hardware resources inside the FPGA chip; loading the second chip configuration file into the FPGA chip to configure multiple processing units in the FPGA chip, and processing sub-units corresponding one-to-one to the network modules in each converter module are configured in the processing unit corresponding to each converter module.

[0011] In some embodiments of the present application, based on the aforementioned scheme, the transformer module includes a Transformer block, and the multiple network modules include multiple parallel attention network modules and multiple parallel expert network modules.

[0012] In some embodiments of the present application, based on the aforementioned scheme, the method further includes: executing a training operation task on the deep learning model through the FPGA chip; or executing an inference operation task on the deep learning model through the FPGA chip.

[0013] According to the second aspect of an embodiment of the present application, a configuration device for an FPGA chip is provided, the device comprising: a first acquisition unit, for acquiring an operation index of each converter module in a deep learning model, the operation index being used to characterize the amount of operation of the converter module; a second acquisition unit, for acquiring the total amount of programmable hardware resources in the FPGA chip, the FPGA chip being used to perform operation tasks on the deep learning model; a configuration unit, for configuring a plurality of processing units in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources, the processing units being adapted to the amount of operation of the converter module.

[0014] According to a third aspect of an embodiment of the present application, a computer program product is provided, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device having the processor executes to implement the operations performed by the method described in the first aspect above.

[0015] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one computer program instruction is stored. The at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the method described in the first aspect above.

[0016] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising one or more processors and one or more memories, wherein at least one computer program instruction is stored in the one or more memories, and the at least one computer program instruction is loaded and executed by the one or more processors to implement the operations performed by the method described in the first aspect above.

[0017] In this application, based on the reconfigurable characteristics of the FPGA chip architecture, by obtaining the computational index of each converter module in the deep learning model and combining it with the total amount of programmable hardware resources in the FPGA chip, efficient configuration of the FPGA chip is achieved. Compared with the existing method of using a fixed-architecture chip to perform deep learning model computing tasks, the technical solution proposed in this application can give full play to the programmable advantages of the FPGA chip, dynamically configure the processing units on the FPGA chip according to the actual computing requirements of different converter modules, so that each converter module obtains hardware resources that match its computing capacity. This on-demand allocation mechanism enables the FPGA chip to flexibly adjust internal hardware resources, improve the efficiency of hardware resource utilization, avoid resource waste, and thus efficiently provide the deep learning model with hardware resources that dynamically adapt to its computing needs, significantly improving the performance and efficiency of the deep learning model reasoning or training process.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0020] Figure 1 A flowchart of a method for configuring an FPGA chip in an embodiment of the present application is shown;

[0021] Figure 2 A block diagram of a configuration device for an FPGA chip in an embodiment of the present application is shown;

[0022] Figure 3A schematic structural diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0025] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should also be noted that in the accompanying drawings, certain components that do not affect the explanation of the technical solutions of this application have been omitted for clarity.

[0026] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0027] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] In order to enable those skilled in the art to better understand this application, the technical concepts and application background involved in this application are first briefly explained.

[0029] FPGA chip: An FPGA (Field Programmable Gate Array) chip is a programmable logic device. It consists of a large number of programmable logic cells (such as lookup tables (LUTs) and flip-flops), programmable interconnect resources, and I / O interfaces. Users can program FPGAs using hardware description languages ​​(such as VHDL or Verilog) to implement various digital logic functions.

[0030] Deep learning models: Deep learning models are artificial neural network models composed of multiple layers (usually three or more) of nonlinear processing units. By learning from large amounts of data, they can automatically extract and represent features within the data, enabling complex pattern recognition and prediction tasks. Deep learning models are a method in the field of machine learning and are widely used in fields such as image recognition, speech recognition, and natural language processing.

[0031] Transformer module: The Transformer module is a basic building block in deep learning models. It can be used to process sequence data and is widely used in fields such as natural language processing and computer vision.

[0032] With the rapid development of deep learning technology, the complexity and computational demands of deep learning models are increasing, and the requirements for supporting hardware are also becoming increasingly stringent. As the most important computational acceleration hardware in the deep learning field, GPUs (graphics processing units) have become the preferred platform for training and inference of large-scale neural network models due to their powerful parallel computing capabilities and high-bandwidth memory access. However, once a GPU is designed or manufactured, its hardware architecture is fixed. Different deep learning models have different architectures and require significantly different hardware resources. Therefore, when faced with diverse deep learning tasks, GPUs with fixed architectures may not achieve optimal resource utilization and may even waste computing power or experience computational bottlenecks. In this context, this application proposes a FPGA chip configuration solution to efficiently provide deep learning models with hardware resources that can dynamically adapt to their computational needs.

[0033] The following describes the implementation details of the technical solution of the embodiment of the present application:

[0034] Reference Figure 1 , shows a flowchart of the configuration method of the FPGA chip in the embodiment of the present application, the configuration method of the FPGA chip can be executed by a device with a computing and processing function, refer to Figure 1 As shown, the configuration method of the FPGA chip includes at least steps 110 to 130, which are described in detail as follows:

[0035] In step 110, an operation index of each converter module in the deep learning model is obtained, where the operation index is used to represent the amount of operation of the converter module.

[0036] In this application, the transformer module can be a Transformer block (also called TransformerBlock). In different deep learning models, the number of transformer modules is generally different. These differences mainly depend on factors such as the design goals, computing resources, expected applications, and performance requirements of the deep learning model. For example, the number of transformer modules in various versions of the large language model GPT-3 ranges from 12 to 96. For example, the large language model DeepSeek-7B contains 32 transformer modules, the large language model DeepSeek-33B contains 48 transformer modules, and the large language model DeepSeek-67B contains 80 transformer modules.

[0037] Each transformer module typically contains multiple network modules, primarily composed of multiple parallel attention network modules (i.e., multi-head attention) and feedforward networks (FFNs). Within the feedforward network, multiple parallel mixture of experts (MOE) modules can be introduced to increase model capacity. Furthermore, each transformer module is typically equipped with auxiliary structures such as normalization and residual connections.

[0038] In this application, the number and types of network modules (such as self-attention, feedforward network, gating mechanism, expert network, etc.) contained in different transformer modules will vary depending on the design goals and implementation methods of the model.

[0039] In this application, the computational index refers to the order of magnitude of the amount of computation required by a converter module during forward reasoning or training. It can be used to characterize the computational load of the converter module, that is, to measure the complexity and computational overhead of the converter module. For example, it can be expressed in FLOPs (Floating Point Operations). Another example is the number of multiplication-addition operations (MACs). In addition, the computational index can also be expressed in terms of computational throughput requirements, parameter count, energy consumption requirements, or any other metric that can reflect the module's computational load.

[0040] Continue to refer to Figure 1 In step 120, the total amount of programmable hardware resources in the FPGA chip is obtained, and the FPGA chip is used to perform the computing task of the deep learning model.

[0041] In this application, the programmable hardware resources in an FPGA chip primarily include lookup tables (LUTs), flip-flops (FFs), digital signal processing units (DSPs, DSP slices / blocks), on-chip memory (BRAMs, block RAMs), and I / O resources. The LUTs are the fundamental units for implementing arbitrary logic functions, the flip-flops are used for sequential logic storage, the DSPs are used for efficient arithmetic operations like multiplication and addition, the on-chip memory is used for data caching and storage, and the I / O resources include high-speed serial / parallel interfaces, which primarily impact external data exchange capabilities.

[0042] In this application, the total amount of programmable hardware resources in an FPGA chip can be obtained based on the specific model of the FPGA chip. For example, the total number of LUTs (i.e., a metric for lookup tables), the total number of FFs (i.e., a metric for flip-flops), the total number of DSP units (i.e., a metric for digital signal processing units), the total BRAM capacity (i.e., a metric for on-chip memory), and the number of I / Os (i.e., a metric for I / O resources) can be obtained based on the specific model of the FPGA chip.

[0043] In this application, the FPGA chip is used as a hardware acceleration platform for the deep learning model, that is, the FPGA chip implements reasoning and / or training operations on the deep learning model.

[0044] Continue to refer to Figure 1 In step 130, a plurality of processing units are configured in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources, and the processing units are adapted to the operation amount of the converter module.

[0045] In this application, multiple processing units (PUs) can be dynamically configured within the FPGA chip based on the computational index of each converter module and the total hardware resources of the FPGA chip. The hardware resource scale of these processing units is adapted to the computational index of each converter module. For example, converter modules with larger computational indexes are allocated more logic units (which may include lookup tables and flip-flops) and DSP units to configure the processing units, while converter modules with smaller computational indexes are allocated fewer hardware resources to configure the processing units, thereby achieving a reasonable allocation of hardware resources.

[0046] In this application, it should be noted that the processing unit configured within the FPGA chip is a collection of hardware resources configured for a specific converter module on the FPGA chip, capable of independently or collaboratively completing specific computing tasks. Each processing unit may include resources such as lookup tables (LUTs), flip-flops (FFs), multipliers, registers, and on-chip RAM. These resources are combined and optimized according to the actual computational requirements of the converter module to achieve efficient data processing capabilities.

[0047] In this application, based on the reconfigurable nature of the FPGA chip architecture, efficient configuration of the FPGA chip is achieved by obtaining the computational index of each converter module in the deep learning model and combining it with the total amount of programmable hardware resources in the FPGA chip. Compared with the existing method of using a fixed-architecture chip to perform deep learning model computation tasks, the technical solution proposed in this application can fully utilize the programmable advantages of the FPGA chip and dynamically configure the processing units on the FPGA chip according to the actual computational requirements of different converter modules, so that each converter module obtains hardware resources that match its computational capacity. This on-demand allocation mechanism enables the FPGA chip to flexibly adjust internal hardware resources, improve hardware resource utilization efficiency, avoid resource waste, and thus efficiently provide the deep learning model with hardware resources that dynamically adapt to its computational needs, significantly improving the performance and efficiency of the deep learning model inference or training process. In addition, the technical solution proposed in this application also has good scalability and adaptability, and can support the deployment of deep learning models of different scales and structures on the same FPGA platform, greatly enhancing the application value of FPGA chips in the field of intelligent computing.

[0048] In this application, Figure 1 In step 130, configuring multiple processing units in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources can be performed according to the following steps 131 to 132:

[0049] Step 131: allocate hardware resources to each converter module according to the operation index of each converter module and the total amount of hardware resources, wherein the hardware resource allocation amount of each converter module is positively correlated with the operation index of each converter module, and the sum of the hardware resource allocation amounts of each converter module is less than or equal to the total amount of hardware resources.

[0050] Step 132: configuring multiple processing units in the FPGA chip based on the hardware resources allocated to each converter module.

[0051] In this application, the total amount of programmable hardware resources in the FPGA chip (such as the total number of logic units, i.e., the total number of LUTs and the total number of FFs) can be used as an overall constraint condition. According to the operation index of each converter module, weighted allocation, proportional allocation or other optimization algorithms are used to allocate a corresponding amount of hardware resources to each converter module. Specifically, the higher the operation index of the converter module, the more hardware resources are allocated to it, ensuring that its high operation requirements can be met; the converter module with a lower operation index is allocated fewer hardware resources to achieve rational use of hardware resources. It should be noted that the sum of the hardware resources allocated to all modules cannot exceed the total amount of hardware resources of the FPGA chip, so as to avoid FPGA chip configuration failure or FPGA chip performance degradation caused by over-allocation of resources.

[0052] In this application, it should be noted that the sum of the hardware resource allocations for each converter module can be less than the total hardware resource allocation. Specifically, when allocating hardware resources to a converter module, the larger the allocation, the better. If the allocation is too large, the allocated hardware resources will not be fully utilized (i.e., resource utilization will be low) during the converter module's computations, resulting in hardware resource waste. Therefore, the ideal hardware resource allocation should ensure that no idle resources are available during the converter module's computations and that no computational tasks within the converter module are queued.

[0053] Furthermore, after allocating hardware resources to each converter module, multiple processing units can be configured within the FPGA chip based on the number and type of hardware resources allocated to each converter module. The number and type of hardware resources for each processing unit (in terms of scale, composition, and functional characteristics) are matched to the computational requirements of the converter module it serves. For example, converter modules with a higher computational index (i.e., a large computational load) can be configured with larger processing units to provide greater parallel computing power and bandwidth support, while modules with a lower computational index (i.e., a smaller computational load) can be configured with smaller or simplified processing units. This configuration process involves the specific mapping and connection of hardware resources such as logic units, DSP units, and storage units within the FPGA to ensure that each processing unit can efficiently execute the computational tasks of its corresponding converter module.

[0054] In this application, through the technical solutions in steps 131 to 132 above, the FPGA chip can dynamically construct a hardware acceleration structure with strong adaptability and high resource utilization according to the computing requirements of different converter modules, thereby improving the overall operating efficiency and performance of the deep learning model.

[0055] In the present application, the allocation of hardware resources to each converter module according to the operation index of each converter module and the total amount of hardware resources can be performed according to steps 1311 to 1312:

[0056] Step 1311 : determining the sum of the operation indices of the converter modules, and determining a first proportion of the operation index of each converter module to the sum of the operation indices.

[0057] Step 1312: Allocate hardware resources to each converter module based on the first proportion corresponding to each converter module, wherein the absolute value of the difference between the second proportion of the hardware resource allocation of each converter module to the total hardware resources and the first proportion is less than the preset proportion.

[0058] In this application, when performing the operation demand analysis of the converter module, the sum of the operation indexes of all converter modules can be counted first, and the sum S is obtained by adding up the operation index of each module. Then, the first proportion of each converter module is calculated, and its formula (1) can be:

[0059]

[0060] in, Indicates the i a first proportion of a converter module; Indicates the i Operation index of each converter module; Represents the sum of the operational indices of each converter module.

[0061] It is understood that the first proportion of the converter module can reflect the weight of the converter module in the overall computing load. This first proportion can be used to quantify the computing requirements of each converter module, providing a basis for subsequent hardware resource allocation, ensuring that hardware resource allocation matches actual computing requirements, thereby avoiding waste or uneven allocation of hardware resources.

[0062] Furthermore, once the first proportion of each converter module is known, the limited FPGA hardware resources (such as the lookup table LUT and flip-flop FF) can be allocated proportionally, that is, the actual hardware resource proportion allocated to each converter module (the second proportion) is as close as possible to the required computing proportion (the first proportion) of each converter module. Specifically, hardware resources can be allocated to each converter module according to its first proportion, the second proportion (actual allocated resource amount / total hardware resource amount) is calculated, and the allocation accuracy is verified to ensure that the difference between the second proportion and the first proportion of each converter module is less than a preset proportion (i.e., a tolerance threshold, such as 1%). By controlling the deviation between the actual allocation proportion and the theoretical required proportion, it can be ensured that the performance of each module is neither limited by insufficient hardware resources nor wasted due to excessive hardware resources in the allocation of hardware resources.

[0063] In order to enable those skilled in the art to better understand the present application, a specific embodiment is described below.

[0064] Assume that a deep learning model has three converter modules, A, B, and C, with floating-point operations per second (FLOPS) requirements (i.e., computational indices) as follows: Converter module A: 60,000 floating-point operations per second (FLOPS); Converter module B: 30,000 floating-point operations per second (FLOPS); Converter module C: 10,000 floating-point operations per second (FLOPS). The total number of lookup tables available for allocation on the FPGA chip is 99,999. The default usage is 1%.

[0065] The first step is to calculate the sum of the operation exponents, which is 60,000 + 30,000 + 10,000 = 100,000 floating-point operations per second.

[0066] The second step is to calculate the first proportion of each converter module: the first proportion of converter module A is 60000 / 100000=0.6; the first proportion of converter module B is 30000 / 100000=0.3; the first proportion of converter module C is 10000 / 100000=0.1.

[0067] In the third step, hardware resources (i.e., lookup tables) are allocated to each converter module based on the first proportion: the number of LUTs allocated to converter module A = 99999 × 0.6 = 59999.4, rounded to 60,000; the number of LUTs allocated to converter module B = 99999 × 0.3 = 29999.7, rounded to 30,000; and the number of LUTs allocated to converter module C = 99999 × 0.1 = 9999.9, rounded to 10,000. Because the sum of the hardware resource allocations for each converter module exceeds one LUT, adjustments are required. In this case, a resource allocation correction algorithm can be used to prioritize reducing the number of LUTs allocated to converter module A, which has the most LUTs, so that the total number of LUTs allocated equals 99999. This means that the number of LUTs allocated to converter module A is adjusted to 59999.

[0068] Finally, since the second proportion of converter module A is 59999 / 99999≈0.59999, the absolute value of the difference |0.59999-0.6|=0.00001<0.01, which meets the allocation requirements.

[0069] In this application, it should be noted that the above examples are intended only to help those skilled in the art better understand the contents of this application. In practice, in the specific hardware resource allocation process, relevant parameters such as the operation index, the amount of hardware resource allocation, and the number of converter modules may be more complex. This application does not limit the scope of protection to the above examples. Any equivalent transformations or modifications made within the spirit and principles of this application shall be included in the scope of protection of this application.

[0070] In this application, by calculating the sum of the operation index and the first proportion, and allocating hardware resources according to the first proportion, the operation requirements of each converter module can be scientifically quantified. In the actual allocation of hardware resources, this condition is met by rounding and fine-tuning. In addition, by ensuring that the absolute value of the difference between the actual allocation proportion (second proportion) of each converter module and its theoretical operation requirement proportion (first proportion) is less than a preset tolerance threshold (such as 1%), the deviation between the actual allocation ratio and the theoretical ratio can be accurately controlled, ensuring the accuracy of hardware resource allocation and making hardware resource allocation both fair and efficient.

[0071] In the present application, the configuration of multiple processing units in the FPGA chip based on the hardware resources allocated to each converter module can be performed according to steps 1321 to 1322:

[0072] Step 1321: Generate a first chip configuration file based on the hardware resources allocated to each converter module, where the first chip configuration file is used to describe the status and connections of the hardware resources inside the FPGA chip.

[0073] Step 1322: load the first chip configuration file into the FPGA chip to configure multiple processing units in the FPGA chip.

[0074] In this application, a configuration file can be used to describe the state and connections of the hardware resources within the FPGA chip. This can be a bitstream file (essentially a "bitstream" that describes how each programmable switch within the FPGA (such as a lookup table (LUT), wires, registers, and logic cells / elements) is connected and operates) or a similar hardware description file.

[0075] It's important to note that the "state" mentioned above refers to the specific internal configuration of each programmable resource (such as a LUT or register). For example, a 4-input LUT can implement 16 input combinations, each of which can be configured to output either 0 or 1. These 16 bits constitute the "state" of the LUT.

[0076] It's also important to note that the "wiring" mentioned above refers to the numerous programmable switches and wire networks within the FPGA, which flexibly connect different units such as LUTs and registers. The configuration file determines which units have signal paths and which do not.

[0077] The state and connections of all programmable resources within the FPGA refer to the specific functions (states) of each configurable functional unit (LUT, register, etc.) in the FPGA, as well as the paths (connections) through which these units are connected.

[0078] In the present application, after the first chip configuration file is generated, the generated first chip configuration file can be loaded into the FPGA chip through the FPGA configuration interface (such as JTAG, SPI, configuration flash memory, etc.), thereby completing the dynamic configuration of the processing unit in the hardware resources. The loading process can be completed by a dedicated configuration tool or host computer software. When the first configuration file is successfully loaded, the hardware resources inside the FPGA chip complete the physical configuration and wiring according to the description of the configuration file, realizing multiple independent or collaborative processing units. These processing units can run in parallel and execute the functions and logic of their respective corresponding converter modules. Through this dynamic hardware configuration method, the parallel processing capabilities and reconfigurable characteristics of the FPGA chip can be fully utilized, thereby improving the overall performance and hardware resource utilization of the deep learning model's computing tasks.

[0079] In the present application, each transformer module includes multiple network modules. As mentioned above, the multiple network modules may include multiple parallel attention network modules and multiple parallel expert network modules.

[0080] Furthermore, after the above step 1322, that is, after configuring multiple processing units in the FPGA chip, the following step 140 may be performed:

[0081] Step 140 : configuring a processing sub-unit corresponding to a network module in each converter module in the processing unit corresponding to each converter module, wherein the processing sub-unit is used to execute a computing task on the network module.

[0082] In this application, within each processing unit of the FPGA chip, a dedicated processing subunit can be configured for each network module, depending on the number and type of network modules within the converter module. This ensures that the computational tasks of each network module are independently completed by dedicated hardware resources, avoiding resource contention and improving the parallelism of deep learning model operations.

[0083] That is to say, necessary hardware resources (such as LUT, register, BRAM, DSP, etc.) can be allocated to each processing sub-unit, and the hardware structure of the processing sub-unit can be customized according to the operation characteristics of the corresponding network module (such as matrix multiplication, convolution, activation function, etc.) to achieve efficient operation acceleration of the network module.

[0084] In this application, the data flow paths between processing subunits ensure that computational results can be efficiently transferred between them, enabling pipeline or parallel processing. Specifically, during the FPGA chip's operational phase, each processing subunit can perform computational tasks (such as forward reasoning, feature transformation, etc.) on its responsible network module based on input data and control signals. The computational results can be directly output or passed to the next-level processing subunit or processing unit, forming a complete data processing flow.

[0085] In this application, by further subdividing the processing unit of each converter module into multiple processing subunits and corresponding them one-to-one with the network modules, finer-grained hardware acceleration and parallel processing can be achieved, thereby significantly improving the parallel computing capabilities of the FPGA chip, significantly improving the performance and efficiency of the FPGA chip in complex neural networks or multi-layer data processing tasks, and giving full play to the advantages of FPGA chip reconfigurability and high parallelization. In addition, by further subdividing the converter module into multiple network modules and configuring an independent processing subunit for each network module, the resource allocation of each processing subunit can be flexibly adjusted according to the complexity of the actual network module, achieving optimal utilization of hardware resources.

[0086] In the present application, based on the hardware resources allocated to each converter module, multiple processing units are configured in the FPGA chip, and a processing sub-unit corresponding to a network module in each converter module is configured in the processing unit corresponding to each converter module. The following steps 141 to 143 can be performed:

[0087] Step 141: Determine the number of network modules included in each converter module.

[0088] Step 142: Generate a second chip configuration file based on the hardware resources allocated to each converter module and the number of network modules contained in each converter module. The second chip configuration file is used to describe the status and connections of the hardware resources inside the FPGA chip.

[0089] Step 143, load the second chip configuration file into the FPGA chip to configure multiple processing units in the FPGA chip, and configure a processing sub-unit corresponding to the network module in each converter module in the processing unit corresponding to each converter module.

[0090] In the present application, first, the internal structure of each converter module can be analyzed in detail to determine the specific number of network modules it contains. By counting each converter module one by one, a corresponding relationship between the converter module and the number of its internal network modules is formed. Afterwards, based on the obtained number of network modules contained in each converter module and the hardware resources allocated to each converter module, the hardware resource allocation scheme is further refined. Specifically, based on the above information, the hardware structure inside the FPGA chip can be designed and planned, including the layout of each processing unit and its internal processing sub-units, as well as the connection relationship between them. Finally, the above hardware resource allocation and structure information is used to generate a second chip configuration file for comprehensively describing the configuration status and connection status of the hardware resources inside the FPGA chip.

[0091] Finally, the generated second chip configuration file can be loaded into the FPGA chip. Based on this configuration file, the FPGA chip automatically configures multiple processing units and further configures processing subunits corresponding to the network modules within the processing unit corresponding to each converter module. This process creates a multi-level parallel hardware structure within the FPGA chip, significantly improving the FPGA chip's parallel processing capabilities and overall operational efficiency.

[0092] In one embodiment of the present application, the training operation task of the deep learning model can be performed based on the FPGA chip configured as described above.

[0093] After configuring the FPGA chip's multi-level processing units and / or processing sub-units, the chip's powerful parallel processing capabilities can be fully utilized to execute deep learning model training operations. The training process includes multiple phases, including forward propagation, loss calculation, backpropagation, and parameter updates. Each processing unit within the FPGA chip can process different transformer modules and the network modules within these transformer modules in parallel, achieving efficient computation at all model layers.

[0094] In this embodiment, the programmable advantages of the FPGA chip are fully utilized. The processing units on the FPGA chip are dynamically configured according to the actual computational requirements of different converter modules, ensuring that each converter module receives hardware resources that match its computational load. This approach allows the FPGA chip to flexibly adjust its internal hardware resources, improving their utilization efficiency and avoiding resource waste. This allows the deep learning model to dynamically and efficiently adapt its hardware resources to its computational requirements, significantly improving the performance and efficiency of the deep learning model training process and reducing model training costs.

[0095] Taking the FPGA chip configured with the technical solution of this application to train the DeepSeekR1 model as an example, the utilization rate of logic units in the chip increased from 40% to 75%, the BRAM utilization rate increased from 50% to 80%, the training throughput increased to 1.2 TFLOPS, the general IP core reuse rate reached 90%, and the development cycle was shortened from 6 months to 2 weeks.

[0096] In another embodiment of the present application, the inference operation task of the deep learning model can also be performed based on the FPGA chip configured as described above.

[0097] After configuring the FPGA chip's multi-level processing units and / or processing sub-units, the chip can also efficiently perform inference (deduction) operations for deep learning models. The inference phase primarily involves forward propagation of input data and output of results. At this point, the FPGA chip has configured the corresponding processing units and sub-units based on the model structure, fully leveraging hardware parallelism to perform batch or pipeline processing of input data, significantly improving inference throughput and real-time performance.

[0098] It can be seen that based on the technical solution proposed in this application, by dynamically configuring the hardware resources in the FPGA chip according to the actual computing requirements of the deep learning model, whether executing the training task of the deep learning model or executing the inference task, the FPGA chip can provide strong support for the efficient computing of the deep learning model by relying on its flexible, reconfigurable and highly parallel hardware architecture. For example, during the model training phase, more computing resources can be configured to speed up the model training; during the model inference phase, more streamlined resources can be configured to reduce power consumption and cost, thus effectively solving the hardware resource waste and performance bottleneck problems existing in the existing technology.

[0099] The following describes an embodiment of the device of the present application, which can be used to execute the configuration method of the FPGA chip in the above-mentioned embodiment of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the configuration method of the FPGA chip in the above-mentioned embodiment of the present application.

[0100] See also Figure 2 , shows a block diagram of the configuration device of the FPGA chip in an embodiment of the present application.

[0101] like Figure 2 As shown, the configuration device 200 of the FPGA chip according to the embodiment of the present application includes: a first acquisition unit 201, a second acquisition unit 202 and a configuration unit 203.

[0102] Among them, the first acquisition unit 201 is used to obtain the operation index of each converter module in the deep learning model, and the operation index is used to characterize the operation amount of the converter module; the second acquisition unit 202 is used to obtain the total amount of programmable hardware resources in the FPGA chip, and the FPGA chip is used to perform the operation task of the deep learning model; the configuration unit 203 is used to configure multiple processing units in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources, and the processing units are adapted to the operation amount of the converter module.

[0103] In some embodiments of the present application, based on the aforementioned scheme, the configuration unit 203 is configured as: allocating hardware resources to each converter module according to the operation index of each converter module and the total amount of hardware resources, wherein the hardware resource allocation amount of each converter module is positively correlated with the operation index of each converter module, and the sum of the hardware resource allocation amounts of each converter module is less than or equal to the total amount of hardware resources; based on the hardware resources allocated to each converter module, configuring multiple processing units in the FPGA chip.

[0104] In some embodiments of the present application, based on the aforementioned scheme, the configuration unit 203 is configured to: determine the sum of the operational indexes of the various converter modules, and determine the first proportion of the operational index of each converter module to the sum of the operational indexes; based on the first proportion corresponding to each converter module, allocate hardware resources to each converter module, wherein the absolute value of the difference between the second proportion of the hardware resource allocation amount of each converter module to the total amount of hardware resources and the first proportion is less than the preset proportion.

[0105] In some embodiments of the present application, based on the aforementioned scheme, the configuration unit 203 is configured to: generate a first chip configuration file based on the hardware resources allocated to each converter module, wherein the first chip configuration file is used to describe the status and connections of the hardware resources inside the FPGA chip; and load the first chip configuration file into the FPGA chip to configure multiple processing units in the FPGA chip.

[0106] In some embodiments of the present application, based on the aforementioned scheme, each converter module includes multiple network modules, and the configuration unit 203 is further configured as: after configuring multiple processing units in the FPGA chip, a processing sub-unit corresponding to the network module in each converter module is configured in the processing unit corresponding to each converter module, and the processing sub-unit is used to perform computing tasks on the network module.

[0107] In some embodiments of the present application, based on the aforementioned scheme, the configuration unit 203 is further configured to: determine the number of network modules contained in each converter module respectively; generate a second chip configuration file based on the hardware resources allocated to each converter module and the number of network modules contained in each converter module, and the second chip configuration file is used to describe the status and connections of the hardware resources inside the FPGA chip; load the second chip configuration file into the FPGA chip to configure multiple processing units in the FPGA chip, and configure processing sub-units corresponding one-to-one to the network modules in each converter module in the processing unit corresponding to each converter module.

[0108] In some embodiments of the present application, based on the aforementioned scheme, the transformer module includes a Transformer block, and the multiple network modules include multiple parallel attention network modules and multiple parallel expert network modules.

[0109] In some embodiments of the present application, based on the aforementioned scheme, the device further includes: a computing module for performing a training computing task on the deep learning model through the FPGA chip; or, performing an inference computing task on the deep learning model through the FPGA chip.

[0110] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device with the processor executes to implement the operations performed by the configuration method of the FPGA chip as described above.

[0111] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the configuration method of the FPGA chip as described above.

[0112] Based on the same inventive concept, the present application also provides an electronic device, referring to Figure 3 , shows a structural schematic diagram of an electronic device in an embodiment of the present application, wherein the electronic device includes one or more memories 304, one or more processors 302, and at least one computer program (computer program instruction) stored in the memory 304 and executable on the processor 302. When the processor 302 executes the computer program, the configuration method of the FPGA chip as described above is implemented.

[0113] Among them, Figure 3 In the present invention, a bus architecture (represented by bus 300) is shown. Bus 300 may include any number of interconnected buses and bridges. Bus 300 links various circuits, including one or more processors represented by processor 302 and memory represented by memory 304. Bus 300 may also link various other circuits, such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and, therefore, will not be described further herein. Bus interface 305 provides an interface between bus 300 and receiver 301 and transmitter 303. Receiver 301 and transmitter 303 may be the same component, namely a transceiver, which provides a means for communicating with various other devices over a transmission medium. Processor 302 is responsible for managing bus 300 and general processing, while memory 304 may be used to store data used by processor 302 when performing operations.

[0114] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Furthermore, the functional units may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0116] The units described as separate components may or may not be physically separate, and the components of the control device may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0117] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, etc. Various media that can store computer program instructions.

[0118] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of the claims of the present application.

Claims

1. A configuration method for an FPGA chip, characterized in that: The method comprises: Obtaining an operation index of each converter module in the deep learning model, where the operation index is used to represent the amount of operation of the converter module; Obtaining the total amount of programmable hardware resources in an FPGA chip, wherein the FPGA chip is used to perform a computing task on the deep learning model; According to the operation index of each converter module and the total amount of hardware resources, multiple processing units are configured in the FPGA chip, and the processing units are adapted to the operation amount of the converter module; the processing unit is a set of hardware resources configured on the FPGA chip for a specific converter module, which can independently or collaboratively complete specific computing tasks, and the resources are combined and optimized according to the actual operation requirements of the converter module.

2. The method according to claim 1, characterized in that The configuring of multiple processing units in the FPGA chip according to the operation index of each converter module and the total amount of hardware resources includes: Allocating hardware resources to each converter module according to the operation index of each converter module and the total amount of hardware resources, wherein the amount of hardware resources allocated to each converter module is positively correlated with the operation index of each converter module, and the sum of the hardware resources allocated to each converter module is less than or equal to the total amount of hardware resources; Based on the hardware resources allocated to the respective converter modules, a plurality of processing units are configured in the FPGA chip.

3. The method according to claim 2, characterized in that Allocating hardware resources to each converter module according to the operation index of each converter module and the total amount of hardware resources includes: Determining a sum of the operational indices of the converter modules, and determining a first proportion of the operational index of each converter module to the sum of the operational indices; Based on the first proportion corresponding to each converter module, hardware resources are allocated to each converter module, wherein the absolute value of the difference between the second proportion of the hardware resource allocation of each converter module to the total hardware resources and the first proportion is less than the preset proportion.

4. The method according to claim 2, characterized in that The configuring of multiple processing units in the FPGA chip based on the hardware resources allocated to the respective converter modules includes: Based on the hardware resources allocated to each converter module, generating a first chip configuration file, wherein the first chip configuration file is used to describe the status and connections of the hardware resources inside the FPGA chip; The first chip configuration file is loaded into the FPGA chip to configure multiple processing units in the FPGA chip.

5. The method according to claim 2, characterized in that Each converter module includes multiple network modules. After configuring multiple processing units in the FPGA chip, the method further includes: A processing sub-unit corresponding to each network module in each converter module is configured in the processing unit corresponding to each converter module, and the processing sub-unit is used to execute the computing task of the network module.

6. The method according to claim 5, characterized in that The method includes configuring multiple processing units in the FPGA chip based on the hardware resources allocated to each converter module, and configuring a processing sub-unit corresponding to a network module in each converter module in the processing unit corresponding to each converter module, including: Determine the number of network modules included in each converter module; Generate a second chip configuration file based on the hardware resources allocated to each converter module and the number of network modules included in each converter module, wherein the second chip configuration file is used to describe the status and connections of the hardware resources inside the FPGA chip; The second chip configuration file is loaded into the FPGA chip to configure multiple processing units in the FPGA chip, and a processing sub-unit corresponding to the network module in each converter module is configured in the processing unit corresponding to each converter module.

7. The method according to claim 6, characterized in that The transformer module includes a Transformer block, and the multiple network modules include multiple parallel attention network modules and multiple parallel expert network modules.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: Executing the training operation task of the deep learning model through the FPGA chip; or, The FPGA chip is used to perform inference calculations on the deep learning model.

9. A configuration device for an FPGA chip, characterized in that: The device comprises: A first acquisition unit is used to obtain an operation index of each converter module in the deep learning model, where the operation index is used to represent the amount of operation of the converter module; A second acquisition unit is used to obtain the total amount of programmable hardware resources in an FPGA chip, where the FPGA chip is used to perform a computing task on the deep learning model; A configuration unit is used to configure multiple processing units in the FPGA chip based on the computing index of each converter module and the total amount of hardware resources, and the processing units are adapted to the computing volume of the converter module; the processing unit is a collection of hardware resources configured on the FPGA chip for a specific converter module, which can independently or collaboratively complete specific computing tasks, and the resources are combined and optimized according to the actual computing requirements of the converter module.

10. A computer program product, characterized in that The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor, so as to enable a computer device having the processor to perform the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one program code, and the at least one program code is loaded and executed by a processor to implement the operations performed by the method according to any one of claims 1 to 8.

12. An electronic device, characterized in that: The electronic device includes one or more processors and one or more memories, wherein at least one program code is stored in the one or more memories, and the at least one program code is loaded and executed by the one or more processors to implement the method according to any one of claims 1 to 8.

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