Method for compressing plaintext matrix and computing device

Abstract

A method for compressing a plaintext matrix and a computing device, the plaintext matrix is obtained, the plaintext matrix is a Fourier transform matrix or an inverse Fourier transform matrix, the plaintext matrix is decomposed to obtain a plurality of sparse matrixes, the number of non-zero diagonals of each sparse matrix except a main diagonal is at most 2, and the product of the plurality of sparse matrixes is the plaintext matrix, dividing the plurality of sparse matrixes into n groups, aiming at any group of sparse matrixes, determining a product of the group of sparse matrixes as a combined matrix corresponding to the group of sparse matrixes, aiming at any combined matrix, determining an access period corresponding to the combined matrix, and respectively performing access on the combined matrix along each diagonal line according to the access period, the compression diagonals corresponding to the combined matrix are determined according to the access result, and the plaintext matrix can be compressed by utilizing the repetition rule of the diagonal elements of the combined matrix obtained after the plaintext matrix is decomposed and combined, so that the space required for storing the plaintext matrix can be reduced, and the efficiency of transmitting the plaintext matrix can be improved.

Description

Technical Field

[0001] The embodiments of this specification belong to the technical field of data processing, and in particular, relate to a method for compressing a plaintext matrix and a computing device. Background Art

[0002] For a fully homomorphic encryption scheme based on the Ring Learning With Errors (RLWE) assumption, homomorphic operations (such as multiplication, addition, etc.) can be performed on the encrypted homomorphic ciphertext to achieve the same effect as performing the same operations on the plaintext. Thus, the plaintext data can be utilized or processed without revealing the plaintext data, and it has broad application prospects in fields such as privacy-preserving machine learning and cloud computing.

[0003] Generally, homomorphic operations on homomorphic ciphertexts are performed by a dedicated computing chip. Such a computing chip has a relatively fast computing speed, but the on-chip memory is generally not high. Thus, during the process of computing homomorphic ciphertexts, it is necessary to frequently transfer the intermediate products and auxiliary tools of the computing process between on-chip and off-chip to ensure that the on-chip memory of the computing chip has sufficient capacity to store various data generated during the current computing process.

[0004] In such a homomorphic encryption scheme, noise will be introduced during the encryption process to ensure the security of the ciphertext. However, when performing relatively complex homomorphic operations (such as homomorphic multiplication) on the ciphertext, the noise in the ciphertext will continuously accumulate and amplify until it affects the correctness of the ciphertext. Thus, it is necessary to continuously bootstrap the ciphertext during the process of performing homomorphic operations on the ciphertext to refresh the ciphertext so that the ciphertext can continue to support more homomorphic operations.

[0005] During the process of bootstrapping the ciphertext, it is necessary to convert the encoding form of the ciphertext. And during the process of converting the encoding form of the ciphertext, it is necessary to multiply the ciphertext by a pre-prepared plaintext matrix. The parameter scale of the plaintext matrix is large, and the matrix contains a large number of complex numbers. Transmitting this plaintext matrix generally requires a large amount of time. If it is transmitted during the process of bootstrapping, it will seriously affect the overall computing speed. On the contrary, it has extremely high requirements for the capacity of the on-chip memory. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for compressing a plaintext matrix and a computing device, including:

[0007] The first aspect of this specification provides a method for compressing a plaintext matrix, and the method includes:

[0008] Obtain a plaintext matrix, where the plaintext matrix is a Fourier transform matrix or an inverse Fourier transform matrix;

[0009] Decompose the plaintext matrix to obtain a number of sparse matrices. For each sparse matrix, the number of non-zero diagonals except the main diagonal is at most 2, and the product of the number of sparse matrices is the plaintext matrix;

[0010] Divide the number of sparse matrices into n groups evenly;

[0011] For any group of sparse matrices, determine the product of the sparse matrices in this group as the combined matrix corresponding to this group of sparse matrices;

[0012] For any combined matrix, determine the fetch cycle corresponding to this combined matrix;

[0013] According to the fetch cycle, fetch data along each diagonal of the combined matrix respectively, and determine each compressed diagonal corresponding to the combined matrix according to the fetch result.

[0014] A second aspect of this specification provides a computing device, including a memory and a processor. An executable code is stored in the memory. When the processor executes the executable code, the method described in the first aspect is implemented.

[0015] An embodiment of this specification provides a method and a computing device for compressing a plaintext matrix. The repeated pattern of the diagonal elements of the combined matrix obtained by decomposing and combining the plaintext matrix can be utilized to compress the plaintext matrix, which can reduce the space required to store the plaintext matrix and improve the efficiency of transmitting the plaintext matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the embodiments of this specification, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments recorded in this specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic diagram of the Fourier transform matrix in this specification;

[0018] Figure 2 It is a schematic flowchart of a method for compressing a plaintext matrix in an embodiment of this specification;

[0019] Figure 3 It is a schematic diagram of a method for decompressing a compressed diagonal in an embodiment of this specification;

[0020] Figure 4 It is a schematic flowchart of a method for decompressing a compressed diagonal in an embodiment of this specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this specification.

[0022] The following will first explain the professional terms involved in this specification.

[0023] Encoding and decoding: In the CKKS encryption scheme, the initial representation form of the plaintext is a vector, and each element in the vector can store a piece of data, while the representation form of the ciphertext is a polynomial, and the coefficients of each term in the polynomial store the encrypted information. Before encrypting the ciphertext, it is first necessary to encode the plaintext vector into a plaintext polynomial. This encoding process presets a set of unit roots X (x1, x2,..., xn ∈ X), regards each element in the plaintext vector as the function values of the corresponding X of the plaintext polynomial, and thus solves for the coefficients of each term of the plaintext polynomial. The decoding process is the opposite of the encoding process. Substituting this set of independent variables into the plaintext polynomial, the plaintext vector can be determined according to the function values of the polynomial. The above encoding process can be achieved by multiplying the arranged plaintext vector by the Fourier transform matrix (Inverse Discrete Fourier Transform, IDFT) matrix. Correspondingly, the decoding process can be achieved by multiplying the coefficients of the arranged plaintext polynomial by the inverse Fourier transform (Discrete Fourier Transform, DFT) matrix. The above IDFT matrix and DFT matrix are collectively referred to as the plaintext matrix in this specification.

[0024] Fourier transform matrix: A matrix representation used for the discrete Fourier transform (Discrete Fourier Transform, DFT). Its matrix form is as Figure 1 shown. The dimension of this Fourier transform matrix is (N, N), where W j (0 ≤ j ≤ N - 1) are different powers of the Nth unit root. Usually, in the CKKS encryption scheme, W j = w 5j .

[0025] It should be noted that the conjugate transpose and normalization of the Fourier transform matrix can obtain the inverse Fourier transform matrix corresponding to this Fourier transform matrix. The form of the inverse Fourier transform matrix will not be elaborated here.

[0026] Figure 2The flowchart shows a method for compressing a plaintext matrix in this specification. This method for compressing a plaintext matrix can be executed using a computing device, and the method includes:

[0027] Step S201: Obtain a plaintext matrix, where the plaintext matrix is a Fourier transform matrix or an inverse Fourier transform matrix.

[0028] First, the computing device obtains the plaintext matrix to be compressed.

[0029] It should be noted that the method provided in this specification can be applied to the bootstrapping step of a homomorphic encryption scheme, or to other scenarios where a Fourier transform matrix needs to be compressed and transmitted. This specification will not elaborate here.

[0030] In addition, for the method as Figure 2 shown, the Fourier transform matrix and the inverse Fourier transform matrix have the same execution process and effect. The following will only introduce the case where the plaintext matrix is a Fourier transform matrix as an example.

[0031] Step S203: Decompose the plaintext matrix to obtain a number of sparse matrices. The number of non-zero diagonals of each sparse matrix except the main diagonal is at most 2, and the product of the number of sparse matrices is the plaintext matrix.

[0032] After the computing device obtains the compressed plaintext matrix, the plaintext can be decomposed, and the plaintext matrix is decomposed into the product of a number of sparse matrices.

[0033] Specifically, according to the description corresponding to the Fourier transform matrix in the term introduction, each element in the plaintext matrix is determined according to . According to the properties of complex numbers:

[0034]

[0035] When the dimension of the plaintext matrix is (N, N) and N = 2 k (k ≥ 2), the plaintext matrix is represented as DFT N . For the row vector A with number K in the DFT N in this plaintext matrix, this row vector A can be represented as The row vector A is divided into an odd-numbered group and an even-numbered group according to the sorting index corresponding to each element, and then the vector A1 corresponding to the odd-numbered group can be obtained and the vector A2 corresponding to the even-numbered group Using the above property (1) of complex numbers to transform the vector A1 and the vector A2, then Furthermore, according to the above property (2) of complex numbers On the other hand, when K < N / 2, for the row vector B numbered K + N / 2 in the plaintext matrix, the row vector B can be expressed as Similarly, decompose the row vector B into an odd-numbered group vector B1 and an even-numbered group B2. Using the property (3) of the above complex numbers, then B2 = A2. Thus, for the submatrix (A, B) T , this submatrix can be arranged as

[0036] Furthermore, perform DFT on this plaintext matrix N on each row vector in the same way, and then the following can be obtained

[0037] Specifically, perform bit reversal on the column indices of each element in the DFT N in binary, determine the column index after bit reversal of each element, and arrange the DFT N according to the column index after bit reversal of each element, then the following can be determined

[0038] where is a plaintext matrix with dimensions (N / 2, N / 2) arranged in the same way.

[0039] Bit reversal means swapping the positions of all bits of the target with respect to the midpoint. Taking the vector (0, 1, 2, 3, 4, 5, 6, 7) as an example, in the initial state, the values of the elements in this vector correspond to the bit indices, the bit index of the 0 element is 000, the bit index of the 1 element is 001,..., and the bit index of the 7 element is 111. After bit reversal, the bit index of the 0 element is 000, the bit index of the 1 element is 100,..., and the bit index of the 7 element is 111. The vector after bit reversal is (0, 4, 2, 6, 1, 5, 3, 7)

[0040] Thus, can be decomposed into:

[0041]

[0042] where E N / 2 is an identity matrix with dimensions (N / 2, N / 2). It can be observed that has only two non-empty diagonals, so this is the first sparse matrix. Continuing, decompose

[0043] in the above method:

[0044]

[0045] Then, the second sparse matrix can be further determined. Since N = 2 k , repeating this process can decompose the plaintext matrix into the product of k sparse matrices -

[0046] where the i-th sparse matrix can be expressed as

[0047] It can be observed that for each sparse matrix, the number of non-zero diagonals except the main diagonal is at most 2.

[0048] Step S205: Divide the several sparse matrices into n groups evenly.

[0049] After obtaining each sparse matrix, the computing device can divide the sparse matrix into n groups evenly. When N = 2 15 , that is, k = 15, there are 15 sparse matrices in total. For example, the sparse matrices can be divided into n = 3 groups, with each group including 5 sparse matrices.

[0050] In some implementation manners, adjacent sparse matrices can be divided into one group according to the order of each sparse matrix decomposed in step S203.

[0051] Step S207: For any group of sparse matrices, determine the product of the sparse matrices in this group as the combined matrix corresponding to this group of sparse matrices.

[0052] After determining each group of sparse matrices, the computing device can determine the product of each group of sparse matrices. According to the characteristics of each sparse matrix - the number of non-zero diagonals except the main diagonal is at most 2. The product of each group of sparse matrices - each combined matrix also has several zero diagonals.

[0053] In some embodiments, when N = 2 15 , performing step S203 obtains 15 decomposed sparse matrices - S1,..., S15. Divide the sparse matrices into n = 3 groups, then the combined matrices are C1 = S5·S4·S3·S2·S1, C2 = S10·S9·S8·S7·S6, and C3 = S15·S14·S13·S12·S11 respectively. Among them, C1 includes 32 non-zero diagonals, and C2 and C3 each include 64 non-zero diagonals.

[0054] Step S209: For any combined matrix, determine the fetch cycle corresponding to this combined matrix.

[0055] For any combined matrix, each diagonal of the combined matrix can be composed of several consecutive repeated elements, and for the same combined matrix, the repetition period of the elements in each diagonal of the combined matrix is the same. Thus, any non-zero diagonal in the combined matrix is obtained. The minimum number of repetitions of the consecutive repeated elements in the non-zero diagonal is determined as the fetching period corresponding to the combined matrix.

[0056] Specifically, according to the property (2) of the foregoing complex numbers, when a + b = c + d, In the process of multiplying to obtain each combined matrix, although the elements in different sparse matrices are not the same, different two elements can obtain the same multiplication result. Thus, according to the foregoing arrangement characteristics of the sparse matrix, after multiplying each sparse matrix, each diagonal in the combined matrix as the multiplication result is composed of several consecutive repeated elements.

[0057] Step S211: According to the fetching period, fetch numbers from the combined matrix along each diagonal respectively, and determine each compressed diagonal corresponding to the combined matrix according to the fetching result.

[0058] As described above, for any combined matrix, each diagonal in the combined matrix has the same "sparsity" - the repetition period of the consecutive repeated elements is the same.

[0059] After determining the fetching period for each combined matrix in step S209, for any combined matrix, the computing device can determine the fetching period corresponding to the combined matrix, and fetch numbers along each diagonal of the combined matrix with the fetching period P as the period - for any diagonal, according to the arrangement order of the elements in the diagonal, every P elements are retained as one fetching result. Through this fetching operation, the consecutive repeated elements in any diagonal of the combined matrix can be compressed into one element. When the length of the combined matrix is N and the fetching period is P, the length of the compressed diagonal corresponding to this diagonal is N / P. Further, when fetching numbers from this diagonal, the fetching results of this diagonal can be arranged in the fetching order, so that for any compressed diagonal, the arrangement order of the elements in the compressed diagonal is the same as the arrangement order of the elements in the diagonal of the combined matrix corresponding to the compressed diagonal.

[0060] On the other hand, the fetching period is determined according to the minimum number of repetitions of the consecutive repeated elements in the diagonal, which can ensure that the fetching result of the diagonal does not miss any element that has appeared in the diagonal.

[0061] In some embodiments, when N = 2 15, Step S203 is executed to obtain 15 decomposed sparse matrices - S1, ..., S15. The sparse matrices are divided into n = 3 groups, and the combined matrices are respectively - combined matrix C1 = S5·S4·S3·S2·S1, combined matrix C2 = S10·S9·S8·S7·S6, combined matrix C3 = S15·S14·S13·S12·S11. Among them, the number of valid data in a non-zero diagonal of the combined matrix C1 is 2 15 pieces, that is, the fetch cycle corresponding to the combined matrix C1 is 0, and all elements in each non-zero diagonal of the combined matrix C1 need to be retained. Further, each compressed diagonal corresponding to the combined matrix C1 is the original non-zero diagonal in the combined matrix C1; the number of valid data in a non-zero diagonal of the combined matrix C2 is 2 10 pieces, that is, the fetch cycle corresponding to the combined matrix C2 is 2 5 . When fetching data from any non-zero diagonal in the combined matrix C2, according to the arrangement order of the elements in the non-zero diagonal, elements can be extracted with a period of 2 5 and retained to the compressed diagonal corresponding to the non-zero diagonal; the number of valid data in a non-zero diagonal of the combined matrix C3 is 2 5 pieces, that is, the fetch cycle corresponding to the combined matrix C2 is 2 10 . When fetching data from any non-zero diagonal in the combined matrix C2, according to the arrangement order of the elements in the non-zero diagonal, elements can be extracted with a period of 2 10 and retained to the compressed diagonal corresponding to the non-zero diagonal.

[0062] It can be seen from this embodiment that using the method provided in this specification for the combined matrix can have different fetch cycles, and when the dimension of the matrix is large, there is an obvious compression effect on the length of the diagonal. On the other hand, according to the embodiment described in step S207, the number of compressible diagonals can reach 80%.

[0063] As Figure 2 shown, a method for compressing a plaintext matrix can utilize the repetition rule of the diagonal elements of the combined matrix obtained after the decomposition and combination of the plaintext matrix to compress the plaintext matrix, which can reduce the space required to store the plaintext matrix and improve the efficiency of transmitting the plaintext matrix.

[0064] In some implementation manners, the dimension of the plaintext matrix is (2 k , 2 k ); in step S203 as Figure 2 shown, the plaintext matrix is decomposed to obtain k sparse matrices with a dimension of (2 k , 2 k ).

[0065] Specifically, reference may be made to the description of step S203.

[0066] In some implementation manners, in step S203 as shown in Figure 2 According to the column index of bit reversal, each element in the plaintext matrix is arranged, and the inverse matrix corresponding to the plaintext matrix is determined as the matrix to be decomposed, and the matrix to be decomposed is decomposed.

[0067] Specifically, reference may be made to the corresponding description of step S203.

[0068] In some implementation manners, in step S203 as shown in 2, the matrix to be decomposed is decomposed into the product of a block diagonal matrix and a sparse matrix. The block diagonal matrix is composed of the same blocks, and each block in the block diagonal matrix corresponds to the matrix to be decomposed after the number of times of the unit root is halved. The block diagonal matrix is used as the updated matrix to be decomposed, and the updated matrix to be decomposed is decomposed into the product of an updated block diagonal matrix and an updated sparse matrix until the updated block diagonal matrix is the identity matrix.

[0069] Specifically, reference may be made to the corresponding description in step S203.

[0070] According to the above formulas (3) and (4), is decomposed. When N = 2 k , when reaching the k-th round, that is, is decomposed:

[0071]

[0072] As can be seen from the above formula, the blocks on the diagonal of the updated block diagonal matrix are This updated block diagonal matrix is the identity matrix and cannot be decomposed further.

[0073] In some implementation manners, in Figure 2 As shown in step S209, for any combined matrix, according to the maximum number of consecutive repeated elements in any non-zero diagonal of the combined matrix, the fetching period corresponding to the combined matrix is determined.

[0074] As described above, the maximum number of consecutive repeated elements in each non-zero diagonal of the combined matrix is the same. The fetching period determined according to any non-zero diagonal of the combined matrix can be applied to other diagonals of the combined matrix.

[0075] Therefore, by statistically analyzing any non-zero diagonal in the combined matrix, the fetching period used by all non-zero diagonals in the combined matrix can be determined.

[0076] In some implementation manners, in Figure 2In step S211 shown above, according to the fetching period, numbers are fetched from the combined matrix along each non-zero diagonal, and each compressed diagonal corresponding to each non-zero diagonal of the combined matrix is determined according to the fetching result.

[0077] It should be noted that when transmitting the combined matrix, only the non-zero diagonals of the combined matrix need to be transmitted. Further, by only determining the positions of the non-zero diagonals in the combined matrix, the combined matrix can be restored through the non-zero diagonals. Therefore, in the fetching process of step S211, only the non-zero diagonals of the combined matrix need to be fetched, and only the compressed diagonals corresponding to the non-zero diagonals need to be determined. This can further reduce the number of compressed diagonals required to store the combined matrix and the total amount of data required to store the combined matrix.

[0078] In some implementation manners, after step S211 shown above, for any combined matrix, the corresponding compressed diagonals and the fetching period of the combined matrix are transmitted to the computing chip, so that the computing chip restores the combined matrix according to the received compressed diagonals and the fetching period. Figure 2 After obtaining the compressed diagonals corresponding to any combined matrix, the computing device can directly transmit the compressed diagonals to the computing chip; or the compressed diagonals can be stored in the memory, and the memory transmits the compressed diagonals to the computing chip in response to the usage requirements of the computing chip. This specification does not make any restrictions here.

[0079] When the computing chip receives the compressed diagonals, since the arrangement order of the elements in each compressed diagonal is the same as the arrangement order of the elements in each diagonal of the combined matrix, the computing chip can decompress the compressed diagonals according to the fetching period. As shown above, the elements in the compressed diagonal are copied, and the groups of copied elements are arranged according to the arrangement order of the elements in the compressed diagonal, and then the original diagonal of the decompressed combined matrix can be obtained. Among them, A, B, C, D, and E are the elements in the compressed diagonal, and P is the fetching period corresponding to the compressed diagonal. Since this decompression process does not involve complex operations, the computing chip can complete the decompression of each compressed diagonal in a short time. Therefore, the process of transmitting the compressed diagonal does not affect other operations that the computing chip is performing.

[0080] Figure 3

[0081]

[0081] It should be noted that in some embodiments, after obtaining the target diagonals corresponding to the same combined matrix, there is no need to splice or combine the target diagonals to restore the complete combined matrix. For example, in the process of DFT operation or IDFT operation using the Baby-Step Giant-Step (BSGS), the target diagonals can be multiplied by the vectors to be transformed with different pre-arranged permutation orders, and through subsequent other operations, the transformation of the representation form of the vectors to be transformed can be achieved.

[0082] In some implementation manners, after the step S211 as Figure 2 shown, each compressed diagonal corresponding to the combined matrix, the position markers corresponding to each compressed diagonal, and the fetch period are transmitted to the computing chip.

[0083] For any combined matrix, the compressed diagonals corresponding thereto in the combined matrix have the same fetch period. Also, in step S211, only the compressed diagonals corresponding to the non-zero diagonals can be determined. To ensure that no information in the combined matrix is lost when transmitting each compressed diagonal, the position markers corresponding to each compressed diagonal and the fetch period can be transmitted to the computing chip, so that the computing chip can obtain the original diagonals in the combined matrix according to each compressed diagonal, and further, according to the position markers corresponding to each compressed diagonal, the computing chip can restore each combined matrix.

[0084] In some implementation manners, after the step S211 as Figure 2 shown, for any combined matrix, each compressed diagonal corresponding to the combined matrix and the fetch period are transmitted to the computing chip, so that the computing chip copies each element in the compressed diagonal according to the fetch period, and arranges the copy results according to the arrangement order of each element in the compressed diagonal to determine the target diagonal corresponding to the compressed diagonal.

[0085] Figure 4 The figure shows a method for decompressing a compressed diagonal provided in this specification. The method is applied to a computing chip and includes:

[0086] Step S401: Obtain the compressed diagonal and the fetch period corresponding to the compressed diagonal. The compressed diagonal is obtained by fetching numbers along the target diagonal of the combined matrix according to the fetch period. The fetch period is determined according to the combined matrix. The combined matrix is a product of a group of sparse matrices, and each sparse matrix is obtained by decomposing a plaintext matrix and is evenly divided into n groups.

[0087] Specifically, each compressed diagonal can be obtained by compressing the plaintext matrix using the method as Figure 2 shown.

[0088] Step S403: Copy each element in the compressed diagonal according to the fetch cycle, and arrange the copy results according to the arrangement order of the elements in the compressed diagonal to determine the target diagonal corresponding to the compressed diagonal.

[0089] Specifically, reference can be made to Figure 3 the corresponding description. This target diagonal is the original diagonal in the combined matrix.

[0090] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software improvements (improvements to method flows). However, with the development of technology, many method flow improvements today can be regarded as direct improvements to hardware circuit structures. Almost all designers obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented using a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logical function is determined by the user programming the device. Designers can program themselves to "integrate" a digital system onto a single PLD, without having to ask a chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a Hardware Description Language (HDL), and there is not just one type of HDL, but many, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones currently are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be aware that by simply performing a little logical programming on the method flow using the above-mentioned several hardware description languages and programming it into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method flow.

[0091] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, it is entirely possible to logically program the method steps to enable the controller to be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. to achieve the same function. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or structures within the hardware component.

[0092] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a server system. Of course, this application does not exclude that with the development of future computer technologies, the computers for implementing the functions of the above embodiments can be, for example, personal computers, laptop computers, in-vehicle human-machine interaction devices, cellular phones, camera phones, smart phones, personal digital assistants, media players, navigation devices, email devices, game consoles, tablet computers, wearable devices, or any combination of these devices.

[0093] Although one or more embodiments of this specification provide method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-creative means. The order of steps listed in the embodiments is only one way among many execution orders of steps and does not represent the only execution order. When actually executed by a device or terminal product, it may be executed in the order of the method shown in the embodiments or the drawings or in parallel (for example, in an environment of parallel processors or multi-threaded processing, or even in a distributed data processing environment). The term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, product or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, product or device. Without further limitation, there is no exclusion of additional identical or equivalent elements in the process, method, product or device comprising the said elements. For example, if terms such as first and second are used to denote names, they do not denote any particular order.

[0094] For convenience of description, when describing the above device, it is divided into various modules according to functions for separate description. Of course, when implementing one or more of this specification, the functions of each module can be implemented in the same or multiple software and / or hardware, or the modules implementing the same function can be realized by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0095] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and the combination of processes and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0096] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction means that implements the functions specified in one or more of the processes and / or blocks Figure 1 in the process or processes and / or blocks Figure 1 specified in the block or blocks.

[0097] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one or more of the processes and / or blocks Figure 1 in the process or processes and / or blocks Figure 1 specified in the block or blocks.

[0098] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0099] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM) and / or non-volatile memory such as read only memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

[0100] Computer-readable media includes both permanent and non-permanent, removable and non-removable media implemented by any method or technology for storing information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technologies, compact disc read only memory (CD-ROM), digital versatile discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage, graphene storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0101] Those skilled in the art should understand that one or more embodiments of this specification can be provided as a method, a system, or a computer program product. Therefore, one or more embodiments of this specification can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, one or more embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0102] One or more embodiments of this specification can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of this specification can also be practiced in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0103] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and reference can be made to the relevant parts of the method embodiments for the related content. In the description of this specification, the description of reference terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0104] The above description is only for the embodiments of one or more embodiments of this specification and is not intended to limit one or more embodiments of this specification. For those skilled in the art, one or more embodiments of this specification can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included within the scope of the claims.

Claims

1. A method for compressing a plaintext matrix, the method comprising: Obtaining a plaintext matrix, where the plaintext matrix is a Fourier transform matrix or an inverse Fourier transform matrix; Decomposing the plaintext matrix to obtain a plurality of sparse matrices, where for each sparse matrix, the number of non-zero diagonals except the main diagonal is at most 2, and the product of the plurality of sparse matrices is the plaintext matrix; Dividing the plurality of sparse matrices into n groups evenly; For any group of sparse matrices, determining the product of the sparse matrices in the group as the combined matrix corresponding to the group of sparse matrices; For any combined matrix, determining the fetching period corresponding to the combined matrix; According to the fetching period, fetching numbers along each diagonal of the combined matrix respectively, and determining each compressed diagonal corresponding to the combined matrix according to the fetching result.

2. The method according to claim 1, where the dimension of the plaintext matrix is (2k, 2k); Decomposing the plaintext matrix to obtain a plurality of sparse matrices, specifically including: Decomposing the plaintext matrix to obtain k sparse matrices with dimension (2k, 2k).

3. The method according to claim 1, decomposing the plaintext matrix, specifically including: Arranging each element in the plaintext matrix according to the bit-reversed column index, and determining the inverse-order matrix corresponding to the plaintext matrix as the matrix to be decomposed; Decomposing the matrix to be decomposed.

4. The method according to claim 3, decomposing the matrix to be decomposed, specifically including: Decomposing the matrix to be decomposed into the product of a block diagonal matrix and a sparse matrix, where the block diagonal matrix is composed of the same blocks, and each block in the block diagonal matrix corresponds to the matrix to be decomposed with the number of unit roots halved; Taking the block diagonal matrix as the updated matrix to be decomposed, and decomposing the updated matrix to be decomposed into the product of an updated block diagonal matrix and an updated sparse matrix until the updated block diagonal matrix is an identity matrix.

5. The method according to claim 1, for any combined matrix, determining the fetching period corresponding to the combined matrix, specifically including: For any combined matrix, determining the fetching period corresponding to the combined matrix according to the maximum number of consecutive repeated elements in any non-zero diagonal of the combined matrix.

6. The method according to claim 1, according to the fetching period, fetching numbers along each diagonal of the combined matrix respectively, and determining each compressed diagonal corresponding to the combined matrix according to the fetching result, specifically including: According to the fetching period, fetching numbers along each non-zero diagonal of the combined matrix, and determining each compressed diagonal corresponding to each non-zero diagonal of the combined matrix according to the fetching result.

7. The method according to claim 1, further comprising: For any combined matrix, transmitting each compressed diagonal corresponding to the combined matrix and the fetching period to a computing chip, so that the computing chip restores the combined matrix according to the received compressed diagonals and the fetching period.

8. The method according to claim 7, transmitting each compressed diagonal corresponding to the combined matrix and the fetching period to a computing chip, specifically including: Transmit each compressed diagonal corresponding to the combined matrix, the position markers corresponding to each compressed diagonal, and the fetch cycle to the computing chip.

9. The method according to claim 7, wherein the method comprises: For any combined matrix, transmit each compressed diagonal corresponding to the combined matrix and the fetch cycle to the computing chip, so that the computing chip copies each element in the compressed diagonal according to the fetch cycle, and arranges the copy results according to the arrangement order of the elements in the compressed diagonal to determine the target diagonal corresponding to the compressed diagonal.

10. A computing device, comprising a memory and a processor, wherein executable code is stored in the memory, and when the processor executes the executable code, the method according to any one of claims 1-9 is implemented.

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