Method, device and equipment for simulating finite-state machine based on spiking neural network and storage medium

Abstract

The invention relates to the technical field of artificial intelligence, in particular to a method, device and equipment for simulating a finite-state machine based on a spiking neural network and a storage medium. The method comprises the following steps: acquiring an input signal; according to the input signal, a corresponding output signal is output through a DTSRNN model which is trained in advance, the DTSRNN model is a model which simulates the state transition process of an FSM by combining the characteristics of the DTSRNN and an SNN, and the output signal is a response signal generated by the DTSRNN model according to the input signal and internal state transition logic. According to the embodiment of the invention, the DTSRNN model combining the characteristics of the DTRNN and the SNN is provided, and the information can be processed in a discrete and sparse mode, which is highly matched with the discrete state conversion process of the FSM, thereby achieving the efficient simulation of the FSM behavior, and greatly improving the performance of a neural network model for simulating the FSM.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and particularly to a method, apparatus, device, and storage medium for simulating a finite state machine based on a spiking neural network. Background Art

[0002] As a classic computational model, the Finite State Machine (FSM) plays an irreplaceable and important role in theoretical computer science and many practical application fields. It can precisely describe systems with a well-defined state space and predictable state transitions, and its application scenarios are extensive, covering complex sequential logic in digital circuits, controller design in control systems, and natural language processing, among many other aspects.

[0003] However, traditional FSM design methods have exposed some obvious limitations in practical applications. First, the FSM can only effectively simulate systems with discrete and transparent states, and is powerless for black-box systems or systems with continuous and dynamic characteristics. Second, when faced with a system of relatively high complexity, the FSM often encounters the problem of state explosion, which not only makes the design process extremely cumbersome, but also significantly increases the difficulty and workload of implementation.

[0004] In recent years, in order to overcome these deficiencies of the traditional FSM, researchers have begun to attempt to combine it with neural networks. This combination aims to fully utilize the complementary advantages of the two modeling paradigms to effectively solve the problems faced by the traditional FSM. Neural networks are excellent at simulating implicit, continuous, and complex systems with their powerful capabilities, but their efficiency is often not satisfactory when dealing with discrete problems that require high stability and precision. Nevertheless, the current neural network methods for simulating FSMs are still not satisfactory in terms of performance and have not been able to provide a reasonable and effective solution. Summary of the Invention

[0005] In view of this, the present disclosure proposes a method, apparatus, device, and storage medium for simulating a finite state machine based on a spiking neural network.

[0006] According to one aspect of the present disclosure, there is provided a method for simulating a finite state machine based on a spiking neural network, the method comprising:

[0007] Obtain an input signal;

[0008] According to the input signal, an output signal corresponding thereto is output by a pre-trained Discrete-time Spiking Recurrent Neural Network (DTSRNN) model. The DTSRNN model is a model that combines the characteristics of a Discrete-time Recurrent Neural Network (DTRNN) and a Spiking Neural Network (SNN) to simulate the state transition process of a FSM. The output signal is a response signal generated by the DTSRNN model according to the input signal and the internal state transition logic.

[0009] In a possible implementation, the DTSRNN model includes an input layer, a hidden layer, and an output layer. The step of outputting, by the pre-trained Discrete-time Spiking Recurrent Neural Network DTSRNN model according to the input signal, a corresponding output signal includes:

[0010] The input signal is converted into a pulse sequence through the input layer. The pulse sequence includes input vectors of multiple time steps.

[0011] In each time step, the neuron model of the hidden layer generates the state vector of the current time step according to the input vector of the current time step and the state vector of the previous time step. The state vector is used to indicate the state transferred by the simulated FSM.

[0012] In each time step, the neuron model of the output layer determines the output vector of the current time step according to the state vector of the current time step; the output vectors of multiple time steps are integrated into the output signal for output.

[0013] In another possible implementation, the step of generating, by the neuron model of the hidden layer, the state vector of the current time step according to the input vector of the current time step and the state vector of the previous time step includes:

[0014] The neuron model of the hidden layer generates the state vector of the current time step according to the input vector of the current time step, the state vector of the previous time step, the membrane potential of the previous time step, a preset weight parameter, a time parameter, and a membrane potential threshold.

[0015] In another possible implementation, both the input signal and the output signal adopt a one-hot encoding form.

[0016] In another possible implementation, the input signal includes text data, and the output signal is used to indicate the classification result, recognition result, or prediction result of the DTSRNN model for the text data; or,

[0017] the input signal includes digital signals in a circuit, and the output signal includes the logical state output generated by the DTSRNN model according to the digital signals; or,

[0018] the input signal includes control signals of a control system, and the output signal is used to indicate the control instructions generated by the DTSRNN model according to the control signals.

[0019] In another possible implementation, the input signal includes input vectors of multiple time steps, the output signal includes output vectors of multiple time steps, and the method further includes:

[0020] For each time step, according to the input vector of the current time step, determine the correct state vector of the current time step through the linear expression relationship of the FSM. The linear expression relationship of the FSM is used to indicate multiplying the input vector of the current time step by the state transition matrix to obtain an intermediate matrix, and the state transition matrix is used to indicate all candidate state transition situations; multiply the state vector of the previous time step by the intermediate matrix to obtain the correct state vector of the current time step;

[0021] Compare the correct state vector of the current time step with the state vector of the current time step determined by the DTSRNN model to determine the verification result of the DTSRNN model, and the verification result is used to indicate the prediction accuracy of the DTSRNN model.

[0022] In another possible implementation, before outputting the corresponding output signal through the pre-trained discrete-time spiking recurrent neural network DTSRNN model according to the input signal, it further includes:

[0023] Obtain a training sample set, where the training sample set includes multiple groups of sample data groups, and each group of the sample data groups includes a sample input signal and a label output signal;

[0024] Train the original parameter model according to multiple groups of the sample data groups by using the error backpropagation algorithm to obtain the DTSRNN model.

[0025] According to another aspect of the present disclosure, there is provided a device for simulating a finite state machine based on a spiking neural network, and the device includes:

[0026] An acquisition module, configured to acquire an input signal;

[0027] A processing module, configured to output a corresponding output signal according to the input signal through a pre-trained DTSRNN model. The DTSRNN model is a model that combines the characteristics of DTRNN and SNN to simulate the state transition process of an FSM. The output signal is a response signal generated by the DTSRNN model according to the input signal and internal state transition logic.

[0028] In a possible implementation, the DTSRNN model includes an input layer, a hidden layer, and an output layer. The processing module is further configured to:

[0029] Convert the input signal into a pulse sequence through the input layer. The pulse sequence includes input vectors of multiple time steps.

[0030] In each time step, generate the state vector of the current time step through the neuron model of the hidden layer according to the input vector of the current time step and the state vector of the previous time step. The state vector is used to indicate the state transferred by the simulated FSM.

[0031] In each time step, determine the output vector of the current time step through the neuron model of the output layer according to the state vector of the current time step; integrate the output vectors of multiple time steps into the output signal for output.

[0032] In another possible implementation, the processing module is further configured to:

[0033] Generate the state vector of the current time step through the neuron model of the hidden layer according to the input vector of the current time step, the state vector of the previous time step, the membrane potential of the previous time step, a preset weight parameter, a time parameter, and a membrane potential threshold.

[0034] In another possible implementation, both the input signal and the output signal adopt a one-hot encoding form.

[0035] In another possible implementation, the input signal includes text data, and the output signal is used to indicate the classification result, recognition result, or prediction result of the DTSRNN model for the text data; or,

[0036] The input signal includes digital signals in a circuit, and the output signal includes a logical state output generated by the DTSRNN model according to the digital signals; or,

[0037] The input signal includes control signals of a control system, and the output signal is used to indicate a control instruction generated by the DTSRNN model according to the control signals.

[0038] In another possible implementation, the input signal includes input vectors for a plurality of time steps, the output signal includes output vectors for a plurality of time steps, and the apparatus further includes: a verification module configured to:

[0039] For each time step, according to the input vector of the current time step, determine the correct state vector of the current time step through the linear expression relationship of the FSM, where the linear expression relationship of the FSM is used to indicate multiplying the input vector of the current time step by the state transition matrix to obtain an intermediate matrix, and the state transition matrix is used to indicate all candidate state transition cases; multiply the state vector of the previous time step by the intermediate matrix to obtain the correct state vector of the current time step;

[0040] Compare the correct state vector of the current time step with the state vector of the current time step determined by the DTSRNN model to determine the verification result of the DTSRNN model, where the verification result is used to indicate the prediction accuracy of the DTSRNN model.

[0041] In another possible implementation, the apparatus further includes: a training module configured to:

[0042] Obtain a training sample set, where the training sample set includes multiple groups of sample data groups, and each group of the sample data groups includes a sample input signal and a labeled output signal;

[0043] Train an original parameter model according to the multiple groups of sample data groups by using the error backpropagation algorithm to obtain the DTSRNN model.

[0044] According to another aspect of the present disclosure, there is provided a computing device including a memory, a processor, and a computer program stored on the memory, where the processor executes the computer program to implement the steps of the above method.

[0045] According to another aspect of the present disclosure, there is provided a non-volatile computer-readable storage medium having a computer program stored thereon, where the computer program, when executed by a processor, implements the steps of the above method.

[0046] According to another aspect of the present disclosure, there is provided a computer program product including a computer program, or a non-volatile computer-readable storage medium carrying the computer program, where the computer program, when executed by a processor, implements the steps of the above method.

[0047] In the embodiments of the present disclosure, an input signal is obtained, and the pre-trained DTSRNN model combines the characteristics of the DTRNN and the SNN to simulate the state transition process of the FSM, thereby generating a corresponding output signal. Since the DTSRNN model integrates the characteristics of the DTRNN and the SNN, it can process information in a discrete and sparse manner, which highly coincides with the discrete state transition process of the FSM. Therefore, the DTSRNN model can accurately generate a response signal according to the input signal and its internal state transition logic, thereby realizing an efficient simulation of the behavior of the FSM, greatly improving the performance of the neural network model in simulating the FSM.

[0048] Other features and aspects of the present disclosure will become clear from the following detailed description of the exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings included in and constituting a part of the specification illustrate exemplary embodiments, features, and aspects of the present disclosure together with the specification, and are used to explain the principles of the present disclosure.

[0050] Figure 1 FIG. shows a schematic structural diagram of a computing device provided by an exemplary embodiment of the present disclosure.

[0051] Figure 2 FIG. shows a flowchart of a method for simulating a finite state machine based on a spiking neural network provided by an exemplary embodiment of the present disclosure.

[0052] Figure 3 FIG. shows a schematic diagram of a LIF neuron model, a DTSRNN model, and corresponding dynamic equations provided by an exemplary embodiment of the present disclosure.

[0053] Figure 4 FIG. shows a schematic diagram of the state transition process of an FSM provided by an exemplary embodiment of the present disclosure.

[0054] Figure 5 FIG. shows a schematic diagram of the conversion between binary coding and one-hot coding provided by an exemplary embodiment of the present disclosure.

[0055] Figure 6 FIG. shows a schematic diagram of the process of the DTSRNN model simulating the FSM provided by an exemplary embodiment of the present disclosure.

[0056] Figure 7 FIG. shows a schematic diagram of the experimental results of the DTSRNN model and the traditional model under a noise signal provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0058] As used herein, the terms "comprising," "including," "having," or variations thereof are open-ended and include one or more stated features, integers, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integers, elements, steps, components, functions, or groups thereof.

[0059] When an element is referred to as being "connected," "coupled," "responsive," or variations thereof to another element, it can be directly connected, coupled, or responsive to the other element, or intervening elements may be present.

[0060] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0061] The term "exemplary" as used herein means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

[0062] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0063] Traditional Recurrent Neural Network (RNN) models have many deficiencies in simulating Finite State Machines (FSMs). On the one hand, the generalization ability of traditional models has not been fully verified, making it difficult to exhibit stable performance in diverse tasks. On the other hand, its working mechanism is essentially different from the discrete state transition characteristics of FSMs, resulting in poor temporal stability and prone to state drift and accuracy degradation. In addition, the current research on the actual mechanism of traditional models simulating FSMs is still insufficient, and there are obvious bottlenecks in the ability of traditional models to learn FSMs under the commonly used binary coding method, which urgently needs to be improved.

[0064] As the third-generation neural network, the Spiking Neural Network (SNN) is one of the important algorithm models in brain-inspired computing. By simulating the neurons and their connection relationships in the human brain, it exhibits rich encoding capabilities, diverse spatio-temporal dynamics mechanisms, and event-driven characteristics, enabling efficient processing of complex spatio-temporal information. Different from traditional neural networks with continuous activation signals, the spike signal transmission mechanism of SNN highly matches the discrete state transition process of the Finite State Machine (FSM). Based on this, the embodiments of this disclosure propose a DTSRNN model that combines the characteristics of the Discrete-Time Recurrent Neural Network (DTRNN) and SNN. This model introduces the SNN mechanism on the basis of DTRNN, which not only significantly improves the generalization ability of the neural network to simulate FSM, but also greatly enhances the learning ability and time stability of the model, providing an innovative and effective solution for efficiently simulating FSM.

[0065] First, an introduction is made to the execution subject involved in this disclosure. Please refer to Figure 1 , which shows a schematic structural diagram of a computing device provided by an exemplary embodiment of this disclosure.

[0066] The computing device can be a terminal or a server. The terminal includes a mobile terminal or a fixed terminal. For example, the terminal can be a mobile phone, a tablet computer, a laptop computer, a desktop computer, and so on. The server can be a single server, or a server cluster composed of several servers, or a cloud computing service center.

[0067] The computing device includes a processor 10, a memory 20, and a communication interface 30. Those skilled in the art can understand that Figure 1 the structure shown in

[0068] does not limit the computing device, and it may include more or fewer components than shown in the figure, or combine some components, or have different component arrangements. Among them:

[0069] The memory 20 can be used to store software programs and modules. The processor 10 executes various functional applications and data processing by running the software programs and modules stored in the memory 20. The memory 20 may mainly include a program storage area and a data storage area. Among them, the program storage area may store an operating system 21, an acquisition module 22, a processing module 23, and application programs 24 required for at least one function, etc.; the data storage area may store data created according to the use of the computing device, etc. The memory 20 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read Only Memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. Correspondingly, the memory 20 may further include a memory controller to provide the processor 10 with access to the memory 20.

[0070] Among them, the processor 10 executes the following functions by running the acquisition module 22: acquiring an input signal. The processor 10 executes the following functions by running the processing module 23: according to the input signal, outputting a corresponding output signal through a pre-trained DTSRNN model. The DTSRNN model is a model that combines the characteristics of DTRNN and SNN to simulate the state transition process of the FSM. The output signal is a response signal generated by the DTSRNN model according to the input signal and the internal state transition logic.

[0071] The method provided by the embodiments of the present disclosure can be implemented in multiple application scenarios, and each application scenario has its specific input signal and output signal. The following are some examples of application scenarios, as well as the physical meanings of the input signals and output signals in these application scenarios:

[0072] 1. In the natural language processing scenario, the input signal includes text data, and the output signal is used to indicate the classification result, recognition result, or prediction result of the DTSRNN model for the text data. In this scenario, the text data can be sentences, paragraphs, or documents in natural language processing tasks, and the output signal can be manifested as semantic classification (such as topic classification) of the text data by the DTSRNN model, named entity recognition (NER) (such as person name and place name recognition). The following are two illustrative examples:

[0073] In an illustrative example, taking the detection of email format as an example, first, other networks or methods are used to perform part-of-speech tagging on the email text. Subsequently, the tagged email text is converted into an input signal through one-hot encoding, where each state corresponds to a possible part-of-speech tag. The input signal is input into the trained DTSRNN model, and the model can judge whether the email format is correct according to the state transition logic. For example, if the model detects that the salutation is missing at the beginning of the email, or the part-of-speech sequence of the body and signature parts does not conform to the conventional format, it can be determined that there is an error in the email format.

[0074] In another illustrative example, for the named entity recognition task, the FSM simulated by the DTSRNN can identify entities with specific meanings from the text, such as person names, place names, organization names, etc. Specifically, the words or part-of-speech tags in the text are one-hot encoded and then input into the trained DTSRNN model. Each state represents a possible entity type or non-entity. Based on the current word and its context information, the DTSRNN model transfers from one state to another and predicts whether the current word belongs to a certain entity by a tag.

[0075] 2. In the digital circuit design scenario, the input signal includes digital signals in the circuit, such as clock signals, control signals, or data input signals. The output signal includes the logical state output generated by the DTSRNN model according to the digital signals, which is used to indicate the current state or the next state of the circuit, such as the output state of a flip-flop or the control signal of a complex sequential logic.

[0076] 3. In the control system scenario, the input signal includes the control signal of the control system, and the generation process of the control signal involves a series of key steps. First, the sensor collects the measured values of key physical quantities such as temperature, pressure, and speed. These measured values are not directly available after collection but need to be further processed to meet the requirements of the system for the input signal. For example, by setting a threshold for the measured value, the continuous physical quantity is converted into a discrete signal so that it can be effectively recognized and processed by the control system. After such a series of processes, these signals can serve as accurate input signals to provide strong support for the efficient operation of the control system. The output signal includes the control instructions generated by the DTSRNN model according to the control signal, such as the motor speed adjustment instruction, the valve opening and closing instruction, or the heater on-off instruction, for achieving precise control of the system.

[0077] From these examples, it can be seen that the DTSRNN model has broad application potential in different application scenarios, can generate corresponding output signals according to specific input signals, and thus realizes the state management and control of complex systems. The embodiments of the present disclosure do not limit this.

[0078] Next, several exemplary embodiments are used to introduce the method for simulating a finite state machine based on a spiking neural network provided by the embodiments of the present disclosure.

[0079] Please refer to Figure 2 , which shows the flowchart of the method for simulating a finite state machine based on a spiking neural network provided by an exemplary embodiment of the present disclosure. This embodiment is exemplified by the method being used in the Figure 1 shown computing device. The method includes the following steps.

[0080] Step 201, obtain the input signal.

[0081] In some embodiments, obtain the original input signal. The input signal can be text data in natural language processing, digital signals in circuits, or control signals in control systems. Preprocess the original input signal to make it suitable for model input. For example, the preprocessing includes normalization, denoising, etc. Convert the processed input signal into the format required by the DTSRNN model. For example, convert the input signal into one-hot encoding form. The processed input signal serves as the input of the DTSRNN model, providing the basic information for the DTSRNN model to process.

[0082] One-hot encoding is a coding method that converts discrete categorical features into binary vectors. Its core idea is to use an N-bit status register to encode N states. Each state is represented by its independent register bit, and at any given time, only one bit is valid (i.e., set to 1), and the remaining bits are 0. For example, for the character set {A, B, C}, the one-hot encoding of A is [1, 0, 0], B is [0, 1, 0], and C is [0, 0, 1].

[0083] Step 202, according to the input signal, output the corresponding output signal through the pre-trained DTSRNN model. The DTSRNN model is a model that combines the characteristics of DTRNN and SNN to simulate the state transition process of FSM. The output signal is the response signal generated by the DTSRNN model according to the input signal and the internal state transition logic.

[0084] The computing device inputs the input signal into the pre-trained DTSRNN model and outputs the corresponding output signal. The DTSRNN model is a neural network model that combines the characteristics of DTRNN and SNN and is used to simulate the state transition process of FSM. This model processes the input signal in discrete time steps and simulates the firing behavior of biological neurons through a spiking mechanism, thereby achieving efficient information processing and state update.

[0085] DTRNN is a recurrent neural network based on discrete time steps and can process sequence data. It captures the time dependence of the input signal through recurrently connected neuron layers.

[0086] SNN is a neural network model that simulates the behavior of biological neurons, and its core is the spiking mechanism. When the membrane potential of a neuron reaches the threshold, a spike signal is generated for information transmission. SNN has time dynamic characteristics and biological interpretability.

[0087] FSM is a mathematical model composed of a finite number of states, transition conditions between states, and actions. The input signal includes input vectors for multiple time steps, and the output signal includes output vectors for multiple time steps. At each time step, FSM determines the state vector for the current time step based on the input vector for the current time step and the state vector for the previous time step, and determines the output vector for the current time step based on the state vector for the current time step.

[0088] The state transition process refers to the process in which FSM determines the state vector for the current time step through a state transition function based on the input vector for the current time step and the state vector for the previous time step. Each state transition may be accompanied by specific actions or outputs.

[0089] The output signal is the response signal generated by the DTSRNN model according to the input signal and the internal state transition logic. It can be the classification result, recognition result or prediction result of text data in natural language processing, the logical state output in a circuit, or the control instruction in a control system. The embodiments of the present disclosure do not limit this.

[0090] In some embodiments, the DTSRNN model can adopt the Leaky-Integrate-and-Fire (LIF) neuron model as its neuron model. The LIF neuron is a classical biological neuron that can simulate the electrophysiological characteristics of biological neurons, including the accumulation and leakage of potential and the behavior of firing pulses when the threshold is reached. By introducing LIF neurons into the model, the DTSRNN can be closer to the working mode of the biological nervous system, and at the same time has higher dynamic adaptability and computational efficiency.

[0091] In some embodiments, the DTSRNN model can be constructed as a neural network with a two-layer recursive structure. The neurons in each layer process information and update their states through the LIF mechanism, and at the same time utilize the characteristics of discrete time steps to achieve frame-by-frame processing of the input signal. This design not only retains the powerful modeling ability of the recursive neural network for time series data, but also introduces the efficient information encoding method of biological neurons through the pulse mechanism, enabling the model to perform well in processing complex state transition tasks and achieving efficient information processing and state update in a way closer to the biological nervous system.

[0092] The DTSRNN model combines the time series processing ability of the DTRNN and the pulse coding and dynamic characteristics of the SNN to simulate the state transition process of the FSM.

[0093] In some embodiments, the DTSRNN model simulates the state transition process of the FSM in the following ways: 1. Input signal processing: The DTSRNN model receives the input signal and encodes it into a pulse sequence. 2. State update and transition: Based on the recursive structure of the DTRNN and the dynamic characteristics of the SNN, the DTSRNN model calculates the next state according to the current state and the input signal. When the membrane potential of the neuron reaches the threshold, a state transition is triggered. 3. Output response: The DTSRNN model generates an output signal according to the state transition logic, and this output signal reflects the response of the FSM to the input signal.

[0094] In some embodiments, the DTSRNN model automatically adjusts its network parameters to improve simulation accuracy by learning the mapping relationship between the input signal and the output signal. Before simulating the state transition process of the FSM using the pre-trained DTSRNN model, there is also a process of training the DTSRNN model. The training process of the DTSRNN model can refer to the relevant descriptions in the following embodiments and will not be introduced here first.

[0095] In summary, the embodiments of the present disclosure obtain an input signal and use a pre-trained DTSRNN model to generate a corresponding output signal according to the input signal. The DTSRNN model combines the characteristics of DTRNN and SNN and can process information in a discrete and sparse manner, which highly matches the discrete state transition process of the FSM. Therefore, the DTSRNN model can accurately generate a response signal according to the input signal and its internal state transition logic, thereby achieving an efficient simulation of the FSM behavior. Moreover, DTSRNN can utilize the pulse signal transmission mechanism of SNN to avoid the problems of accuracy degradation and state drift of traditional DTRNN when processing long sequences. Even in the case of noisy input signals, it can still stably learn and simulate the state transition logic of the FSM. The sparse event-driven characteristic of SNN enables only a few neurons to be activated in most time steps, reducing unnecessary computations, improving computational efficiency, and lowering the running cost of the model. This method is not only applicable to specific FSM tasks but also shows good adaptability in simulating state machines with different complexities, verifying its generalization ability in various scenarios.

[0096] In some embodiments, the DTSRNN model includes an input layer, a hidden layer, and an output layer.

[0097] The input layer is the first layer of the DTSRNN model and is responsible for receiving external input data and converting it into a format that can be processed inside the DTSRNN model. In the DTSRNN model, the input signal is converted into a pulse sequence through the input layer. The pulse sequence includes input vectors for multiple time steps. This pulse sequence is a way of encoding the input data and is used to simulate the pulse firing characteristics of biological neurons.

[0098] The hidden layer is a layer between the input layer and the output layer of the DTSRNN model. Its function is to convert the input data into a higher-level feature representation. The hidden layer includes neuron models, which are the basic computational units in the DTSRNN model, and the neuron models can be LIF neuron models. A neuron model includes one or more neurons, and the number of neurons and the connection method depend on the specific neural network architecture. At each time step, through the neuron models in the hidden layer, based on the input vector at the current time step and the state vector at the previous time step, a state vector at the current time step is generated, and the state vector is used to indicate the state to which the simulated FSM transitions.

[0099] In some embodiments, a state vector at the current time step can be generated through the neuron models in the hidden layer according to the input vector at the current time step, the state vector at the previous time step, the membrane potential at the previous time step, preset weight parameters, time parameters, and a membrane potential threshold.

[0100] Among them, the initial value of the state vector can be preset or random. The membrane potential represents the potential state of the neuron model. In the DTSRNN model, the membrane potential at the previous time step may affect the generation of the state vector at the current time step, and the initial value of the membrane potential can be preset. The weight parameters can be preset, the time parameters can be preset or dynamically trainable, and the membrane potential threshold can be preset. When the membrane potential reaches or exceeds the membrane potential threshold, the neuron model will fire a pulse or change its state.

[0101] The output layer is the last layer of the DTSRNN model, and its function is to output the processing result of the DTSRNN model on the input data. That is, at each time step, through the neuron models in the output layer, based on the state vector at the current time step, the output vector at the current time step is determined. After the output vectors of multiple time steps, the output vectors of multiple time steps are integrated into an output signal for output.

[0102] In some embodiments, an output vector at the current time step can be generated through the neuron models in the output layer according to the state vector at the current time step, the membrane potential at the previous time step, preset weight parameters, time parameters, and a membrane potential threshold. It should be noted that the weight parameters, time parameters, and membrane potential threshold of the output layer and the hidden layer can be the same or different. The specific choice depends on the design goals and application scenarios of the network. For example, in some simplified designs, the hidden layer and the output layer may share weight parameters to reduce the model complexity; while in more complex tasks, in order to better adapt to different functional requirements, their weight parameters, time parameters, and membrane potential threshold usually vary.

[0103] In a schematic example, such as Figure 3As shown Figure 3 (a) in is a schematic diagram of a LIF neuron model in the related art. The input signals of the LIF neuron model are (x1, x2, …, x n ), which are weighted and summed through weights (w1, w2, …, w n ). The result V t of the weighted sum is processed through a soft Reset mechanism, and the processed V t is sent to the Fire module, which determines whether to trigger a pulse output by comparing with a preset threshold. If the processed V t exceeds the preset threshold, it outputs 1, indicating that the neuron model has fired an action potential; otherwise, it outputs 0, indicating that the neuron model has not fired an action potential. The final output is a binary signal, i.e., 0 or 1, which reflects whether the neuron model responds to the input signal.

[0104] Figure 3 (b) in is an example diagram of the DTSRNN model provided by an embodiment of the present disclosure. The DTSRNN model generates the state vector y 1 (t) of the current time step based on the input vector x(t) of the current time step, the state vector y 1 (t - 1) of the previous time step, and a preset weight matrix W1. Based on the state vector y 1 (t) of the current time step and a preset weight matrix W2, the output vector y 2 (t) of the current time step is determined. The weight matrix W1 represents the weight matrix from the input layer to the hidden layer, and the weight matrix W2 represents the weight matrix from the hidden layer to the output layer. Here, t is a positive integer.

[0105] Figure 3 (c) in includes formula (1), formula (2), and formula (3). Formula (1) is the basic dynamic equation of the LIF neuron model in the related art, and formula (2) and formula (3) are the dynamic equations of the DTSRNN model provided by an embodiment of the present disclosure. In these formulas, v represents the membrane potential of the neuron model, which changes with time and reflects the charging state of the neuron model. x represents the pulse signal, which is a direct manifestation of the neuron model firing an action potential. w 1 [j, i] represents an element in the weight matrix W1, indicating the connection weight from the j-th neuron in the input layer to the i-th neuron in the hidden layer. w 2 [j, i] represents an element in the weight matrix W2, indicating the connection weight from the j-th neuron in the hidden layer to the i-th neuron in the output layer. Here, i and j are both positive integers. α τ is a trainable time parameter used to adjust the leakage rate of the membrane potential. α τThe value range of v is a value greater than 0 and less than 1. th th is the membrane potential threshold. When the membrane potential reaches or exceeds the membrane potential threshold, the neuron model will fire an action potential. The subscript t represents the time index, that is, the t-th time step. The superscript represents the layer index of the neuron model. That is, the superscript 1 represents the first layer, i.e., the hidden layer, and the superscript 2 represents the second layer, i.e., the output layer. Fire represents the step function, such as the Heaviside function, which is used to simulate the instantaneous behavior of the neuron model firing an action potential. When the membrane potential exceeds the membrane potential threshold, the output of the step function jumps from 0 to 1, indicating that the neuron model has fired an action potential.

[0106] These equations show how the DTSRNN model processes information through the LIF neuron model and processes sequential data through the recurrent connections of the RNN. The DTSRNN model demonstrates its combined characteristics in the following aspects: 1. Spiking neural network characteristics: The DTSRNN model uses the basic dynamic equations of the LIF neuron model to simulate the membrane potential changes of neurons and the process of firing action potentials. This spiking characteristic enables the DTSRNN model to process input signals at discrete time steps and transmit information by firing action potentials, which is similar to the working mode of biological neurons. 2. Recurrent neural network characteristics: The DTSRNN model introduces recurrent connections through dynamic equations, making the state of neurons depend not only on the input at the current time step but also on the state at the previous time step. This recurrent characteristic enables the model to process sequential data and capture the temporal dependencies in the input signals. 3. Dynamic time parameter mechanism: The DTSRNN model introduces a trainable time parameter α to achieve dynamic adjustment of the leakage rate of the membrane potential of the neuron model. This mechanism enables the DTSRNN model to adaptively adjust the sensitivity of neurons according to the characteristics of the input signals and the learning process of the network, so as to better capture the dynamic changes of the input signals.

[0107] In an embodiment of the present disclosure, a DTSRNN model is constructed by referring to the mechanism of biological neurons using discrete pulse signals to transmit information. That is, the DTSRNN model simulates the discrete state transition process of the FSM through discretized time steps and a sparse information transmission method. This design enables the model to process input signals in an efficient manner and generate response signals according to the internal state logic. In this DTSRNN model, through linear processing, the state transition process of the FSM is presented in the most discrete and sparse form. In some embodiments, for a time series input, the output signal generated by the DTSRNN model is a series of state mapping results corresponding to the time steps, that is, the input signal includes input vectors of multiple time steps, the output signal includes output vectors of multiple time steps, and each output vector corresponds to the state vector of that time step. There is a mapping relationship between the linear expression relationship of the DTSRNN model and the FSM, and this mapping relationship can be used to verify the accuracy of the prediction of the DTSRNN model.

[0108] In some embodiments, for each time step, according to the input vector of the current time step, the correct state vector of the current time step is determined through the linear expression relationship of the FSM. The linear expression relationship of the FSM is used to indicate multiplying the input vector of the current time step by the state transition matrix to obtain an intermediate matrix, and the state transition matrix is used to indicate all candidate state transition situations; multiplying the state vector of the previous time step by the intermediate matrix to obtain the correct state vector of the current time step; comparing the correct state vector of the current time step with the state vector of the current time step determined by the DTSRNN model can evaluate the verification result of the DTSRNN model, and further judge the accuracy of the prediction of the DTSRNN model.

[0109] In addition, once the correct state vector of the current time step is determined through the linear expression relationship of the FSM, the correct output vector of the current time step can be determined based on the correct state vector of the current time step. By comparing the correct output vector of the current time step with the output vector of the current time step generated by the DTSRNN model, the performance of the DTSRNN model can be further verified. In some embodiments, the process of determining the correct output vector of the current time step based on the correct state vector of the current time step can be implemented through a mapping function, that is, converting the state vector into an output vector through a mapping function. This mapping function can be linear or non-linear, and the embodiments of the present disclosure do not limit this.

[0110] This verification method can not only ensure the accuracy of the DTSRNN model when processing time series data, but also provide a systematic way to evaluate and improve the model's performance by comparing with the linear expression relationship of the FSM. This method provides an effective verification mechanism for the application of the DTSRNN model in time series prediction tasks, which helps to improve the reliability and practicality of the model.

[0111] Taking a simple FSM as an example, such as Figure 4 shown, which shows a schematic diagram of the state transition process of an FSM provided by an exemplary embodiment of the present disclosure and is expressed in the way of linear algebra. Further, it includes the following parts:

[0112] (a), Truth table: used to uniquely determine the state transition rule, showing all possible combinations of the state vector s and the input vector x of the FSM, as well as the corresponding next state vector.

[0113] (b), Input vector, state vector and state transition matrix: x t represents the input vector at the t-th time step. s t-1 represents the state vector at the (t - 1)-th time step, where each element s i corresponds to the activation degree of the i-th state (usually 0 or 1, representing discrete states), and both i and t are positive integers. The state transition matrix K is used to define the transition rule between states and can be defined as an m×n×n matrix (m is the total number of inputs, n is the total number of states), and each element k ij in the matrix represents a possible state to which it can transfer (usually a one-hot encoded vector).

[0114] (c), Linear expression of state transition, which is divided into two main steps:

[0115] Step 1: Calculate the intermediate matrix K′: Multiply the input vector x t by the state transition matrix K to obtain a new matrix, that is, the intermediate matrix K′.

[0116] Step 2: Calculate the next state vector s t : Multiply the state vector s t-1 at the (t - 1)-th time step by the intermediate matrix K′ obtained in Step 1 to obtain the state vector s t at the t-th time step. The t-th state vector is a 4×1 column vector, representing the new state to which the FSM transfers under the given input vector at the t-th time step and the state vector at the (t - 1)-th time step.

[0117] (d), Visualization of matrix multiplication: Step 1: Shows the input vector x tThe process of multiplying by the state transition matrix K to obtain the intermediate matrix K'. Step 2: shows the state vector s t-1 Multiplying by the intermediate matrix K' to obtain the next state vector s t The process of.

[0118] Figure 4 Through the truth table, input vector, state vector and state transition matrix, the state transition rules of the FSM are described in detail, and how to express these rules by means of linear algebra (i.e., matrix multiplication) is shown. This linear expression provides a basis for using the DTSRNN model to simulate the FSM. In this way, the discrete state transition process of the FSM can be presented in the most discrete and sparse form, thereby improving the learning ability of the neural network in simulating the state machine.

[0119] The above state transition rules can be stored in the form of a three-dimensional matrix. From time step t - 1 to t, the implementation of state transition can be completed by matrix multiplication. However, the implementation of this process requires that the input signal and output signal must be in one-hot encoded form (while the input and output signals of traditional FSMs are usually binary encoded). The one-hot encoded signals make the information itself tend to be discrete and sparse, which not only highly coincides with the discrete nature of the finite state machine state transition, but also echoes the discreteness and sparsity of the spiking neural network. Therefore, this encoding method significantly improves the learning ability of the neural network in simulating finite state machines.

[0120] Therefore, in some embodiments, when using DTSRNNs to simulate FSMs, both the input signal and the output signal are in one-hot encoded form, that is, the one-hot encoded input signal is input into the pre-trained DTSRNN model, and the corresponding one-hot encoded output signal is output. Taking a simple part-of-speech tagging task as an example, as Figure 5 shown, which shows a schematic diagram of the conversion between binary encoding and one-hot encoding provided by an exemplary embodiment of the present disclosure. The figure shows how to convert text data into two encoding methods of binary encoding and one-hot encoding. The content is as follows:

[0121] (a), Encoding of text data, the text data is: "Finite state machines are very useful.". Four different words (or categories) are extracted from the text data: a, n, v, ad. Each word is mapped to a binary encoding and a one-hot encoding. For example, the binary encoding of the word "a" is "00", and the one-hot encoding of the word "a" is "0001".

[0122] (b), Encoding conversion, which shows how to convert binary encoding to one-hot encoding. For example, the binary encoding "00" is converted to the one-hot encoding "0001", the binary encoding "01" is converted to the one-hot encoding "0010", and so on.

[0123] (c), Input sequence, which shows the binary input sequence and the one-hot input sequence. Binary input sequence: The input at each time step is a binary encoding. One-hot input sequence: The input at each time step is a one-hot encoding.

[0124] When simulating an FSM, the input signal can be a vector of one-hot encodings. This encoding method makes the input signal more discrete and sparse, matching the discrete state transition process of the FSM, thereby improving the learning ability of the neural network in simulating state machines.

[0125] After combining the one-hot encoding, the schematic diagram of the process of the DTSRNN model simulating the FSM is as Figure 6 shown, and the figure contains several key parts:

[0126] 1. State transition diagram of the FSM: The circular diagram on the right side of the figure shows an unknown FSM, listing the various states (S0, S1, S2, S3) of the FSM and their corresponding outputs. For example, the output of state S0 is 0, the output of state S1 is 1, and so on.

[0127] 2. Input and output sequences: The input sequence x = (1 0 1 1 1 0 0 0 1 0 1 0 1) T represents the input signal, which is converted to the input of the neural network after one-hot encoding. The output sequence y label = (1 1 1 1 1 1 0 0 0 0) T represents the expected output signal.

[0128] 3. State transition diagram of the FSM: The circular diagram on the right side of the figure shows an unknown FSM, which contains the various states (S0, S1, S2, S3) of the FSM. The transitions between states are determined by the input signal.

[0129] 4. DTSRNN model: The DTSRNN model is a two-layer recurrent neural network combined with LIF neurons. The model generates the state vector y 1 (t) of the current time step based on the input vector x(t) of the current time step and the state vector y 1 (t - 1) of the previous time step. The output vector y 1 (t) of the current time step is determined based on the state vector y 2 (t) of the current time step.

[0130] 5. Output Prediction: The output sequence y generated by the DTSRNN model 2 = (y0 y1 y2 y3 y4 y5 y6 y7 y8 y9) T represents the actual output signal for predicting the output of the FSM. Both the input signal and the output signal are in one-hot encoding form. Through these key parts, the DTSRNN model can persistently and stably simulate the function of the unknown FSM under the guidance of one-hot encoding.

[0131] It can be seen that the core of the embodiments of the present disclosure lies in the design of the working process of its neural network: it is no longer the traditional continuous type, but adopts a discrete and sparse processing method. This design is particularly suitable for processing FSMs whose complexity is limited within a specific threshold. Under the guidance of a finite-length signal, the DTSRNN model provided by the embodiments of the present disclosure can efficiently learn and master the internal operation mechanism of the FSM. When performing a prediction task, the DTSRNN model demonstrates high accuracy and stability, and can accurately simulate the behavior of the state machine.

[0132] Compared with the traditional RNN model, the DTSRNN model provided by the embodiments of the present disclosure performs better in terms of robustness. Even when the input signal is disturbed by noise, the DTSRNN model can still accurately capture and learn the core mechanism of the FSM. This high tolerance for noise makes the DTSRNN model more reliable in practical applications, especially in scenarios where the signal environment is complex or unstable. In short, the DTSRNN model provides a more powerful and flexible tool for simulating and predicting the behavior of the FSM through its unique discrete and sparse working process.

[0133] In the embodiments of the present disclosure, the DTSRNN model is used to simulate the FSM according to the input signal and then output the corresponding output signal. To achieve this function, the DTSRNN model needs to be trained, and its training process mainly includes the following steps:

[0134] 1. Obtain a training sample set, which includes multiple groups of sample data groups. Each group of sample data groups includes a sample input signal and a labeled output signal. Among them, the sample input signal is the input basis for model training, and the labeled output signal is the target output that the model needs to learn, which is used to guide the training direction of the model.

[0135] 2. According to multiple groups of sample data groups, use the error backpropagation algorithm to train the original parameter model to obtain the DTSRNN model.

[0136] Furthermore, for each sample data group among multiple groups of sample data groups, the sample input signal is input into the original parameter model. The model processes the input signal according to the current parameter configuration to obtain the sample output signal. Next, the sample output signal generated by the model is compared with the label output signal corresponding to the sample. By calculating the difference between the two, a loss value is obtained. This loss value is used to indicate the error between the training result and the output signal label, reflecting the current performance of the model. Based on the loss values corresponding to multiple groups of sample data groups, the DTSRNN model is trained using the error backpropagation algorithm. This algorithm calculates the gradient of the loss value with respect to the model parameters and propagates the error layer by layer from the output layer to the input layer, thereby updating the model parameters to reduce the loss value. This process is repeated until the loss value of the model converges to a satisfactory level, and finally the optimized DTSRNN model is obtained.

[0137] To further improve the training efficiency and performance of the model, the high-performance spatio-temporal gradient descent method, i.e., the Spatio Temporal Backpropagation (STBP) algorithm, can be used for model training. This algorithm not only considers the gradient propagation in the time dimension but also takes into account the information in the space dimension, enabling the model to learn and optimize more efficiently in a complex spatio-temporal data environment. Through the STBP algorithm, the DTSRNN model can better capture the spatio-temporal features of the input signal, thus more accurately simulating the behavior of the FSM and outputting results highly consistent with the label output signal. Through the above detailed and systematic training steps, the DTSRNN model can effectively learn the complex mapping relationship between the input signal and the output signal, providing powerful prediction and simulation capabilities for subsequent application scenarios.

[0138] In some exemplary experiments, through the random FSM verification experiment, based on the state machine mechanism analysis shown above Figure 3 a large number of variously complex FSMs can be randomly generated. Based on these FSMs, a corresponding data set is established and used to test the performance of the DTSRNN model. The experimental results show that under the one-hot encoding condition, the DTSRNN model exhibits excellent learning ability, can efficiently simulate the behavior of the finite state machine, and has strong generalization ability.

[0139] In some other exemplary experiments, a robustness and mechanism comparison experiment between the DTSRNN model and traditional models (such as the RNN model) under noise signals was conducted. The pre-trained DTSRNN model and traditional models were used for prediction, and noise signals were introduced during the prediction process. The experimental results of the DTSRNN model and traditional models under noise signals are as Figure 7As shown. Among them, (a) represents the performance of the DTSRNN model, and (b) represents the performance of the traditional model. It can be clearly seen from the figure that the DTSRNN model shows significantly better robustness than the traditional model in a noisy environment, and to a certain extent, it has a self-correction mechanism, enabling it to maintain high-precision prediction performance in a complex signal environment. This means that even in the presence of noise interference, the DTSRNN model can maintain a high prediction accuracy, thus achieving more reliable performance in a complex signal environment. In contrast, when faced with the same noise interference, the prediction performance of the traditional model is greatly affected, showing lower robustness and self-correction ability. This indicates that in a noisy environment, the prediction results of the traditional model are more likely to be incorrect and difficult to self-correct. Therefore, through the above experiments, the superior performance of the DTSRNN model in a noisy environment can be verified. The DTSRNN model not only demonstrates stronger robustness but also has a self-correction mechanism to a certain extent, which enables it to maintain high-precision prediction performance in a complex signal environment, thus having greater potential and value in practical applications.

[0140] In summary, the method provided by the embodiments of the present disclosure introduces biological neurons that are more in line with the essence of FSM on the basis of the traditional architecture. This design not only significantly improves the stability and efficiency of the network when simulating the behavior of FSM, but also further optimizes the model performance by using one-hot encoding to replace the traditional binary encoding method.

[0141] Furthermore, this improvement shows significant advantages in two key aspects: on the one hand, it significantly improves the temporal stability. By accurately simulating the transition process of FSM, the model can more stably reproduce the behavior of FSM when processing time series data, thus effectively enhancing the modeling ability of dynamic systems. On the other hand, based on an in-depth analysis of the process of the neural network learning FSM, the model shows stronger learning ability in simulating state machines and can more efficiently master complex FSM logic.

[0142] In addition, the embodiments of the present disclosure also propose a brand-new linear expression method to accurately describe the transition process of FSM, and based on this, a special training sample set is constructed, providing strong support for model training.

[0143] In practical applications, considering the interference of signal noise, the DTSRNN model shows stronger robustness than the traditional RNN model, enabling it to adapt to a wider range of complex scenarios, thus greatly expanding its application scope.

[0144] The following is the device embodiment of the embodiments of the present disclosure. For parts not elaborated in detail in the device embodiment, reference can be made to the technical details disclosed in the above method embodiment.

[0145] An embodiment of the present disclosure provides an apparatus for simulating a finite state machine based on a spiking neural network. The apparatus can be implemented in whole or in part as a computing device through software, hardware, or a combination of both. The apparatus includes: an acquisition module and a processing module.

[0146] The acquisition module is configured to acquire an input signal;

[0147] The processing module is configured to output a corresponding output signal according to the input signal through a pre-trained DTSRNN model. The DTSRNN model is a model that combines the characteristics of DTRNN and SNN to simulate the state transition process of FSM. The output signal is a response signal generated by the DTSRNN model according to the input signal and the internal state transition logic.

[0148] In a possible implementation manner, the DTSRNN model includes an input layer, a hidden layer, and an output layer. The processing module is further configured to:

[0149] Convert the input signal into a pulse sequence through the input layer. The pulse sequence includes input vectors of multiple time steps;

[0150] In each time step, generate a state vector of the current time step through the neuron model of the hidden layer according to the input vector of the current time step and the state vector of the previous time step. The state vector is used to indicate the state transferred by the simulated FSM;

[0151] In each time step, determine an output vector of the current time step through the neuron model of the output layer according to the state vector of the current time step; integrate the output vectors of multiple time steps into an output signal for output.

[0152] In another possible implementation manner, the processing module is further configured to:

[0153] Generate a state vector of the current time step through the neuron model of the hidden layer according to the input vector of the current time step, the state vector of the previous time step, the membrane potential of the previous time step, a preset weight parameter, a time parameter, and a membrane potential threshold.

[0154] In another possible implementation manner, both the input signal and the output signal adopt a one-hot encoding form.

[0155] In another possible implementation manner, the input signal includes text data, and the output signal is used to indicate the classification result, recognition result, or prediction result of the DTSRNN model for the text data; or,

[0156] The input signal includes digital signals in a circuit, and the output signal includes a logic state output generated by the DTSRNN model according to the digital signals; or,

[0157] The input signal includes the control signal of the control system, and the output signal is used to indicate the control instruction generated by the DTSRNN model according to the control signal.

[0158] In another possible implementation, the input signal includes input vectors of multiple time steps, the output signal includes output vectors of multiple time steps, and the device further includes: a verification module, configured to:

[0159] For each time step, according to the input vector of the current time step, determine the correct state vector of the current time step through the linear expression relationship of the FSM. The linear expression relationship of the FSM is used to indicate multiplying the input vector of the current time step by the state transition matrix to obtain an intermediate matrix, and the state transition matrix is used to indicate all candidate state transition situations; multiply the state vector of the previous time step by the intermediate matrix to obtain the correct state vector of the current time step;

[0160] Compare the correct state vector of the current time step with the state vector of the current time step determined by the DTSRNN model to determine the verification result of the DTSRNN model, and the verification result is used to indicate the prediction accuracy of the DTSRNN model.

[0161] In another possible implementation, the device further includes: a training module, configured to:

[0162] Obtain a training sample set, where the training sample set includes multiple groups of sample data groups, and each group of sample data groups includes a sample input signal and a label output signal;

[0163] Train the original parameter model according to multiple groups of sample data groups by using the error backpropagation algorithm to obtain the DTSRNN model.

[0164] It should be noted that when the device provided in the above embodiments implements its functions, only the above-mentioned division of each functional module is used for illustration. In actual applications, the above functions can be allocated to different functional modules according to actual needs, that is, the content structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0165] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0166] An embodiment of the present disclosure further provides a computing device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the above method.

[0167] Embodiments of the present disclosure also provide a non - volatile computer - readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above - mentioned method are implemented.

[0168] Embodiments of the present disclosure also provide a computer program product, including a computer program, or a non - volatile computer - readable storage medium carrying the computer program. When the computer program is executed by a processor, the steps of the above - mentioned method are implemented.

[0169] A computer - readable storage medium can be a tangible device that can hold and store programs / instructions used by an instruction - execution device. A computer - readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples (non - exhaustive list) of the computer - readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read - only memory (ROM), an erasable programmable read - only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read - only memory (CD - ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punched card or raised structures in grooves storing instructions thereon, and any suitable combination of the above. The computer - readable storage medium used herein is not construed as an instantaneous signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through an optical fiber cable), or electrical signals transmitted through wires.

[0170] The computer programs (or computer - readable program instructions) described herein can be downloaded from a computer - readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter or network interface in each computing / processing device receives the computer - readable program instructions from the network and forwards the computer - readable program instructions for storage in the computer - readable storage medium in each computing / processing device.

[0171] A computer program (or computer program instructions) for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer-readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0172] Aspects of the present disclosure are described herein with reference to the flowchart and / or block diagram of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart and / or block diagram, and the combinations of blocks in the flowchart and / or block diagram, can be implemented by computer-readable program instructions.

[0173] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, thereby producing a machine such that when these instructions are executed by the processor of the computer or other programmable data processing apparatus, a device is produced that implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause a computer, a programmable data processing apparatus, and / or other devices to work in a specific manner. Thus, the computer-readable medium storing the instructions includes a manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0174] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0175] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified function or act, or by a combination of dedicated hardware and computer instructions.

[0176] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for simulating a finite state machine based on a spiking neural network, characterized in that The method includes: Obtaining an input signal; According to the input signal, outputting a corresponding output signal through a pre-trained discrete-time spiking recurrent neural network (DTSRNN) model. The DTSRNN model is a model that combines the characteristics of a discrete-time recurrent neural network (DTRNN) and a spiking neural network (SNN) to simulate the state transition process of a finite state machine (FSM). The output signal is a response signal generated by the DTSRNN model according to the input signal and internal state transition logic.

2. The method according to claim 1, characterized in that, The DTSRNN model includes an input layer, a hidden layer, and an output layer. The step of outputting a corresponding output signal through a pre-trained discrete-time spiking recurrent neural network (DTSRNN) model according to the input signal includes: Converting the input signal into a spike train through the input layer. The spike train includes input vectors of multiple time steps; In each time step, through the neuron model of the hidden layer, generating the state vector of the current time step according to the input vector of the current time step and the state vector of the previous time step. The state vector is used to indicate the state transferred by the simulated FSM; In each time step, through the neuron model of the output layer, determining the output vector of the current time step according to the state vector of the current time step; integrating the output vectors of multiple time steps into the output signal for output.

3. The method according to claim 2, wherein The step of generating the state vector of the current time step through the neuron model of the hidden layer according to the input vector of the current time step and the state vector of the previous time step includes: Generating the state vector of the current time step through the neuron model of the hidden layer according to the input vector of the current time step, the state vector of the previous time step, the membrane potential of the previous time step, a preset weight parameter, a time parameter, and a membrane potential threshold.

4. The method according to any one of claims 1 to 3, characterized in that, Both the input signal and the output signal adopt the one-hot encoding form.

5. The method according to any one of claims 1 to 3, wherein The input signal includes text data, and the output signal is used to indicate the classification result, recognition result, or prediction result of the DTSRNN model for the text data; or The input signal includes digital signals in a circuit, and the output signal includes the logical state output generated by the DTSRNN model according to the digital signals; or The input signal includes control signals of a control system, and the output signal is used to indicate the control instruction generated by the DTSRNN model according to the control signals.

6. The method according to any one of claims 1 to 3, characterized in that The input signal includes input vectors of multiple time steps, and the output signal includes output vectors of multiple time steps. The method further includes: For each time step, according to the input vector of the current time step, the correct state vector of the current time step is determined through the linear expression relationship of the FSM. The linear expression relationship of the FSM is used to indicate that the input vector of the current time step is multiplied by the state transition matrix to obtain an intermediate matrix, and the state transition matrix is used to indicate all candidate state transition situations; multiply the state vector of the previous time step by the intermediate matrix to obtain the correct state vector of the current time step; Compare the correct state vector of the current time step with the state vector of the current time step determined by the DTSRNN model to determine the verification result of the DTSRNN model, and the verification result is used to indicate the prediction accuracy of the DTSRNN model.

7. The method according to any one of claims 1 to 3, characterized in that, Before the output of the corresponding output signal through the pre-trained discrete-time spiking recurrent neural network DTSRNN model according to the input signal, it further includes: Obtain a training sample set, where the training sample set includes multiple groups of sample data groups, and each group of the sample data groups includes a sample input signal and a label output signal; According to multiple groups of the sample data groups, use the error backpropagation algorithm to train the original parameter model to obtain the DTSRNN model.

8. An apparatus for simulating a finite state machine based on a spiking neural network, characterized in that, The device includes: An acquisition module for acquiring an input signal; A processing module for outputting a corresponding output signal through the pre-trained DTSRNN model according to the input signal. The DTSRNN model is a model that combines the characteristics of DTRNN and SNN to simulate the state transition process of the FSM, and the output signal is a response signal generated by the DTSRNN model according to the input signal and the internal state transition logic.

9. A computing device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 7.

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