Display device

Abstract

The display device is configured to be driven in units of frames, and includes a pixel driving circuit electrically connected to a light emitting diode. The pixel driving circuit includes a first transistor and a second transistor. The first transistor includes a second electrode electrically connected to the light emitting diode and a gate electrode electrically connected to the second node. The second transistor includes a first electrode configured to receive a data signal and a gate electrode configured to receive a second scan signal. The frames include a first frame and a second frame, the data signals include a first data signal provided in the first frame and a second data signal provided in the second frame, and the second scan signals provided in the first frame and the second frame may have different waveforms.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0001098, filed on January 3, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments described herein relate to a display device and a method of driving the display device. Background Art

[0004] A display device may be composed of various electronic components such as an electronic module, a display panel configured to display an image, and an input sensor configured to sense an external input. These electronic components may be electrically connected to each other through signal lines arranged in various ways. The display panel includes a plurality of pixels. Each of the plurality of pixels includes a light - emitting element configured to emit light and a pixel driving circuit configured to control the amount of current flowing into the light - emitting element. Summary of the Invention

[0005] One or more embodiments described herein provide a display device having improved display quality.

[0006] One or more embodiments described herein provide a display device having reduced power consumption.

[0007] One or more embodiments described herein may provide a display device that reduces or prevents an afterimage effect.

[0008] One or more embodiments described herein may provide a display device suitable for a high - speed driving environment.

[0009] Embodiments of the inventive concept provide a display device including: a display panel configured to be driven in units of frames and including pixels, the pixels including a pixel driving circuit and a light - emitting diode electrically connected to the pixel driving circuit, wherein the pixel driving circuit includes: a first transistor including a first electrode configured to receive a first driving voltage and electrically connected to a first node, a second electrode electrically connected to the light - emitting diode, and a gate electrode electrically connected to a second node; and a second transistor including a first electrode configured to receive a data signal, a second electrode electrically connected to the first node, and a gate electrode configured to receive a second scan signal, wherein a frame includes consecutive first and second frames, the data signal includes a first data signal and a second data signal different from the first data signal, and when the first data signal is provided in the first frame and the second data signal is provided in the second frame, the second scan signal provided in the first frame has a waveform different from the waveform of the second scan signal provided in the second frame.

[0010] In an embodiment, the second data signal may have a voltage level higher than that of the first data signal.

[0011] In an embodiment, the second scan signal provided in the first frame may have a first pulse width, and the second scan signal provided in the second frame may have a second pulse width different from the first pulse width.

[0012] In an embodiment, the second pulse width may be less than the first pulse width.

[0013] In an embodiment, the light-emitting diode is configured to emit light having a first gray value in the first frame, and the light-emitting diode is configured to emit light having a second gray value higher than the first gray value in the second frame.

[0014] In an embodiment, the second scan signal provided in the first frame may have a first amplitude, and the second scan signal provided in the second frame may have a second amplitude different from the first amplitude.

[0015] In an embodiment, the first amplitude may be greater than the second amplitude.

[0016] In an embodiment, the display device may further include: a driving capacitor connected between the first voltage line and the second node, and a first driving voltage is provided through the first voltage line.

[0017] In an embodiment, the display device may further include: a third transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the second node, and a gate electrode configured to receive the second scan signal.

[0018] In an embodiment, the display device may further include: a fourth transistor including a first electrode electrically connected to the second node, a second electrode configured to receive an initialization voltage, and a gate electrode configured to receive a first scan signal different from the second scan signal.

[0019] In an embodiment, the display device may further include: a fifth transistor including a first electrode configured to receive the first driving voltage, a second electrode electrically connected to the first node, and a gate electrode configured to receive an emission signal.

[0020] In an embodiment, the display device may further include: a sixth transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the light-emitting diode, and a gate electrode configured to receive an emission signal.

[0021] In an embodiment, the display device may further include a seventh transistor including a first electrode electrically connected to a first electrode of a light-emitting diode, a second electrode configured to receive an initialization voltage, and a gate electrode configured to receive a second scan signal.

[0022] In an embodiment of the inventive concept, a display device includes a display panel configured to be driven in units of frames and including pixels, where each pixel includes a pixel driving circuit and a light-emitting diode electrically connected to the pixel driving circuit. The pixel driving circuit may include a first transistor including a first electrode configured to receive a first driving voltage and electrically connected to a first node, a second electrode electrically connected to the light-emitting diode, and a gate electrode electrically connected to a second node; and a second transistor including a first electrode configured to receive a data signal, a second electrode electrically connected to the first node, and a gate electrode configured to receive a second scan signal. A frame includes consecutive first and second frames, the data signal includes a first data signal and a second data signal different from the first data signal, and when the first data signal is provided in the first frame and the second data signal is provided in the second frame, a pulse width of the second scan signal provided in the first frame is different from a pulse width of the second scan signal provided in the second frame.

[0023] In an embodiment, the light-emitting diode is configured to emit light having a first gray value in the first frame, and the light-emitting diode is configured to emit light having a second gray value higher than the first gray value in the second frame.

[0024] In an embodiment, the second data signal may have a voltage level higher than a voltage level of the first data signal.

[0025] In an embodiment, the second scan signal provided in the first frame may have a first pulse width, and the second scan signal provided in the second frame may have a second pulse width less than the first pulse width.

[0026] In an embodiment, the display device may further include a third transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the second node, and a gate electrode configured to receive the second scan signal.

[0027] In an embodiment, the display device may further include a fourth transistor including a first electrode electrically connected to the second node, a second electrode configured to receive an initialization voltage, and a gate electrode configured to receive a first scan signal different from the second scan signal.

[0028] In an embodiment, the display device may further include a fifth transistor including a first electrode configured to receive a first driving voltage, a second electrode electrically connected to the first node, and a gate electrode configured to receive an emission signal.

[0029] According to one or more additional embodiments, a method for controlling the operation of a display device is provided. The display device includes pixels, and each pixel includes a pixel driving circuit electrically connected to a light-emitting diode. The pixel driving circuit includes a driving transistor and a compensation transistor that is controlled by a scanning signal to place the driving transistor in a diode-connected state.

[0030] The method may include: charging a node coupled to the gate of the driving transistor based on the voltage of a first data signal applied in a first frame, and charging the node to a first target voltage based on a first parameter of the scanning signal; controlling light emission from the light-emitting diode of the pixel based on the first target voltage; determining a difference between the voltage of a second data signal and the voltage of the first data signal; determining a second parameter of the scanning signal based on the difference between the voltage of the second data signal and the voltage of the first data signal; in a second frame, charging the node coupled to the gate of the driving transistor based on the voltage of the second data signal, and charging the node to a second target voltage based on the second parameter of the scanning signal; and controlling light emission from the light-emitting diode of the pixel based on the second target voltage.

[0031] The first parameter may be a first pulse width of the scanning signal, the second parameter may be a second pulse width of the scanning signal, and the second pulse width may be less than the first pulse width. The first parameter may be a first amplitude of the scanning signal, the second parameter may be a second amplitude of the scanning signal, and the second amplitude may be less than the first amplitude. The first data signal may correspond to a first gray level value, the second data signal may correspond to a second gray level value, and the second gray level value may be greater than the first gray level value. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0033] Figure 1 is a perspective view of a display device according to an embodiment of the inventive concept;

[0034] Figure 2 is a block diagram of a display device according to an embodiment of the inventive concept;

[0035] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept;

[0036] Figure 4 is a view for describing a frame according to an embodiment of the present disclosure;

[0037] Figure 5is a timing diagram for describing the operation of a display device in the (n-1)-th frame according to an embodiment of the inventive concept;

[0038] Figure 6 is a timing diagram for describing the voltage of a second node according to a second scan signal in the (n-1)-th frame according to an embodiment of the inventive concept;

[0039] Figure 7 is a timing diagram for describing the operation of a display device in the n-th frame according to an embodiment of the inventive concept;

[0040] Figure 8 is a timing diagram for describing the voltage of a second node according to a second scan signal in the n-th frame according to an embodiment of the inventive concept;

[0041] Figure 9 is a timing diagram for describing the operation of a display device in the n-th frame according to an embodiment of the inventive concept; and

[0042] Figure 10 is a timing diagram for describing the voltage of a second node according to a second scan signal in the n-th frame according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0043] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element, or intervening third elements may be present. The term "and / or" includes any and all combinations of one or more of the associated items.

[0044] Terms such as "first" and "second" may be used to describe various components, but these components should not be limited by these terms. Such terms are only used to distinguish one element from other elements. For example, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component, without departing from the scope of the present disclosure. Unless the context clearly dictates otherwise, singular expressions include plural expressions.

[0045] It should be understood that the terms "comprising" or "having" are intended to indicate the presence of the features, wholes, steps, operations, elements, components, or combinations thereof stated in the present disclosure, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, or combinations thereof.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. Additionally, it will be further understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view of a display device 1000 according to an embodiment of the inventive concept.

[0049] Reference Figure 1 , the display device 1000 may be activated according to an electrical signal. The display device 1000 may include various embodiments. For example, the display device 1000 may be used for small and medium-sized display devices such as desktop computers, laptop computers, personal digital assistants (PDAs), vehicle navigation units, gaming machines, or cameras. In other embodiments, the display device 1000 may be used for large display devices such as televisions, monitors, or outdoor billboards. Additionally, the above-described content is presented only as an example and may also be used for other electronic devices without departing from the scope of the inventive concept. In an embodiment, the exemplary display device 1000 is shown as a smart phone.

[0050] The display device 1000 may include a display surface 1000-F parallel to a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The display surface 1000-F may include a transmissive region 1000-T and a border region 1000-B.

[0051] An image 1000-I may be displayed in the transmissive region 1000-T toward a third direction DR3. The third direction DR3 may be referred to as a thickness direction. The image 1000-I may be a still image or a moving image. In Figure 1 , examples of the image 1000-I are given in the form of a clock window and icons. The display surface 1000-F on which the image 1000-I is displayed may correspond to the front surface of the display device 1000.

[0052] In an embodiment, the front surface (or top surface) and the back surface (or bottom surface) of the display device 1000 may be based on the direction of the display image 1000-I. The front surface and the back surface may face each other in a third direction DR3, and the normal directions of the front surface and the back surface may be parallel to the third direction DR3. In the specification, the expression "when viewed in a plan view" may mean when viewed from the third direction DR3. The image 1000-I may not be displayed in the bezel area 1000-B.

[0053] Figure 2 is a block diagram of a display device 1000 according to an embodiment of the inventive concept.

[0054] Referring to Figure 2 , the display device 1000 includes a display panel DP, a driving controller 100, a data driving circuit 200, and a voltage generator 300. The display panel DP may include a plurality of pixels PX.

[0055] The driving controller 100 receives image information RGB and a control signal CTRL from a host or other external source. The driving controller 100 generates image data DATA by converting the data format of the image information RGB to meet the interface specification with the data driving circuit 200. The driving controller 100 outputs a scan control signal SCS, a data control signal DCS, and a transmission control signal ECS.

[0056] The data driving circuit 200 receives the data control signal DCS and the image data DATA from the driving controller 100. The data driving circuit 200 converts the image data DATA into a data signal and outputs the data signal to corresponding pixels PX among the plurality of pixels PX through a plurality of data lines DL1 to DLm, which will be described in more detail below. The data signal is an analog voltage corresponding to the gray value of the image data DATA.

[0057] The voltage generator 300 generates voltages for operating the display panel DP. In an embodiment, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0058] The display panel DP includes scan lines GIL1 to GILn and GWL1 to GWLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and a plurality of pixels PX. The scan lines GIL1 to GILn and GWL1 to GWLn may include a first set of scan lines GIL1 to GILn and a second set of scan lines GWL1 to GWLn. The display panel DP may further include a scan driving circuit SD and an emission driving circuit EDC. In an embodiment, the scan driving circuit SD is disposed on a first side of the display panel DP. The scan lines GIL1 to GILn and GWL1 to GWLn extend from the scan driving circuit SD in a first direction DR1 and may be arranged in an alternating relationship in a second direction DR2.

[0059] The display panel DP may include a display area DA corresponding to the transmissive area 1000-T and a non-display area NDA corresponding to a border area 1000-B (e.g., see Figure 1 ). A plurality of pixels PX may be disposed in the display area DA, and the scan driving circuit SD and the emission driving circuit EDC may be disposed in the non-display area NDA, which may, for example, overlap partially or entirely with the border area 1000-B.

[0060] The emission driving circuit EDC is disposed on a second side of the display panel DP. The emission control lines EML1 to EMLn extend from the emission driving circuit EDC in a direction opposite to the first direction DR1.

[0061] The first scan lines GIL1 to GILn, the second scan lines GWL1 to GWLn, and the emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from a data driving circuit 200 in a direction opposite to the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0062] In Figure 2 the example shown, the scan driving circuit SD and the emission driving circuit EDC are arranged to face each other, and the pixels PX are inserted between the scan driving circuit SD and the emission driving circuit EDC, but the inventive concept is not limited thereto. For example, the scan driving circuit SD and the emission driving circuit EDC may be arranged adjacent to each other on either the first side or the second side of the display panel DP. In an embodiment, the scan driving circuit SD and the emission driving circuit EDC may be incorporated into one integrated circuit.

[0063] A plurality of pixels PX are electrically connected to first scan lines GIL1 to GILn, second scan lines GWL1 to GWLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm. Each of the plurality of pixels PX can be electrically connected to two scan lines and one emission control line. For example, as Figure 2 shown, the pixels PX in the first row can be connected to the first first scan line GIL1, the first second scan line GWL1, and the first emission control line EML1. Additionally, the pixels PX in the j-th row can be connected to the j-th first scan line GILj, the j-th second scan line GWLj, and the j-th emission control line EMLj. This connection of the scan lines and the emission control lines depends on the specific structure of each pixel driving circuit (e.g., the number and arrangement of transistors), and thus, can be different between embodiments.

[0064] In one embodiment, each of the second scan lines GWL1 to GWLn can be connected to at least one transistor among the plurality of transistors included in one pixel PX. For example, the j-th second scan line GWLj can be connected to the gate electrodes of the second transistor T2 (e.g., see Figure 3 ), the third transistor T3 (e.g., see Figure 3 ), and the seventh transistor T7 (e.g., see Figure 3 ).

[0065] Each of the emission control lines EML1 to EMLn can be connected to at least one transistor among the plurality of transistors included in one pixel PX. For example, the j-th emission control line EMLj can be connected to the gate electrodes of the fifth transistor T5 (e.g., see Figure 3 ) and the sixth transistor T6 (e.g., see Figure 3 ).

[0066] Each of the plurality of pixels PX includes a light-emitting diode ED and a pixel driving circuit PXC configured to control light emission from the light-emitting diode ED (e.g., see Figure 3 ). The pixel driving circuit PXC can include one or more transistors and one or more capacitors. The scan driving circuit SD and the emission driving circuit EDC can include transistors provided by the same process as the pixel driving circuit PXC.

[0067] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT from a voltage generator 300.

[0068] The scan driving circuit SD receives a scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit SD may output scan signals to the first scan lines GIL1 to GILn and the second scan lines GWL1 to GWLn. Operations related to the second scan lines GWL1 to GWLn will be described in detail below.

[0069] Figure 3 is an equivalent circuit diagram of the pixel PXij, which may represent the circuit structure of each of the plurality of pixels PX according to an embodiment of the inventive concept. In Figure 3 the example equivalent circuit diagram of, the pixel PXij is connected to Figure 2 the i-th data line DLi among the data lines DL1 to DLm shown in, the j-th first scan line GILj among the first scan lines GIL1 to GILn, the j-th second scan line GWLj among the second scan lines GWL1 to GWLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0070] Figure 2 Each of the plurality of pixels PX shown in may have the same circuit structure as the equivalent circuit diagram of the pixel PXij shown in Figure 3 In this example, the pixel driving circuit PXC of the pixel PXij may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7. Each of the first to seventh transistors T1 to T7 may be a P-type transistor having an oxide semiconductor as a semiconductor layer. The activation level of the P-type transistor may be a low-level voltage, and the non-activation level of the P-type transistor may be a high-level voltage. The circuit structure of the pixel PX according to an embodiment of the inventive concept is not limited to Figure 3 . Figure 3 The pixel driving circuit PXC shown in is only an example, and in other embodiments, the structure of the pixel driving circuit PXC may be different.

[0071] More specifically, referring to Figure 3 , the pixel PXij of the display device according to an embodiment includes first to seventh transistors T1 to T7, a driving capacitor Cst, and at least one light-emitting diode ED. In this embodiment, an example in which one pixel PXij includes one light-emitting diode ED will be described.

[0072] The j-th first scan line GILj may transmit a first scan signal GI j, and the j-th second scan line GWLj may transmit a second scan signal GWj. The j-th emission control line EMLj may transmit an emission signal EMj, and the i-th data line DLi may transmit a data signal Di. The data signal Di may have the same as that input to the display device 1000 (for example, seeFigure 2 ) corresponding voltage levels of the RGB image information. The first to third voltage lines VL1, VL2, and VL3 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT, respectively.

[0073] The first transistor T1 can be a driving transistor electrically connected between the first voltage line VL1 and the light-emitting diode ED. The first transistor T1 includes a first electrode electrically connected to the first voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via the sixth transistor T6, and a gate electrode connected to one end of the driving capacitor Cst. The first electrode can be connected to the first node ND1, and the gate electrode can be connected to the second node ND2. The first electrode of the first transistor T1 can receive the first driving voltage ELVDD through the first voltage line VL1 (when the fifth transistor T5 is activated). As described, the first transistor T1 can be referred to as a driving transistor.

[0074] The second transistor T2 is electrically connected between the i-th data line DLi and the first node ND1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first node ND1, and a gate electrode connected to the j-th second scan line GWLj. The first electrode of the second transistor T2 can receive the data signal Di through the i-th data line DLi. The gate electrode of the second transistor T2 can receive the second scan signal GWj through the j-th second scan line GWLj. The second transistor T2 can be turned on according to the second scan signal GWj to transmit the data signal Di to the first node ND1. Thus, the data signal Di can be transmitted to the first transistor T1.

[0075] The third transistor T3 can be a compensation transistor electrically connected between the second node ND2 and the second electrode of the first transistor T1. The third transistor T3 includes a first electrode connected to the first voltage line VL1 through the driving capacitor Cst, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the j-th second scan line GWLj. The first electrode of the third transistor T3 can be connected to the second node ND2. The gate electrode of the third transistor T3 can receive the second scan signal GWj through the j-th second scan line GWLj. The third transistor T3 can be turned on according to the second scan signal GWj to connect the gate electrode of the first transistor T1 and the second electrode of the first transistor T1, thereby placing the first transistor T1 in a diode-connected state. The third transistor T3 can be referred to as a compensation transistor.

[0076] The fourth transistor T4 may be connected between the second node ND2 and the third voltage line VL3. The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third voltage line VL3, and a gate electrode connected to the gate electrode of the j-th first scan line GILj. The first electrode of the fourth transistor T4 may be connected to the second node ND2. The second electrode of the fourth transistor T4 may receive the initialization voltage VINT through the third voltage line VL3. The gate electrode of the fourth transistor T4 may receive the first scan signal GIj through the j-th first scan line GILj. The first scan signal GIj may be different from the second scan signal GWj in terms of timing (as described, for example, with reference to Figure 5 ). The fourth transistor T4 is turned on according to the first scan signal GIj to transmit the initialization voltage VINT to the gate electrode of the first transistor T1 and perform an initialization operation for initializing the voltage of the gate electrode of the first transistor T1.

[0077] The fifth transistor T5 may be connected between the first voltage line VL1 and the first node ND1. The fifth transistor T5 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th emission control line EMLj. When connected in this way, the second electrode of the fifth transistor T5 may be connected to the first node ND1. The first electrode of the fifth transistor T5 may receive the first driving voltage ELVDD through the first voltage line VL1. The gate electrode of the fifth transistor T5 may receive the emission signal EMj through the j-th emission control line EMLj.

[0078] The sixth transistor T6 may be electrically connected between the first transistor T1 and the light-emitting diode ED. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the j-th emission control line EMLj. The gate electrode of the sixth transistor T6 may receive the emission signal EMj through the j-th emission control line EMLj.

[0079] The fifth transistor T5 and the sixth transistor T6 may be turned on substantially simultaneously according to the emission signal EMj. Accordingly, a current path may be provided between the first voltage line VL1 and the light-emitting diode ED. The current flowing through this current path may be a driving current Id for causing the light-emitting diode ED to emit light in proportion to the voltage of the data signal Di. The driving current Id may include a first driving current Id1 and a second driving current Id2 provided in different frames. For example, the first driving current Id1 may flow in the (n - 1)-th frame FRn-1 (see Figure 5 ), and the second driving current Id2 may flow in the n-th frame FRn (see Figure 7 ).

[0080] The seventh transistor T7 may be electrically connected between the light emitting diode ED and the third voltage line VL3. The seventh transistor T7 includes a first electrode connected to the anode of the light emitting diode ED, a second electrode connected to the third voltage line VL3, and a gate electrode connected to the j-th second scan line GWLj. The second electrode of the seventh transistor T7 may receive an initialization voltage VINT through the third voltage line VL3. The gate electrode of the seventh transistor T7 may receive a second scan signal GWj through the j-th second scan line GWLj. Therefore, the second transistor T2, the third transistor T3, and the seventh transistor T7 may be activated substantially simultaneously. The seventh transistor T7 is turned on according to the second scan signal GWj to bypass the residual current of the anode of the light emitting diode ED to the third voltage line VL3.

[0081] As described above, one end of the driving capacitor Cst may be connected to the gate electrode of the first transistor T1 through the second node ND2 , and the other end may be connected to the first voltage line VL1 .

[0082] The cathode of the light emitting diode ED may be connected to a second voltage line VL2 configured to transmit the second driving voltage ELVSS. The structure of the pixel PXij according to the embodiment is not limited to Figure 3 The structure shown in FIG. 1 and in other embodiments, the number of transistors and / or capacitors included in one pixel and their connection relationship may be different.

[0083] Figure 4 is a view for explaining a frame FR according to an embodiment of the present disclosure.

[0084] refer to Figure 4 , the display panel DP may be driven in units of one frame FR (for example, see Figure 2 ) to display image 1000-I (see, for example, Figure 1 In one embodiment, a plurality of frames FR may be provided. For example, the plurality of frames FR may include an n-2th frame FRn-2, an n-1th frame FRn-1, an nth frame FRn, and an n+1th frame FRn+1.

[0085] Before the specified time point t, the display panel DP (see Figure 2 ) can be based on the data signal Di having a relatively low voltage level (see Figure 3 ) and display the same as image 1000-I (see Figure 1 ) corresponding to the light. For example, in the n-2th frame FRn-2 and the n-1th frame FRn-1, the display panel DP (see Figure 2 ) can display a black image.

[0086] After a predetermined time point t, pixels PXij of a display panel DP (see Figure 2 ) can display light corresponding to an image 1000 - I (see Figure 3 ) based on a data signal Di having a relatively high voltage level. For example, in an nth frame FRn and an (n + 1)th frame FRn+1, pixels PXij of the display panel DP (see Figure 1 ) can display a white image. Figure 2

[0087] Figure 5 Figure 6 is a timing diagram for describing an operation of a display device in an (n - 1)th frame FRn-1 according to an embodiment of the inventive concept. is a timing diagram for describing a voltage level of a second node ND2 according to a second scan signal GWj in an (n - 1)th frame according to an embodiment of the inventive concept.

[0088] Figures 3 to 6 Referring to , the (n - 1)th frame FRn-1 may include first through fifth time periods t1, t2, t3, t4, and t5. The first through fourth time periods t1 through t4 may be referred to as non-emission time periods. The fifth time period t5 may be referred to as an emission time period. Specifically, the first time period t1 may be referred to as an initialization time period. The second time period t2 may be referred to as a first holding time period. The third time period t3 may be referred to as a compensation time period or a data writing time period. The fourth time period t4 may be referred to as a second holding time period.

[0089] In the first time period t1, a first scan signal GIj may be at an active level. The active level of the first scan signal GIj may be a low level. However, this is merely an example, and the active level of a signal according to an embodiment is not limited thereto. For example, for an NMOS implementation of a fourth transistor T4, the active level of the signal may be a high level.

[0090] In the first time period t1, a second scan signal GWj and an emission signal EMj may be at a non-active level. The non-active level of the second scan signal GWj and the emission signal EMj may be a high level. However, this is merely an example, and the non-active level of a signal according to an embodiment is not limited thereto. For example, for an NMOS implementation, the non-active level of the signal may be a low level.

[0091] The data signal Di may have a predetermined voltage level. The data signal Di may include a first data signal DATA1. In the third time period t3, the data signal Di may be the first data signal DATA1.

[0092] ​In operation, the fourth transistor T4 may be turned on in response to a first scan signal GIj having an active level. In this case, an initialization voltage VINT may be supplied to the second node ND2. In other words, the gate electrode of the first transistor T1 may be charged with the initialization voltage VINT. Here, any residual current that may be present in the gate electrode of the first transistor T1 may be removed.

[0093] A second (or first holding) period t2 may be consecutive to the first period t1. During the second period t2, the first scan signal GIj, the second scan signal GWj, and the emission signal EMj may be at inactive levels. The inactive level of the first scan signal GIj may be a high level.

[0094] A third (or compensation or data writing) period t3 may be consecutive to the second period t2. During the third period t3, the second scan signal GWj may be at an active level, and the first scan signal GIj and the emission signal EMj may be at inactive levels. The active level of the second scan signal GWj may be a low level.

[0095] The target voltage may be determined according to the voltage level of the data signal Di. The second node ND2 is charged to the target voltage to drive the first transistor T1. The target voltage may include a first target voltage TGV1 (for example, see Figure 6 ). When the data signal Di is the first data signal DATA1, the target voltage of the second node ND2 may be referred to as the first target voltage TGV1. The process of charging the second node ND2 to the first target voltage TGV1 will be described below.

[0096] The second transistor T2 and the third transistor T3 may be turned on in response to a second scan signal GWj having an active level. The second scan signal GWj may have a waveform having a first pulse width WD1 and a first amplitude AMP1 in the (n - 1)th frame FRn - 1. (As will be discussed in more detail below, the waveform of the second scan signal GWj in the frame FRn may be controlled to be different from the waveform of the second scan signal GWj in the (n - 1)th frame FRn - 1 to provide improved performance. The difference in the waveforms may be manifested as different pulse widths and / or different amplitudes of the second scan signal GWj.)

[0097] When the second transistor T2 is turned on, the first data signal DATA1 can be supplied to the first node ND1 through the i-th data line DLi. Subsequently, when the third transistor T3 is turned on, the first transistor T1 is diode-connected and forward-biased. When the data signal Di is the first data signal DATA1, the first target voltage TGV1 obtained by reducing the threshold voltage (Vth) of the first transistor T1 from the first data signal DATA1 is applied to the gate electrode of the first transistor T1. In other words, the voltage at the second node ND2 can increase to the first target voltage TGV1 during the third period t3.

[0098] The first driving voltage ELVDD and the first target voltage TGV1 can be applied to the corresponding ends of the driving capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in the driving capacitor Cst.

[0099] Meanwhile, the seventh transistor T7 can also be turned on in response to the second scan signal GWj having an active level. When the seventh transistor T7 is turned on, any remaining current that may exist on the anode of the light-emitting diode ED can be removed, for example, by bypassing it to the third voltage line VL3.

[0100] The fourth (or second holding) period t4 can be consecutive to the third period t3. In the fourth period t4, the first scan signal GIj, the second scan signal GWj, and the emission signal EMj can be at non-active levels.

[0101] The fifth (or emission) period t5 can be consecutive to the fourth period t4. In the fifth period t5, the emission signal EMj can be at an active level, and the first scan signal GIj and the second scan signal GWj can be at non-active levels. The active level of the emission signal EMj can be a low level.

[0102] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to the emission signal EMj having an active level. Accordingly, the first driving current Id1 can flow from the first voltage line VL1 through the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light-emitting diode ED, and the second voltage line VL2. When the first driving current Id1 flows through the light-emitting diode ED, the pixel PXij emits light corresponding to the voltage level of the first data signal DATA1. The pixel PXij can emit light with the first gray value in the (n - 1)-th frame FRn-1. In other words, the display panel DP (see Figure 2 ) can have the first gray value in the (n - 1)-th frame FRn-1. For example, the first gray value can be gray value 0, and the image 1000-I (see Figure 1 ) can be represented as black.

[0103] Figure 7 is a timing diagram for describing the operation of a display device in the n-th frame FRn according to an embodiment of the inventive concept. Figure 8 is a timing diagram for describing the voltage at a second node ND2 according to a second scan signal GWj in the n-th frame according to an embodiment of the inventive concept. In Figures 7 to 8 the description, the same reference numerals are assigned to the components described with reference to Figure 5 and Figure 6 and their description will be omitted.

[0104] Referring to Figures 3 to 8 , the n-th frame FRn may refer to the frame provided immediately after a predetermined time point t, as shown in Figure 4 . The display panel DP (see Figure 2 ) may display a white image from a black image based on the predetermined time point t. Here, the voltage difference between the data signals provided from the black image and the white image may increase.

[0105] The n-th frame FRn may include a first period to a fifth period t1, t2, t3-1, t4, and t5. The n-th frame FRn may be consecutive to the (n-1)-th frame FRn-1.

[0106] The data signal Di may have a predetermined voltage level. The data signal Di may further include a second data signal DATA2. The data signal Di may be the second data signal DATA2 in the third period t3-1.

[0107] The third period t3-1 may be consecutive to the second period t2. The second scan signal GWj may be at an active level in at least a part of the third period t3-1. In the third period t3-1, the first scan signal GIj and the emission signal EMj may be at an inactive level.

[0108] The memory of the driving controller 100 (see Figure 2 ) may include a pulse width look-up table, in which a target voltage is set for each voltage difference between a first data signal DATA1 and a second data signal DATA2 provided to the i-th data line DLi (see Figure 3 ) during the (n-1)-th frame FRn-1 and the n-th frame FRn, and the pulse width of the second scan signal GWj for each target voltage is stored. (In another embodiment, the driving controller 100 may include an amplitude look-up table, which will be used in a manner described in more detail below).

[0109] The second node ND2 may be charged to the target voltage to drive the first transistor T1. When the data signal Di is the second data signal DATA2, the target voltage of the second node ND2 may be referred to as a second target voltage TGV2.

[0110] The pulse width of the second scan signal GWj can be controlled based on a pulse width look-up table. The pixel driving circuit PXC can charge the second node ND2 to a second target voltage TGV2 in response to the second scan signal GWj whose pulse width is controlled. The process of charging the second node ND2 to the second target voltage TGV2 will be described below.

[0111] The second transistor T2 and the third transistor T3 can be turned on in response to the second scan signal GWj having an active level. The second scan signal GWj provided in the nth frame FRn can have a waveform different from the waveform of the second scan signal GWj provided in the (n - 1)th frame FRn-1. The different waveform for the nth frame FRn can have one or more parameters (e.g., pulse width, amplitude, etc.) different from one or more parameters (e.g., pulse width, amplitude, etc.) of the waveform of the second scan signal GWj provided in the (n - 1)th frame FRn-1. For example, the second scan signal GWj provided in the nth frame FRn can have a waveform having an active level during the duration of a second pulse width WD2. The second pulse width WD2 can be different from the first pulse width WD1. For example, the second pulse width WD2 can be less than the first pulse width WD1. Accordingly, the second data signal DATA2 can be provided to the second node ND2 for a time length corresponding to the second pulse width WD2. In other embodiments, as discussed below, the second scan signal GWj can have a different pulse width whose pulse width is greater than the second pulse width WD2.

[0112] When the second transistor T2 is turned on, the second data signal DATA2 can be provided to the first node ND1 through the ith data line DLi. The second data signal DATA2 can be different from the first data signal DATA1. For example, the second data signal DATA2 can have a voltage level higher than the voltage level of the first data signal DATA1. The second scan signal GWj provided in the (n - 1)th frame FRn-1 when the first data signal DATA1 is provided can have a waveform different from the waveform of the second scan signal GWj provided in the nth frame FRn when the second data signal DATA2 is provided (e.g., different pulse widths and / or different amplitudes).

[0113] When the third transistor T3 is turned on, the first transistor T1 is diode-connected and forward-biased. When the data signal Di is the second data signal DATA2, the second target voltage TGV2 after reducing the threshold voltage (Vth) of the first transistor T1 from the second data signal DATA2 is applied to the gate electrode of the first transistor T1. In other words, the voltage at the second node ND2 can reach (be charged to) the second target voltage TGV2.

[0114] The first driving voltage ELVDD and the second target voltage TGV2 can be applied to both ends of the driving capacitor Cst, and charges corresponding to the voltage difference between the two ends can be stored in the driving capacitor Cst.

[0115] In the fifth period t5, the fifth transistor T5 and the sixth transistor T6 can be turned on in response to the emission signal EMj. Accordingly, the second driving current Id2 can flow from the first voltage line VL1 through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting diode ED, and then flow to the second voltage line VL2. When the second driving current Id2 flows through the light-emitting diode ED, the pixel PXij emits light corresponding to the voltage level of the second data signal DATA2. The pixel PXij can emit light with a second gray value in the nth frame FRn. The second gray value can be greater than the first gray value. For example, the display panel DP (e.g., see Figure 2 ) can have a second gray value in the nth frame FRn. For example, the second gray value can be the gray value 127 that appears as white.

[0116] The second driving current Id2 can be determined based on Equations 1 to 3 provided below.

[0117]

[0118] Vgs = ELVDD - (Vdata2 - Vth)…(2)

[0119]

[0120] In Equations 1 to 3, μ can be the field mobility, Cox can be the capacitance of the gate insulating film, W / L can be the width of the first transistor T1 divided by the length, and Vgs can be the gate-source voltage of the first transistor T1. Vdata2 can be the voltage level of the second data signal DATA2 transmitted through the second transistor T2 and is applied for a duration as long as the time corresponding to the second pulse width WD2. In one embodiment, μ and Cox can be constants. The expression (Vdata2 - Vth) can be the second target voltage TGV2 as shown, for example, in Figure 8 , that is, the charge amount of the second node ND2. This can be verified in Equation 3, which shows that as the charge amount of the second node ND2 decreases, the second driving current Id2 increases.

[0121] In Equations 1 to 3, a description is provided based on the second driving current Id2. When the data signal Di is the first data signal DATA1, in Equations 1 to 3, Vdata2 is changed to the voltage level of the first data signal DATA1, and the first driving current Id1 can be determined based on Equations 1 to 3.

[0122] In addition, the threshold voltage (Vth) of the first transistor T1 included in each of the pixels PX may vary according to the characteristics of the first transistor T1. However, according to the inventive concept, through the operation of the transistors in the first to fourth time periods t1, t2, t3-1, and t4, the threshold voltage (Vth) of the first transistor T1 may not affect the driving current Id flowing through the light-emitting diode ED. Referring to Equation 3, in the fifth time period t5, the driving current Id flowing through the light-emitting diode ED may not be affected by the threshold voltage (Vth) of the first transistor T1. Accordingly, the image 1000-I (see Figure 2 ) can be uniformly maintained in brightness on the display panel DP (see Figure 1 ). Accordingly, pixels PX and a display device 1000 (see Figure 1 ) having improved display quality can be provided.

[0123] In some display devices, the display panel DP may display a black image in frames FRn-2 and FRn-1 before a specified time point t. In this case, when the display panel DP displays a white image in frames FRn and FRn+1 after the specified time point t, due to the hysteresis characteristic of the first transistor T1, a step efficiency (where the gray level of the display panel DP becomes lower than the desired gray level and / or brightness) may occur in the nth frame FRn, which is the first frame after the specified time point t. In this case, when the black image changes to a white image, the user may see an afterimage due to the decrease in brightness in the nth frame FRn. However, according to the inventive concept, in order to charge the second node ND2 only to the second target voltage TGV2, the pixel driving circuit PXC may receive a second scan signal GWj having a second pulse width WD2. Accordingly, the display panel DP (see Figure 2 ) can obtain the desired second gray value in the nth frame FRn. In addition, the afterimage can be reduced or removed. Accordingly, a display device 1000 (see Figure 2 ) having improved display quality can be provided.

[0124] On the other hand, if the second data signal DATA2 has the first pulse width WD1, the second data signal DATA2 can be compensated so as to adjust the amount of charge of the second node ND2 according to the second target voltage TGV2. However, when the second data signal DATA2 is compensated, the gray scale range exhibited by the data driving circuit 200 (see Figure 2 ) may increase. In this case, due to the increase in the gray scale display range, the power consumption of the data driving circuit 200 (see Figure 2 ) may increase. However, according to the inventive concept, only the pulse width of the second scan signal GWj can be controlled to charge the second node ND2 to the second target voltage TGV2. Accordingly, a display device 1000 (see Figure 2 ) having reduced power consumption can be provided.

[0125] In addition, according to the inventive concept, the pulse width of the second scan signal GWj may have a relatively small second pulse width WD2 in the nth frame FRn compared to the first pulse width WD1 of the second scan signal GWj provided in the (n - 1)th frame FRn-1. Accordingly, the display device according to an embodiment of the inventive concept can be easily applied to a high-speed driving environment.

[0126] Figure 9 FIG. is a timing diagram for describing the operation of the display device in the nth frame FRn' according to another embodiment of the inventive concept. Figure 10 FIG. is a timing diagram for describing the voltage at the second node ND2 according to the second scan signal GWj in the nth frame according to an embodiment of the inventive concept. As will be discussed in more detail below, the waveform of the second scan signal GWj is different from Figure 7 the waveform of the second scan signal GWj in the embodiment of Figures 9 to 10 . In the description of Figure 5 and Figure 6 , the same reference numerals are assigned to the same components described in

[0127] Reference Figures 3 to 6 , Figure 9 and Figure 10 , the nth frame FRn' may include first to fifth time periods t1, t2, t3-2, t4, and t5. The nth frame FRn' may be consecutive to the (n - 1)th frame FRn-1. The waveforms of the first scan signal GIj and the emission signal EMj may be the same as or similar to the waveforms of these signals shown in Figure 7 .

[0128] The waveform of the second scan signal GWj in the third time period t3-2 may be different from Figure 7The waveform of the second scan signal GWj in the third time period t3-1. The third time period t3-2 can be consecutive to the second time period t2. In the third time period t3-2, the second scan signal GWj can be at an active level, and the first scan signal GIj and the emission signal EMj can be at an inactive level. The data signal Di can be the second data signal DATA2 in the third time period t3-2.

[0129] The memory of the driving controller 100 (see Figure 2 ) can include an amplitude look-up table, in which a target voltage is set for each voltage difference between the first data signal DATA1 and the second data signal DATA2, and the amplitude of the second scan signal GWj for each target voltage is stored. In this case, during the (n-1)th frame FRn-1 and the nth frame FRn’, the second data signal DATA2 is supplied to the ith data line DLi (see Figure 3 ).

[0130] The amplitude of the second scan signal GWj can be controlled based on the amplitude look-up table. The pixel driving circuit PXC can charge the second node ND2 to the second target voltage TGV2 in response to the second scan signal GWj whose amplitude is controlled. Here, the amplitude of the second scan signal GWj can be controlled. The process of charging the second node ND2 to the second target voltage TGV2 will be described below.

[0131] The second transistor T2 and the third transistor T3 can be turned on in response to the second scan signal GWj. The second scan signal GWj provided in the nth frame FRn’ can have a waveform different from the waveform of the second scan signal GWj provided in the (n-1)th frame FRn-1. For example, the second scan signal GWj provided in the nth frame FRn’ has a second amplitude AMP2 different from (e.g., smaller than) Figure 5 the first amplitude AMP1 of the second scan signal GWj applied in Figure 5 . That is, the second amplitude AMP2 can have a magnitude different from the magnitude of the first amplitude AMP1 (see

[0132] When the second transistor T2 is turned on, the second data signal DATA2 can be supplied to the first node ND1 through the ith data line DLi. The second data signal DATA2 can be different from the first data signal DATA1 applied in the (n-1)th frame FRn-1. For example, the second data signal DATA2 can have a voltage level higher than the voltage level of the first data signal DATA1.

[0133] When the third transistor T3 is turned on, the first transistor T1 is diode-connected and forward-biased. Here, the second scan signal GWj has a second amplitude AMP2 that is smaller than the first amplitude AMP1. Accordingly, the time at which the second transistor T2 is turned on can be delayed by a delay period DS.

[0134] When the second transistor T2 is turned on after the delay period DS (e.g., Figure 10 ), the second node ND2 can be charged. Subsequently, a second target voltage TGV2 obtained by reducing the threshold voltage (Vth) of the first transistor T1 from the second data signal DATA2 is applied to the gate electrode of the first transistor T1. In other words, as Figure 10 illustrated, the voltage at the second node ND2 can reach the second target voltage TGV2.

[0135] The first driving voltage ELVDD and the second target voltage TGV2 can be applied to respective ends of the driving capacitor Cst, and charges corresponding to the voltage difference between the respective ends can be stored in the driving capacitor Cst.

[0136] In addition, the seventh transistor T7 can be turned on in response to the activation level of the second scan signal GWj. When the seventh transistor T7 is turned on, any residual current that may be present at the anode of the light-emitting diode ED can be removed, e.g., by being bypassed to the third voltage line VL3.

[0137] In the fifth period t5, the fifth transistor T5 and the sixth transistor T6 can be turned on in response to the emission signal EMj. Accordingly, a second drive current Id2 can flow from the first voltage line VL1 through the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light-emitting diode ED, and the second voltage line VL2. When the second drive current Id2 flows through the light-emitting diode ED, the pixel PXij emits light corresponding to the voltage level of the second data signal DATA2. The pixel PXij can emit light having a second gray value in the n-th frame FRn'. The second gray value can be greater than the first gray value. For example, the display panel DP (see Figure 2 ) can have the second gray value in the n-th frame FRn'. For example, the second gray value can be the gray value 127 that appears as white.

[0138] The display panel DP may be at a specified time point t (see Figure 4)The previous frames FRn-2 and FRn-1 display black images. When the display panel DP displays white images in the frames FRn and FRn+1 after a specified time point t, due to the hysteresis characteristic of the first transistor T1, a stepping efficiency may occur in the nth frame FRn, which is the first frame for displaying a white image, where the gray level of the display panel DP becomes lower than the desired gray level. As a result, when the black image changes to a white image, the user may see an afterimage due to the reduction in brightness in the nth frame FRn'. However, according to the inventive concept, in order to charge the second node ND2 only to the second target voltage TGV2, the pixel driving circuit PXC may receive a second scan signal GWj having a second amplitude AMP2. Accordingly, the display panel DP (see Figure 2 ) may obtain the desired second gray value in the nth frame FRn'. Additionally, the afterimage may be reduced or eliminated. Accordingly, a display device 1000 with improved display quality may be provided (see Figure 2 ).

[0139] According to the above description, different from the (n-1)th frame FRn-1, the pixel driving circuit PXC may control the second scan signal GWj in the nth frame FRn or FRn' so as to charge the second node ND2 only to the second target voltage TGV2. For example, the pulse width or amplitude of the second scan signal GWj may be controlled. Accordingly, in the nth frame FRn or FRn', the display panel DP may obtain the desired second gray value. The afterimage may also be reduced or eliminated. Accordingly, a display device 1000 with improved display quality may be provided. In one embodiment, different look-up tables may be referred to control the pulse width and amplitude of the second scan signal GWj.

[0140] Although the present invention has been described with reference to exemplary embodiments of the present invention, it will be apparent to those of ordinary skill in the art to which the present invention pertains that various changes and modifications can be made to the described embodiments without departing from the spirit and technical scope of the present invention as defined in the claims and their equivalents. Therefore, the scope of the inventive concept should not be restricted or limited by the foregoing description, but should be determined by the broadest permissible interpretation of the claims. Embodiments may be combined to form additional embodiments.

Claims

1. A display device, comprising: A display panel configured to be driven in units of frames, the display panel including pixels, the pixels including pixel driving circuits and light emitting diodes electrically connected to the pixel driving circuits, wherein the pixel driving circuits include: A first transistor including a first electrode configured to receive a first driving voltage and electrically connected to a first node, a second electrode electrically connected to the light emitting diode, and a gate electrode electrically connected to a second node; and A second transistor including a first electrode configured to receive a data signal, a second electrode electrically connected to the first node, and a gate electrode configured to receive a second scanning signal, wherein: The frame includes consecutive first and second frames, The data signal includes a first data signal and a second data signal different from the first data signal, and When the first data signal is provided in the first frame and the second data signal is provided in the second frame, the second scanning signal provided in the first frame has a waveform different from the waveform of the second scanning signal provided in the second frame.

2. The display device according to claim 1, wherein, The second data signal has a voltage level higher than the voltage level of the first data signal.

3. The display device according to claim 1, wherein: The second scanning signal provided in the first frame has a first pulse width, and The second scanning signal provided in the second frame has a second pulse width different from the first pulse width.

4. The display device according to claim 3, wherein, The second pulse width is less than the first pulse width.

5. The display device according to claim 1, wherein: The light emitting diode is configured to emit light having a first gray value in the first frame, and The light emitting diode is configured to emit light having a second gray value higher than the first gray value in the second frame.

6. The display device according to claim 1, wherein: The second scanning signal provided in the first frame has a first amplitude, and The second scanning signal provided in the second frame has a second amplitude different from the first amplitude.

7. The display device according to claim 6, wherein, The first amplitude is greater than the second amplitude.

8. The display device according to any one of claims 1-7, further comprising: A driving capacitor connected between a first voltage line and the second node, the first driving voltage being provided through the first voltage line.

9. The display device according to any one of claims 1-7, further comprising: A third transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the second node, and a gate electrode configured to receive the second scanning signal.

10. The display device according to any one of claims 1-7, further comprising: A fourth transistor includes a first electrode electrically connected to the second node, a second electrode configured to receive an initialization voltage, and a gate electrode configured to receive a first scan signal different from the second scan signal.

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