Display device, display panel driving method, computer equipment and storage medium

Abstract

The invention relates to a display device, a display panel driving method, computer equipment, a computer readable storage medium and a computer program product. The device comprises a display panel which comprises at least two rows and at least two columns of pixels, and each row of pixels is connected with a signal scanning line; the driving data signal output module is used for transmitting a driving data signal through a driving data signal line group; the demultiplexing module comprises at least two multiplexer switch tubes and is used for controlling the charging state of pixels in the display panel according to the driving data signal; and the time sequence control module is used for controlling the multiplexer switch tube corresponding to the last pixel of the current pixel row to be continuously switched on under the condition that the last pixel of the current pixel row is charged, so that the corresponding pixels in the next row and in the same column start to be charged preferentially. By adopting the device, the overall turnover frequency of the MUX can be reduced, so that the electric quantity consumed by the MUX drive is saved, and the effect of saving power consumption is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of OLED display, and particularly to a display device, a display panel driving method, a computer device, a computer-readable storage medium, and a computer program product. Background Art

[0002] In the field of modern display technologies, especially in organic light-emitting diode (OLED) display technology, reducing power consumption and improving display efficiency are the continuously pursued goals. With the continuous improvement of the display quality requirements for mobile devices and high-end display products, how to reduce energy consumption while ensuring the display effect has become an urgent technical problem to be solved.

[0003] In traditional display driving circuits, multiplexers (MUX) are widely used to control the charging and discharging processes of pixels to achieve image display. However, with the increase in display resolution and display size, the number of flips of the MUX circuit also increases, resulting in a significant increase in power consumption. In addition, frequent MUX flips may also cause display noise and image flicker, affecting the display quality.

[0004] Therefore, there is an urgent need for a display device, a display panel driving method, a computer device, a computer-readable storage medium, and a computer program product that can reduce the overall number of flips of the MUX, thereby saving the power consumed by MUX driving and achieving the effect of power saving. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a display device, a display panel driving method, a computer device, a computer-readable storage medium, and a computer program product that can reduce the overall number of flips of the MUX, thereby saving the power consumed by MUX driving and achieving the effect of power saving.

[0006] In a first aspect, the present application provides a display device, including:

[0007] The display panel, including pixels in at least two rows and at least two columns, and each row of pixels is connected to a signal scanning line;

[0008] The driving data signal output module is used to transmit driving data signals through the driving data signal line group;

[0009] The demultiplexing module, including at least two multiplexer switching tubes, is used to control the charging state of the pixels in the display panel according to the driving data signals;

[0010] The timing control module is used to control the multiplexer switch transistor corresponding to the last pixel of the current pixel row to continuously conduct when the charging of the last pixel of the current pixel row is completed, so that the corresponding pixels in the next row and in the same column start charging preferentially.

[0011] In one embodiment, the device further includes a display driver chip; the driving data signal line group includes at least one first output data line and at least two second output data lines, the first output data line is connected to the second output data line, and the number of the first output data lines is less than the number of the second output data lines;

[0012] Wherein, the first output data line, the timing control module and the driving data signal output module are all encapsulated inside the display driver chip, and the second output data line is arranged outside the display driver chip.

[0013] In one embodiment, all pixels in the same column are connected to the same multiplexer switch transistor.

[0014] In one embodiment, the last pixel of the current pixel row is the last pixel from left to right in the current pixel row.

[0015] In one embodiment, the last pixel of the current pixel row is the first pixel from left to right in the current pixel row.

[0016] In one embodiment, each second output data line corresponds to a multiplexer switch transistor, different multiplexer switch transistors are respectively controlled by different driving data signals, and the working timings of different driving data signals do not overlap in the time domain.

[0017] In one embodiment, the quantity ratio between the first output data line and the second output data line is m:n, where n is the number of multiplexer switch transistors.

[0018] In a second aspect, the present application further provides a method for driving a display panel, including:

[0019] Obtaining the pixel quantity arrangement data of the display panel and the number of multiplexer switch transistors included in the demultiplexing module;

[0020] When the pixel quantity arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switch transistors, transmitting a driving data signal through the driving data signal line group, where the driving data signal is used to control the charging state of the pixels in the display panel;

[0021] When the last pixel in the current pixel row finishes charging, control the multiplexer switch transistor corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts charging preferentially.

[0022] In a third aspect, the present application further provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0023] Obtain the pixel quantity arrangement data of the display panel and the number of multiplexer switch transistors included in the demultiplexing module;

[0024] When the pixel quantity arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switch transistors, transmit a driving data signal through the driving data signal line group, and the driving data signal is used to control the charging state of the pixels in the display panel;

[0025] When the last pixel in the current pixel row finishes charging, control the multiplexer switch transistor corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts charging preferentially.

[0026] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0027] Obtain the pixel quantity arrangement data of the display panel and the number of multiplexer switch transistors included in the demultiplexing module;

[0028] When the pixel quantity arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switch transistors, transmit a driving data signal through the driving data signal line group, and the driving data signal is used to control the charging state of the pixels in the display panel;

[0029] When the last pixel in the current pixel row finishes charging, control the multiplexer switch transistor corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts charging preferentially.

[0030] In a fifth aspect, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the following steps are implemented:

[0031] Obtain the pixel number arrangement data of the display panel and the number of multiplexer switching transistors included in the demultiplexing module;

[0032] When the pixel number arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switching transistors, transmit a driving data signal through the driving data signal line group, and the driving data signal is used to control the charging state of the pixels in the display panel;

[0033] When the last pixel in the current pixel row is charged, control the multiplexer switching transistor corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts to be charged preferentially.

[0034] The above display device, display panel driving method, computer device, computer-readable storage medium and computer program product, by controlling the corresponding MUX switching transistor to continuously conduct after the last pixel in the current pixel row is charged, can make the corresponding pixel in the next row and the same column start to be charged preferentially. This design reduces the number of flips of the MUX, thereby reducing power consumption; through the intelligent control of the timing control module, the charging sequence of the pixels can be optimized, making the charging process more efficient, reducing the charging time, and improving the response speed of the display panel; due to reducing the number of flips of the MUX, display noise and image flicker can be reduced, thereby improving the display quality and making the displayed image clearer and more stable; reducing power consumption and heat generation helps to improve the stability and reliability of the entire display system and extend the service life of the device. The design of this display device allows for flexible adjustment of the charging sequence and timing control to adapt to different display requirements and application scenarios, improving the adaptability of the system. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a design diagram of a display driving circuit in the traditional technology;

[0037] Figure 2 It is a structural block diagram of a display device in an embodiment;

[0038] Figure 3 It is a design diagram of a display driving circuit in an embodiment;

[0039] Figure 4 The waveform diagram of the first charging method for each row of pixels in the display panel in one embodiment;

[0040] Figure 5 The waveform diagram of the second charging method for each row of pixels in the display panel in one embodiment;

[0041] Figure 6 The schematic diagram of the charging trajectory for each row of pixels in the display panel in one embodiment;

[0042] Figure 7 The schematic diagram of the quantity between the first output data line and the second output data line in one embodiment;

[0043] Figure 8 The schematic diagram of the overall structure of the display device in one embodiment;

[0044] Figure 9 The schematic diagram of the flow of the display panel driving method in one embodiment;

[0045] Figure 10 The internal structure diagram of a computer device in one embodiment. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] In the current display technology field, especially in the organic light-emitting diode (OLED) display technology, the key performance indicators of a display device include power consumption, display efficiency and image quality. With the rapid development of mobile devices, high-end TVs and other display products, the market demand for high-resolution, low-power and high-image-quality display technologies is increasing day by day. However, the traditional display driving circuit design has some limitations in meeting these requirements.

[0048] In a traditional display driving circuit, the pixels of a display panel are usually controlled for charging and discharging through a multiplexer (MUX) to achieve image display. Figure 1 Shows the design diagram of the display driving circuit of the traditional technology, which includes four multiplexers (MUX1, MUX2, MUX3, MUX4). The pixels in the figure are marked with numbers 1 to 4, and each pixel is connected to the driving circuit through a MUX.

[0049] MUX1 controls the pixels 1 in the first, third, and fifth columns; MUX2 controls the pixels 2 in the second, fourth, and sixth columns; MUX3 controls the pixels 3 in the first, third, and fifth columns; MUX4 controls the pixels 4 in the second, fourth, and sixth columns.

[0050] First row charging: MUX1 is turned on to charge the pixels 1 in the first, third, and fifth columns; MUX2 is turned on to charge the pixels 2 in the second, fourth, and sixth columns; Second row charging: MUX3 is turned on to charge the pixels 3 in the first, third, and fifth columns; MUX4 is turned on to charge the pixels 4 in the second, fourth, and sixth columns. Repeat the above process, and MUX1, MUX2, MUX3, and MUX4 are turned on in sequence to charge the pixels in each row.

[0051] However, since the charging and discharging of each pixel need to be controlled by an independent MUX, as the resolution of the display panel increases, the number of required MUXs also increases, resulting in a significant increase in the number of IC Sources. This not only increases the complexity of the circuit design but also may lead to higher manufacturing costs. In a narrow bezel design, the space in the panel routing area is very limited. Since more IC Sources need to be wired, it becomes more difficult to perform effective wiring in the limited space, thus increasing the difficulty of implementing the narrow bezel design. Also, since each MUX needs to be flipped multiple times during each charging cycle to select different input signals, this frequent flipping operation results in a significant increase in power consumption.

[0052] To solve the above problems, the display device provided in the embodiments of the present application, as Figure 2 and Figure 3 shown, includes a display panel, a demultiplexing module, a driving data signal line group, a timing control module, and a driving data signal output module;

[0053] The display panel includes at least two rows and at least two columns of pixels, and each row of pixels is connected to a signal scanning line;

[0054] The driving data signal output module is used to transmit driving data signals through the driving data signal line group;

[0055] The demultiplexing module includes at least two multiplexer switching tubes and is used to control the charging state of the pixels in the display panel according to the driving data signals;

[0056] The timing control module is used to control the multiplexer switching tube corresponding to the last pixel in the current pixel row to continuously conduct when the charging of the last pixel in the current pixel row is completed, so that the corresponding pixels in the next row and in the same column start charging preferentially.

[0057] Specifically, the display panel (such as an OLED) is the core part of the display device, which consists of multiple pixels. These pixels are arranged in rows and columns, and each pixel is a light-emitting unit that can be independently controlled. Each row of pixels is connected to a signal scan line (also known as a gate scan line) for activating the pixels row by row.

[0058] The driving data signal output module is responsible for transmitting the driving data signal to the demultiplexing module through the driving data signal line group. The driving data signal contains information for controlling the brightness and color of the pixels.

[0059] The demultiplexing module includes at least two multiplexer (MUX) switching tubes. These switching tubes control which pixels should be charged (i.e., activated to emit light) according to the driving data signal. The role of the multiplexer is to select an input signal and transmit it to the output, and here it is used to select which pixel's driving signal should be applied.

[0060] The timing control module is responsible for controlling the timing of pixel charging to ensure that the pixels are activated in the correct order. It ensures that when the last pixel in the current row finishes charging, the corresponding multiplexer switching tube remains conducting, so that the corresponding pixel in the next row and the same column can start charging preferentially without selecting the first charging pixel in the next row for charging, enabling the current MUX not to flip in the next charging cycle and continue to work; this design can improve the charging efficiency, reduce the charging time, and thus improve the display performance.

[0061] In a traditional display driving circuit, each MUX needs to flip in each charging cycle to select different pixels for charging. This flipping operation increases power consumption because each flip involves a change in the circuit state, which requires energy consumption. Through the design of the timing control module, it can be ensured that after the last pixel in a row finishes charging, the current MUX does not need to flip to the first pixel in the next row, but can directly continue to charge the corresponding pixel in the next row. In this way, the state of the MUX can remain unchanged in multiple charging cycles, thereby reducing the number of flips.

[0062] Since the number of flips of the MUX is reduced, the energy consumption required for each flip also decreases. This is because a change in the circuit state (i.e., flipping) usually requires additional energy. In addition, when the MUX does not need to flip, it can directly enter the next charging cycle, which can reduce the charging interval, improve the charging efficiency, and further reduce power consumption. By reducing the number of flips of the MUX, it is also possible to reduce the signal interference caused by the flipping operation, which helps to improve the display quality and reduce the maintenance cost.

[0063] In an exemplary embodiment, such as Figure 2As shown, the device further includes a display driving chip; the driving data signal line group includes at least one first output data line and at least two second output data lines, the first output data line is connected to the second output data line, and the number of the first output data lines is less than that of the second output data lines;

[0064] Among them, the first output data line, the timing control module, and the driving data signal output module are all encapsulated inside the display driving chip, and the second output data line is arranged outside the display driving chip.

[0065] Specifically, the first output data line, the timing control module, and the driving data signal output module are all encapsulated inside the display driving chip. This means that these components are integrated on the same chip, which helps to reduce the complexity of external wiring and improve the reliability and performance of the system. The second output data line is arranged outside the display driving chip. This design allows more flexibility because more data lines can be added as needed without modifying the internal design of the chip.

[0066] In this embodiment, by encapsulating the key components inside the chip, the complexity of external wiring can be reduced and the manufacturing cost can be lowered; the integrated design can reduce the signal transmission delay and improve the display performance; the external second output data line provides extended flexibility and more data lines can be added as needed to support higher-resolution display panels or more complex display functions; by optimizing the number and layout of the data lines, the power consumption during signal transmission can be reduced.

[0067] In an exemplary embodiment, all pixels in the same column are connected to the same multiplexer switch transistor.

[0068] Specifically, as Figure 3 shown, Figure 3 is a design diagram of a display driving circuit according to an embodiment of the present application. In Figure 3 , MUX1, MUX2, and MUX3 respectively control different pixel columns: MUX1 controls the pixels in the first column and the fourth column, MUX2 controls the pixels in the second column and the fifth column, and MUX3 controls the pixels in the third column and the sixth column. All pixels in each column are connected to the MUX controlling that column through their respective connection lines. This means that when a MUX is activated, it will control the charging states of all pixels in that column, and during the progressive scan process, the pixels on that pixel column will be charged row by row.

[0069] During the charging process, the MUX charges the pixels in the columns it controls in sequence according to the indication of the selection signal. For example, as Figure 4As shown, S1 activates MUX1, and MUX1 charges pixel 1 in the first column. S1 activates MUX2, and MUX2 charges pixel 2 in the second column. S1 activates MUX3, and MUX3 charges pixel 3 in the third column. When scanning the next row of pixels, S1 activates MUX1, and MUX1 charges pixel 4 in the first column. S1 activates MUX2, and MUX2 charges pixel 5 in the second column. S1 activates MUX3, and MUX3 charges pixel 6 in the third column.

[0070] Alternatively, as Figure 5 shown, S1 activates MUX1, and MUX1 charges pixel 1 in the first column. S1 activates MUX2, and MUX2 charges pixel 2 in the second column. S1 activates MUX3, and MUX3 charges pixel 3 in the third column. When scanning the next row of pixels, S1 activates MUX3, and MUX3 charges pixel 6 in the third column. S1 activates MUX2, and MUX2 charges pixel 5 in the second column. S1 activates MUX1, and MUX1 charges pixel 4 in the first column.

[0071] In this embodiment, by connecting all the pixels in the same column to the same MUX, the complexity of wiring can be reduced because each pixel only needs to be connected to one MUX instead of directly connecting to multiple parts of the driving circuit. By precisely controlling the activation and deactivation of the MUX, unnecessary charging operations can be reduced, thereby reducing power consumption.

[0072] In an exemplary embodiment, the last pixel in the current pixel row is the last pixel from left to right in the current pixel row.

[0073] Specifically, the charging sequence starts from the leftmost pixel and proceeds in the order from left to right until the rightmost pixel in the row is charged.

[0074] For example, as Figure 5 and Figure 6 shown, in the first pixel row, the charging sequence may be 1 (first column) → 2 (second column) → 3 (third column). After the first pixel row is charged, charging starts from the pixels in the next pixel row (i.e., the second pixel row) of the current pixel column, that is, the pixel charging sequence is 6 (third column) → 5 (second column) → 4 (first column). When the first pixel row is the current pixel row, the last pixel in the current pixel row is the last pixel from left to right in the current pixel row (i.e., pixel 3). Under this rule, the pixels in each row of the display panel are charged according to a serpentine charging trajectory (as shown by the dotted line trajectory in Figure 6 ).

[0075] In this embodiment, this charging method helps to charge the display panel more evenly because it does not simply charge in row or column order, but moves in a serpentine manner across the entire panel, which may help reduce problems such as display unevenness or image retention; and, by optimizing the charging sequence, power consumption caused by unnecessary signal flips or circuit state changes may be reduced.

[0076] In an exemplary embodiment, the last pixel of the current pixel row is the first pixel from left to right in the current pixel row.

[0077] Specifically, as can be seen from the above, the pixels in each row of the display panel are charged according to a serpentine charging trajectory. Therefore, as Figure 5 and Figure 6 shown, after the second pixel row is charged, if the third pixel row needs to be charged, the pixel charging sequence from the first row to the third pixel row is: 1 (the first column) → 2 (the second column) → 3 (the third column) → 6 (the third column) → 5 (the second column) → 4 (the first column) → 1 (the first column) → 2 (the second column) → 3 (the third column). When the second pixel row is the current pixel row, the last pixel of the current pixel row is the first pixel from left to right in the current pixel row (i.e., pixel 4).

[0078] In this embodiment, this charging method helps to charge the display panel more evenly because it does not simply charge in row or column order, but moves in a serpentine manner across the entire panel, which may help reduce problems such as display unevenness or image retention; and, by optimizing the charging sequence, power consumption caused by unnecessary signal flips or circuit state changes may be reduced.

[0079] In an exemplary embodiment, each second output data line corresponds to a multiplexer switch transistor, and different multiplexer switch transistors are respectively controlled by different drive data signals, and the operating timings of different drive data signals do not overlap in the time domain.

[0080] Specifically, each second output data line is connected to a specific multiplexer (MUX) switch transistor. This means that if there are multiple second output data lines, each second output data line directly controls a MUX switch transistor. Each MUX switch transistor is controlled by a unique drive data signal. These signals contain specific information for controlling the pixel charging state.

[0081] The operating timings of the drive data signals do not overlap in the time domain, indicating that at any given time point, only one drive data signal is active. This design ensures that at any moment, only one MUX switch transistor is active, thus avoiding signal conflicts and unnecessary power consumption.

[0082] Exemplarily, assume there is a display driving circuit that includes three second output data lines, which are respectively connected to three MUX switch transistors (MUX1, MUX2, MUX3). Each MUX switch transistor controls the charging of a column of pixels in the display panel.

[0083] Drive data signal:

[0084] Signal D1 controls MUX1 and is responsible for charging the first column of pixels.

[0085] Signal D2 controls MUX2 and is responsible for charging the second column of pixels.

[0086] Signal D3 controls MUX3 and is responsible for charging the third column of pixels.

[0087] Operating timing:

[0088] At time T1, only signal D1 is activated, MUX1 is turned on, and the first column of pixels is charged.

[0089] At time T2, only signal D2 is activated, MUX2 is turned on, and the second column of pixels is charged.

[0090] At time T3, only signal D3 is activated, MUX3 is turned on, and the third column of pixels is charged.

[0091] In this embodiment, by ensuring that only one MUX switch transistor is activated at any moment, unnecessary power consumption is reduced, the pixel charging process is optimized, and the overall efficiency of the display device is improved; different drive data signals do not overlap in the time domain, reducing the possibility of signal conflicts and improving the reliability of the system.

[0092] In an exemplary embodiment, the quantity ratio between the first output data line and the second output data line is m:n, where n is the number of multiplexer switch transistors.

[0093] Specifically, the quantity ratio m:n represents the quantity relationship between the first output data line and the second output data line.

[0094] Such as Figure 7 shown, if the ratio is 1:3, this means there is 1 first output data line and 3 second output data lines; or there are 2 first output data lines and 6 second output data lines, and so on; each second output data line is connected to a MUX switch transistor, and these MUX switch transistors respectively control the charging of three columns of pixels in the display panel.

[0095] Such as Figure 7As shown, on the left side, in the traditional display driving scheme, the pixels of the display panel are controlled for charging and discharging through a multiplexer (MUX) to achieve image display. In this scheme, the driving data signal output module inside the display driving chip transmits control signals to the outside through the first output data line. At the same time, multiple second output data lines extend from the outside of the display driving chip and are connected to each MUX switching tube on the display panel. These data lines are responsible for transmitting signals to each pixel of the panel to control their charging states. However, this design often requires a relatively large number of data lines, resulting in a large routing area on the panel, which is not conducive to achieving a narrow bezel design. At the same time, it may also increase power consumption and cost.

[0096] On the right side, the improved display driving scheme realizes more efficient pixel control by optimizing the layout and quantity of data lines. In this scheme, the driving data signal output module inside the display driving chip transmits control signals through a smaller number of first output data lines. At the same time, the optimized number of second output data lines is also reduced, but it can still cover all the MUX switching tubes that need to be controlled. This design reduces the routing area, helps to shorten the panel bezel, and achieves the narrow bezel effect. By reducing the number of data lines and optimizing the routing layout, the improved scheme not only helps to reduce power consumption and cost, but also improves the overall performance and reliability of the display device, bringing a better visual experience to users.

[0097] In this embodiment, by reducing the number of first output data lines, the wiring design inside the display driving chip can be simplified and the complexity can be reduced; by precisely controlling the activation time of each MUX switching tube, the efficiency of pixel charging can be improved and power consumption can be reduced; the number of second output data lines can be increased as needed to support the control of more columns of pixels, providing flexibility in design.

[0098] Each module in the above display device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above respective modules.

[0099] Based on the same inventive concept, the embodiment of the present application also provides a display panel driving method for use in the above-mentioned display device. The implementation solution provided by this driving method to solve problems is similar to the implementation solution described in the above display device.

[0100] The display panel driving method provided by the embodiment of the present application can be applied to a display device as Figure 8 shown. Among them, the display device can be a display device such as a mobile phone or a tablet computer. Specifically, referring to Figure 2, showing a schematic diagram of the overall structure of a display device in an embodiment. The display device 10 may include a display panel 102. The display panel may be an organic light-emitting diode (OLED) display panel.

[0101] In an exemplary embodiment, as Figure 9 shown, a display panel driving method is provided, including the following steps S902 to step S906. Wherein:

[0102] Step S902, obtaining the pixel number arrangement data of the display panel and the number of multiplexer switching transistors included in the demultiplexing module;

[0103] Step S904, when the pixel number arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switching transistors, transmitting a driving data signal through a driving data signal line group, and the driving data signal is used to control the charging state of the pixels in the display panel;

[0104] Step S906, when the last pixel in the current pixel row is charged, controlling the multiplexer switching transistor corresponding to the last pixel in the current pixel row to be continuously turned on, so that the corresponding pixels in the next row and in the same column start to be charged preferentially.

[0105] In the above display panel driving method, by controlling the corresponding MUX switching transistor to be continuously turned on after the last pixel in the current pixel row is charged, the corresponding pixels in the next row and in the same column can start to be charged preferentially. This design reduces the number of flips of the MUX, thereby reducing power consumption; through the intelligent control of the timing control module, the charging order of the pixels can be optimized, making the charging process more efficient, reducing the charging time, and improving the response speed of the display panel; since the number of flips of the MUX is reduced, display noise and image flicker can be reduced, thereby improving the display quality and making the displayed image clearer and more stable; reducing power consumption and heat generation helps to improve the stability and reliability of the entire display system and extend the service life of the device. The design of the display device allows flexible adjustment of the charging order and timing control to adapt to different display requirements and application scenarios and improve the adaptability of the system.

[0106] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders.

[0107] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in Figure 10 . The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store pixel drive data. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, it implements a display panel driving method.

[0108] Those skilled in the art can understand that Figure 10 the structure shown in is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0109] In an exemplary embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented:

[0110] Obtain the pixel number arrangement data of the display panel and the number of multiplexer switch tubes included in the demultiplexing module;

[0111] When the pixel number arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scan line, and the demultiplexing module includes at least two multiplexer switch tubes, transmit a drive data signal through a group of drive data signal lines. The drive data signal is used to control the charging state of the pixels in the display panel;

[0112] When the last pixel in the current pixel row is fully charged, control the multiplexer switch tube corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts to charge preferentially.

[0113] In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the following steps are implemented:

[0114] Obtain the pixel quantity arrangement data of the display panel and the quantity of multiplexer switching tubes included in the demultiplexing module;

[0115] When the pixel quantity arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switching tubes, transmit a driving data signal through a driving data signal line group, and the driving data signal is used to control the charging state of the pixels in the display panel;

[0116] When the last pixel in the current pixel row is charged, control the multiplexer switching tube corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts to be charged preferentially.

[0117] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0118] Obtain the pixel quantity arrangement data of the display panel and the quantity of multiplexer switching tubes included in the demultiplexing module;

[0119] When the pixel quantity arrangement data indicates that the display panel includes at least two rows and at least two columns of pixels, each row of pixels is connected to a signal scanning line, and the demultiplexing module includes at least two multiplexer switching tubes, transmit a driving data signal through a driving data signal line group, and the driving data signal is used to control the charging state of the pixels in the display panel;

[0120] When the last pixel in the current pixel row is charged, control the multiplexer switching tube corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixel in the next row and the same column starts to be charged preferentially.

[0121] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0122] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0123] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0124] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A display device, characterized in that, The display device includes a display panel, a demultiplexing module, a group of driving data signal lines, a timing control module, and a driving data signal output module; The display panel includes pixels arranged in at least two rows and at least two columns, and pixels in each row are connected to signal scanning lines; The driving data signal output module is configured to transmit driving data signals through the group of driving data signal lines; The demultiplexing module includes at least two multiplexer switch transistors and is configured to control the charging states of the pixels in the display panel according to the driving data signals; The timing control module is configured to control the multiplexer switch transistor corresponding to the last pixel in the current pixel row to continuously conduct when the last pixel in the current pixel row finishes charging, so that the corresponding pixels in the next row and in the same column start charging preferentially.

2. The device according to claim 1, characterized in that The device further includes a display driving chip; the group of driving data signal lines includes at least one first output data line and at least two second output data lines, the first output data line is connected to the second output data lines, and the number of the first output data lines is less than the number of the second output data lines; Wherein, the first output data line, the timing control module, and the driving data signal output module are all encapsulated inside the display driving chip, and the second output data lines are arranged outside the display driving chip.

3. The device according to claim 1, characterized in that, All pixels in the same column are connected to the same multiplexer switch transistor.

4. The device according to claim 3, characterized in that, The last pixel in the current pixel row is the last pixel from left to right in the current pixel row.

5. The device according to claim 3, characterized in that, The last pixel in the current pixel row is the first pixel from left to right in the current pixel row.

6. The device according to claim 2, characterized in that, Each of the second output data lines corresponds to a multiplexer switch transistor, different multiplexer switch transistors are respectively controlled by different driving data signals, and the working timings of different driving data signals do not overlap in the time domain.

7. The device according to claim 2, characterized in that, The quantity ratio between the first output data line and the second output data lines is m:n, where n is the number of multiplexer switch transistors.

8. A driving method of a display device, characterized in that, Applied to the display device according to any one of claims 1-7 above, the method includes: Obtaining the pixel quantity arrangement data of the display panel and the number of multiplexer switch transistors included in the demultiplexing module; When the pixel quantity arrangement data indicates that the display panel includes pixels arranged in at least two rows and at least two columns, pixels in each row are connected to signal scanning lines, and the demultiplexing module includes at least two multiplexer switch transistors, transmitting driving data signals through the group of driving data signal lines, where the driving data signals are used to control the charging states of the pixels in the display panel; When the last pixel in the current pixel row finishes charging, controlling the multiplexer switch transistor corresponding to the last pixel in the current pixel row to continuously conduct, so that the corresponding pixels in the next row and in the same column start charging preferentially.

9. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to claim 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to claim 8 are implemented.

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