Pixel circuits for display screens

Abstract

The present application discloses a pixel circuit for a display screen, belonging to the field of display technology. It includes: a first capacitor and a second capacitor connected in series, the second capacitor is connected to a first voltage; the drain of the first transistor is connected to a first electrical signal, and the source of the first transistor is connected to the first capacitor; the drain of the fourth transistor is connected to the first voltage, and the source of the fifth transistor is connected to the anode of the light-emitting diode; the drain of the sixth transistor is connected to a second electrical signal, and the seventh transistor is connected to the source of the eighth transistor; the source of the second transistor is connected to the gate of the eighth transistor; the drain of the third transistor is connected to a second voltage, and the source is connected between the drain of the fifth transistor and the drain of the eighth transistor; the transistor is configured to enter a corresponding state based on the working stage of the pixel circuit to compensate for the drain of the eighth transistor in the first dimming stage. The pixel circuit for a display screen of the present application can achieve a hysteresis compensation effect to reduce brightness fluctuations.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a pixel circuit for a display screen. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) displays have become a strong candidate for the next generation of mainstream displays. AMOLED display backplane technology has evolved from hydrogenated amorphous silicon thin-film transistors (aSi:H TFTs) to low-temperature polycrystalline silicon (LTPS) TFTs, and finally to low-temperature polycrystalline silicon and oxide (LTPO) TFTs. Flicker is a critical issue in low-frame-rate drive. Related technologies primarily focus on compensating the on-threshold Vth of the driver TFT (D-TFT). This approach maintains the gate voltage of the LTPS driver TFT to maintain the circuit's drive frequency between 1 and 120 Hz. However, this circuit structure is complex and results in significant hysteresis. Greater brightness fluctuations lead to poor display quality in low-frame-rate applications. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. To this end, this application proposes a pixel circuit for a display screen that can achieve hysteresis compensation, effectively reduce brightness fluctuations, and improve display effects in low frame rate applications. The circuit structure is simple and easy to implement, occupies a small space, and has a low design cost.

[0004] In a first aspect, the present application provides a pixel circuit for a display screen, the method comprising:

[0005] A first capacitor and a second capacitor connected in series, wherein the second capacitor is connected to a first voltage;

[0006] a first transistor, wherein a drain of the first transistor is connected to a first electrical signal, and a source of the first transistor is connected to the first capacitor;

[0007] a fourth transistor, an eighth transistor, and a fifth transistor connected in series, wherein the drain of the fourth transistor is connected to the first voltage, and the source of the fifth transistor is connected to the anode of the light-emitting diode;

[0008] a sixth transistor and a seventh transistor connected in series, wherein the drain of the sixth transistor is connected to the second electrical signal, and the seventh transistor is connected to the source of the eighth transistor;

[0009] a second transistor, wherein a source of the second transistor is connected to the gate of the eighth transistor;

[0010] a third transistor, wherein a drain of the third transistor is connected to the second voltage, and a source of the third transistor is connected between the drain of the fifth transistor and the drain of the eighth transistor;

[0011] The transistor is configured to enter a corresponding state based on a working stage of the pixel circuit to compensate the drain of the eighth transistor in a first dimming stage, wherein the state includes on or off, and the second voltage is adjusted accordingly based on a change in the working stage.

[0012] According to the pixel circuit for a display screen of the present application, by applying a negative gate-drain bias in the first dimming stage, shallowly trapped electrons near the drain in the gate insulating layer can be released to restore the initial state. In the first dimming stage, the third transistor is turned on, and the second sub-voltage of the high voltage is transmitted to the fourth connection point, that is, the drain of the eighth transistor, so that the gate-drain bias becomes more negative, so that the trapped electrons can be released as much as possible to achieve the effect of hysteresis compensation, effectively reduce brightness fluctuations, and improve the display effect in low frame rate application scenarios; and the circuit structure is simple and easy to implement, occupies a small space, and has a low design cost.

[0013] According to an embodiment of the present application, in the first dimming stage, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are turned on, and the other transistors are turned off.

[0014] According to one embodiment of the present application, the first dimming stage also includes a hysteresis compensation stage. When entering the hysteresis compensation stage, the third transistor, the seventh transistor and the eighth transistor are turned on, and the other transistors are turned off; the hysteresis compensation stage lasts for a target duration, which is less than the duration of the first dimming stage, and the second voltage is adjusted to a second sub-voltage.

[0015] According to one embodiment of the present application, in the second dimming stage, the fourth transistor, the fifth transistor and the sixth transistor are turned on, and the other transistors are turned off, the second electrical signal is greater than the first voltage, and the second dimming stage is a stage after and adjacent to the first dimming stage.

[0016] According to one embodiment of the present application, in the anode reset stage, the third transistor, the fifth transistor, the seventh transistor and the eighth transistor are turned on, and the other transistors are turned off; the second voltage is adjusted to a first sub-voltage, and the first sub-voltage is less than the turn-on voltage of the light-emitting diode.

[0017] According to one embodiment of the present application, in the initialization phase, the first transistor, the fourth transistor, the seventh transistor, and the eighth transistor are turned on, and the other transistors are turned off.

[0018] According to one embodiment of the present application, in the compensation stage, the first transistor, the third transistor, the seventh transistor and the eighth transistor are turned on, and the other transistors are turned off; the second voltage is adjusted to a first sub-voltage, and the first sub-voltage is less than the second sub-voltage.

[0019] According to one embodiment of the present application, in the data writing phase, the second transistor, the seventh transistor, and the eighth transistor are turned on, and the other transistors are turned off.

[0020] According to one embodiment of the present application,

[0021] The gate of the first transistor is connected to a first level signal; the gate of the second transistor is connected to a second level signal, and the gate of the third transistor is connected to a third level signal via an inverter;

[0022] The gate of the fourth transistor is connected to the fourth level signal via an inverter, the gate of the fifth transistor is connected to the fifth level signal via an inverter, the gate of the sixth transistor is connected to the sixth level signal, and the gate of the seventh transistor is connected to the sixth level signal via an inverter;

[0023] Each level signal is converted between high and low levels based on the working stage to control the state of the corresponding transistor; the ratio of the low level duration of the sixth level signal to the dimming cycle duration is determined based on the brightness of the display screen.

[0024] According to one embodiment of the present application, the transistor is a low-temperature polysilicon oxide thin film transistor.

[0025] According to one embodiment of the present application, the first transistor, the second transistor and the sixth transistor are N-type transistors; the third transistor, the fourth transistor, the fifth transistor, the seventh transistor and the eighth transistor are P-type transistors.

[0026] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0027] By applying a negative gate-drain bias in the first dimming stage, shallowly trapped electrons near the drain in the gate insulating layer can be released to restore the initial state. In the first dimming stage, the third transistor is turned on, and the high-voltage second sub-voltage is transmitted to the fourth connection point, i.e., the drain of the eighth transistor, so that the gate-drain bias becomes more negative, so that the trapped electrons can be released as much as possible to achieve the effect of hysteresis compensation, effectively reduce brightness fluctuations, and improve the display effect in low frame rate application scenarios; and the circuit structure is simple and easy to implement, occupies a small space, and has a low design cost.

[0028] Furthermore, while directly compensating the drain of the eighth transistor, PWM dimming can also be added to the gate of the eighth transistor. By using high-frequency PWM dimming (such as 3840Hz, 2160Hz PWM dimming) at low brightness, the SVM of the screen can be effectively reduced, thereby achieving eye protection and further improving the display effect.

[0029] Furthermore, by setting the data writing stage and the threshold voltage compensation stage as independent stages, the writing and compensation times do not affect each other, so that a sufficient compensation effect can be guaranteed even at a high frame rate, further improving the display effect.

[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0032] Figure 1 This is one of the structural schematic diagrams of a pixel circuit for a display screen provided in an embodiment of the present application;

[0033] Figure 2 is a signal timing diagram of a pixel circuit for a display screen provided in an embodiment of the present application;

[0034] Figure 3 This is the second structural diagram of a pixel circuit for a display screen provided in an embodiment of the present application;

[0035] Figure 4 This is the third structural diagram of the pixel circuit for a display screen provided in an embodiment of the present application;

[0036] Figure 5 This is the fourth structural diagram of the pixel circuit for a display screen provided in an embodiment of the present application;

[0037] Figure 6 This is the fifth structural diagram of the pixel circuit for a display screen provided in an embodiment of the present application;

[0038] Figure 7 This is the sixth structural diagram of a pixel circuit for a display screen provided in an embodiment of the present application;

[0039] Figure 8 This is the seventh structural diagram of a pixel circuit for a display screen provided in an embodiment of the present application;

[0040] Figure 9 This is the eighth structural diagram of the pixel circuit for a display screen provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0042] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0043] like Figure 1 As shown, the pixel circuit for the display screen includes: a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor D-TFT.

[0044] It is understandable that the circuit principle of the display screen is based on the electroluminescent properties of organic materials under the action of an electric field. The core is the combination of electroluminescence and transistor drive. High-definition display is achieved through the light emission of organic materials and precise circuit control. The display screen may include an OLED display screen. In some embodiments, the display screen may be an active matrix organic light-emitting diode (AMOLED) display screen.

[0045] In some embodiments, the transistor is a low temperature polysilicon oxide thin film transistor (LTPO TFT).

[0046] In some embodiments, the first transistor T1, the second transistor T2, and the sixth transistor T6 are N-type transistors, such as N-type indium gallium zinc oxide transistors (IGZO TFTs); the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor D-TFT are P-type transistors, such as P-type low-temperature polysilicon transistors (LTPS TFTs).

[0047] The first capacitor C1 and the second capacitor C2 are storage capacitors. The first capacitor C1 and the second capacitor C2 are connected in series. Figure 1The connection point between the first capacitor C1 and the second capacitor C2 is the third connection point N3. The capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2. The specific capacitance value can be based on user-defined settings, such as setting the first capacitor C1 to 40fF and the second capacitor C2 to 10fF, etc. This application is not limited here.

[0048] Continue to refer Figure 1 One end of the second capacitor C2 away from the third connection point N3 is connected to the first voltage VDD, one end of the first capacitor C1 away from the third connection point N3 is connected to the source of the first transistor T1, and the connection point between the first capacitor C1 and the source of the first transistor T1 is the second connection point N2.

[0049] The drain of the first transistor T1 is connected to the first electrical signal Vref1 , and the gate of the first transistor T1 is connected to the first level signal S1 (n).

[0050] The fourth transistor T4, the eighth transistor D-TFT and the fifth transistor T5 are connected in series, wherein the drain of the fourth transistor T4 is connected to the first voltage VDD, the gate of the fourth transistor T4 is connected to the fourth level signal EM(n), and the source of the fourth transistor T4 is connected to the source of the eighth transistor D-TFT via the first connection point N1.

[0051] The gate of the eighth transistor D-TFT is connected to the second connection point N2, the drain of the eighth transistor D-TFT is connected to the drain of the fifth transistor T5 via the fourth connection point N4, the source of the fifth transistor T5 is connected to the anode of the light emitting diode, and the gate of the fifth transistor T5 is connected to the fifth level signal EM(n-1).

[0052] In some embodiments, the light-emitting diode may be an organic light-emitting diode (OLED).

[0053] Continue to refer Figure 1 The sixth transistor T6 and the seventh transistor T7 are connected in series, wherein the drain of the sixth transistor T6 is connected to the second electrical signal Vref2, the source of the sixth transistor T6 is connected to the seventh transistor T7 via the third connection point N3, and the other end of the seventh transistor T7 is connected to the first connection point N1 and is connected to the source of the eighth transistor D-TFT. The gates of the seventh transistor T7 and the sixth transistor T6 are both used to receive the sixth electrical signal.

[0054] The source of the second transistor T2 is connected to the gate of the eighth transistor D-TFT through the second connection point N2 , the drain of the second transistor T2 is used to receive the third electrical signal VDATA, and the gate of the second transistor T2 is used to access the second level signal S2 (n).

[0055] The drain of the third transistor T3 is connected to the second voltage, the source of the third transistor T3 is connected between the drain of the fifth transistor T5 and the drain of the eighth transistor D-TFT, and the connection point is the fourth connection point N4; the gate of the third transistor T3 is used to receive the third level signal S3 (n).

[0056] The first voltage, VDD, is a positive power supply voltage used to provide the driving current for the OLED pixel and is typically at a high level. For AMOLED, VDD is typically between 4V and 6V, such as 5V. In the TFT driver circuit, VDD is also used to charge the pixel capacitor.

[0057] The second voltage is adjusted accordingly based on the change of the working stage. The second voltage includes a first sub-voltage Vint and a second sub-voltage Vh. The second sub-voltage Vh is greater than the first sub-voltage Vint.

[0058] The first sub-voltage Vint should be lower than the turn-on voltage of the light emitting diode. For example, the first sub-voltage Vint can be set to 0V or lower than 0V to ensure that no current flows through the light emitting diode during the anode initialization stage.

[0059] The magnitude and frequency of the second sub-voltage Vh can be determined based on the display frequency and brightness, and can be adjusted accordingly to ensure effective compensation for hysteresis. For example, when displaying at 10Hz and 50nA brightness, the second sub-voltage Vh can be applied at 30Hz and 9.2V to fully compensate for hysteresis and maintain a stable current and the driver transistor's turn-on threshold Vth. When displaying at 10Hz and 10nA brightness, the second sub-voltage Vh can be applied at 30Hz and 8.5V.

[0060] In actual implementation, the second voltage is adjusted accordingly based on the change of the working stage, that is, based on the change of the specific working stage, it is determined whether to select the first sub-voltage Vint or the second sub-voltage Vh in the current working stage.

[0061] The third electrical signal VDATA is a data voltage used to control the brightness (grayscale) of the light-emitting diode. By adjusting the gate voltage of the eighth transistor D-TFT, the current flowing through the light-emitting diode is changed, and the brightness of the light-emitting diode is correspondingly adjusted, thereby adjusting the brightness of the display screen.

[0062] In AMOLED, the third electrical signal VDATA is usually provided by the source driver IC and usually ranges from 0V to 5V, depending on the grayscale (such as 8bit=256 levels). 0V is the darkest (black) and 5V is the brightest (white).

[0063] The first electrical signal Vref1 is a fixed value of a current magnitude parameter, which can be customized by the user, such as being set to 3.5V, 4V, or 4.5V.

[0064] It's understood that the brightness of the display is determined by the current flowing through the LEDs, which is determined by both the first electrical signal Vref1 and the third electrical signal VDATA. By changing the third electrical signal VDATA, the current can be changed accordingly, thereby changing the brightness of the display. If the first electrical signal Vref1 decreases by 1V, to ensure the current remains constant before and after the change in the first electrical signal Vref1, the third electrical signal VDATA can be reduced by 1V accordingly.

[0065] The second electrical signal Vref2 should be greater than the first voltage VDD to ensure that in the second dimming stage, that is, when the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, the voltage at the second connection point N2 will be raised by Vref2-VDD, and the voltage at the first connection point N1 remains unchanged at VDD, so that the gate-source voltage VGS of the eighth transistor D-TFT is less than the turn-on threshold, the eighth transistor D-TFT is turned off, and the light-emitting diode does not emit light.

[0066] Each transistor is configured to enter a corresponding state based on the working stage of the pixel circuit to compensate the drain of the eighth transistor in the first dimming stage, so that the gate-drain bias of the eighth transistor becomes more negative, thereby allowing the captured electrons to be released as much as possible to achieve the effect of hysteresis compensation.

[0067] The state includes on or off.

[0068] like Figure 2 As shown, the working cycle of the pixel circuit includes a first stage and a pulse width modulation (PWM) dimming stage located after the first stage. The first stage includes the following stages in sequence: an anode reset stage (Ta / r), an initialization stage (Tint), a compensation stage (Tcomp), and a data writing stage (Tprog).

[0069] The PWM dimming stage includes multiple dimming cycles, each of which includes: a first dimming stage (P1) and a second dimming stage (P2). The first dimming stage is a stage in which the light-emitting diode emits light for a long time and performs hysteresis compensation; the second dimming stage is a stage in which the light-emitting diode does not emit light.

[0070] In some embodiments, the first dimming stage may further include a hysteresis compensation stage, the duration of which is a target duration that is much shorter than the duration of the first dimming stage. The target duration may be user-defined, such as 30 us or 32 us.

[0071] The hysteresis compensation stage is used to perform short-term hysteresis compensation, and the light-emitting diode does not emit light during the hysteresis compensation stage.

[0072] The first level signal S1(n), the second level signal S2(n), the third level signal S3(n), the fourth level signal EM(n), the fifth level signal EM(n-1), and the sixth level signal EM(n-2) are signals used to control the on / off state of corresponding transistors. For example, when the received level signal is high, the corresponding transistor is on; when the received level signal is low, the corresponding transistor is off. With the exception of the eighth transistor D-TFT, the on / off state of the other transistors is controlled by the corresponding level signals. Before the PWM dimming stage, the seventh transistor T7 remains on; in the second dimming stage, the seventh transistor T7 is turned off.

[0073] In some embodiments, continue to refer to Figure 1 , the gate of the first transistor T1 is connected to the first level signal S1 (n); the gate of the second transistor T2 is connected to the second level signal S2 (n), and the gate of the third transistor T3 is connected to the third level signal S3 (n) through the inverter;

[0074] The gate of the fourth transistor T4 is connected to the fourth level signal EM(n) via an inverter, the gate of the fifth transistor T5 is connected to the fifth level signal EM(n-1) via an inverter, the gate of the sixth transistor T6 is connected to the sixth level signal EM(n-2), and the gate of the seventh transistor T7 is connected to the sixth level signal EM(n-2) via an inverter.

[0075] Each level signal is converted between high and low levels based on the working stage to control the state of the corresponding transistor; the ratio of the low level duration of the sixth level signal EM(n-2) to the dimming cycle duration is determined based on the brightness of the display.

[0076] In this embodiment, the inverter is used to invert the input level signal. For example, when the sixth level signal EM(n-2) is at a high level, the sixth transistor T6 is turned on. However, after the sixth level signal EM(n-2) is inverted by the inverter, the level input to the gate of the seventh transistor T7 becomes a low level, and the seventh transistor T7 is turned off.

[0077] Of course, in other embodiments, the inverter may not be provided, and the same function can be achieved by adjusting the level of the signal. The specific setting can be made according to actual needs, and this application does not limit it here.

[0078] Continue to refer Figure 2For each level signal, its high and low levels are adjusted accordingly with the changes in the working stage.

[0079] In some embodiments, the sixth level signal EM(n-2) is at a low level in the first phase and the first dimming phase (P1), and the on and off states of the sixth transistor T6 and the seventh transistor T7 are opposite.

[0080] Continue to refer Figure 2 In some embodiments, after entering the PWM dimming stage, when entering the first dimming stage (P1), after a certain delay, the fourth-level signal EM(n) and the fifth-level signal EM(n-1) may be set to a high level, so that the fourth transistor T4 and the fifth transistor T5 are turned off, the third-level signal S3(n) is set to a low level, and the third transistor T3 is turned on; hysteresis compensation is performed for a shorter target duration; and hysteresis compensation ends before the end of the first dimming stage. At this time, the fourth-level signal EM(n) and the fifth-level signal EM(n-1) are set to a low level, so that the fourth transistor T4 and the fifth transistor T5 are turned on, and the third-level signal S3(n) is set to a high level, and the third transistor T3 is turned off.

[0081] The delay duration and target duration can be customized by the user, and this application does not limit this.

[0082] In the data writing phase, the second level signal S2(n) is high level, and in other phases it remains low level. The changes of each level signal with the phase are as follows: Figure 2 As shown, no further details are given here.

[0083] According to the pixel circuit for a display screen provided in an embodiment of the present application, by applying a short negative gate-drain bias VGD in the first dimming stage, shallowly trapped electrons near the drain in the gate insulating layer can be released to restore the initial state, that is, by controlling the third transistor T3 to be turned on, the high-voltage second sub-voltage Vh is transmitted to the fourth connection point N4, that is, the drain of the eighth transistor D-TFT, so that VGD becomes more negative, so that the trapped electrons can be released as much as possible, so as to achieve the effect of hysteresis compensation, effectively reduce brightness fluctuations, and improve the display effect in low frame rate application scenarios; and the circuit structure is simple and easy to implement, occupies a small space, and has a low design cost.

[0084] The following uses OLED light-emitting diodes as an example to illustrate the circuit display principle.

[0085] In some embodiments, during the anode reset phase, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the eighth transistor D-TFT are turned on, and the other transistors are turned off; the second voltage is less than or equal to the turn-on voltage of the light emitting diode.

[0086] In this embodiment, the anode reset phase (Ta / r) is used to improve low grayscale non-uniformity and increase the contrast of the OLED.

[0087] like Figure 3 As shown, in the anode reset stage, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the eighth transistor D-TFT are turned on, and the other transistors are turned off. The second voltage is set to the first sub-voltage Vint, and the first sub-voltage Vint is less than or equal to the turn-on voltage of the light-emitting diode, preventing current from flowing through the light-emitting diode. At this time, the light-emitting diode does not work and displays a black image.

[0088] In some embodiments, during the initialization phase, the first transistor T1 , the fourth transistor T4 , the seventh transistor T7 , and the eighth transistor D-TFT are turned on, and the other transistors are turned off.

[0089] In this embodiment, the initialization phase (Tint) is used to initialize the voltages of the gate and source nodes of the eighth transistor D-TFT.

[0090] like Figure 4 As shown, during the initialization phase, the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor D-TFT are turned on, while the other transistors are turned off. The gate node of the eighth transistor D-TFT, i.e., the second connection point N2, is connected to the first electrical signal Vref1 via the first transistor T1 and initialized to the first electrical signal Vref1. The voltage Vg at the second connection point N2 equals Vref1. The source node of the eighth transistor D-TFT, i.e., the first connection point N1, is connected to the first voltage VDD via the fourth transistor T4 and initialized to the first voltage VDD. In this phase, the gate-source voltage VGS of the eighth transistor D-TFT is: Vref1-VDD.

[0091] In some embodiments, during the compensation phase, the first transistor T1 , the third transistor T3 , the seventh transistor T7 , and the eighth transistor D-TFT are turned on, and the other transistors are turned off.

[0092] In this embodiment, Figure 5 As shown, in the compensation stage (Tcomp), the first transistor T1, the third transistor T3, the seventh transistor T7 and the eighth transistor D-TFT are turned on, the other transistors are turned off, and the second voltage is set to the first sub-voltage Vint.

[0093] In this case, the gate of the eighth transistor D-TFT is connected to the first electrical signal Vref1 via the second connection point N2 and the first transistor T1, and the voltage Vg at the second connection point N2 is equal to Vref1; the drain of the eighth transistor D-TFT is connected to the first sub-voltage Vint via the fourth connection point N4 and the third transistor T3, and the voltage Vd at the fourth connection point N4 is equal to Vint; the absolute value of the gate-source voltage |VGS| of the eighth transistor D-TFT is greater than the absolute value of the turn-on threshold |Vth| of the eighth transistor D-TFT, that is, |Vref1-VDD|>|Vth|, and the eighth transistor D-TFT is turned on. Since the first sub-voltage Vint is relatively low, current flows from the first connection point N1 through the eighth transistor D-TFT and the third transistor T3 to Vint in sequence, causing the first connection point N1 to discharge through the third transistor T3, and the voltage at the first connection point N1 gradually decreases, and finally decreases to Vref1+|Vth|, and the eighth transistor D-TFT is turned off. At this time, the voltage Vg at the second connection point N2 = Vref1, and the voltage Vs at the first connection point N1 = Vref1 + |Vth|, which is equivalent to the first capacitor C1 storing the threshold voltage of the eighth transistor D-TFT to achieve threshold voltage compensation.

[0094] The duration of the compensation phase can be freely extended and will not be affected by the writing of the third electrical signal VDATA. It is understandable that at high frame rates, the time of one frame will become shorter. For example, at 60Hz, one frame is 16.6ms, and at 120Hz it is 8.3ms.

[0095] During the research and development process, the inventors discovered that in the related technology, the data writing stage and the threshold voltage compensation stage are simultaneous, and at a high refresh rate, the writing time will be limited and shortened, and the compensation time will also be shortened, resulting in the capacitor not accurately storing the Vth value.

[0096] In the present application, the data writing stage and the threshold voltage compensation stage are set as independent stages, so that the writing and compensation times do not affect each other. For example, if the writing time Tprog is 2us, Tcomp can also be extended to 19us, so that sufficient compensation effect can be guaranteed even at a high frame rate.

[0097] According to the pixel circuit for a display screen provided in an embodiment of the present application, by setting the data writing stage and the threshold voltage compensation stage as independent stages, the writing and compensation times do not affect each other, so that a sufficient compensation effect can be guaranteed even at a high frame rate, further improving the display effect.

[0098] In some embodiments, during the data writing phase, the second transistor T2 , the seventh transistor T7 , and the eighth transistor D-TFT are turned on, and the other transistors are turned off.

[0099] In this embodiment, Figure 6 As shown, in the data writing phase (Tprog), the second transistor T2, the seventh transistor T7, and the eighth transistor D-TFT are turned on, and the other transistors are turned off. The third electrical signal VDATA is transmitted to the gate of the eighth transistor D-TFT, that is, the second connection point N2, through the second transistor T2. At this time, the voltage Vg at the second connection point N2 is updated to: Vg=VDATA; one end of the first capacitor C1 and the second capacitor C2 connected in series is connected to the first voltage VDD, and the voltage value of the other end is Vg=VDATA. According to the capacitive coupling effect, the voltage at the first connection point N1 can be calculated as:

[0100]

[0101] Wherein, Vs is the voltage at the first connection point N1 during the data writing phase; Vth is the turn-on threshold of the eighth transistor D-TFT.

[0102] In some embodiments, in the first dimming stage, the fourth transistor T4 , the fifth transistor T5 , the seventh transistor T7 , and the eighth transistor D-TFT are turned on, and the other transistors are turned off.

[0103] In this embodiment, the dimming stage includes a first dimming stage and a second dimming stage. The first dimming stage is a stage where the LED emits light and performs hysteresis compensation. The second dimming stage is a stage where the LED does not emit light.

[0104] like Figure 7 As shown, in the first dimming stage (P1), the sixth transistor T6 is turned off and the seventh transistor T7 is turned on. At this time, the voltage at the first connection point N1, that is, the source voltage of the eighth transistor D-TFT is: Vs=VDD. Since the capacitor voltage cannot change suddenly, the voltage on the other side of the first capacitor C1, that is, the gate voltage of the eighth transistor D-TFT (that is, the voltage at the second connection point N2) is:

[0105]

[0106] Wherein, Vg is the voltage at the second connection point N2 in the first dimming stage.

[0107] The current Ioled flowing through the light-emitting diode is:

[0108]

[0109] Wherein, k is a parameter; VSG is the source-gate voltage of the eighth transistor D-TFT; and Vth is the turn-on threshold of the eighth transistor D-TFT.

[0110] , μ is the mobility of the driver tube, Cox is the oxide layer capacitance, and W / L is the width-to-length ratio of the driver tube channel. Among these three values, μ and Cox are fixed values, which are determined by the process of the tube itself. The channel width W and length L can be customized based on the user, such as setting the channel width W to 3um and the channel length L to 16um, etc. This application does not limit this.

[0111] At this time, the light-emitting diode emits light. It can be seen that the current Ioled flowing through the light-emitting diode is independent of the turn-on threshold Vth of the eighth transistor D-TFT and the first voltage VDD, and is only related to the first electrical signal Vref1 and the third electrical signal VDATA. In this way, the current magnitude is not affected by the drift of the threshold voltage (i.e., the turn-on threshold) of the D-TFT.

[0112] In some embodiments, as Figure 8 As shown, when entering the hysteresis compensation stage in the first dimming stage, the third transistor T3, the seventh transistor T7 and the eighth transistor D-TFT are turned on, and the other transistors are turned off.

[0113] In this embodiment, the hysteresis compensation stage lasts for a target duration, which is shorter than the duration of the first dimming stage. The target duration is a relatively short duration, such as a duration that is difficult for human eyes to perceive.

[0114] In the hysteresis compensation stage, the second voltage is adjusted to the second sub-voltage Vh. Figure 2 , the second sub-voltage Vh is greater than the first sub-voltage Vint.

[0115] In the actual implementation process, continue to refer to Figure 8 , the higher second sub-voltage Vh is transmitted to the fourth connection point N4 through the third transistor T3, that is, the drain voltage of the eighth transistor D-TFTD-TFT is Vh, and the drain voltage of the eighth transistor D-TFT increases from the previous smaller first sub-voltage Vint to the larger second sub-voltage Vh, which is equivalent to applying a more negative gate-drain bias (VGD) to the eighth transistor D-TFT, which can release as many shallowly trapped electrons in the gate insulating layer near the drain as possible to restore the initial state, thereby achieving the effect of hysteresis compensation.

[0116] In the hysteresis compensation stage, the fifth transistor T5 is turned off and the light-emitting diode does not emit light. However, since the duration of the hysteresis compensation stage is short, it is difficult for the human eye to distinguish. In the first dimming stage, the light-emitting diode perceived by the human eye can be roughly considered to be in a light-emitting state all the time, and the impact on the visual effect can be roughly ignored.

[0117] During the research and development process, the inventors also discovered that in related technologies, LTPO circuits mainly focus on compensating for the threshold voltage of the D-TFT without improving the hysteresis effect. The industry's latest 8T1C LTPO circuit compensates for the source end of the D-TFT. Compared with the previous 7T1C LTPO circuit, it mainly has an additional reset TFT transistor to compensate for the D-TFT source. The disadvantage is that it cannot directly compensate the drain of the D-TFT.

[0118] It's important to note that in LTPO TFT pixel circuits, flickering at low frame rates is caused not only by leakage current from the switching TFT but also by hysteresis of the D-TFT. At conventional frame rates (e.g., 60 Hz), the perceived brightness variations caused by D-TFT hysteresis are less noticeable. Instantaneous brightness variations due to hysteresis do not result in visible flicker at conventional refresh rates (e.g., 60 Hz) because the perceived brightness fluctuations are well below the flicker fusion threshold. However, minimizing temporal brightness fluctuations is crucial at low refresh rates, as human flicker sensitivity increases strongly at frequencies around 10-15 Hz. At these low frame rates, the pixel circuit's sensitivity to the dynamic behavior of the D-TFT (i.e., hysteresis) increases. Greater hysteresis leads to greater brightness fluctuations, and consequently, more perceptible flicker at low refresh rates.

[0119] The main reason for hysteresis is the inconsistency between the carrier capture and emission rates of D-TFT interface state traps. The trapped electrons cannot be released in time. Its principle is as follows:

[0120] (1) During the Vth sampling period, Vs is sampled and VGS_P is programmed based on the sampled Vth and VDATA. The emission cycle starts with the expected OLED current Ids_A to obtain the desired brightness.

[0121] (2) Luminous period: After data programming and Vth sampling, the pressure applied to the drive transistor causes the IV characteristics of the thin film transistor to drift. Since VGS is programmed to VGS_P, the emission current becomes Ids_B, resulting in brightness changes.

[0122] Related technologies often only focus on compensating the driving TFT (D-TFT) Vth without alleviating the hysteresis effect, which makes the LTPO screen prone to flickering problems and is unsatisfactory in terms of eye protection.

[0123] In the present application, the above method can be used to directly compensate the drain of the D-TFT, so that VGD becomes more negative, the captured electrons can be released as much as possible, and the IV curve of the driving thin film transistor drifts less and establishes faster. In this way, the amplitude and duration of the brightness fluctuation will be reduced, making the flicker more difficult to detect, improving the eye protection effect, and thus improving the display effect and user experience.

[0124] According to the pixel circuit for a display screen provided in an embodiment of the present application, by controlling the third transistor T3, the seventh transistor T7, and the eighth transistor D-TFT to be turned on for a short time during the first dimming stage, the high-voltage second sub-voltage Vh is transmitted to the fourth connection point N4, i.e., the drain of the eighth transistor D-TFTD-TFT, so that the VGD of the eighth transistor D-TFTD-TFT becomes more negative, thereby allowing the trapped electrons to be released as much as possible to achieve the effect of hysteresis compensation, thereby reducing the probability of stroboscopic display caused by low frame rate driving, effectively reducing brightness fluctuations, and improving the display effect in low frame rate application scenarios.

[0125] In some embodiments, in the second dimming stage, the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 are turned on, the other transistors are turned off, and the second electrical signal Vref2 is greater than the first voltage VDD.

[0126] In this embodiment, Figure 9 As shown, in the second dimming stage (P2), the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on, and the third transistor T3 and the seventh transistor T7 are turned off.

[0127] In actual implementation, the second electrical signal Vref2 is transmitted to the third connection point N3 through the sixth transistor T6. Since the capacitor voltage cannot change suddenly, the voltage on the other side of the first capacitor C1, that is, the gate of the eighth transistor D-TFT (the second connection point N2) is:

[0128]

[0129] Wherein, Vg is the voltage at the second connection point N2 in the second dimming stage.

[0130] The voltage at the first connection point N1 , ie, the source voltage of the eighth transistor D-TFT, is: Vs=Vdd.

[0131] Compared with the voltage at the second connection point N2 in the first dimming stage, the voltage at the second connection point N2 in the second dimming stage increases by Vref2-VDD, that is, the voltage at the second connection point N2 is raised; the voltage Vs at the first connection point N1 remains unchanged at VDD, so that the |VGS| of the eighth transistor D-TFT is less than |Vth|, the eighth transistor D-TFT is turned off, and the light-emitting diode stops emitting light.

[0132] According to the pixel circuit for a display screen provided in an embodiment of the present application, in the second dimming stage, the sixth transistor T6 is controlled to be turned on and the seventh transistor T7 is turned off, so that the voltage at the second connection point N2 is raised, causing the eighth transistor D-TFT to be turned off and the light-emitting diode to stop emitting light.

[0133] In some embodiments, during the PWM dimming stage, the frequency of the sixth level signal EM(n-2) is set to be greater than a preset dimming frequency.

[0134] In this embodiment, the preset frequency is a relatively high frequency and can be customized by the user. In some embodiments, the frequency of the sixth level signal EM(n-2) can be set according to the refresh rate of the display screen.

[0135] In the PWM dimming stage, the sixth level signal EM (n-2) is made to repeat continuously as a periodic signal, and the screen brightness is controlled by adjusting the proportion of the low level duration of the sixth level signal EM (n-2) within a dimming cycle. The low level duration corresponds to the duration of the first dimming stage. The higher the proportion of the low level duration, the longer the conduction time of the seventh transistor T7, the longer the duration of the first dimming stage, and the higher the screen brightness, and vice versa.

[0136] For example, at a 120Hz refresh rate, if one frame has three dimming cycles, the PWM dimming frequency is 360Hz. The pulse frequency of PWM dimming is typically much higher than the flicker frequency that the human eye can perceive (generally above 100Hz). This allows the human eye to perceive average brightness rather than rapid flickering. By adjusting the duty cycle of the sixth level signal EM(n-2) pulse (i.e., the ratio of the high-level time to the total cycle time within a dimming cycle), the average brightness of the light source can be controlled.

[0137] According to the pixel circuit for a display screen provided in an embodiment of the present application, while directly compensating the drain of the D-TFT, PWM dimming can also be added to the gate end of the eighth transistor D-TFT. By using high-frequency PWM dimming (such as 3840Hz, 2160Hz PWM dimming) at low brightness, the sub-pixel visual modulation (SVM) of the screen can be effectively reduced, thereby achieving an eye protection effect and further improving the display effect.

[0138] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0139] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of this application.

[0140] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0141] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0142] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A pixel circuit for a display screen, characterized in that: include: A first capacitor and a second capacitor connected in series, wherein the second capacitor is connected to a first voltage; a first transistor, wherein a drain of the first transistor is connected to a first electrical signal, and a source of the first transistor is connected to the first capacitor; a fourth transistor, an eighth transistor, and a fifth transistor connected in series, wherein the drain of the fourth transistor is connected to the first voltage, and the source of the fifth transistor is connected to the anode of the light-emitting diode; a sixth transistor and a seventh transistor connected in series, wherein the drain of the sixth transistor is connected to the second electrical signal, and the seventh transistor is connected to the source of the eighth transistor; a second transistor, wherein a source of the second transistor is connected to the gate of the eighth transistor; a third transistor, wherein a drain of the third transistor is connected to the second voltage, and a source of the third transistor is connected between the drain of the fifth transistor and the drain of the eighth transistor; The transistor is configured to enter a corresponding state based on a working stage of the pixel circuit to compensate the drain of the eighth transistor in a first dimming stage, wherein the state includes on or off, and the second voltage is adjusted accordingly based on a change in the working stage.

2. The pixel circuit for a display screen according to claim 1, wherein: In the first dimming stage, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are turned on, and the other transistors are turned off.

3. The pixel circuit for a display screen according to claim 2, wherein: The first dimming stage also includes a hysteresis compensation stage. When entering the hysteresis compensation stage, the third transistor, the seventh transistor and the eighth transistor are turned on, and the other transistors are turned off; the hysteresis compensation stage lasts for a target duration, which is less than the duration of the first dimming stage, and the second voltage is adjusted to a second sub-voltage.

4. The pixel circuit for a display screen according to claim 2, wherein: In the second dimming stage, the fourth transistor, the fifth transistor and the sixth transistor are turned on, the other transistors are turned off, the second electrical signal is greater than the first voltage, and the second dimming stage is a stage subsequent to and adjacent to the first dimming stage.

5. The pixel circuit for a display screen according to any one of claims 1 to 4, wherein: In the anode reset stage, the third transistor, the fifth transistor, the seventh transistor and the eighth transistor are turned on, and the other transistors are turned off; the second voltage is adjusted to a first sub-voltage, and the first sub-voltage is less than the turn-on voltage of the light emitting diode.

6. The pixel circuit for a display screen according to any one of claims 1 to 4, characterized in that: In the initialization stage, the first transistor, the fourth transistor, the seventh transistor, and the eighth transistor are turned on, and the other transistors are turned off.

7. The pixel circuit for a display screen according to any one of claims 1 to 4, characterized in that: In the compensation stage, the first transistor, the third transistor, the seventh transistor and the eighth transistor are turned on, and the other transistors are turned off; the second voltage is adjusted to a first sub-voltage, and the first sub-voltage is less than the second sub-voltage.

8. The pixel circuit for a display screen according to any one of claims 1 to 4, characterized in that: During the data writing phase, the second transistor, the seventh transistor, and the eighth transistor are turned on, and the other transistors are turned off.

9. The pixel circuit for a display screen according to any one of claims 1 to 4, characterized in that: The gate of the first transistor is connected to a first level signal; the gate of the second transistor is connected to a second level signal, and the gate of the third transistor is connected to a third level signal via an inverter; The gate of the fourth transistor is connected to the fourth level signal via an inverter, the gate of the fifth transistor is connected to the fifth level signal via an inverter, the gate of the sixth transistor is connected to the sixth level signal, and the gate of the seventh transistor is connected to the sixth level signal via an inverter; Each level signal is converted between high and low levels based on the working stage to control the state of the corresponding transistor; The ratio of the low level duration of the sixth level signal to the dimming cycle duration is determined based on the brightness of the display screen.

10. The pixel circuit for a display screen according to any one of claims 1 to 4, characterized in that: The transistor is a low-temperature polysilicon oxide thin film transistor.

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