Voltage regulation driving circuit and method thereof, display panel and display equipment

Abstract

The invention discloses a voltage regulation driving circuit and method, a display panel and a display device, and relates to the technical field of display, the circuit comprises a time sequence control module, and the time sequence control module is used for determining a gray scale mapping voltage according to the current pixel brightness degree of an input video image and a preset gray scale sequence; the power supply module is connected with the time sequence control module, and the power supply module is used for adjusting the original output voltage of the input video image into gray mapping voltage in the frame blanking period and then outputting the gray mapping voltage to the driving integration module; the signal processing module is respectively connected with the time sequence control module and the power supply module, and the signal processing module is used for collecting a gray mapping voltage sent by the power supply module to the driving integration module, generating a voltage compensation signal according to the gray mapping voltage and an original output voltage, and outputting the voltage compensation signal to the driving integration module; and the gray mapping voltage is fed back to the time sequence control module to correct the gray mapping voltage of the driving integration module, so that the display power consumption is reduced while the image display quality is ensured.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a voltage regulation driving circuit, a method thereof, a display panel, and a display device. Background Art

[0002] With the continuous development of display technologies, how to reduce the power consumption of LCD (Liquid Crystal Display) products has become an important development direction in the display field.

[0003] Currently, the power consumption of the OC (Output Coupling) terminals of LCD screens mainly focuses on four parts: TCON IC (Timing Controller Integrated Circuit), PMIC (Power Management Integrated Circuit), Driver IC (Driver Integrated Circuit), and Panel (display panel). Existing power consumption reduction technologies are mainly limited to the optimization of each part itself. For example, the TCON IC reduces power consumption by reducing Core Power, the PMIC uses multi-IC integration to achieve low power consumption, and the Panel uses new materials such as IGZO (Indium Gallium Zinc Oxide) and LTPS (Low Temperature Poly-Silicon) to reduce power consumption. However, although these technologies can reduce power consumption to a certain extent, they only perform limited optimization on each individual integrated circuit and do not fundamentally solve the problem of high overall power consumption. Especially in the Driver IC, a high AVDD voltage causes high power consumption problems, while reducing the AVDD voltage may lead to a decline in image display quality.

[0004] Therefore, how to reduce the power consumption of LCD products while ensuring image display quality is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0005] The main objective of the present application is to provide a voltage regulation driving circuit, a method thereof, a display panel, and a display device, aiming to reduce the power consumption of LCD products while ensuring image display quality.

[0006] To achieve the above objective, the present application provides a voltage regulation driving circuit, and the voltage regulation driving circuit includes:

[0007] The voltage regulation driving circuit includes:

[0008] A timing control module, which is configured to determine a grayscale mapping voltage according to the current pixel brightness level of an input video image and a preset grayscale level sequence;

[0009] A power supply module, which is connected to the timing control module and is configured to adjust the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module during the frame blanking period and then output it to the driving integration module;

[0010] A signal processing module, which is respectively connected to the timing control module and the power supply module, and is configured to collect the grayscale mapping voltage sent by the power supply module to the driving integration module, and generate a voltage compensation signal according to the grayscale mapping voltage and the original output voltage, and feedback it to the timing control module to correct the grayscale mapping voltage of the driving integration module.

[0011] In one embodiment, the signal processing module includes:

[0012] A signal acquisition unit, which is connected to the transmission link from the power supply module to the driving integration module, and is configured to collect the grayscale mapping voltage output by the power supply module to the driving integration module during the frame blanking period;

[0013] A control unit, which is respectively connected to the signal acquisition unit and the timing control module, and is configured to determine a voltage compensation signal according to the grayscale mapping voltage and the original output voltage, and send the voltage compensation signal to the timing control module.

[0014] In addition, to achieve the above object, the present application further provides a voltage regulation driving method, which is applied to the voltage regulation driving circuit described in any one of the above, and the voltage regulation driving method includes:

[0015] After the timing control module determines the grayscale mapping voltage according to the current pixel brightness level of the input video image and the preset grayscale level sequence, the power supply module adjusts the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module during the frame blanking period and then outputs it to the driving integration module;

[0016] The signal processing module collects the grayscale mapping voltage sent by the power supply module to the driving integration module, determines a voltage compensation signal according to the grayscale mapping voltage and the original output voltage, and feeds back the voltage compensation signal to the timing control module to correct the grayscale mapping voltage of the driving integration module.

[0017] In one embodiment, the step of the timing control module determining the gray-scale mapping voltage according to the current pixel brightness level of the input video image and the preset gray-scale level sequence includes:

[0018] Obtain the current pixel brightness level of the input video image through the timing control module;

[0019] Traverse the preset gray-scale level sequence according to the current pixel brightness level to obtain the gray-scale mapping voltage.

[0020] In one embodiment, the step of obtaining the current pixel brightness level of the input video image through the timing control module includes:

[0021] Collect the pixel distribution brightness of multiple consecutive frames of the input video image through the timing control module;

[0022] Detect whether the absolute brightness difference between the pixel distribution brightness of two adjacent frames exceeds a preset brightness mutation threshold, accumulate the consecutive frame numbers that satisfy that the absolute brightness difference does not exceed the brightness mutation threshold, and perform time filtering processing on the pixel distribution brightness of the consecutive frame numbers to obtain the current pixel brightness level.

[0023] In one embodiment, the step of traversing the preset gray-scale level sequence according to the current pixel brightness level to obtain the gray-scale mapping voltage includes:

[0024] Traverse the current pixel brightness level in sequence according to the preset gray-scale level sequence, where the gray-scale level sequence includes multiple preset gray-scale levels arranged in descending order of gray-scale;

[0025] If the current pixel brightness level is within the brightness level interval corresponding to the currently traversed preset gray-scale level, then use the currently traversed preset gray-scale level as the target gray-scale level to which the current pixel brightness level belongs, and use the preset voltage value mapped by the target gray-scale level as the gray-scale mapping voltage.

[0026] In one embodiment, determine the voltage compensation signal according to the gray-scale mapping voltage and the original output voltage;

[0027] Detect whether the voltage difference between the gray-scale mapping voltage and the original output voltage is greater than zero;

[0028] If the voltage difference is greater than zero, determine that the voltage compensation signal is the negative voltage difference;

[0029] If the voltage difference is less than zero, determine that the voltage compensation signal is the positive voltage difference.

[0030] In one embodiment, the step of feeding back the voltage compensation signal to the timing control module to correct the gray-scale mapping voltage of the driving integrated module includes:

[0031] After the timing control module receives the voltage compensation signal fed back by the signal processing module, the voltage compensation signal is superimposed on the gray-scale mapping voltage of the driving integrated module to obtain a corrected gray-scale mapping voltage.

[0032] In addition, to achieve the above object, the present application further provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the voltage regulation driving circuit described in any one of the above.

[0033] In addition, to achieve the above object, the present application further provides a display device, which includes the above display panel;

[0034] Or a memory, a processor, and a voltage regulation driving program stored on the memory and executable on the processor. When the processor executes the voltage regulation driving program, the steps of the voltage regulation driving method described in any one of the above are implemented.

[0035] The voltage regulation driving circuit provided by the present application, through the collaborative optimization of the timing control module, the power supply module, the signal processing module, and the driving integrated module, significantly reduces the driving power consumption of the LCD while ensuring the image display quality. Specifically, based on the current pixel brightness level of the input video image and the preset gray-scale level sequence, the timing control module can effectively match the gray-scale mapping voltage corresponding to the current pixel brightness level, achieving the purpose of adaptively and dynamically adjusting the voltage according to the current pixel brightness level, avoiding the high power consumption problem caused by a single fixed high AVDD voltage, and fundamentally reducing the overall driving power consumption of the LCD; Next, during the frame blanking period, the power supply module switches the original output voltage of the input video image to the gray-scale mapping voltage and then outputs it to the driving integrated module, realizing voltage regulation during the non-display period between frames (i.e., the frame blanking period) to avoid image display interference caused by voltage fluctuations and ensuring the stability of the gray-scale mapping voltage input to the driving integrated module; At this time, the signal processing module synchronously collects the gray-scale mapping voltage output by the power supply module to the driving integrated module during the frame blanking period, generates a voltage compensation signal based on the gray-scale mapping voltage and the original output voltage, and feeds it back to the timing control module to correct the gray-scale mapping voltage of the driving integrated module, thereby effectively eliminating the voltage deviation caused by circuit loss or noise, preventing power consumption waste caused by too high gray-scale mapping voltage or display abnormality caused by too low voltage, and finally achieving the purpose of significantly reducing the driving power consumption of the LCD while ensuring the image display quality. Description of the Drawings

[0036] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or in the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 is the structural block diagram of the first embodiment of the voltage regulation drive circuit of this application;

[0039] Figure 2 is the schematic diagram of the drive process involved in the first embodiment of the voltage regulation drive circuit of this application;

[0040] Figure 3 is the schematic diagram of the hardware architecture involved in the first embodiment of the voltage regulation drive circuit of this application;

[0041] Figure 4 is the schematic diagram of the frame filtering period involved in the voltage regulation drive method of this application;

[0042] Figure 5 is the schematic diagram of the structure of the display device involved in the solution of the embodiment of this application.

[0043] Explanation of the reference numerals in the drawings:

[0044] 10. Timing control module; 20. Power supply module; 30. Drive integration module; 40. Signal processing module; 41. Signal acquisition unit; 42. Control unit.

[0045] The realization of the objectives of this application, functional features, and advantages will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0046] The following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0047] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of this application, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0048] In addition, if the descriptions such as "first" and "second" are involved in the embodiments of the present application, these descriptions of "first", "second", etc. are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0049] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0050] With the continuous development of display technology, how to reduce the power consumption of LCD (Liquid Crystal Display) products has become an important development direction in the display field.

[0051] Currently, the power consumption of the OC (Output Coupling) terminals of the LCD screen is mainly concentrated in four parts: TCON IC (Timing Controller Integrated Circuit), PMIC (Power Management Integrated Circuit), Driver IC (Driver Integrated Circuit), and Panel (display panel). The existing power consumption reduction technologies are mainly limited to the optimization of each part itself. For example, the TCON IC reduces power consumption by reducing the Core Power, the PMIC uses multi-IC integration to achieve low power consumption, and the Panel uses new materials such as IGZO (Indium Gallium Zinc Oxide) and LTPS (Low Temperature Poly-Silicon) to reduce power consumption. However, although these technologies can reduce power consumption to a certain extent, they only perform limited optimization for each individual integrated circuit and do not fundamentally solve the problem of high overall power consumption. Especially in the Driver IC, the high AVDD voltage causes high power consumption problems, while reducing the AVDD voltage may lead to a decline in image display quality.

[0052] Therefore, while ensuring the image display quality, how to reduce the power consumption of LCD products is a technical problem that needs to be solved urgently at present.

[0053] To solve the display defects existing in the above-mentioned existing LCD display technology, the present application provides a voltage regulation driving circuit and method, a display panel, and a display device.

[0054] An embodiment of the present application provides a voltage regulation driving circuit. Refer to Figure 1 as shown Figure 1 is a structural block diagram of the first embodiment of the voltage regulation driving circuit of the present application. The voltage regulation driving circuit includes:

[0055] A timing control module 10, which is configured to determine a gray-scale mapping voltage according to the current pixel brightness degree of the input video image and a preset gray-scale level sequence.

[0056] In this embodiment, refer to Figures 1 to 2 , after the video signal of the input video image is input to the timing control module 10, the timing control module 10 acquires the pixel point data of each frame of the input video image frame by frame to calculate the current pixel brightness degree, which is used to characterize the overall pixel brightness feature of the input video image. Since the preset gray-scale level sequence is composed of multiple preset gray-scale levels arranged from high to low in gray-scale, after determining the current pixel brightness degree of the input video image, the preset gray-scale level that matches the current pixel brightness degree can be found from the preset gray-scale level sequence, and the voltage preset value mapped by the matched preset gray-scale level is used as the gray-scale mapping voltage corresponding to the current pixel brightness degree, realizing the adaptive dynamic voltage regulation based on the current pixel brightness degree, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, and thus significantly reducing the overall driving power consumption of the LCD.

[0057] It should be noted that the timing control module 10 can be understood as a TCON IC (Timing Controller Integrated Circuit), and this timing control integrated circuit is at least integrated with Figure 3 an image detection module and an image AVDD controller module shown in the communication connection. Among them, the image detection module is pre-set with a gray-scale level sequence, which is provided with multiple preset gray-scale levels arranged from high to low in gray-scale, and the voltage preset value mapped by each preset gray-scale level. The expression of this gray-scale level sequence is as follows:

[0058] AVDD0[[L(01)] [L(02)] [L(03)]…[L(0n)]]

[0059] AVDD1[[L(11)] [L(12)] [L(13)]…[L(1n)]]

[0060] AVDD2[[L(21)] [L(22)] [L(23)]…[L(2n)]]

[0061] AVDD3[[L(31)] [L(32)] [L(33)]…[L(3n)]]

[0062] AVDD4[[L(41)] [L(42)] [L(43)]…[L(4n)]]

[0063] AVDD5[[L(51)] [L(52)] [L(53)]…[L(5n)]]

[0064] That is, the gray level sequence can be set with 6 preset gray levels arranged from high to low in gray scale, and the number of preset gray levels can also be customized according to application requirements, which is not limited in this application. Specifically, each voltage preset value is used to mark the corresponding preset gray level. For example, the preset gray level corresponding to the voltage AVDD0 is marked as the AVDD0 level, and the brightness level interval where the AVDD0 level is located is [[L(01)][L(02)][L(03)]…[L(0n)]], where [L(01)], [L(02)], [L(03)], [L(03)], …, and …[L(0n)] respectively represent the gray values of this brightness level interval. In addition, AVDD0 level > AVDD1 level > AVDD2 level > AVDD3 level > AVDD4 level > AVDD5 level, that is, the highest gray value brightness is the AVDD0 level, and the lowest gray value brightness is the AVDD5 level.

[0065] In a specific embodiment, referring to Figures 2 to 3 , the image detection module first collects the pixel point data of each frame of the input video image frame by frame; subsequently, the image detection module converts the pixel data of each pixel point in each frame of the input video image into the corresponding brightness gray value according to the time sequence (i.e., the chronological order); specifically, assume Figure 2The checkerboard-shaped image shown is the input video image. Each rectangular shape in the input video image represents a pixel point. By accumulating the product data of the red pixel value and the red weight ratio, the product data of the green pixel value and the green weight ratio, and the product data of the blue pixel value and the blue weight ratio in the pixel at the second row and second column, the brightness gray value of the pixel at the second row and second column can be accurately obtained as 32. Next, the gray average value of all the brightness gray values of each frame of the image is further calculated, and this gray average value is used as the pixel distribution brightness of this frame of the picture. Subsequently, the image detection module performs temporal filtering processing based on the pixel distribution brightness of all frames, and can accurately obtain the current pixel brightness degree reflecting the gray type of the input image. Next, through the communication connection between the image detection module and the image AVDD controller module, the image detection module transmits the current pixel brightness degree reflecting the gray type of the input image to the image AVDD controller module. Subsequently, the image AVDD controller module queries the preset gray level sequence, accurately matches the preset gray level corresponding to the current pixel brightness degree, and uses the voltage preset value mapped by the matched preset gray level as the gray mapping voltage corresponding to the current pixel brightness degree, so as to achieve adaptive dynamic voltage regulation based on the current pixel brightness degree, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD.

[0066] The power supply module 20, the power supply module 20 is connected to the timing control module 10, and the power supply module 20 is configured to adjust the original output voltage of the input video image to the gray mapping voltage sent by the timing control module 10 during the frame blanking period and then output it to the driving integration module 30.

[0067] In this embodiment, the power supply module 20 provided in the present application stores the original output voltage required to output the input video image of the current frame to the driving integration module 30. Exemplarily, referring to Figure 3 , the timing control module 10 establishes a connection with the power supply module 20 based on the IIC W / R communication method. That is, the timing control module 10 sends the corresponding voltage preset value (i.e., the gray mapping voltage) to the power supply module 20 through the IIC W / R communication method according to the matched preset gray level. At this time, after receiving the gray mapping voltage sent by the timing control module 10, the power supply module 20 immediately triggers a preset voltage regulation command, and switches the original output voltage to the gray mapping voltage (i.e., Figure 2 the shown V_avdd) during the non-display period between the current frame and the next frame (i.e., the frame blanking period) and transmits it to the driving integration module 30, realizing voltage regulation during the non-display period between frames to avoid screen flicker caused by voltage fluctuations, and further improving the image display quality of the display device.

[0068] A signal processing module 40, the signal processing module 40 is respectively connected to the timing control module 10 and the power supply module 20, and the signal processing module 40 is configured to collect the gray-scale mapping voltage sent by the power supply module 20 to the drive integration module 30, and generate a voltage compensation signal based on the gray-scale mapping voltage and the original output voltage, and feedback it to the timing control module 10 to correct the gray-scale mapping voltage of the drive integration module 30.

[0069] In this embodiment, referring to Figure 1 , the signal processing module 40 is connected to the transmission link for the power supply module 20 to provide the gray-scale mapping voltage to the drive integration module. The signal processing module 40 synchronously collects the gray-scale mapping voltage sent by the power supply module 20 to the drive integration module 30 during the frame blanking period; next, after generating a voltage compensation signal based on the gray-scale mapping voltage and the original output voltage, it is fed back to the timing control module 10 to correct the gray-scale mapping voltage of the drive integration module 30, thereby effectively eliminating the voltage deviation caused by circuit loss or noise, preventing power consumption waste caused by too high gray-scale mapping voltage or display abnormality caused by too low voltage, and finally realizing ensuring the image display quality while significantly reducing the LCD drive power consumption.

[0070] In a specific embodiment, referring to Figure 2 , the signal processing module 40 establishes a connection with the timing control module 10 based on the IIC W / R communication method. The timing control module 10 establishes a connection with the power supply module 20 based on the IIC W / R communication method. After the power supply module 20 feeds back the original output voltage required for displaying the input video image of the current frame to the timing control module 10 through the IIC W / R communication method, the timing control module 10 sends the original output voltage to the signal processing module 40 through the IIC W / R communication method for the signal processing module 40 to store the original output voltage.

[0071] Further, in some feasible embodiments, the signal processing module 40 includes:

[0072] A signal acquisition unit 41, the signal acquisition unit 41 is connected to the transmission link from the power supply module 20 to the drive integration module 30, and the signal acquisition unit 41 is configured to collect the gray-scale mapping voltage output by the power supply module 20 to the drive integration module 30 during the frame blanking period.

[0073] In this embodiment, referring to Figure 2, the signal acquisition unit 41 in the signal processing module 40 is connected to the transmission link through which the power supply module 20 provides the gray-scale mapping voltage to the driving integration module. Specifically, when the power supply module 20 switches the original output voltage to the gray-scale mapping voltage and transmits it to the driving integration module 30 during the frame blanking period, the signal acquisition unit 41 samples the gray-scale mapping voltage transmitted from the power supply module 20 to the driving integration module 30 through its own ADC sampling channel during the frame blanking period.

[0074] It should be noted that the signal acquisition unit 41 can be understood as an analog-to-digital converter.

[0075] A control unit 42, the control unit 42 is respectively connected to the signal acquisition unit 41 and the timing control module 10, and the control unit 42 is configured to determine a voltage compensation signal based on the gray-scale mapping voltage and the original output voltage, and send the voltage compensation signal to the timing control module 10.

[0076] In this embodiment, referring to Figure 2 , according to the communication connection between the control unit 42 and the signal acquisition unit 41, the control unit 42 can receive the gray-scale mapping voltage sent by the signal acquisition unit 41; according to the connection established by the control unit 42 with the timing control module 10 based on the IIC W / R communication method, the control unit 42 can also receive the original output voltage required for the power supply module 20 to output to the driving integration module 30 to display the input video image of the current frame fed back by the timing control module 10; next, an Figure 3 The image quality compensation module shown is used to determine the voltage compensation signal by comparing the gray-scale mapping voltage and the original output voltage, and send the voltage compensation signal to the timing control module 10 through the IIC W / R communication method, so that the timing control module 10 can perform secondary compensation on the gray-scale mapping voltage of the driving integration module 30, preventing excessive power consumption caused by too high gray-scale mapping voltage or display anomalies caused by too low voltage, and finally achieving the guarantee of image display quality while significantly reducing the LCD driving power consumption.

[0077] In summary, through the collaborative optimization of the timing control module 10, the power supply module 20, the signal processing module 40, and the drive integration module 30, the voltage regulation drive circuit provided in this application significantly reduces the LCD drive power consumption while ensuring the image display quality. Specifically, based on the current pixel brightness level of the input video image and the preset gray level sequence, the timing control module 10 can effectively match the gray mapping voltage corresponding to the current pixel brightness level, achieving the purpose of adaptively and dynamically adjusting the voltage according to the current pixel brightness level, avoiding the high power consumption problem caused by a single fixed high AVDD voltage, and fundamentally reducing the overall drive power consumption of the LCD. Next, during the frame blanking period, the power supply module 20 switches the original output voltage of the input video image to the gray mapping voltage and outputs it to the drive integration module 30, realizing voltage regulation during the non-display period between frames (i.e., the frame blanking period) to avoid image display interference caused by voltage fluctuations and ensuring the stability of the gray mapping voltage input to the drive integration module 30. At this time, the signal processing module 40 synchronously collects the gray mapping voltage output by the power supply module 20 to the drive integration module 30 during the frame blanking period, generates a voltage compensation signal based on the gray mapping voltage and the original output voltage, and feeds it back to the timing control module 10 to correct the gray mapping voltage of the drive integration module 30, thereby effectively eliminating the voltage deviation caused by circuit loss or noise, preventing power consumption waste caused by too high a gray mapping voltage or display anomalies caused by too low a voltage, and ultimately achieving the goal of significantly reducing the LCD drive power consumption while ensuring the image display quality.

[0078] Further, based on the first embodiment of the voltage regulation drive circuit of this application, a second embodiment of the voltage regulation drive method of this application is proposed. Refer to Figure 3 , Figure 3 which is a schematic flowchart of the second embodiment of the voltage regulation drive method of this application.

[0079] The voltage regulation drive method of this application is applied to the voltage regulation drive circuit in any of the above, and the voltage regulation drive method of this application is executed by a display device applied to the voltage regulation drive circuit. The voltage regulation drive method of this application includes the following implementation steps S10 to step S20.

[0080] Step S10: After the timing control module 10 determines the gray mapping voltage based on the current pixel brightness level of the input video image and the preset gray level sequence, during the frame blanking period, the power supply module 20 adjusts the original output voltage of the input video image to the gray mapping voltage sent by the timing control module 10 and outputs it to the drive integration module 30.

[0081] In this embodiment, refer to Figures 1 to 2, after the video signal of the input video image is input to the timing control module 10, the timing control module 10 collects the pixel data of each frame of the input video image frame by frame to calculate the current pixel brightness level, and this current pixel brightness level is used to characterize the overall pixel brightness feature of the input video image. Since the preset gray level sequence is composed of multiple preset gray levels arranged from high to low in gray scale, after determining the current pixel brightness level of the input video image, the preset gray level that matches the current pixel brightness level can be found from the preset gray level sequence, and the preset voltage value mapped by the matched preset gray level is used as the gray scale mapping voltage corresponding to the current pixel brightness level, realizing the adaptive dynamic voltage regulation based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, and thus significantly reducing the overall driving power consumption of the LCD. Next, since the timing control module 10 establishes a connection with the power supply module 20 based on the IIC W / R communication method, the timing control module 10 sends the corresponding voltage preset value (i.e., the gray scale mapping voltage) to the power supply module 20 through the IIC W / R communication method according to the matched preset gray level. At this time, after receiving the gray scale mapping voltage sent by the timing control module 10, the power supply module 20 immediately triggers the preset voltage regulation instruction, and switches the original output voltage of the input video image to the gray scale mapping voltage (i.e., Figure 2 the V_avdd shown) during the non-display period between the current frame and the next frame (i.e., the frame blanking period) and transmits it to the driving integration module 30, realizing the voltage regulation during the non-display period between frames to avoid screen flicker caused by voltage fluctuations, and thus improving the image display quality of the display device.

[0082] Step S20: The signal processing module 40 collects the gray scale mapping voltage sent by the power supply module 20 to the driving integration module 30, determines a voltage compensation signal according to the gray scale mapping voltage and the original output voltage, and feeds back the voltage compensation signal to the timing control module 10 to correct the gray scale mapping voltage of the driving integration module 30.

[0083] In this embodiment, referring to Figure 1 , the signal processing module 40 is connected to the transmission link through which the power supply module 20 provides the gray scale mapping voltage to the driving integration module. The signal processing module 40 synchronously collects the gray scale mapping voltage sent by the power supply module 20 to the driving integration module 30 during the frame blanking period; next, after generating a voltage compensation signal according to the gray scale mapping voltage and the original output voltage, it is fed back to the timing control module 10 to correct the gray scale mapping voltage of the driving integration module 30, thus effectively eliminating the voltage deviation caused by circuit loss or noise, preventing power consumption waste caused by too high gray scale mapping voltage or display abnormality caused by too low voltage, and finally realizing ensuring the image display quality while significantly reducing the LCD driving power consumption.

[0084] Further, in some feasible embodiments, the above step S10: The timing control module 10 determines the gray-scale mapping voltage according to the current pixel brightness level of the input video image and a preset gray-scale level sequence, and may further include the following implementation steps S101 to step S102.

[0085] Step S101: Obtain the current pixel brightness level of the input video image through the timing control module 10;

[0086] Step S102: Traverse the preset gray-scale level sequence according to the current pixel brightness level to obtain the gray-scale mapping voltage.

[0087] In this embodiment, after obtaining the current pixel brightness level of the input video image through the timing control module 10, traverse the preset gray-scale level sequence according to the current pixel brightness level to determine the voltage preset value corresponding to the target gray-scale level to which the current pixel brightness level belongs as the gray-scale mapping voltage, realizing the adaptive dynamic voltage regulation based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, and thus significantly reducing the overall driving power consumption of the LCD.

[0088] In a specific embodiment, if the current pixel brightness level is [L(23)], the expression for determining the gray-scale mapping voltage by traversing the preset gray-scale level sequence based on the current pixel brightness level is as follows:

[0089]

[0090] Specifically, traverse whether the brightness level interval [[L(01)] [L(02)] [L(03)]…[L(0n)]] corresponding to the AVDD0 level exists the current pixel brightness level [L(23)]; if the brightness level interval corresponding to the AVDD0 level does not exist the [L(23)], then continue to traverse whether the brightness level interval [[L(11)] [L(12)] [L(13)]…[L(1n)]] corresponding to the AVDD1 level exists the current pixel brightness level [L(23)]; if the brightness level interval corresponding to the AVDD1 level does not exist the [L(23)], then continue to traverse whether the brightness level interval [[L(21)] [L(22)] [L(23)]…[L(2n)]] corresponding to the AVDD2 level exists the current pixel brightness level [L(23)]; since the brightness level interval [[L(21)] [L(22)] [L(23)]…[L(2n)]] corresponding to the AVDD2 level exists the current pixel brightness level [L(23)], then determine that the gray-scale mapping voltage represented by AVDD(IP) is the voltage preset value AVDD3.

[0091] Further, in some other feasible embodiments, step S101: obtaining the current pixel brightness level of the input video image through the timing control module 10 may further include the following implementation steps S1011 to S1012.

[0092] Step S1011: Collect the pixel distribution brightness of multiple consecutive frames of the input video image through the timing control module 10.

[0093] In this embodiment, the pixel distribution brightness of multiple consecutive frames of the input video image is collected through the timing control module 10. Specifically, taking five consecutive frames of the input video image as a frame filtering period, where Figure 4 the frames 1 to 5 shown are the first frame filtering period, Figure 4 the frames n to n + 4 shown are the nth frame filtering period. This way of setting the frame filtering period is based on the dynamic characteristics of the video signal and actual processing requirements, which can not only capture the short-term changes of the video content, but also not cause processing delays due to too long a period, affecting the real-time performance of the system. Taking Figure 4 the frame filtering period of the frames 1 to 5 shown as an example, the timing control module 10 sequentially collects the pixel point data of the frames 1 to 5 of the input video image, and converts the data of each pixel point in each frame image into the corresponding brightness gray value to calculate the gray average value of all the brightness gray values of each frame image, and takes the gray average value of each frame image as the pixel distribution brightness of the corresponding frame.

[0094] It should be noted that the frame filtering period can be customized according to the user's needs, and this application does not make any restrictions here.

[0095] Step S1012: Detect whether the absolute brightness difference between the pixel distribution brightness of two adjacent frames exceeds a preset brightness mutation threshold, and accumulate the number of consecutive frames that satisfy that the absolute brightness difference does not exceed the brightness mutation threshold, and perform time filtering processing on the pixel distribution brightness of the consecutive frames to obtain the current pixel brightness level.

[0096] In this embodiment, the absolute brightness difference between the pixel distribution brightness of two adjacent frames of images is calculated, and this absolute brightness difference is compared with a preset brightness mutation threshold. When the absolute brightness difference exceeds the preset brightness mutation threshold, an abnormal brightness change can be detected in a timely manner, providing an accurate judgment basis for subsequent corresponding processing measures; next, the number of consecutive frames that satisfy the condition that the absolute brightness difference is less than the brightness mutation threshold is accumulated, so as to comprehensively consider the brightness stability of the input video image over a period of time, and can effectively filter out short-term and non-persistent brightness fluctuation interferences; next, time filtering is performed on the pixel distribution brightness of the accumulated consecutive frames, further smoothing the brightness data, removing the influence of noise and local brightness anomalies, obtaining a more stable and accurate current pixel brightness level, and further being able to more truly reflect the overall brightness state of the input video image at the current moment.

[0097] In a specific embodiment, assume that the pixel distribution brightness of the input video image at frame 1 is L1, the pixel distribution brightness of the input video image at frame 2 is L2, the pixel distribution brightness of the input video image at frame 3 is L3, the pixel distribution brightness of the input video image at frame 4 is L4, and the pixel distribution brightness of the input video image at frame 5 is L5; if |L1 - L2| < Lth, |L2 - L3| < Lth, |L3 - L4| < Lth, |L4 - L5| > Lth, then the number of consecutive frames that satisfy the condition that the absolute brightness difference is less than the brightness mutation threshold Lth is frames 1 to 4, so as to filter out the brightness mutation of L5; next, based on the pixel distribution brightness corresponding to each of frames 1 to 4, an average value process is performed to obtain the current pixel brightness level of the input video image.

[0098] Further, in some feasible embodiments, the above step S102: traversing a preset gray level sequence according to the current pixel brightness level to obtain a gray mapping voltage may further include the following implementation steps S1021 to S1022.

[0099] Step S1021: Traverse the current pixel brightness level in sequence according to a preset gray level sequence, where the gray level sequence includes a plurality of preset gray levels arranged in descending order of gray scale.

[0100] In this embodiment, traversing the current pixel brightness level in sequence according to a preset gray level sequence (a plurality of preset gray levels arranged in descending order of gray scale) can comprehensively and orderly check the matching possibility between the current pixel brightness level and each gray level. This traversing method ensures that no potential gray level attribution situation is missed, providing a complete search range for accurately determining the target gray level.

[0101] Step S1022: If the current pixel brightness level is within the brightness level range corresponding to the currently traversed preset gray level, then use the currently traversed preset gray level as the target gray level to which the current pixel brightness level belongs, and use the preset voltage value mapped by the target gray level as the gray scale mapping voltage.

[0102] In this embodiment, if the current pixel brightness level is within the brightness level range corresponding to the currently traversed preset gray level, then use the currently traversed preset gray level as the target gray level to which the current pixel brightness level belongs, and use the preset voltage value mapped by the target gray level as the gray scale mapping voltage, achieving adaptive dynamic voltage regulation based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD.

[0103] Further, in some other feasible embodiments, the above step S20: determining the voltage compensation signal according to the gray scale mapping voltage and the original output voltage may further include the following implementation steps S201 to S203.

[0104] Step S201: Detect whether the voltage difference between the gray scale mapping voltage and the original output voltage is greater than zero.

[0105] In this embodiment, detecting whether the voltage difference between the gray scale mapping voltage and the original output voltage is greater than zero can accurately determine the voltage difference situation between the two, providing a clear judgment basis for determining the direction of the voltage compensation signal in the subsequent steps.

[0106] Step S202: If the voltage difference is greater than zero, then determine that the voltage compensation signal is a negative voltage difference.

[0107] In this embodiment, if the voltage difference is greater than zero, then determine that the voltage compensation signal is a negative voltage difference. Exemplarily, if the voltage difference ΔV is greater than zero (i.e., the voltage difference ΔV is a positive value), determine that the voltage compensation signal is a negative voltage difference, and this negative voltage difference is the opposite number -ΔV of ΔV.

[0108] In a specific embodiment,

[0109] AVDD(ΔIP1) = [+VD(01), +VD(02), +VD(03), ……, +VD(0n)]; AVDD(ΔIP2) = [-VD(01), -VD(02), -VD(03), ……, -VD(0n)]. The AVDD(ΔIP1) region is set to store the voltage difference between the grayscale mapped voltage and the original output voltage, while the AVDD(ΔIP2) region stores the compensation value corresponding to each voltage difference. For example, if the voltage difference ΔV between the grayscale mapped voltage and the original output voltage is +VD(01), the compensation value corresponding to +VD(01) can be found from the AVDD(ΔIP2) region as -VD(01).

[0110] Step S203: If the voltage difference is less than zero, determine that the voltage compensation signal is the positive voltage difference.

[0111] In this embodiment, if the voltage difference is less than zero, determine that the voltage compensation signal is the positive voltage difference. Exemplarily, if the voltage difference is less than zero (i.e., the voltage difference ΔV is negative), determine that the voltage compensation signal is the positive voltage difference, and this positive voltage difference is the opposite number +ΔV of ΔV.

[0112] In summary, by comparing the voltage difference between the grayscale mapped voltage and the original output voltage, this application realizes compensation with voltage signals in the opposite direction according to the actual voltage difference situation, ensures the accuracy of the grayscale mapped voltage output, prevents power consumption waste caused by too high grayscale mapped voltage or display abnormalities caused by too low grayscale mapped voltage, and finally realizes ensuring the image display quality while significantly reducing the LCD driving power consumption.

[0113] Further, in some feasible embodiments, the above step S20: feeding back the voltage compensation signal to the timing control module 10 to correct the grayscale mapped voltage of the drive integration module 30 may further include the following implementation step A10.

[0114] Step A10: After the timing control module 10 receives the voltage compensation signal fed back by the signal processing module 40, superimpose the voltage compensation signal on the grayscale mapped voltage of the drive integration module 30 to obtain the corrected grayscale mapped voltage.

[0115] In this embodiment, after the timing control module 10 receives the voltage compensation signal fed back by the signal processing module 40, superimpose the voltage compensation signal on the grayscale mapped voltage of the drive integration module 30 to obtain the corrected grayscale mapped voltage, thereby realizing the purpose of secondary compensation for the grayscale mapped voltage of the drive integration module 30, preventing power consumption waste caused by too high grayscale mapped voltage or display abnormalities caused by too low grayscale mapped voltage, and finally realizing ensuring the image display quality while significantly reducing the LCD driving power consumption.

[0116] In addition, the present application further provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the voltage regulation driving circuit according to any one of the above.

[0117] In addition, the present application further provides a display device. Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the display device involved in the embodiment solution of the present application. The display device in the embodiment of the present application may specifically be a device that locally runs the voltage regulation driving method.

[0118] As Figure 5 shown, the display device in the embodiment of the present application may include: a display panel or a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard). Optionally, the user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0119] The memory 1005 is disposed on the display device main body. A program is stored on the memory 1005, and when the program is executed by the processor 1001, corresponding operations are realized. The memory 1005 is further used to store parameters for the display device to use. The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. Optionally, the memory 1005 may also be a storage device independent of the foregoing processor 1001.

[0120] Those skilled in the art can understand that Figure 5 the display device structure shown in

[0121] does not constitute a limitation on the display device, and may include more or fewer components than shown in the figure, or combine some components, or have different component arrangements. Figure 5 As

[0122] shown, in Figure 5 the display device shown, the processor 1001 may be used to call the voltage regulation driving program stored in the memory 1005 and execute the steps of the voltage regulation driving method as described above.

[0123] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article or system. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or system including that element.

[0124] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0125] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that makes a contribution to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium as described above (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to enable a display device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0126] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A voltage regulation driving circuit, characterized in that, The voltage regulation and driving circuit includes: A timing control module, which is configured to determine a gray-scale mapping voltage according to the current pixel brightness level of the input video image and a preset gray-scale level sequence; A power supply module, which is connected to the timing control module. The power supply module is configured to adjust the original output voltage of the input video image to the gray-scale mapping voltage sent by the timing control module during the frame blanking period and then output it to the driving integration module; A signal processing module, which is respectively connected to the timing control module and the power supply module. The signal processing module is configured to collect the gray-scale mapping voltage sent by the power supply module to the driving integration module, and generate a voltage compensation signal according to the gray-scale mapping voltage and the original output voltage, and feedback it to the timing control module to correct the gray-scale mapping voltage of the driving integration module.

2. The voltage regulation driving circuit according to claim 1, wherein The signal processing module includes: A signal acquisition unit, which is connected to the transmission link from the power supply module to the driving integration module. The signal acquisition unit is configured to collect the gray-scale mapping voltage output by the power supply module to the driving integration module during the frame blanking period; A control unit, which is respectively connected to the signal acquisition unit and the timing control module. The control unit is configured to determine a voltage compensation signal according to the gray-scale mapping voltage and the original output voltage, and send the voltage compensation signal to the timing control module.

3. A voltage regulation driving method, characterized in that, The voltage regulation and driving method is applied to the voltage regulation and driving circuit according to any one of claims 1 to 2. The voltage regulation and driving method includes: After the timing control module determines the gray-scale mapping voltage according to the current pixel brightness level of the input video image and the preset gray-scale level sequence, the power supply module adjusts the original output voltage of the input video image to the gray-scale mapping voltage sent by the timing control module during the frame blanking period and then outputs it to the driving integration module; The signal processing module collects the gray-scale mapping voltage sent by the power supply module to the driving integration module, determines a voltage compensation signal according to the gray-scale mapping voltage and the original output voltage, and feeds back the voltage compensation signal to the timing control module to correct the gray-scale mapping voltage of the driving integration module.

4. The voltage regulation driving method according to claim 3, characterized in that The steps for the timing control module to determine the gray-scale mapping voltage according to the current pixel brightness level of the input video image and the preset gray-scale level sequence include: Obtaining the current pixel brightness level of the input video image through the timing control module; Traversing the preset gray-scale level sequence according to the current pixel brightness level to obtain the gray-scale mapping voltage.

5. The voltage regulation driving method according to claim 4, characterized in that, The steps for obtaining the current pixel brightness level of the input video image through the timing control module include: Collecting the pixel distribution brightness of multiple consecutive frames of the input video image through the timing control module; Detect whether the absolute brightness difference between the brightness of the pixel distributions in two adjacent frames exceeds a preset brightness mutation threshold, and accumulate the number of consecutive frames that satisfy that the absolute brightness difference does not exceed the brightness mutation threshold. Perform temporal filtering processing on the brightness of the pixel distributions of the consecutive frames to obtain the current pixel brightness level.

6. The voltage regulation driving method according to claim 4, wherein The step of traversing a preset gray level sequence according to the current pixel brightness level to obtain a gray scale mapping voltage includes: Traverse the current pixel brightness level in sequence according to a preset gray level sequence, where the gray level sequence includes a plurality of preset gray levels arranged in descending order of gray scale; If the current pixel brightness level is within the brightness level interval corresponding to the currently traversed preset gray level, then use the currently traversed preset gray level as the target gray level to which the current pixel brightness level belongs, and use the preset voltage value mapped by the target gray level as the gray scale mapping voltage.

7. The voltage regulation driving method according to claim 3, characterized in that Determine a voltage compensation signal based on the gray scale mapping voltage and the original output voltage; Detect whether the voltage difference between the gray scale mapping voltage and the original output voltage is greater than zero; If the voltage difference is greater than zero, then determine that the voltage compensation signal is a negative voltage difference; If the voltage difference is less than zero, then determine that the voltage compensation signal is a positive voltage difference.

8. The voltage regulation driving method according to claim 3, wherein The step of feeding back the voltage compensation signal to the timing control module to correct the gray scale mapping voltage of the driving integrated module includes: After the timing control module receives the voltage compensation signal fed back by the signal processing module, superimpose the voltage compensation signal on the gray scale mapping voltage of the driving integrated module to obtain a corrected gray scale mapping voltage.

9. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the voltage regulation driving circuit according to any one of claims 1 to 2.

10. A display device, characterized in that, The display device includes the display panel according to claim 9; Or, A memory, a processor, and a voltage regulation driving program stored on the memory and executable on the processor. When the processor executes the voltage regulation driving program, the steps of the voltage regulation driving method according to any one of claims 3 to 8 are implemented.

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