Adaptive noise suppression method of data strobe signal and memory element

Abstract

The present disclosure provides a method for adaptive noise suppression of a data strobe signal and a memory element using the same. The method comprises the following steps of: judging whether a first data strobe signal and a second data strobe signal meet a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setpoint (MRSV) associated with a first on-die terminator and a second on-die terminator is greater than N; and in response to the MRSV not greater than N, respectively disconnecting a first resistor and a second resistor from a first input end and a second input end of a differential amplifier, and in response to the MRSV being greater than N, the first resistor and the second resistor are respectively coupled to the first input end and the second input end of the differential amplifier.

Description

[0001] Cross-reference

[0002] This application claims priority to U.S. Patent Application No. 18 / 402,797 (i.e., the priority date is "January 3, 2024"), the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic circuit. In particular, it relates to a method for adaptively suppressing noise in a data strobe signal and a memory element using the method. Background Art

[0004] LPDDR4 (Low Power Double Data Rate 4) memory is a mobile version of DDR4 (Double Data Rate 4) memory. A memory controller can control data access to an LPDDR4 memory via command control signals, data signals, and data strobe signals. However, when the write data strobe (WDQS) function of the memory controller is turned off, the logical state of the data strobe signal from the memory controller may be affected by the noise thereon because the noise is amplified by the differential amplifier in the circuit receiver of the LPDDR4 memory, resulting in a malfunction or failure of the LPDDR4 memory control circuit. Therefore, a method for adaptively suppressing noise in a data strobe signal and a memory element using the method are needed to solve the above problems.

[0005] The above description of "Prior Art" only provides background art and does not admit that the above description of "Prior Art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "Prior Art" should not be taken as any part of the present disclosure. Summary of the Invention

[0006] One embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and a receiver circuit. The control circuit is configured to control data access to the memory cell array. The receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The receiver circuit includes a differential amplifier, a first on-die terminator, a second on-die terminator, a noise suppression control circuit, a first noise suppression circuit, and a second noise suppression circuit. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. The first on-die terminator is coupled to a first input terminal of the differential amplifier. The second on-die terminator is coupled to a second input terminal of the differential amplifier. The noise suppression control circuit is configured to generate a noise suppression control signal according to a mode register setting value corresponding to the first on-die terminator and the second on-die terminator. The first noise suppression circuit is configured to selectively couple a first resistor to the first input terminal of the differential amplifier according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal. The second noise suppression circuit is configured to selectively couple a second resistor to the second input terminal of the differential amplifier according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal.

[0007] Another embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and an interface circuit. The control circuit is configured to control data access to the memory cell array. The interface circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The interface circuit includes a receiver circuit. The receiver circuit is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In response to the first data strobe signal and the second data strobe signal satisfying a predetermined condition, the receiver circuit is further configured to selectively couple a first resistor and a second resistor to the first data strobe signal and the second data strobe signal respectively for noise suppression based on a mode register setting value.

[0008] Another embodiment of the present disclosure provides an adaptive noise suppression method for a memory element. The memory element includes a receiver circuit having a differential amplifier, a first on-die terminator, and a second on-die terminator. The method includes the following steps: determining whether a first data strobe signal and a second data strobe signal from a memory controller satisfy a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setting value associated with the first on-die terminator and the second on-die terminator is greater than N, where N is a positive integer; and in response to the mode register setting value not being greater than N, disconnecting a first resistor and a second resistor from a first input terminal and a second input terminal of the differential amplifier respectively; and in response to the mode register setting value being greater than N, coupling the first resistor and the second resistor to the first input terminal and the second input terminal of the differential amplifier respectively.

[0009] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the detailed description of the present disclosure below can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers in the drawings, and the element numbers in the drawings represent similar elements throughout the description.

[0011] Figure 1 is a block diagram illustrating an electronic component according to an embodiment of the present disclosure.

[0012] Figure 2 is a circuit diagram illustrating the receiver circuit according to an embodiment of the present disclosure.

[0013] Figures 3A to 3F is a waveform diagram illustrating the data strobe signal during a write operation according to an embodiment of the present disclosure.

[0014] Figure 4 is a circuit diagram illustrating the receiver circuit according to another embodiment of the present disclosure.

[0015] Figure 5A is a circuit diagram illustrating the receiver circuit in a first configuration according to an embodiment of the present disclosure.

[0016] Figure 5B is a schematic diagram of an equivalent circuit, illustrating Figure 5A the receiver circuit.

[0017] Figure 6A is a circuit schematic diagram, illustrating the receiver circuit of an embodiment of the present disclosure in a second configuration.

[0018] Figure 6B is a schematic diagram of an equivalent circuit, illustrating Figure 6A the receiver circuit.

[0019] Figure 7A is a circuit schematic diagram, illustrating the receiver circuit of an embodiment of the present disclosure in a third configuration.

[0020] Figure 7B is a schematic diagram of an equivalent circuit, illustrating Figure 7A the receiver circuit.

[0021] Figure 8A is a circuit schematic diagram, illustrating the receiver circuit of an embodiment of the present disclosure in a fourth configuration.

[0022] Figure 8B is a schematic diagram of an equivalent circuit, illustrating Figure 8A the receiver circuit.

[0023] Figure 9A is a circuit schematic diagram, illustrating the receiver circuit of an embodiment of the present disclosure in a fourth configuration.

[0024] Figure 9B is a schematic diagram of an equivalent circuit, illustrating Figure 9A the receiver circuit.

[0025] Figure 10 is a circuit schematic diagram, illustrating the receiver circuit of another embodiment of the present disclosure.

[0026] Figure 11 is a circuit schematic diagram, illustrating the receiver circuit of yet another embodiment of the present disclosure.

[0027] Figure 12 is a flowchart, illustrating the data strobe signal adaptive noise suppression method of an embodiment of the present disclosure.

[0028] Description of reference numerals:

[0029] 11: Instruction control signal

[0030] 12: Data signal

[0031] 13: Data strobe signal

[0032] 14: Data strobe signal

[0033] 15: Bus

[0034] 100: Electronic component

[0035] 110: Memory controller

[0036] 120: Memory element

[0037] 121: Interface circuit

[0038] 122: Control circuit

[0039] 123: Memory cell array

[0040] 200: Receiver circuit

[0041] 202: Differential amplifier

[0042] 302: Noise

[0043] 304: Noise

[0044] 306: Noise

[0045] 400: Receiver circuit

[0046] 402: Differential amplifier

[0047] 410: Noise suppression control circuit 412A: Noise suppression circuit

[0048] 412B: Noise suppression circuit

[0049] 500: Receiver circuit

[0050] 502: Differential amplifier

[0051] 600: Receiver circuit

[0052] 602: Differential amplifier

[0053] 610: Noise suppression control circuit 612A: Noise suppression circuit

[0054] 612B: Noise suppression circuit

[0055] 700: Receiver circuit

[0056] 702: Differential amplifier

[0057] 712A: Noise suppression circuit

[0058] 712B: Noise suppression circuit

[0059] 800: Receiver circuit

[0060] 802: Differential amplifier

[0061] 810: Noise suppression control circuit

[0062] 812A: Noise suppression circuit

[0063] 812B: Noise suppression circuit

[0064] 900: Receiver circuit

[0065] 902: Differential amplifier

[0066] 910: Noise suppression control circuit

[0067] 912A: Noise suppression circuit

[0068] 912B: Noise suppression circuit

[0069] 1000: Receiver circuit

[0070] 1100: Receiver circuit

[0071] 1104: Amplifier

[0072] 1106: Amplifier

[0073] 1210: Step

[0074] 1211: Receiver circuit

[0075] 1220: Step

[0076] 1230: Step

[0077] 1240: Step

[0078] A1: Connection terminal

[0079] A2: Connection terminal

[0080] B1: Node

[0081] B2: Node

[0082] CR: Output resistance value

[0083] DQS_c, DQS_t: Data strobe signal

[0084] DQS_c’, DQS_t’: Data strobe signal

[0085] *DQS_c, *DQS_t: Data strobe signal

[0086] DR: Resistor

[0087] MRS: Mode register set

[0088] MRSV: Mode register set value

[0089] NSC: Noise Suppression Control Signal

[0090] ODT1: On-Die Terminator

[0091] ODT2: On-Die Terminator

[0092] Q1~Q6: Transistors

[0093] RODT: Resistance Value

[0094] T: Clock Period

[0095] t(n-4), t(n-3), t(n-2), t(n-1), t0, t1, t2, t3, t4, t5, t6: Time

[0096] tWPRE: Duration

[0097] VA: Specific Voltage

[0098] VB1: Voltage

[0099] VB2: Voltage Detailed Implementation Manner

[0100] The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include an embodiment where the first and second components are in direct contact, or it may include an embodiment where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specifically stated in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0101] It should be understood that although terms such as first, second, and third may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the teachings of the inventive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0102] References to "an example" or "an embodiment" in the specification mean that the particular features, structures, or characteristics described in connection with the example are included in at least one example of the disclosure. Thus, the phrases "in an example" or "in an embodiment" that appear in various places in the specification are not necessarily all referring to the same example. Additionally, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0103] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0104] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly. Additionally, it should also be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0105] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0106] It should be understood that when an element or a layer is referred to as being "formed on" another element or layer, it can be formed directly or indirectly on the other element or layer. That is to say, for example, there may be intermediate elements or layers. In contrast, when an element or a layer is referred to as being "directly formed on" another element, there are no intermediate elements or layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0107] Figure 1 is a block diagram illustrating an electronic component 100 according to an embodiment of the present disclosure.

[0108] In some embodiments, the electronic component 100 may include a memory controller 110 and a memory element 120, as Figure 1 shown. The memory controller 110 may be implemented by a central processing unit (CPU), a microprocessor, a digital signal processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a radio frequency integrated circuit (RFIC).

[0109] In some embodiments, the memory element 120 may be a dynamic random access memory (DRAM). In other embodiments, other types of memories may be used. For the purpose of description, the present disclosure may focus on, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM) such as LPDDR4, but the scope of the embodiments is not limited to any specific memory technology or standard.

[0110] In some embodiments, the memory element 120 may include an interface circuit 121, a control circuit 122, and a memory cell array 123. The interface circuit 121 may be configured to transmit and receive a plurality of data signals 12 via a bus 15, and receive a plurality of instruction control signals 11 and data strobe signals DQS_c and DQS_t from the memory controller 110 via the bus 15. In other words, the interface circuit 121 may include a TX circuit (not explicitly shown) for the data signals 12, and an RX circuit (not explicitly shown) for the instruction control signals 11, the data signals 12, and the data strobe signals DQS_c and DQS_t.

[0111] In some embodiments, the data strobe signal DQS_c may be a complementary signal of the data strobe signal DQS_t. For example, when the data strobe signal DQS_t is in a high logic state (e.g., 1), the data strobe signal DQS_c is in a low logic state (e.g., 0). When the data strobe signal DQS_t is in a low logic state (e.g., 0), the data strobe signal DQS_c is in a high logic state (e.g., 1). In some embodiments, if a write data strobe (WDQS) function of the memory controller 110 is not enabled or is not implemented correctly, the logic states of the data strobe signals DQS_t and DQS_c may be the same.

[0112] In some embodiments, the RX circuit for the data strobe signals DQS_c and DQS_t may be referred to as Figure 1 A receiver circuit 1211 is shown. The receiver circuit 1211 may be configured to correct the data strobe signals DQS_c and DQS_t with inappropriate logic states and / or timing to generate data strobe signals 13 and 14. The data strobe signals 13 and 14 may be data strobe signals (e.g., *DQS_c and *DQS_t) having correct logic states conforming to the LPDDR4 standard defined by the JEDEC Solid State Technology Association (i.e., abbreviated as JEDEC).

[0113] In some embodiments, the control circuit 122 may perform a read operation or a write operation according to the command control signal 11 and the data strobe signals 13 and 14. For example, during a write operation, the memory element 120 may receive a write command (e.g., including the command control signal 11 and the data signal 12) from the memory controller 110 via the bus 15, and then the control circuit 122 may store the received data in the memory cell array 123. During a read operation, the memory element 120 may receive a read command signal (e.g., the command control signal 11) from the memory controller 110 via the bus 15, and then the control circuit 122 may access data from each memory cell of the memory cell array 123, and transmit those bits of the data (e.g., the data signal 12) to the memory controller 110 via the bus 15.

[0114] Figure 2 is a circuit diagram illustrating a receiver circuit 200 according to an embodiment of the present disclosure. Figures 3A to 3E is a waveform diagram illustrating a data strobe signal during a write operation according to an embodiment of the present disclosure. Figure 1 , Figure 2 and Figures 3A to 3E .

[0115] In some embodiments, Figure 1The illustrated receiver circuit 1211 can be implemented using Figure 2 the illustrated receiver circuit 200. The receiver circuit 200 can include a differential amplifier 202 configured to amplify data strobe signals DQS_c and DQS_t to generate data strobe signals *DQS_c and *DQS_t. Additionally, the negative input terminal and the positive input terminal of the differential amplifier 202 can be coupled to on-die terminators ODT1 and ODT2, respectively. The on-die terminators ODT1 and ODT2 can be configured to suppress noise on the received data strobe signals DQS_c and DQS_t. Further, the memory controller 110 can transmit the data strobe signals DQS_t and DQS_c from connections A1 and A2 to nodes B1 and B2 of the receiver circuit 200 through a corresponding output resistance value (or characteristic resistance) CR. In some embodiments, the output resistance value CR of each of the connections A1 and A2 of the memory controller 110 can be approximately 50 ohms, but the present disclosure is not limited thereto.

[0116] For example, the receiver circuit 200 can receive data strobe signals DQS_c and DQS_t at its positive input terminal (e.g., +) and negative input terminal (e.g., -), respectively, to generate data strobe signals *DQS_c and *DQS_t. In some embodiments, the amplitudes of the data strobe signals DQS_c and DQS_t can be between 50mv and 100mv, which may not have sufficient voltage levels (e.g., 0.6V or 1.1V for LPDDR4 DRAM) for the control circuit 122 to perform a write operation or a read operation. The amplitudes of the data strobe signals *DQS_c and *DQS_t can be approximately 0.6V or 1.1V, and the control circuit 122 can perform a write operation or a read operation according to the command control signal 11 and the data strobe signals *DQS_c and *DQS_t.

[0117] In some embodiments, assuming that the memory element 120 is an LPDDR4 DRAM and the memory controller 110 follows the LPDDR4 standard (e.g., the write data strobe (WDQS) function is enabled), when the memory controller 110 issues a write command to the memory element 120, at time t0, before the memory controller 110 issues a write preamble to the memory element 120, the data strobe signals DQS_t and DQS_c should be kept in a low logic state and a high logic state, respectively. The duration tWPRE of the write preamble can last for two clock cycles (e.g., from time t0 to time t4) until the control circuit 122 receives data (e.g., data signal 12) at time t4, and the data strobe signals DQS_t and DQS_c can vary during the duration tWPRE of the write preamble, as Figure 3A illustrated.

[0118] However, in some cases, the WDQS function of the memory controller 110 may not be enabled or may not be correctly implemented, resulting in the logical states of the data strobe signals DQS_t and DQS_c being uncertain during a period of time (e.g., the time interval from time t(n - 4) to time t0) before the write preamble received by the control circuit 122 at time t0.

[0119] For example, as Figure 3A shown, the time interval between every two adjacent time points from t(n - 4) to t6 can be half a clock cycle T / 2. In other words, two time intervals (e.g., from t0 to t2) can constitute a clock cycle T.

[0120] At time t0, the memory controller 110 issues a write preamble tWPRE. If the WDQS function is turned off, as Figure 3A shown, during a period of time (e.g., from time t(n - 4) to time t0) before the write preamble tWPRE is issued at time t0, the logical states of the data strobe signals DQS_t and DQS_c may be uncertain. This situation can cause the control circuit 122 to malfunction during a write operation.

[0121] More specifically, during the period before time t0, the logical states of the data strobe signals DQS_t and DQS_c have four conditions. Under the first condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c may remain in a low logical state during a period of time before the control circuit 122 receives the write preamble at time t0, as Figure 3B shown. Since the first condition does not meet the requirements of the write operation of the JEDEC - defined LPDDR4 standard, the first condition can cause the control circuit 122 to malfunction during the write operation.

[0122] Under the second condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c may remain in a high logical state during a period of time before the control circuit 122 receives the write preamble at time t0, as Figure 3C shown. Since the second condition does not meet the requirements of the write operation of the JEDEC - defined LPDDR4 standard, the second condition can cause the control circuit 122 to malfunction during the write operation.

[0123] Under the third condition, the WDQS function of the memory controller 110 can be enabled, and the data strobe signals DQS_t and DQS_c are maintained at a low logic state and a high logic state, respectively, for a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3D shown. Since the third condition meets the requirements of the write operation of the LPDDR4 standard defined by JEDEC, the third condition will not cause the control circuit 122 to malfunction during the write operation.

[0124] Under the fourth condition, the WDQS function of the memory controller 110 can be enabled, and the data strobe signals DQS_t and DQS_c are maintained at a high logic state and a low logic state, respectively, for a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3E shown. Since the fourth condition complies with the LPDDR4 standard defined by JEDEC, the fourth condition will not cause the control circuit 122 to malfunction during the write operation.

[0125] Now please refer again to Figure 2 . In some embodiments, the resistance values of the on-die terminators ODT1 and ODT2 can vary among multiple preset resistance values, which can include 40 ohms, 60 ohms, 80 ohms, 120 ohms, 240 ohms, and an open-circuit resistance value, and they are determined by the setting values of the corresponding mode registers in the memory element 120 set by the memory controller 110 (for example, Figure 1 a register in the mode register bank MRS of the control circuit 122 in ). In some embodiments, when the setting values (MRSV) of the mode registers corresponding to the on-die terminators ODT1 and ODT2 are set to 0, the on-die terminators ODT1 and ODT2 can be turned off to act as an open circuit (for example, resistance value = ∞). When the setting values of the mode registers corresponding to the on-die terminators ODT1 and ODT2 are set to 1, 2, 3, 4, and 5, the resistance values of the on-die terminators ODT1 and ODT2 can be 40 ohms, 60 ohms, 80 ohms, 120 ohms, and 240 ohms, respectively, but the present disclosure is not limited thereto.

[0126] In some embodiments, when the WDQS function is turned off, the memory controller 110 may set the mode registers corresponding to the on-die terminators ODT1 and ODT2 to a specific value (for example, 0), such that the on-die terminators ODT1 and ODT2 are turned off to act as an open circuit. In this case, the amplitude of the noise received by the receiver circuit 1211 will not be suppressed. Figure 2The differential amplifier 202 shown amplifies the data strobe signals DQS_t and DQS_c and the noise on the data strobe signals DQS_t and DQS_c. In some embodiments, the amplitude of the data strobe signals DQS_t and DQS_c can be approximately between 300 mV and 600 mV, and the amplitude of the noise on the data strobe signals DQS_t and DQS_c can be approximately between 80 mV and 170 mV.

[0127] When the data strobe signals DQS_t and DQS_c are in the low logic state and the WDQS function is turned off, the amplified noise can reach an amplitude similar to that of the data strobe signals DQS_t and DQS_c in the high logic state. Therefore, the amplified noise will be more likely to cause the data strobe signals DQS_t and DQS_c to change from the low logic state to the high logic state, potentially causing malfunction or failure of the control circuit 122.

[0128] Please refer to Figure 3F , noise 302 and 304 are on the data strobe signal DQS_t, and noise 306 is on the data strobe signal DQS_c. Noise 302 and 306 can have an amplitude higher than a specific voltage VA (e.g., approximately 90 mV), and noise 304 can have an amplitude lower than the specific voltage VA. More specifically, when the amplitude of the noise on the data strobe signal DQS_t or DQS_c is higher than the specific voltage VA (such as noise 302 and 306), the amplified noise will cause the data strobe signals DQS_t and DQS_c to change from the low logic state to the high logic state, potentially causing malfunction or failure of the control circuit 122. Figure 4 The receiver circuit 400 shown provides a solution to this problem, and its details will be further discussed.

[0129] Figure 4 is a circuit schematic diagram illustrating the receiver circuit 400 of another embodiment of the present disclosure.

[0130] In some embodiments, Figure 1 the receiver circuit 1211 shown can be implemented using Figure 4 the receiver circuit 400 shown. The receiver circuit 400 can include a differential amplifier 402, on-die terminators ODT1 and ODT2, and noise suppression circuits 412A and 412B. The operations of the on-die terminators ODT1 and ODT2 can be similar to those of the on-die terminators ODT1 and ODT2 shown Figure 2 , and the details thereof will not be repeated here.

[0131] In some embodiments, the differential amplifier 402 may be configured to amplify data strobe signals DQS_c and DQS_t (e.g., input data strobe signals) to generate data strobe signals *DQS_c and *DQS_t.

[0132] In some embodiments, the noise suppression circuits 412A and 412B may be configured to suppress noise of data strobe signals DQS_t and DQS_c from terminals A1 and A2 of the memory controller 110, respectively. For example, the noise suppression circuit 412A may be coupled in parallel to the on-die terminator ODT1, and they may be coupled to the negative input terminal (-) of the differential amplifier 402. The noise suppression circuit 412B may be in parallel with the on-die terminator ODT2, and they may be coupled to the positive input terminal (+) of the differential amplifier 402.

[0133] In some embodiments, the noise suppression control circuit 410 may be configured to use a noise suppression control signal NSC to control the noise suppression circuits 412A and 412B to couple or decouple respective resistors DR to and from the negative input terminal and the positive input terminal of the differential amplifier 402. Specifically, the noise suppression circuits 412A and 412B may be controlled based on the data strobe signals DQS_t and DQS_c and the noise suppression control signal NSC from the noise suppression control circuit 410. For example, the noise suppression circuit 412A may include transistors Q1 to Q3 and respective resistors DR. The transistors Q1, Q2, and Q3 may be used as switches controlled by the data strobe signals *DQS_c and *DQS_t and the noise suppression control signal NSC, respectively. Additionally, the noise suppression circuit 412B may include transistors Q4 to Q6 and corresponding resistors DR. The transistors Q4, Q5, and Q6 may be used as switches controlled by the data strobe signals *DQS_c and *DQS_t and the noise suppression control signal NSC, respectively. In some embodiments, the resistance value of the resistor DR may be approximately 40 ohms, but the present disclosure is not limited thereto. Those skilled in the art may modify the resistance value of the resistor DR according to actual requirements.

[0134] In some embodiments, in response to the noise suppression control signal NSC being in a low logic state, the transistors Q3 and Q6 may be turned off, resulting in the ground paths of the respective resistors DR being cut off. Therefore, regardless of whether the data strobe signals *DQS_t and *DQS_c are in a high logic state or a low logic state, the respective resistors DR may be decoupled from the negative input terminal and the positive input terminal of the differential amplifier 402.

[0135] In response to the noise suppression control signal NSC being in a high logic state, transistors Q3 and Q6 can be turned on, causing the ground paths of the respective resistors DR to be turned on. At this time, the coupling or decoupling of the resistor DR can depend on the logic states of the data strobe signals *DQS_t and *DQS_c. For example, when the data strobe signals *DQS_t and *DQS_c are in a low logic state, transistors Q1, Q2, Q4, and Q5 are turned on, causing the respective resistors DR to be coupled to the negative input terminal and the positive input terminal of the differential amplifier 402.

[0136] When any one of the data strobe signals *DQS_t and *DQS_c is in a high logic state, the paths from the negative input terminal to the respective resistors DR and from the positive input terminal to the other respective resistors DR can be cut off, causing the respective resistors DR to be decoupled from the negative input terminal and the positive input terminal of the differential amplifier 402. For example, when the data strobe signals *DQS_t and *DQS_c are in a high logic state and a low logic state respectively, transistors Q1 and Q4 are turned on, and transistors Q2 and Q5 are turned off, causing the respective resistors DR to be decoupled from the negative input terminal and the positive input terminal of the differential amplifier 402. Similarly, when the data strobe signals *DQS_t and *DQS_c are in a low logic state and a high logic state respectively, transistors Q2 and Q5 are turned on, and transistors Q1 and Q4 are turned off, causing the respective resistors DR to be decoupled from the negative input terminal and the positive input terminal of the differential amplifier 402. Likewise, when the data strobe signals *DQS_t and *DQS_c are both in a high logic state, transistors Q1 - Q2 and Q4 - Q5 are turned off, causing the respective resistors DR to be decoupled from the negative input terminal and the positive input terminal of the differential amplifier 402.

[0137] The structure of the noise suppression control circuit 410 for generating the noise suppression control signal NSC will be described in the embodiments of FIGS. 5 to 9 below.

[0138] Figure 5A is a circuit schematic diagram illustrating a receiver circuit in a first configuration according to an embodiment of the present disclosure. Figure 5B is an equivalent circuit schematic diagram illustrating Figure 5A the receiver circuit of

[0139] In some embodiments, Figure 1 the receiver circuit 1211 shown can be implemented using Figure 5A the receiver circuit 500 shown. The receiver circuit 500 can include a differential amplifier 502 and on - die terminators ODT1 and ODT2. It should be understood that Figure 5A the receiver circuit 500 shown may not be equipped with Figure 4The noise suppression control circuit 410 and the noise suppression circuits 412A and 412B as shown. Additionally, the mode register setting values corresponding to the on-die terminators ODT1 and ODT2 can be set to 0 by the memory controller 110, causing the on-die terminators ODT1 and ODT2 to turn off (e.g., the resistance values RODT of the on-die terminators ODT1 and ODT2 are ∞), as Figure 5A shown. At this time, the data strobe signals DQS_t and DQS_t can be transmitted from the connection terminals A1 and A2 to the nodes B1 and B2 (e.g., the negative input terminal and the positive input terminal of the differential amplifier 502) through the respective output resistance values CR, as shown in the figure Figure 5B .

[0140] Assume that the amplitude of the noise on the data strobe signal DQS_t is 134 mV. Then the voltage VB1 at the node B1 can be calculated as VB1 = 134 * (RODT / (CR + RODT)) = 134 * (∞ / (50 + ∞)) = 134 mV. The voltage VB2 at the node B2 can be calculated in a similar manner. Specifically, when the on-die terminators ODT1 and ODT2 are turned off and no noise suppression circuit is provided, the noise on the data strobe signals DQS_t and DQS_c will not be suppressed, and the logic states of the data strobe signals *DQS_t and *DQS_c generated by the differential amplifier 502 will be affected by the noise.

[0141] Figure 6A is a circuit schematic diagram illustrating a receiver circuit in a second configuration according to an embodiment of the present disclosure. Figure 6B is an equivalent circuit schematic diagram illustrating Figure 6A the receiver circuit.

[0142] In some embodiments, Figure 1 the receiver circuit 1211 as shown can be implemented using Figure 6A the receiver circuit 600 as shown. The receiver circuit 600 can include a differential amplifier 602, a noise suppression control circuit 610, on-die terminators ODT1 and ODT2, and noise suppression circuits 612A and 612B. For the purpose of description, assume that the data strobe signals *DQS_t and *DQS_c are in the low logic state and the noise suppression control signal NSC is in the high logic state, causing the transistors Q1 to Q6 to conduct. Therefore, the respective resistors DR can be coupled to the negative input terminal and the positive input terminal of the differential amplifier 602. Additionally, the mode register setting values corresponding to the on-die terminators ODT1 and ODT2 can be set to 0 by the memory controller 110, causing the on-die terminators ODT1 and ODT2 to turn off (e.g., the resistance values RODT of the on-die terminators ODT1 and ODT2 are ∞), as Figure 6A shown. At this time, the equivalent schematic diagram of the receiving circuit 600 can be referred to FIG. 6.

[0143] Assume that the amplitude of the noise on the data strobe signal DQS_t is 134 mV. Then the voltage VB1 at node B1 can be calculated as VB1 = 134 * (DR / (CR + DR)) = 134 * (40 / (50 + 40)) = 59.5 mV. The voltage VB2 at node B2 can be calculated in a similar manner. Specifically, when the on-die terminators ODT1 and ODT2 are turned off and the transistors Q1 to Q6 of the noise suppression circuits 612A and 612B are turned on, the amplitudes of the noise on the data strobe signals DQS_t and DQS_c can be reduced below a specific voltage, such as approximately 90 mV. This prevents the logic states of the data strobe signals *DQS_t and *DQS_c generated by the differential amplifier 602 from being affected by the noise.

[0144] Figure 7A is a circuit schematic diagram illustrating a receiver circuit in a third configuration according to an embodiment of the present disclosure. Figure 7B is an equivalent circuit schematic diagram illustrating Figure 7A the receiver circuit of

[0145] In some embodiments, Figure 7A the illustrated receiver circuit 700 may include noise suppression circuits 712A and 712B similar to the noise suppression circuits 412A and 412B in Figure 4 . For purposes of description, assume that the data strobe signals *DQS_t and *DQS_c are in a high logic state and the noise suppression control signal NSC is also in a high logic state, causing the transistors Q1 - Q2 and Q4 - Q5 to be turned off and the transistors Q3 and Q6 to be turned on. Accordingly, each resistor DR can be disconnected from the negative input terminal and the positive input terminal of the differential amplifier 702. Additionally, the mode register settings corresponding to the on-die terminators ODT1 and ODT2 can be set to 1 by the memory controller 110, resulting in the resistance values RODT of the on-die terminators ODT1 and ODT2 being 40 ohms, as shown in Figure 7A . At this time, the equivalent schematic diagram of the receiving circuit 700 can be referred to Figure 7B .

[0146] Assume that the amplitude of the noise on the data strobe signal DQS_t is 134 mV. Then the voltage VB1 at node B1 can be calculated as VB1 = 134 * (RODT / (CR + RODT)) = 134 * (40 / (50 + 40)) = 59.5 mV. The voltage VB2 at node B2 can be calculated in a similar manner. Specifically, when the on-die terminators ODT1 and ODT2 are turned on and the transistors Q1 to Q6 of the noise suppression circuits 712A and 712B are turned off, the amplitudes of the noise on the data strobe signals DQS_t and DQS_c can be reduced below a specific voltage, for example, approximately 90 mV. This prevents the logic states of the data strobe signals *DQS_t and *DQS_c generated by the differential amplifier 702 from being affected by the noise.

[0147] Figure 8A is a circuit schematic diagram illustrating a receiver circuit in a fourth configuration according to an embodiment of the present disclosure. Figure 8B is an equivalent circuit schematic diagram illustrating Figure 8A the receiver circuit of

[0148] In some embodiments, Figure 8A the illustrated receiver circuit 800 may include noise suppression circuits 812A and 812B similar to the noise suppression circuits 412A and 412B in Figure 4 For the purpose of description, assume that the data strobe signals *DQS_t and *DQS_c are in a low logic state, causing the transistors Q1 - Q2 and Q4 - Q5 to be turned on.

[0149] In some embodiments, the noise suppression control circuit 810 may determine the logic state of the noise suppression control signal NSC based on the mode register setting values corresponding to the on-die terminators ODT1 and ODT2. For example, when the mode register setting value is greater than a specific value (e.g., 2), the noise suppression control circuit 810 may set the noise suppression control signal NSC to a high logic state, causing the transistors Q3 and Q6 to be turned on and each resistor DR to be coupled to the negative input terminal and the positive input terminal of the differential amplifier 802. Additionally, when the mode register setting value is equal to or less than the specific value (e.g., 2), the noise suppression control circuit 810 may set the noise suppression control signal NSC to a low logic state, causing the transistors Q3 and Q6 to be turned off and each resistor DR to be disconnected from the negative input terminal and the positive input terminal of the differential amplifier 802.

[0150] In a first case, the memory controller 110 may set the mode register setting values corresponding to the on-die terminators ODT1 and ODT2 to 1, resulting in the resistance value RODT of the on-die terminators ODT1 and ODT2 being 40 ohms, as Figure 8AAs shown. If the noise suppression control circuit 810 sets the noise suppression control circuit signal NSC to a high logic state regardless of the mode register settings corresponding to the on-die terminators ODT1 and ODT2, the transistors Q3 and Q6 conduct, causing each resistor DR to be coupled to the negative input terminal and the positive input terminal of the differential amplifier 802.

[0151] Please refer to Figure 8B , assuming that the amplitude of the noise on the data strobe signal DQS_t is 134 mV, the voltage VB1 at node B1 (e.g., DQS_t) can be calculated as VB1 = 134 * ((DR / / RODT) / (CR+(DR / / RODT))) = 134 * ((40 / / 40) / (50+(40 / / 40))) = 134 * (20 / (50+20)) = 38.3 mV. The voltage VB2 at node B2 (e.g., DQS_c) can be calculated in a similar manner. Specifically, when the on-die terminators ODT1 and ODT2 are conducting and the transistors Q1 to Q6 of the noise suppression circuits 812A and 812B are conducting, the amplitude of the noise on the data strobe signals DQS_t and DQS_c can be reduced below a specific voltage, for example, approximately 90 mV. This prevents the logic states of the data strobe signals *DQS_t and *DQS_c generated by the differential amplifier 802 from being affected by the noise. However, when the resistance values of the on-die terminators ODT1 and ODT2 are relatively small (e.g., 40 or 60 ohms), the noise suppression ability of the receiver circuit 800 may be too strong, resulting in the amplitudes of the data strobe signals DQS_c and DQS_t being overly suppressed.

[0152] In a second case, the memory controller 110 can set the mode register settings corresponding to the on-die terminators ODT1 and ODT2 to 4, resulting in the resistance value RODT of the on-die terminators ODT1 and ODT2 being 120 ohms. Additionally, the noise suppression control circuit 910 can set the noise suppression control signal NSC to a low logic state based on the mode register settings corresponding to the on-die terminators ODT1 and ODT2, causing each resistor DR to be coupled to the negative input terminal and the positive input terminal of the differential amplifier 802.

[0153] Please refer to Figure 8B, assuming that the amplitude of the noise on the data strobe signal DQS_t is 134 mV, the voltage VB1 at node B1 (e.g., DQS_t) can be calculated as VB1 = 134 * ((DR / / RODT) / (CR + (DR / / RODT))) = 134 * ((40 / / 120) / (50 + (40 / / 120))) = 134 * (30 / (50 + 30)) = 50.3 mV. The voltage VB2 at node B2 (e.g., DQS_c) can be calculated in a similar manner. Specifically, when the on-die terminators ODT1 and ODT2 are turned on and the transistors Q1 to Q6 of the noise suppression circuits 812A and 812B are turned on, the amplitude of the noise on the data strobe signals DQS_t and DQS_c can be reduced below a specific voltage, for example, approximately 90 mV. This prevents the logic states of the data strobe signals *DQS_t and *DQS_c generated by the differential amplifier 802 from being affected by the noise. It should be understood that in the second case, the amplitudes of the data strobe signals DQS_t and DQS_c are not overly suppressed.

[0154] Figure 9A is a circuit schematic diagram illustrating a receiver circuit in a fourth configuration according to an embodiment of the present disclosure. Figure 9B is an equivalent circuit schematic diagram illustrating Figure 9A the receiver circuit of

[0155] In some embodiments, Figure 9A the illustrated receiver circuit 900 may include noise suppression circuits 912A and 912B similar to the noise suppression circuits 412A and 412B in Figure 4 . For the purpose of description, assume that the data strobe signals *DQS_t and *DQS_c are in a low logic state, causing the transistors Q1 - Q2 and Q4 - Q5 to be turned on. Additionally, the mode register settings corresponding to the on-die terminators ODT1 and ODT2 can be set to 1 by the memory controller 110, resulting in the resistance value RODT of the on-die terminators ODT1 and ODT2 being 40 ohms, as shown in Figure 9A . Therefore, the noise suppression control circuit 910 can set the noise suppression control signal NSC to a low logic state based on the mode register settings, causing each resistor DR to be disconnected from the negative input terminal and the positive input terminal of the differential amplifier 802.

[0156] Please refer to Figure 9B, assuming the amplitude of the noise on the data strobe signal DQS_t is 134 mV, the voltage VB1 (e.g., DQS_t) at node B1 can be calculated as VB1 = 134 * (RODT / (CR + RODT)) = 134 * (40 / (50 + 40)) = 59.5 mV. The voltage VB2 (e.g., DQS_c) at node B2 (e.g., DQS_c) can be calculated in a similar manner. Specifically, when the on-die terminators ODT1 and ODT2 are turned off and the transistors Q3 and Q6 of the noise suppression circuits 912A and 912B are turned off, the amplitude of the noise on the data strobe signals DQS_t and DQS_c can be reduced below a specific voltage, e.g., approximately 90 mV. This prevents the logic states of the data strobe signals *DQS_t and *DQS_c generated by the differential amplifier 902 from being affected by the noise.

[0157] Figure 10 is a circuit schematic diagram illustrating a receiver circuit according to another embodiment of the present disclosure.

[0158] Figure 10 The illustrated receiver circuit 1000 can be similar Figure 4 to the illustrated receiver circuit 400, except that the transistors Q1 and Q4 are controlled by the data strobe signal DQS_c, while the transistors Q2 and Q5 are controlled by the data strobe signal DQS_t. Figure 10 The operation of the illustrated receiver circuit 1000 can be similar to Figure 4 that of the illustrated receiver circuit 400, and will not be described in detail herein.

[0159] Figure 11 is a circuit schematic diagram illustrating a receiver circuit according to yet another embodiment of the present disclosure.

[0160] Figure 11 The illustrated receiver circuit 1100 can be similar Figure 4 to the illustrated receiver circuit 400, except that the transistors Q1 and Q4 are controlled by the data strobe signal DQS_c’, and the transistors Q2 and Q5 are controlled by the data strobe signal DQS_t’.

[0161] In some embodiments, the memory element 120 may be operated using a supply voltage of 0.6V or 1.1V. However, the amplitudes of the data strobe signals DQS_c and DQS_t from the memory controller 110 are between 50mv and 100mv, and their voltage levels are not sufficient for the control circuit 122 to perform write or read operations on the memory element 120. Additionally, since the threshold voltages of the transistors Q1 - Q2 and Q4 - Q5 can be between 0.5V and 0.7V, the amplitudes of the data strobe signals DQS_c and DQS_t are not sufficient to turn on the transistors Q1 - Q2 and Q4 - Q5. The amplitudes of the amplified data strobe signals DQS_c’ and DQS_t’ generated by the amplifiers 1104 and 1106 can be between 0.6V and 1.1V, and their voltage levels are sufficient for the control circuit 122 to perform write or read operations on the memory element 120 and are sufficient to turn on the transistors Q1 - Q2 and Q4 - Q5. Figure 11 The operation of the illustrated receiver circuit 1100 can be similar to Figure 4 the operation of the illustrated receiver circuit 400, which will not be elaborated herein.

[0162] Figure 12 is a flowchart illustrating a data strobe signal adaptive noise suppression method 1200 according to an embodiment of the present disclosure. Please refer to Figure 1 、 Figure 4 and Figure 12 .

[0163] Step 1210: Determine whether a first data strobe signal (e.g., first DQS, e.g., DQS_c) and a second data strobe signal (e.g., second DQS, e.g., DQS_t) from a memory controller (e.g., memory controller 110) satisfy a first condition (e.g., DQS_c = DQS_t = 0). When it is determined that the first data strobe signal and the second data strobe signal satisfy the first condition, execute step 1220. When it is determined that the first data strobe signal and the second data strobe signal do not satisfy the first condition, execute step 1230. For example, when the write data strobe (WDQS) function of the memory controller is turned off, the data strobe signals DQS_t and DQS_c in the low logic state from the memory controller may be affected by the noise thereon because the noise will be amplified by the differential amplifier in the receiving circuit of the LPDDR4 memory, resulting in faults or failures in the LPDDR4 memory control circuit.

[0164] Step 1220: Determine whether a mode register setting value (MRSV) corresponding to a first die terminator (e.g., ODT1) and a second die terminator (e.g., ODT2) is greater than N, where N is a positive integer. For example, the noise suppression control circuit 410 may determine whether the mode register setting value is greater than N (e.g., 2). In response to the mode register setting value being greater than N, step 1240 is executed. In response to the mode register setting value being equal to or less than N, step 1230 is executed.

[0165] In some embodiments, when the mode register setting value (MRSV) corresponding to the die terminators ODT1 and ODT2 is set to 0, the die terminators ODT1 and ODT2 may be turned off to act as open circuits (e.g., resistance = ∞). When the mode register setting value corresponding to the die terminators ODT1 and ODT2 is set to 1, 2, 3, 4, and 5, the resistance values of the die terminators ODT1 and ODT2 may be 40 ohms, 60 ohms, 80 ohms, 120 ohms, and 240 ohms respectively, but the present disclosure is not limited thereto.

[0166] Step 1230: Disconnect a first resistor (e.g., low-side resistor DR) and a second resistor (e.g., high-side resistor DR) from a first input terminal (e.g., negative input terminal) and a second input terminal (e.g., positive input terminal) of the differential amplifier (e.g., differential amplifier 402) respectively. For example, when the MRSV is equal to or lower than N (e.g., 2), it may indicate that the resistance values of the die terminators ODT1 and ODT2 are relatively low, such as about 40 or 60 ohms. If the respective resistors DR of the noise suppression circuits 412A and 412B are coupled to the negative input terminal and the positive input terminal of the differential amplifier 402, the noise suppression ability of the receiver circuit 400 may be too strong, resulting in over-suppression of the data strobe signals DQS_t and DQS_c. Therefore, the noise suppression control circuit 410 may issue a noise suppression control signal NSC of a low logic state to turn off transistors Q3 and Q6, causing the respective resistors DR to be disconnected from the negative input terminal and the positive input terminal of the differential amplifier 402.

[0167] Step 1240: Couple the first resistor (e.g., low-side resistor DR) and the second resistor (e.g., high-side resistor DR) to the first input terminal (e.g., negative input terminal) and the second input terminal (e.g., positive input terminal) of the differential amplifier (e.g., differential amplifier 402), respectively. For example, when MRSV is greater than N (e.g., 2), it may indicate that the resistance values of the on-die terminators ODT1 and ODT2 on the die are relatively high, such as approximately 80, 120, or 240 ohms. If the respective resistors DR of the noise suppression circuits 412A and 412B are coupled to the negative input terminal and the positive input terminal of the differential amplifier 402, the noise suppression ability of the receiver circuit 400 will not be too strong, resulting in the data strobe signals DQS_t and DQS_c not being overly suppressed. Therefore, the noise suppression control circuit 410 can issue a noise suppression control signal NSC in a high logic state to turn on the transistors Q3 and Q6, causing the respective resistors DR to be coupled to the negative input terminal and the positive input terminal of the differential amplifier 402.

[0168] One embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and a receiver circuit. The control circuit is configured to control data access to the memory cell array. The receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The receiver circuit includes a differential amplifier, a first on-die terminator, a second on-die terminator, a noise suppression control circuit, a first noise suppression circuit, and a second noise suppression circuit. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. The first on-die terminator is coupled to a first input terminal of the differential amplifier. The second on-die terminator is coupled to a second input terminal of the differential amplifier. The noise suppression control circuit is configured to generate a noise suppression control signal according to a mode register setting value corresponding to the first on-die terminator and the second on-die terminator. The first noise suppression circuit is configured to selectively couple a first resistor to the first input terminal of the differential amplifier according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal. The second noise suppression circuit is configured to selectively couple a second resistor to the second input terminal of the differential amplifier according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal.

[0169] In some embodiments, a first resistance value of the first on-die terminator and a second resistance value of the second on-die terminator are substantially the same.

[0170] In some embodiments, the first resistance value and the second resistance value are determined based on a mode register setting value corresponding to the first die terminal and the second die terminal.

[0171] In some embodiments, when the mode register setting value is equal to 0, the first die terminal and the second die terminal are open.

[0172] In some embodiments, when the mode register setting value is set to 1, a third resistance value of the first resistor and a fourth resistance value of the second resistor are substantially equal to the first resistance value and the second resistance value.

[0173] In some embodiments, in response to the mode register setting value being greater than a specific value, the noise suppression control signal generated by the noise suppression control circuit is in a high logic state, and in response to the mode register setting value being equal to or less than the specific value, the noise suppression control signal generated by the noise suppression control circuit is in a low logic state. The specific value is 2.

[0174] In some embodiments, the first noise suppression circuit includes a first transistor, a second transistor, a first resistor, and a third transistor. The first transistor has a control terminal coupled to the third data strobe signal, a first terminal coupled to the first input terminal of the differential amplifier, and a second terminal coupled to a first node. The second transistor has a control terminal coupled to the fourth data strobe signal, a first terminal coupled to the first node, and a second terminal coupled to a second node. The first resistor is coupled between the second node and a third node. The third transistor has a control terminal coupled to the noise suppression control signal, a first terminal coupled to the third node, and a second terminal coupled to a ground voltage.

[0175] In some embodiments, the second noise suppression circuit includes a fourth transistor, a fifth transistor, a second resistor, and a sixth transistor. The fourth transistor has a control terminal coupled to the third data strobe signal, a first terminal coupled to the second input terminal of the differential amplifier, and a second terminal coupled to a fourth node. The fifth transistor has a control terminal coupled to the fourth data strobe signal, a first terminal coupled to the fourth node, and a second terminal coupled to a fifth node. The second resistor is coupled between the fifth node and a sixth node. The sixth transistor has a control terminal coupled to the noise suppression control signal, a first terminal coupled to the sixth node, and a second terminal coupled to the ground voltage.

[0176] In some embodiments, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are P-type transistors, and the third transistor and the sixth transistor are N-type transistors.

[0177] In some embodiments, when any one of the third data strobe signal and the fourth data strobe signal is in a high logic state, the first resistor and the second resistor are respectively disconnected from the first input terminal and the second input terminal of the differential amplifier.

[0178] In some embodiments, when the third data strobe signal and the fourth data strobe signal are in the low logic state and the noise suppression control signal is in the high logic state, the first resistor and the second resistor are respectively coupled to the first input terminal and the second input terminal of the differential amplifier.

[0179] Another embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and an interface circuit. The control circuit is configured to control data access of the memory cell array. The interface circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The interface circuit includes a receiver circuit. The receiver circuit is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In response to the first data strobe signal and the second data strobe signal satisfying a predetermined condition, the receiver circuit is further configured to selectively couple a first resistor and a second resistor to the first data strobe signal and the second data strobe signal respectively for noise suppression based on a mode register setting value.

[0180] In some embodiments, the receiver circuit includes a differential amplifier, a first on-die terminator, and a second on-die terminator. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal. The first on-die terminator is coupled to a first input terminal of the differential amplifier. The second on-die terminator is coupled to a second input terminal of the differential amplifier. A first resistance value of the first on-die terminator and a second resistance value of the second on-die terminator are determined based on the mode register setting value.

[0181] In some embodiments, a first resistance value of the first on-die terminator and a second resistance value of the second on-die terminator are substantially the same.

[0182] In some embodiments, when the mode register setting value is equal to 0, the first on-die terminator and the second on-die terminator are open circuits.

[0183] In some embodiments, the receiver circuit further includes a noise suppression control circuit, a first noise suppression circuit, and a second noise suppression circuit. The noise suppression control circuit is configured to generate a noise suppression control signal based on the mode register setting values corresponding to the first die terminator and the second die terminator. The first noise suppression circuit is configured to selectively couple the first resistor to the first input terminal of the differential amplifier according to a first control signal, a second control signal, and the noise suppression control signal. The second noise suppression circuit is configured to selectively couple the second resistor to the second input terminal of the differential amplifier according to the first control signal, the second control signal, and the noise suppression control signal.

[0184] In some embodiments, the first control signal and the second control signal are the third data strobe signal and the fourth data strobe signal, respectively.

[0185] In some embodiments, the first control signal and the second control signal are the first data strobe signal and the second data strobe signal, respectively.

[0186] In some embodiments, the receiver circuit further includes a first amplifier and a second amplifier. The first amplifier is configured to amplify the first data strobe signal to generate a first amplified data strobe signal. The second amplifier is configured to amplify the second data strobe signal to generate a second amplified data strobe signal. The first control signal and the second control signal are the first amplified data strobe signal and the second amplified data strobe signal, respectively.

[0187] In some embodiments, when the mode register setting value is set to 1, a third resistance value of the first resistor and a fourth resistance value of the second resistor are substantially equal to the first resistance value and the second resistance value.

[0188] In some embodiments, in response to the mode register setting value being greater than a specific value, the noise suppression control signal generated by the noise suppression control circuit is in a high logic state. In response to the mode register setting value being equal to or less than the specific value, the noise suppression control signal generated by the noise suppression control circuit is in a low logic state. The specific value is 2.

[0189] In some embodiments, the first noise suppression circuit includes a first transistor, a second transistor, a first resistor, and a third transistor. The first transistor has a control terminal coupled to the first control signal, a first terminal coupled to the first input terminal of the differential amplifier, and a second terminal coupled to a first node. The second transistor has a control terminal coupled to the second control signal, a first terminal coupled to the first node, and a second terminal coupled to a second node. The first resistor is coupled between the second node and a third node. The third transistor has a control terminal coupled to the noise suppression control signal, a first terminal coupled to the third node, and a second terminal coupled to a ground voltage.

[0190] In some embodiments, the second noise suppression circuit includes a fourth transistor, a fifth transistor, a second resistor, and a sixth transistor. The fourth transistor has a control terminal coupled to the first control signal, a first terminal coupled to the second input terminal of the differential amplifier, and a second terminal coupled to a fourth node. The fifth transistor has a control terminal coupled to the second control signal, a first terminal coupled to the fourth node, and a second terminal coupled to a fifth node. The second resistor is coupled between the fifth node and a sixth node. The sixth transistor has a control terminal coupled to the noise suppression control signal, a first terminal coupled to the sixth node, and a second terminal coupled to the ground voltage.

[0191] In some embodiments, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are P-type transistors, and the third transistor and the sixth transistor are N-type transistors.

[0192] Another embodiment of the present disclosure provides an adaptive noise suppression method for a memory element. The memory element includes a receiver circuit having a differential amplifier, a first on-die terminator, and a second on-die terminator. The method includes the following steps: determining whether a first data strobe signal and a second data strobe signal from a memory controller satisfy a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setting value associated with the first on-die terminator and the second on-die terminator is greater than N, where N is a positive integer; and in response to the mode register setting value not being greater than N, disconnecting a first resistor and a second resistor from a first input terminal and a second input terminal of the differential amplifier, respectively; and in response to the mode register setting value being greater than N, coupling the first resistor and the second resistor to the first input terminal and the second input terminal of the differential amplifier, respectively.

[0193] In some embodiments, the method further comprises the steps of: in response to the first data strobe signal and the second data strobe signal satisfying the first condition, decoupling the first resistor and the second resistor from the first input terminal and the second input terminal of the differential amplifier, respectively.

[0194] In some embodiments, the first condition indicates that the first data strobe signal and the second data strobe signal are in a low logic state.

[0195] In some embodiments, a first resistance value of the first die terminator and a second resistance value of the second die terminator are determined based on the mode register setting values corresponding to the first die terminator and the second die terminator.

[0196] In some embodiments, the receiver circuit further comprises a noise suppression control circuit, a first noise suppression circuit, and a second noise suppression circuit. The method further comprises the steps of: amplifying the first data strobe signal and the second data strobe signal by the differential amplifier to generate a third data strobe signal and a fourth data strobe signal; generating a noise suppression control signal by the noise suppression control circuit according to the mode register setting values corresponding to the first die terminator and the second die terminator; selectively coupling the first resistor to the first input terminal of the differential amplifier by the first noise suppression circuit according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal; and selectively coupling the second resistor to the second input terminal of the differential amplifier by the second noise suppression circuit according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal.

[0197] In some embodiments, in response to the mode register setting value being greater than a specific value, the noise suppression control signal generated by the noise suppression control circuit is in a high logic state, and in response to the mode register setting value being equal to or less than the specific value, the noise suppression control signal generated by the noise suppression control circuit is in a low logic state.

[0198] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0199] Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can be used according to the present disclosure and have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: A memory cell array; A control circuit configured to control data access to the memory cell array; And A receiver circuit configured to receive a first data strobe signal and a second data strobe signal from a memory controller, wherein the receiver circuit includes: A differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal; A first on-die terminator coupled to a first input of the differential amplifier; A second on-die terminator coupled to a second input of the differential amplifier; A noise suppression control circuit configured to generate a noise suppression control signal according to a mode register setting value corresponding to the first on-die terminator and the second on-die terminator; A first noise suppression circuit configured to selectively couple a first resistor to the first input of the differential amplifier according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal; and A second noise suppression circuit configured to selectively couple a second resistor to the second input of the differential amplifier according to the third data strobe signal, the fourth data strobe signal, and the noise suppression control signal.

2. The memory element according to claim 1, wherein a first resistance value of the first on-die terminator and a second resistance value of the second on-die terminator are substantially the same.

3. The memory element according to claim 2, wherein the first resistance value and the second resistance value are determined according to the mode register setting value corresponding to the first on-die terminator and the second on-die terminator.

4. The memory element according to claim 3, wherein when the mode register setting value is equal to 0, the first on-die terminator and the second on-die terminator are open circuits.

5. The memory element according to claim 4, wherein when the mode register setting value is set to 1, a third resistance value of the first resistor and a fourth resistance value of the second resistor are substantially equal to the first resistance value and the second resistance value.

6. The memory element according to claim 1, wherein in response to the mode register setting value being greater than a specific value, the noise suppression control signal generated by the noise suppression control circuit is in a high logic state, and in response to the mode register setting value being equal to or less than the specific value, the noise suppression control signal generated by the noise suppression control circuit is in a low logic state.

7. The memory element according to claim 6, wherein the specific value is 2.

8. The memory element according to claim 6, wherein the first noise suppression circuit includes: A first transistor having a control end coupled to the third data strobe signal, a first end coupled to the first input of the differential amplifier, and a second end coupled to a first node; A second transistor having a control end coupled to the fourth data strobe signal, a first end coupled to the first node, and a second end coupled to a second node; The first resistor is coupled between the second node and a third node; and a third transistor having a control terminal coupled to the noise suppression control signal, a first terminal coupled to the third node, and a second terminal coupled to a ground voltage.

9. The memory element according to claim 8, wherein the second noise suppression circuit comprises: a fourth transistor having a control terminal coupled to the third data strobe signal, a first terminal coupled to the second input terminal of the differential amplifier, and a second terminal coupled to a fourth node; a fifth transistor having a control terminal coupled to the fourth data strobe signal, a first terminal coupled to the fourth node, and a second terminal coupled to a fifth node; the second resistor coupled between the fifth node and a sixth node; and a sixth transistor having a control terminal coupled to the noise suppression control signal, a first terminal coupled to the sixth node, and a second terminal coupled to the ground voltage.

10. The memory element according to claim 9, wherein the first transistor, the second transistor, the fourth transistor, and the fifth transistor are P-type transistors, and the third transistor and the sixth transistor are N-type transistors.

11. The memory element according to claim 10, wherein when any one of the third data strobe signal and the fourth data strobe signal is in the high logic state, the first resistor and the second resistor are respectively decoupled from the first input terminal and the second input terminal of the differential amplifier.

12. The memory element according to claim 11, wherein when the third data strobe signal and the fourth data strobe signal are in the low logic state and the noise suppression control signal is in the high logic state, the first resistor and the second resistor are respectively coupled to the first input terminal and the second input terminal of the differential amplifier.

13. A memory element, comprising: a memory cell array; a control circuit configured to control data access of the memory cell array; and an interface circuit configured to receive a first data strobe signal and a second data strobe signal from a memory controller, wherein the interface circuit comprises: a receiver circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal; wherein in response to the first data strobe signal and the second data strobe signal satisfying a predetermined condition, the receiver circuit is further configured to selectively couple a first resistor and a second resistor to the first data strobe signal and the second data strobe signal respectively for noise suppression based on a mode register setting value.

14. The memory element according to claim 13, wherein the receiver circuit comprises: a differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal; a first on-die terminator coupled to a first input terminal of the differential amplifier; and A second on-die terminator coupled to a second input of the differential amplifier; wherein a first resistance value of the first on-die terminator and a second resistance value of the second on-die terminator are determined based on the mode register setting.

15. The memory element according to claim 14, wherein the first resistance value of the first on-die terminator and the second resistance value of the second on-die terminator are substantially the same.

16. The memory element according to claim 15, wherein when the mode register setting is equal to 0, the first on-die terminator and the second on-die terminator are open circuits.

17. The memory element according to claim 15, wherein the receiver circuit further comprises: a noise suppression control circuit configured to generate a noise suppression control signal according to the mode register setting corresponding to the first on-die terminator and the second on-die terminator; a first noise suppression circuit configured to selectively couple the first resistor to the first input of the differential amplifier according to a first control signal, a second control signal, and the noise suppression control signal; and a second noise suppression circuit configured to selectively couple the second resistor to the second input of the differential amplifier according to the first control signal, the second control signal, and the noise suppression control signal.

18. The memory element according to claim 17, wherein the first control signal and the second control signal are the third data strobe signal and the fourth data strobe signal respectively.

19. The memory element according to claim 17, wherein the first control signal and the second control signal are the first data strobe signal and the second data strobe signal respectively.

20. The memory element according to claim 17, wherein the receiver circuit further comprises: a first amplifier configured to amplify the first data strobe signal to generate a first amplified data strobe signal; and a second amplifier configured to amplify the second data strobe signal to generate a second amplified data strobe signal; wherein the first control signal and the second control signal are the first amplified data strobe signal and the second amplified data strobe signal respectively.

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