Decoder device and decoding method used in flash memory controller
By introducing the first and second bucket shifters operating in parallel in the flash memory controller, the problems of high complexity and long delay in the prior art are solved, and the calculation accuracy and efficiency are improved.
Patent Information
- Application Number
- CN202410270906.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-02
- Filing Date
- 2024-03-11
- Publication Date
- 2025-07-04
AI Technical Summary
The decoder circuits in existing flash memory controllers have high design complexity and low calculation accuracy, and traditional bucket shifter circuits need to wait for operation to complete, resulting in a long delay.
A new decoder device is adopted, including a symmetry calculation check circuit, a first and second barrel shifter, a variable weighting and calculation circuit and a flip circuit. The first and second barrel shifters operating in parallel are rotated in the field of variable nodes, reducing the circuit design complexity and delay stages.
Improve the calculation accuracy and efficiency of the decoder, reduce circuit design complexity and delay time, and achieve faster data processing.
Smart Images
Figure CN120260651A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a decoding mechanism, particularly a decoder device and a decoding method used in a flash memory controller.
Background Art
[0002] Generally speaking, two traditional barrel shifter circuits are required for the current decoder circuit. The rotation calculation operation of one traditional barrel shifter circuit rotates from the domain of the variable node to the domain of the check node, and the rotation calculation operation of the other traditional barrel shifter circuit then rotates back from the domain of the check node to the domain of the variable node. These two traditional barrel shifter circuits are located in the same circuit loop, so the number of delay stages of the circuit unit is also relatively large, which greatly affects the calculation accuracy of the decoder circuit. In addition, the operation of rotating between the domain of the variable node and the domain of the check node in the prior art also results in a relatively high circuit design complexity of the traditional barrel shifter circuit, making it difficult to implement.
Summary of the Invention
[0003] Therefore, one of the objectives of the present invention is to provide a novel decoder device and a decoding method in a flash memory controller to solve the problems encountered in the prior art.
[0004] According to an embodiment of the present invention, a decoder device used in a flash memory controller is disclosed. The flash memory controller is used to be coupled between a host device and a flash memory. The decoder device includes a syndrome calculation check circuit, a first barrel shifter, a second barrel shifter, a variable weighted sum calculation circuit, and a flip circuit. The syndrome calculation check circuit is used to calculate a syndrome value of a variable node V i of a parity check matrix according to multiple bits of the received input data, where the parity check matrix includes multiple variable nodes V1 to V N and multiple check nodes C1 to C M forming an N×M sub-matrix, and the value of i is one of 1 to N. The first barrel shifter is coupled to the syndrome calculation check circuit and is used to rotate the syndrome value of the variable node V i to the vertical direction of a variable node V i+1 to generate an estimated syndrome value of the variable node V i+1 The second barrel shifter is coupled to the syndrome calculation check circuit and is used to rotate a syndrome value of a variable node V i-1 to a variable node V i+Δin the vertical direction to generate information of a rotated syndrome value. A variable weighted sum calculation circuit is coupled to the second barrel shifter and is used to determine a plurality of weight values according to the information of the plurality of rotated syndrome values output by the second barrel shifter to perform a weighted sum calculation on the information of the plurality of rotated syndrome values to generate a flip function value. A flip circuit is coupled to the variable weighted sum calculation circuit and is used to compare the flip function value with a flip threshold to generate a flip result. The syndrome calculation check circuit determines whether to correct a specific bit of the plurality of bits according to the flip result. When it is determined to correct the specific bit, the syndrome calculation check circuit performs the variable node V based on the corrected bit i+1 of a syndrome value, and when it is determined not to correct the specific bit, the syndrome calculation check circuit uses the estimated syndrome value generated by the first barrel shifter for the variable node V i+1 as the syndrome value of the variable node V i+1 According to an embodiment of the present invention, there is further disclosed a decoding method for a decoder device used in a flash memory controller. The flash memory controller is used to be coupled between a host device and a flash memory, and the decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of a variable node V of a parity check matrix according to a plurality of bits of received input data. The parity check matrix includes a plurality of variable nodes V1 to V
[0005] and a plurality of check nodes C1 to C i forming an N×M submatrix, where the value of i is one of 1 to N; using a first barrel shifter to rotate the syndrome value of the variable node V N to the vertical direction of a variable node V M to generate an estimated syndrome value of the variable node V i ; using a second barrel shifter to rotate a syndrome value of a variable node V i+1 to the vertical direction of a variable node V i+1 to generate information of a rotated syndrome value; using a variable weighted sum calculation circuit to determine a plurality of weight values according to the information of the plurality of rotated syndrome values output by the second barrel shifter to perform a weighted sum calculation on the information of the plurality of rotated syndrome values to generate a flip function value; and comparing the flip function value with a flip threshold to generate a flip result. Wherein the syndrome calculation check circuit determines whether to correct a specific bit of the plurality of bits according to the flip result. When it is determined to correct the specific bit, the syndrome calculation check circuit performs the variable node V based on the corrected bit i-1 ; using a second barrel shifter to rotate a syndrome value of a variable node V i+Δ to the vertical direction of a variable node V i+1a symptom value, and when it is determined not to correct the specific bit, the symptom calculation check circuit uses the variable node V generated by the first barrel shifter i+1 of the estimated symptom value as the variable node V i+1 of the symptom value.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a block diagram of a flash memory controller according to an embodiment of the present invention.
[0007] Figure 2 is Figure 1 a circuit diagram of a bit flip decoder device included in the flash memory controller shown.
[0008] Figure 3 is a schematic diagram of the implementation comparison between the second barrel shifter of the present invention and the barrel shifter of the prior art.
[0009]
SYMBOL DESCRIPTION
[0010] 100: Flash memory controller
[0011] 101: Host device
[0012] 102: Flash memory
[0013] 105DR: De-randomizer
[0014] 105R: Randomizer
[0015] 110DE: Decoder
[0016] 110EN: Encoder
[0017] 205: Channel value memory
[0018] 210: Variable node memory
[0019] 215: Bit flip decoder
[0020] 220: Symptom calculation check circuit
[0021] 225A: First barrel shifter
[0022] 225B: Second barrel shifter
[0023] 230: Variable weighted sum calculation circuit
[0024] 235: Flip circuit
DETAILED DESCRIPTION
[0025] Please refer to Figure 1 and Figure 2 ,Figure 1 FIG. Figure 1 is a block diagram of a flash memory controller 100 according to an embodiment of the present invention. Figure 2 FIG. Figure 1 Figure 1 is a circuit diagram of a bit flipping decoder device included in the flash memory controller 100 shown. As Figure 1 shown, the flash memory controller 100 is coupled between a host device 100 and a flash memory 102. The flash memory controller 100 includes a randomizer 105R, a de-randomizer 105DR, an encoder 110EN, and a decoder 110DE. The flash memory 102 includes a plurality of flash memory chips, such as NAND flash memory chips. For example, when the host device 101 desires to write a data to one or more flash memory chips in the flash memory 102, the data to be written (e.g., simply referred to as a write data) is first transmitted to the flash memory controller 100. The randomizer 105R performs a randomization operation on the write data to generate a randomized write data, eliminating the data skew of the write data to reduce the occurrence of bit errors. Then, the encoder 110EN performs an encoding operation (e.g., encoding with a low-density parity-check code (LDPC), but not limited) on the randomized write data to generate an encoded write data, and writes the encoded write data to one or more flash memory chips of the flash memory 102.
[0026] In addition, when the host device 101 desires to read a data from one or more flash memory chips in the flash memory 102, the data to be read (e.g., simply referred to as a read data) is first transmitted to the flash memory controller 100. The decoder 110DE performs a decoding operation (e.g., LDPC decoding operation, but not limited) on the read data to generate a decoded read data, and transmits the decoded read data to the de-randomizer 105DR. Then, the de-randomizer 105DR performs a de-randomization operation on the decoded data to generate a de-randomized read data, and transmits the de-randomized read data to the host device 101.
[0027] It should be noted that the randomizer 105R and the de-randomizer 105DR operate in pairs. In another embodiment, the flash memory controller 100 may also not include the randomizer 105R and the de-randomizer 105DR; this example also applies to the present invention.
[0028] As Figure 2As shown, the decoder 110DE is, for example, a bit flip decoder device and includes a channel value memory 205, a variable node memory 210, and a bit flip decoder 215. The bit flip decoder 215 includes a syndrome calculation check unit / circuit, a first barrel shifter 225A, a second barrel shifter 225B, a variable weighted-sum calculation unit / circuit 230, and a flipping unit / circuit 235.
[0029] In one embodiment, the operations of both the first barrel shifter 225A and the second barrel shifter 225B are parallel to the operation of the flipping circuit 235. That is, the operations of both the first barrel shifter 225A and the second barrel shifter 225B and the operation of the flipping circuit 235 can be processed simultaneously and separately, without waiting for any one operation to complete before being able to operate. Compared with the prior art flipping operation that must wait for the barrel shifting operation to complete before being able to operate, the present invention can save a large amount of time.
[0030] In addition, the operation of the bit flip decoder device 110DE is a rotation in the all variable domain. The rotations of the two barrel shifters 225A and 225B in this case for bit positions according to the content of a parity check matrix are only from the domain of variable nodes to the domain of variable nodes, and do not involve a conversion from the domain of variable nodes to the domain of check nodes. Compared with the prior art barrel shifting operation that involves a conversion from the domain of variable nodes to the domain of check nodes, which requires a relatively complex circuit to implement, the two barrel shifters 225A and 225B of the present invention are relatively easy to implement in terms of circuit.
[0031] Specifically, the value of the read data initially received by the decoder 110DE from the flash memory 102 will be stored in the channel value memory 205. In this embodiment, the decoder 110DE is applied to a storage device, so the received data value may be, for example, data read from one or more flash memories. If it is applied to a communication system, the received data value may be, for example, data received from a mobile communication device such as a mobile phone. The channel value memory 205 may receive and store the value of the read data in the form of a code word. At this time, the value of the received data is located in the field of the variable node.
[0032] The variable node memory 210 is used to store the value obtained by converting the symptom value from the domain of one variable node to the domain of another variable node after the symptom value is calculated. For example, when performing a rotation operation on the domain of a column and a row of variable nodes, for example, when calculating the variable node V of the i-th row, i When performing a rotation operation on the symptom value, the variable node V of the i-1th row needs to be stored first. i-1 The value of the rotation operation on the syndrome value needs to use the variable node memory 210 to store the value of the rotation operation on the syndrome value of different variable nodes. Therefore, the variable node memory 210 is equivalently used to store the intermediate value generated when the rotation operation is performed.
[0033] Please refer to Figure 2 , Figure 2 For example, a parity check matrix shown in FIG. 1 includes N variable nodes V1 to V N (N is, for example, 8) and M check nodes C1 to C M (M is, for example, 4) to form N×M (for example, 32) sub-matrices, each of which includes a black dot representing a value of 1, and a value of a blank space not including a black dot is 0. For example, a sub-matrix corresponding to a check node C1 in the vertical direction of the variable node V7 is an n-order identity matrix, where n is, for example, 10 or 12 (but not limited), corresponding to the number of bits of received input data (not limited); Figure 2 The sub-matrix shown is a 12-order matrix, but this is not a limitation of the present invention. The values included in other sub-matrices are similar, and are not described in detail for simplicity.
[0034] The conversion / rotation operation of the present invention is an operation that converts / rotates a symptom value from the domain of one variable node to the domain of another variable node to obtain the rotated value, and does not involve the operation of converting / rotating from the domain of one variable node to the domain of one check node. Therefore, the design complexity and circuit cost of the barrel shifter can be reduced. Specifically, the symptom calculation check circuit 220 will first perform the symptom value calculation of different variable nodes (such as V i-1 、V i ) in sequence according to the data values stored in the channel value memory 205 (i.e., the read data values, such as 10 or 12 bits). The value of i is one of 1 to N. For example, the symptom value calculation of variable node V6 is performed, that is, the sub-matrix of all check nodes corresponding to the vertical direction of variable node V6 is used to calculate a symptom value for the read data value in sequence. Then, the first barrel shifter 225A will rotate the symptom value calculated by the symptom calculation check circuit 220 to the vertical direction of the next variable node V i+1 to generate an estimated symptom value of the variable node V i+1 , that is, the first barrel shifter 225A will rotate the symptom value of variable node V6 calculated by the symptom calculation check circuit 220 to the vertical direction of the next variable node V7.
[0035] In addition, the second barrel shifter 225B needs to be able to rotate the symptom value of the variable node V i-1 calculated by the symptom calculation check circuit 220 to the vertical direction of the variable node V i+Δ at most in sequence. The value of Δ can be designed as, for example, the maximum number of delay stages of the circuit units included in the bit flip decoder 215. For example, in this embodiment, the delay stage of the circuit units of the loop formed by the symptom calculation check circuit 220 and the first barrel shifter 225A is 2 levels, and the delay stage of the circuit units of the loop formed by the symptom calculation check circuit 220, the second barrel shifter 225B, the variable weighted sum calculation circuit 230, and the flip circuit 235A is 4 levels. Therefore, the value of Δ can be designed as 4. That is, in an embodiment, the second barrel shifter 225B will rotate the symptom value of the variable node V i-1 calculated by the symptom calculation check circuit 220 to the vertical direction of the variable node V i+4 at most. If i is equal to 6 (but not limited), the second barrel shifter 225B will rotate the symptom value of the variable node V5 calculated by the symptom calculation check circuit 220 to the direction of the variable node V2. When the barrel shifter performs rotation and selects the last variable node V8, it will start from the first variable node V1 again.
[0036] Next, the variable weighted sum calculation circuit 230 will calculate a weighted sum based on the rotated syndrome values generated by the rotation of the second barrel shifter 225B (i.e., the syndrome values of the variable node V i-1 are rotated to the direction of the variable node V i+4 ), for the information of the multiple rotated syndrome values corresponding to the previous multiple bits stored in the variable node memory 210 (e.g., multiple syndrome values previously rotated to the direction of the variable node), for example, the variable weighted sum calculation circuit 230 can determine multiple weighted values according to the information of the multiple rotated syndrome values corresponding to the previous multiple bits to perform a weighted sum calculation on the multiple rotated syndrome values to generate a flipping function value. Then, the flipping circuit 235 will compare the flipping function value with a flipping threshold to determine whether to flip a currently received bit (i.e., determine whether to flip a bit (e.g., '1') to another bit '0', but not limited), to generate a flipping result, where the flipping threshold can also be dynamically updated by the variable weighted sum calculation circuit 230. The syndrome calculation check circuit 220 then corrects or does not correct a specific bit (e.g., the currently latest received bit) among the multiple bits according to a flipping result (the bit is flipped or not flipped) of the flipping circuit 235. For example, when performing bit correction, the syndrome calculation check circuit 22 will use the corrected bit to recalculate the syndrome value of the variable node V i+1 , otherwise, it can directly use the estimated syndrome value rotated by the first barrel shifter 225A to the variable node V i+1 to obtain the syndrome value of the variable node V i+1 . In an embodiment, when the syndrome value calculated using the corrected bit is equal to 0, it can indicate that the data of the multiple bits has been correctly decoded, that is, for example, the errors in the original multiple bits have been corrected to obtain the correct data.
[0037] Compared with the prior art, the rotation of the barrel shifter in the prior art is from the domain of one variable node to the domain of one check node, and then back from the domain of the check node to the domain of the variable node. The barrel shifter in the prior art is more difficult to implement. Please refer to Figure 3 , Figure 3 is a schematic diagram for comparing the implementation of the second barrel shifter 225B of the present invention with the barrel shifter of the prior art. As Figure 3As shown in part (a), when the received input data is z bits, in the implementation of the selector circuit of the prior art barrel shifter, the range of the input shift index value, for example, needs to include 0 to (z - 1), that is, the prior art barrel shifter needs to be able to support the situation of shifting (z - 1) bits. In addition, the rotation operation of the prior art barrel shifter rotates from the neighborhood of a variable node to the neighborhood of a check node, and then rotates back from the neighborhood of the check node to the neighborhood of the variable node. For example, taking the parity check matrix shown in Figure 2 rotating from the direction of variable node V6 to the direction of check node C1 and then rotating back from the direction of check node C1 to the direction of variable node V6 as an example, for the position arrangement of the black dot data in the first sub-matrix of variable node V6, taking a 10-order sub-matrix as an example, it is, for example, {8, 9, 0, 1,..., 5, 6, 7} in sequence. The prior art barrel shifter, for example, needs to subtract 8 from the position information to shift the data of each black dot in the first sub-matrix 8 bits to the left to achieve the rotation from the direction of variable node V6 to the direction of check node C1. Then, when rotating back from the direction of check node C1 to the direction of variable node V6, it is necessary to shift the data of each black dot 8 bits to the right to cancel the previous rotation. Then, in the embodiment of the present invention, when rotating from the direction of variable node V6 to the direction of variable node V7, the first barrel shifter 225A only needs to shift the data of each black dot in the above first sub-matrix 8 bits to the left to be able to achieve the rotation from the direction of variable node V6 to the direction of variable node V7.
[0038] In addition, as Figure 3 shown in part (b), when the received input data is z bits, in the implementation of the second barrel shifter 225B in the embodiment of the present invention, the range of the input shift index value, for example, needs to include 0 to ε, that is, the second barrel shifter 225B needs to be able to support the situation of shifting ε bits, where ε = max{V i+Δ - V i-1}. For example, when Δ is equal to 4, the second barrel shifter 225B needs to rotate the values in the directions of different variable nodes V1 to V8 to the corresponding directions of variable nodes V1 to V8. Therefore, according to the content of the parity check matrix shown in Figure 2 , it can be known that the second barrel shifter 225B only needs to be able to support the situation of shifting ε bits and does not need to support the situation of shifting z - 1 bits. That is to say, ε can be less than the value of z - 1. In this way, the circuit design of the second barrel shifter 225B can be more easily implemented, reducing the circuit cost.
[0039] In summary, the two barrel shifters 225A and 225B of the present invention are located on two different arithmetic circuits. Therefore, the rotation operations of the barrel shifters 225A and 225B can be processed simultaneously and in parallel. In addition, since the arithmetic circuit where the barrel shifter 225B of the present invention is located does not involve rotation operations between the variable node domain and the check node domain, one circuit unit delay stage can be reduced compared with the prior art. That is, one unit processing time can be saved compared with the prior art, and operations can be performed more instantaneously than the prior art. Therefore, the resulting syndrome value result will be more accurate.
[0040] Furthermore, other different sequences can also be applied to the parity check matrix of the embodiments of the present invention. For example, a Sidon sequence with strictly increasing values can be used for implementation, or different sequences with strictly decreasing values can also be used for implementation.
[0041] The above description is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
Claims
1. A decoder device used in a flash memory controller, the flash memory controller being used to couple between a host device and a flash memory, and the decoder device comprising: A syndrome calculation check circuit for calculating a syndrome value of a variable node V of a parity check matrix according to a plurality of bits of received input data, where the parity check matrix includes a plurality of variable nodes V1 to V i and a plurality of check nodes C1 to C N form N×M sub-matrices, and the value of i is one of 1 to N; M A first bucket shifter, coupled to the symptom calculation and inspection circuit, is used to rotate the symptom value of the variable node V i to the vertical direction of a variable node V i+1 to generate an estimated symptom value of the variable node V i+1 ; A second barrel shifter, coupled to the symptom calculation and inspection circuit, is used to rotate a symptom value of a variable node V i-1 to the vertical direction of a variable node V i+Δ to generate information of a rotated symptom value; A variable weighted sum calculation circuit is coupled to the second barrel shifter, and is used to determine a plurality of weight values according to the information of the plurality of rotated symptom values output by the second barrel shifter, so as to perform a weighted sum calculation on the information of the plurality of rotated symptom values to generate a flip function value; And A flip circuit, coupled to the variable weighted sum calculation circuit, for comparing the flip function value with a flip threshold to generate a flip result; Among them, the symptom calculation and checking circuit determines whether to correct a specific bit of the multiple bits according to the flip result. When it is determined to correct the specific bit, the symptom calculation and checking circuit performs the variable node V based on the corrected bit i+1 of a symptom value. When it is determined not to correct the specific bit, the symptom calculation and checking circuit uses the estimated symptom value of the variable node V generated by the first barrel shifter i+1 as the symptom value of the variable node V i+1 of the symptom value.
2. The decoder device according to claim 1, characterized in that Both the first barrel shifter and the second barrel shifter operate in the variable node domain and do not perform an operation of rotating from a variable node domain to a check node domain.
3. The decoder device according to claim 1, characterized in that, The value of Δ is equal to the maximum number of delay stages of the circuit units included in the decoder device.
4. The decoder device according to claim 3, characterized in that, The value of Δ is equal to 4.
5. The decoder device according to claim 1, wherein, The first barrel shifter and the second barrel shifter operate in parallel, and the circuit loop where the first barrel shifter is located is different from the circuit loop where the second barrel shifter is located.
6. A decoding method for a decoder device used in a flash memory controller, the flash memory controller being used to couple between a host device and a flash memory, and the decoding method comprising: Use a syndrome calculation check circuit to calculate a variable node V of a parity check matrix based on multiple bits of received input data i of a syndrome value, the parity check matrix including multiple variable nodes V1 to V N and multiple check nodes C1 to C M forming an N×M submatrix, where the value of i is one of 1 to N; Use a first barrel shifter to rotate the syndrome value of the variable node V i to the vertical direction of a variable node V i+1 to generate an estimated syndrome value of the variable node V i+1 ; Use a second barrel shifter to rotate a symptom value of a variable node V i-1 to a vertical direction of a variable node V i+Δ to generate information of a rotated symptom value; Using a variable weighted sum calculation circuit to determine a plurality of weight values according to the information of the plurality of rotated syndrome values output by the second barrel shifter to perform a weighted sum calculation on the information of the plurality of rotated syndrome values to generate a flip function value; and Comparing the flip function value with a flip threshold to generate a flip result; Among them, the symptom calculation and inspection circuit determines whether to correct a specific bit of the multiple bits according to the flip result. When it is determined to correct the specific bit, the symptom calculation and inspection circuit performs the variable node V based on the corrected bit. i+1 of a symptom value, and when it is determined not to correct the specific bit, the symptom calculation and inspection circuit uses the estimated symptom value generated by the first barrel shifter for the variable node V i+1 as the symptom value of the variable node V i+1 of.
7. The decoding method according to claim 6, characterized in that Both the first barrel shifter and the second barrel shifter operate in the variable node domain and do not perform an operation of rotating from a variable node domain to a check node domain.
8. The decoding method according to claim 6, characterized in that The value of Δ is equal to the maximum number of delay stages of the circuit units included in the decoder device.
9. The decoding method according to claim 8, wherein The value of Δ is equal to 4.
10. The decoding method according to claim 6, wherein The first barrel shifter and the second barrel shifter operate in parallel, and the circuit loop where the first barrel shifter is located is different from the circuit loop where the second barrel shifter is located.