Shift register and gate drive circuit

Abstract

The invention discloses a shift register and a gate drive circuit. The shift register comprises an input module, a first control module, a second control module and a first output module, the first control module is connected with the first node and the second node and used for controlling the potential of the second node according to the potential of the first node. The second control module is connected with the input module and / or the first control module and is used for controlling positive correlation or negative correlation between the potential of the third node and the potential of the second node; the first output module is respectively connected with the second node and the third node, and is used for responding to the potential of the second node and outputting the first potential signal as a first scanning signal, or responding to the potential of the third node and outputting the second potential signal as the first scanning signal; at least one of the input module, the first control module and the second control module comprises a P-type transistor and an N-type transistor. The shift register provided by the embodiment of the invention is relatively low in power consumption.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a shift register and a gate driving circuit. Background Art

[0002] With the continuous development of display technologies, the application scope of display panels is becoming increasingly wide, and people's requirements for display panels are also getting higher and higher. A display panel includes a pixel circuit and a shift register that provides a scanning signal for the pixel circuit. Existing shift registers have the problem of high power consumption. Summary of the Invention

[0003] The present invention provides a shift register and a gate driving circuit with relatively low power consumption.

[0004] In a first aspect, an embodiment of the present invention provides a shift register, including: an input module, a first control module, a second control module, and a first output module; an output end of the input module is connected to a first node, and is configured to control a potential of the first node according to a first clock signal, a second clock signal, and an input signal; the first control module is respectively connected to the first node and a second node, and is configured to control a potential of the second node according to the potential of the first node; the second control module is connected to the input module and / or the first control module, and is configured to control a potential of a third node to be positively or negatively correlated with the potential of the second node; the first output module is respectively connected to the second node and the third node, and is configured to output a first potential signal as a first scanning signal in response to the potential of the second node, or output a second potential signal as the first scanning signal in response to the potential of the third node; wherein, at least one of the input module, the first control module, and the second control module includes a P-type transistor and an N-type transistor.

[0005] In a second aspect, an embodiment of the present invention provides a gate driving circuit, including: the shift register provided in the first aspect; wherein an output end of the previous-stage shift register is connected to an input end of an input module of the next-stage shift register.

[0006] In a third aspect, an embodiment of the present invention provides a gate driving circuit, including: the shift register of the first aspect, and the shift register of the first aspect is used as a starting shift register, wherein a fourth inverter is included in the first control module of the starting shift register; the fourth inverter is connected between the first node and the second node, and is configured to transmit a first potential signal or a second potential signal to the second node in response to the potential of the first node.

[0007] Optionally, the fourth inverter includes a twenty-third transistor and a twenty-fourth transistor. The gate of the twenty-third transistor is connected to the first node, the first pole of the twenty-third transistor is connected to the first potential signal, and the second pole of the twenty-third transistor is connected to the second node; the gate of the twenty-fourth transistor is connected to the first node, the first pole of the twenty-fourth transistor is connected to the second potential signal, and the second pole of the twenty-fourth transistor is connected to the second node. Optionally, the twenty-third transistor is a P-type transistor and the twenty-fourth transistor is an N-type transistor.

[0008] Optionally, the first control module further includes a fifth inverter and a fourth potential control unit; the fifth inverter is connected between the second node and the eighth node for inverting the potential of the second node and transmitting it to the eighth node; the control terminal of the fourth potential control unit is connected to the second clock signal, the first terminal of the fourth potential control unit is connected to the first node, and the second terminal of the fourth potential control unit is connected to the eighth node. The fourth potential control unit is configured to respond to the second clock signal and transmit the potential of the eighth node to the first node.

[0009] Optionally, the fifth inverter includes a twenty-fifth transistor and a twenty-sixth transistor. The gate of the twenty-fifth transistor is connected to the second node, the first pole of the twenty-fifth transistor is connected to the first potential signal, and the second pole of the twenty-fifth transistor is connected to the eighth node; the gate of the twenty-sixth transistor is connected to the second node, the first pole of the twenty-sixth transistor is connected to the second potential signal, and the second pole of the twenty-sixth transistor is connected to the eighth node. Optionally, the twenty-fifth transistor is a P-type transistor and the twenty-sixth transistor is an N-type transistor.

[0010] Optionally, the fourth potential control unit includes a twenty-seventh transistor. The gate of the twenty-seventh transistor serves as the control terminal of the fourth potential control unit, the first pole of the twenty-seventh transistor serves as the first terminal of the fourth potential control unit, and the second pole of the twenty-seventh transistor serves as the second terminal of the fourth potential control unit. Optionally, the twenty-seventh transistor is an N-type transistor.

[0011] Optionally, the second control module includes a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor. The gate of the twenty-eighth transistor is connected to the gate of the twenty-fifth transistor, the first pole of the twenty-eighth transistor is connected to the first potential signal, and the second pole of the twenty-eighth transistor is connected to the gate of the thirty-first transistor and the first pole of the twenty-ninth transistor; the gate of the thirtieth transistor is connected to the eighth node and the second node, the first pole of the thirtieth transistor is connected to the first potential signal, and the second pole of the thirtieth transistor is connected to the gate of the twenty-ninth transistor and the first pole of the thirty-first transistor. The second poles of the twenty-ninth transistor and the thirty-first transistor are both connected to the third potential signal.

[0012] The gate driving circuit further includes a multi-stage output shift register; in the starting shift register, a first control module is configured to output a shift signal; the output shift register includes: a driving control module, a stage transmission output module, a transmission control module, and a second output module; an output end of the driving control module is connected to a ninth node and is configured to transmit the shift signal to the ninth node in response to a first clock signal; the stage transmission output module is connected to the ninth node and is configured to output a first potential signal or a second potential signal to a first output end of the stage transmission output module according to the potential of the ninth node, and is configured to output the first potential signal or the second potential signal to a second output end of the stage transmission output module according to the potential of the first output end of the stage transmission output module; the transmission control module is connected to the first output end and the second output end and is configured to control the potential of a first control end of the second output module according to the potentials of the first output end and the second output end; the first control end of the second output module is connected to the transmission control module, a second control end of the second output module is connected to the first output end of the stage transmission output module, and the second output module is configured to output the first potential signal as a second scan signal in response to the potential of the second control end, or output the second potential signal as the second scan signal in response to the potential of the first control end; wherein, an input end of a first-stage output shift register is connected to the first control module of the starting shift register, and an input end of an (i + 1)-th stage output shift register is connected to the first output end of the stage transmission output module of the i-th stage output shift register, and i is an integer greater than or equal to 1.

[0013] The shift register provided by an embodiment of the present invention includes an input module, a first control module, a second control module, and a first output module. The input module controls the potential of a first node according to a first clock signal, a second clock signal, and an input signal. The first control module controls the potential of a second node according to the potential of the first node. The second control module controls the potential of a third node to be positively or negatively correlated with the potential of the second node, so as to control the first output module to output the first potential signal as a first scan signal in response to the potential of the second node, or output the second potential signal as the first scan signal in response to the potential of the third node, ensuring a stable output of the first scan signal. By setting that at least one of the input module, the first control module, and the second control module includes a P-type transistor and an N-type transistor, wherein the N-type transistor has lower dynamic power consumption than the P-type transistor, therefore, the P-type transistor and the N-type transistor are used in cooperation, which can effectively reduce the power consumption.

[0014] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 It is a schematic structural diagram of a shift register provided by an embodiment of the present invention;

[0017] Figure 2 It is a driving timing diagram of a shift register provided by an embodiment of the present invention;

[0018] Figure 3 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0019] Figure 4 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0020] Figure 5 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0021] Figure 6 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0022] Figure 7 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0023] Figure 8 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention

[0024] Figure 9 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0025] Figure 10 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0026] Figure 11 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0027] Figure 12 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0028] Figure 13 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0029] Figure 14It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0030] Figure 15 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0031] Figure 16 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0032] Figure 17 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0033] Figure 18 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0034] Figure 19 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0035] Figure 20 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0036] Figure 21 It is a driving timing diagram of another shift register provided by an embodiment of the present invention;

[0037] Figure 22 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0038] Figure 23 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0039] Figure 24 It is a driving timing diagram of another shift register provided by an embodiment of the present invention;

[0040] Figure 25 It is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0041] Figure 26 It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0042] Figure 27 It is a schematic structural diagram of an output shift register provided by an embodiment of the present invention;

[0043] Figure 28 It is a driving timing diagram of an output shift register provided by an embodiment of the present invention. Detailed implementation manners

[0044] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solution in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0046] Figure 1 is a schematic structural diagram of a shift register provided by an embodiment of the present invention. As Figure 1 shown, the shift register includes: an input module 10, a first control module 20, a second control module 30, and a first output module 40.

[0047] The output end of the input module 10 is connected to the first node N1, and is used to control the potential of the first node N1 according to the first clock signal CLK1, the second clock signal CLK2, and the input signal SIN.

[0048] The first control module 20 is respectively connected to the first node N1 and the second node N2, and is used to control the potential of the second node N2 according to the potential of the first node N1.

[0049] The second control module 30 is connected to the input module 10 and / or the first control module 20, and is used to control the potential of the third node N3 to be positively or negatively correlated with the potential of the second node N2. Figure 1 The situation where the second control module 30 is connected to the first control module 20 is schematically shown.

[0050] The first output module 40 is respectively connected to the second node N2 and the third node N3, and is used to respond to the potential of the second node N2 and output the first potential signal VGH as the first scan signal S1, or respond to the potential of the third node N3 and output the second potential signal VGL as the first scan signal S1. Among them, at least one of the input module 10, the first control module 20, and the second control module 30 includes a P-type transistor and an N-type transistor.

[0051] Specifically, the display panel where the shift register is located includes a plurality of pixel circuits and light-emitting elements. The shift register is connected to the pixel circuits, and the pixel circuits are connected to the light-emitting elements. The output terminal OUT of the shift register outputs a first scan signal S1. The first scan signal S1 can be used to control the conduction timing of the transistors in the pixel circuit, and further control the pixel circuit to generate a driving current, so that the light-emitting element emits light in response to the driving current. Among them, the output terminal of the first output module 40 serves as the output terminal OUT of the shift register.

[0052] When the types of transistors included in the first output module 40 are the same, the second control module 30 is used to control the potential of the third node N3 to be negatively correlated with the potential of the second node N2. When the types of transistors included in the first output module 40 are different, the second control module 30 is used to control the potential of the third node N3 to be positively correlated with the potential of the second node N2. Exemplarily, when the transistors connected to the second node N2 and the third node N3 are both P-type transistors, the second control module 30 is used to control the potential of the third node N3 to be negatively correlated with the potential of the second node N2. When the transistor connected to the second node N2 is a P-type transistor and the transistor connected to the third node N3 is an N-type transistor, the second control module 30 is used to control the potential of the third node N3 to be negatively correlated with the potential of the second node N2.

[0053] Figure 2 is a driving timing diagram of a shift register provided by an embodiment of the present invention, which can be used to drive Figure 1 the shift register shown in Figure 1 and Figure 2 , the input signal SIN, the first clock signal CLK1, and the second clock signal CLK2 can include a low level and a high level. Optionally, the high level is the same as the first potential signal, and the low level is the same as the second potential signal.

[0054] Among them, the input signal SIN can be a pulse signal with adjustable pulse width. The potentials of the first potential signal VGH and the second potential signal VGL are opposite. For example, when the first potential signal VGH is a high-level signal, the second potential signal VGL is a low-level signal, or when the first potential signal VGH is a low-level signal, the second potential signal VGL is a high-level signal. In this embodiment and the following embodiments, it is schematically illustrated by taking the first potential signal VGH as a high-level signal and the second potential signal VGL as a low-level signal as an example.

[0055] Referring to Figure 1 and Figure 2 , the driving timing of the shift register includes five stages, namely a first stage P1, a second stage P2, a third stage P3, a fourth stage P4, and a fifth stage P5. Taking the signal input by the first potential signal VGH as a high-level signal and the second potential signal VGL as a low-level signal as an example.

[0056] In the first stage P1, the input signal SIN and the first clock signal CLK1 are at low level, and the second clock signal CLK2 is at high level. The input module 10 controls the potential of the first node N1 to be at low level according to the first clock signal CLK1, the second clock signal CLK2 and the input signal SIN. The first control module 20 controls the potential of the second node N2 to be at high level according to the low level of the first node N1. The second control module 30 controls the potential of the third node N3 to be negatively correlated with the potential of the second node N2, that is, the second control module 30 controls the potential of the third node N3 to be at low level. The first output module 40 responds to the potential of the third node N3 and outputs the second potential signal VGL as the first scan signal S1. That is, in the first stage P1, the first scan signal S1 output by the first output module 40 is a low level signal.

[0057] In the second stage P2, the input signal SIN and the first clock signal CLK1 jump to high level, and the second clock signal CLK2 jumps to low level. The input module 10 controls the potential of the first node N1 to jump from low level to high level according to the first clock signal CLK1, the second clock signal CLK2 and the input signal SIN. The first control module 20 controls the potential of the second node N2 to be at low level according to the high level of the first node N1. The second control module 30 controls the potential of the third node N3 to be negatively correlated with the potential of the second node N2, that is, the second control module 30 controls the potential of the third node N3 to be at high level. The first output module 40 responds to the low potential of the second node N2 and outputs the first potential signal VGH as the first scan signal S1. That is, in the second stage P2, the first scan signal S1 output by the first output module 40 is a high level signal.

[0058] In the third stage P3, the input signal SIN remains at high level, the first clock signal CLK1 jumps to low level, and the second clock signal CLK2 jumps to high level. The first node N1 remains at the high level of the previous stage. The first control module 20 controls the potential of the second node N2 to be at low level according to the high level of the first node N1. The second control module 30 controls the potential of the third node N3 to be negatively correlated with the potential of the second node N2, that is, the second control module 30 controls the potential of the third node N3 to be at high level. The first output module 40 responds to the potential of the second node N2 and outputs the first potential signal VGH as the first scan signal S1. That is, in the third stage P3, the first scan signal S1 output by the first output module 40 is a high level signal.

[0059] In the fourth stage P4, the input signal SIN remains high, the first clock signal CLK1 transitions to high, and the second clock signal CLK2 transitions to low. The input module 10 controls the potential of the first node N1 to be low according to the first clock signal CLK1, the second clock signal CLK2, and the input signal SIN. The first control module 20 controls the potential of the second node N2 to be high based on the low potential of the first node N1. The second control module 30 controls the potential of the third node N3 to be negatively correlated with the potential of the second node N2, that is, the second control module 30 controls the potential of the third node N3 to be low. The first output module 40 responds to the potential of the third node N3 and outputs the second potential signal VGL as the first scan signal S1. That is, in the fourth stage P4, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0060] In the fifth stage P5, the input signal SIN remains high, the first clock signal CLK1 transitions to low, and the second clock signal CLK2 transitions to high. The first node N1 maintains the low potential of the fourth stage P4. The first control module 20 controls the potential of the second node N2 to be high based on the low potential of the first node N1. The second control module 30 controls the potential of the third node N3 to be negatively correlated with the potential of the second node N2, that is, the second control module 30 controls the potential of the third node N3 to be low. The first output module 40 responds to the potential of the third node N3 and outputs the second potential signal VGL as the first scan signal S1. That is, in the fifth stage P5, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0061] The shift register provided by the embodiment of the present invention includes an input module, a first control module, a second control module, and a first output module. By setting that at least one of the input module, the first control module, and the second control module includes a P-type transistor and an N-type transistor, this combination forms the basis of a complementary metal oxide semiconductor (CMOS) structure. In a CMOS circuit, when the P-type transistor and the N-type transistor are working, when one is conducting, the other is cutoff, making the static current almost zero. Only when the transistor state switches (i.e., the circuit flips) will there be current flow, effectively reducing power consumption.

[0062] Figure 3 is a schematic structural diagram of another shift register provided by the embodiment of the present invention. Refer to Figure 3 , the second control module 30 is respectively connected to the first node N1 and the third node N3, and is used to respond to the potential of the first node N1 and transmit the first potential signal VGH or the third potential signal VGL2 to the third node N3.

[0063] Specifically, during the operation of the shift register, when the first node N1 is at a high potential, the second control module 30 transmits the first potential signal VGH to the third node N3; when the first node N1 is at a low potential, the second control module 30 transmits the third potential signal VGL2 to the third node N3.

[0064] Optionally, the absolute value of the difference between the third potential signal VGL2 and the first potential signal VGH is greater than the absolute value of the difference between the second potential signal VGL and the first potential signal VGH. That is, |VGL2 - VGH| > |VGL - VGH|. Exemplarily, if the first potential signal VGH is 5V, the second potential signal VGL is 0V, and the third potential signal VGL2 is -3V, then |5 - (-3)| = 8 and |5 - 0| = 5, satisfying this condition.

[0065] Optionally, the absolute value of the difference between the third potential signal VGL2 and the second potential signal VGL is less than the absolute value of the difference between the third potential signal VGL2 and the first potential signal VGH. That is, |VGL2 - VGL| < |VGL2 - VGH|. Exemplarily, if the first potential signal VGH is 5V, the second potential signal VGL is 0V, and the third potential signal VGL2 is -3V, then |-3 - 0| = 3 and |5 - (-3)| = 8, conforming to this relationship.

[0066] When the output transistor connected to the third node N3 is a P-type transistor, it conducts when the gate voltage is at a low potential relative to the source voltage and cuts off when at a high potential. When the P-type transistor frequently switches between the conducting and cutoff states, if the potential is not set reasonably, it is likely to cause fluctuations in the output signal and form ripples. When the second control module 30 transmits the third potential signal VGL2 to the third node N3, due to the sufficient potential difference between the third potential signal VGL2 and the second potential signal VGL, it ensures that the transistor is fully conducting. The fully conducting transistor can provide a stable current path, avoiding signal distortion and fluctuations caused by insufficient conduction.

[0067] Figure 4 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 4 , optionally, the second control module 30 includes a first inverter 301 and a first control unit 302. The first inverter 301 is respectively connected to the first node N1 and the fourth node N4, and is used to invert the potential of the first node N1 and output it to the fourth node N4.

[0068] The first control unit 302 is respectively connected to the first node N1, the third node N3, and the fourth node N4, and is used to transmit the first potential signal VGH or the third potential signal VGL2 to the third node N3 according to the potentials of the first node N1 and the fourth node N4.

[0069] Specifically, the first inverter 301 is used to invert the potential of the first node N1. In a digital circuit, an inverter is a basic logic gate circuit, and its output level is opposite to the input level. For example, if the potential of the first node N1 is high, after being processed by the first inverter 301, the potential output to the fourth node N4 will become low; conversely, if the potential of the first node N1 is low, the potential of the fourth node N4 will become high.

[0070] The first control unit 302 selects one of the first potential signal VGH and the third potential signal VGL2 to transmit to the third node N3 according to the potential conditions of the first node N1 and the fourth node N4. For example, when the first node N1 is at a high potential and the fourth node N4 is at a low potential, the first control unit 302 will transmit the first potential signal VGH to the third node N3; when the first node N1 is at a low potential and the fourth node N4 is at a high potential, the first control unit 302 will transmit the third potential signal VGL2 to the third node N3. In this way, the first control unit 302 realizes the flexible control of the output potential signal according to different node potential states, so as to meet the functional requirements of the shift register in different working stages.

[0071] Figure 5 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 5 Optionally, the first inverter 301 includes a first transistor T1 and a second transistor T2.

[0072] The gate of the first transistor T1 is connected to the first node N1, the first pole of the first transistor T1 is connected to the first potential signal VGH, and the second pole of the first transistor T1 is connected to the fourth node N4.

[0073] The gate of the second transistor T2 is connected to the first node N2, the first pole of the second transistor T2 is connected to the second potential signal, and the second pole of the second transistor T2 is connected to the fourth node N4. Optionally, the first transistor is a P-type transistor and the second transistor T2 is an N-type transistor.

[0074] Specifically, when the first node N1 is at a low potential, the first transistor T1 (P-type transistor) is turned on and the second transistor T2 (N-type transistor) is turned off, and the first potential signal VGH is transmitted to the fourth node N4, and the fourth node N4 is at a high potential. When the first node N1 is at a high potential, the first transistor T1 is turned off and the second transistor T2 is turned on, and the second potential signal VGL is transmitted to the fourth node N4, and the fourth node N4 is at a low potential.

[0075] Continue to refer to Figure 5, optionally, the first control unit 302 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0076] The gate of the third transistor T3 is connected to the first node N1. The first pole of the third transistor T3 receives the first potential signal VGH. The second pole of the third transistor T3 is connected to the gate of the sixth transistor T6 and the first pole of the fifth transistor T5.

[0077] The gate of the fourth transistor T4 is connected to the fourth node N4. The first pole of the fourth transistor T4 receives the first potential signal VGH. The second pole of the fourth transistor T4 is connected to the gate of the fifth transistor T5 and the first pole of the sixth transistor T6.

[0078] The gate of the sixth transistor T6 is connected to the third node N3. The second poles of both the fifth transistor T5 and the sixth transistor T6 receive the third potential signal VGL2. Optionally, the third transistor T3 and the fourth transistor T4 are P-type transistors, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0079] Specifically, the first control unit 302 controls the conduction and cutoff of the fifth transistor T5 and the sixth transistor T6 according to the potential combination of the first node N1 and the fourth node N4 through the cooperative work of four transistors, so as to realize the selection of the signal transmitted to the third node N3.

[0080] Exemplarily, when the first node N1 is at a low potential and the fourth node N4 is at a high potential, the third transistor T3 is turned on and the fourth transistor T4 is turned off. When the third transistor T3 is turned on, the gate of the sixth transistor T6 obtains a high potential and is turned on, transmitting the third potential signal VGL2 to the third node N3; the fifth transistor T5 is turned off because there is no high potential input to its gate. When the first node N1 is at a high potential and the fourth node N4 is at a low potential, the third transistor T3 is turned off and the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, the gate of the fifth transistor T5 obtains a high potential and is turned on, transmitting the third potential signal VGL2 to the second pole of the third transistor T3; the sixth transistor T6 is turned off because there is no high potential input to its gate.

[0081] Figure 6 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 6 , optionally, the input module 10 includes a first potential control unit 101, a second inverter 102, and a second potential control unit 103.

[0082] The output terminal of the first potential control unit 101 is connected to the fifth node N5, and is used to respond to the first clock signal CLK1 and transmit the input signal SIN to the fifth node N5. The second inverter 102 is connected between the fifth node N5 and the sixth node N6, and is used to invert the potential of the fifth node N5 and then transmit it to the sixth node N6. The second potential control unit 103 is connected between the sixth node N6 and the first node N1, and is used to respond to the second clock signal CLK2 and transmit the potential of the sixth node N6 to the first node N1.

[0083] Specifically, when the first clock signal CLK1 is at a high level, the first potential control unit 101 is in a cut-off state, allowing the input signal SIN to pass through and reach the fifth node N5; when the first clock signal CLK1 is at a low level, the first potential control unit 101 is in a conducting state, blocking the transmission of the input signal SIN.

[0084] The second inverter 102 is used to invert the potential of the fifth node N5 and then transmit it to the sixth node N6. That is to say, if the potential of the fifth node N5 is at a high level, after being processed by the second inverter 102, the potential transmitted to the sixth node N6 will become a low level; conversely, if the potential of the fifth node N5 is at a low level, the potential of the sixth node N6 will become a high level.

[0085] The second potential control unit 103 responds to the second clock signal CLK2 and transmits the potential of the sixth node N6 to the first node N1. When the second clock signal CLK2 is at a high level, the second potential control unit 103 is cut off, blocking the transmission of the potential; when the second clock signal CLK2 is at a low level, the second potential control unit 103 is conducting, transmitting the potential of the sixth node N6 to the first node N1.

[0086] Figure 7 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 7 , optionally, the first potential control unit 101 includes a seventh transistor T7. The gate of the seventh transistor T7 is connected to the first clock signal CLK1, the first pole of the seventh transistor T7 is connected to the input signal SIN, and the second pole of the seventh transistor T7 is connected to the fifth node N5. Optionally, the seventh transistor T7 is a P-type transistor.

[0087] Specifically, since the seventh transistor T7 is a P-type transistor, when the first clock signal CLK1 is at a low level, the seventh transistor T7 is conducting. At this time, the input signal SIN can be transmitted to the fifth node N5 through the conducting seventh transistor T7. When the first clock signal CLK1 is at a high level, the seventh transistor T7 is cut off. In the cut-off state, the input signal SIN cannot be transmitted to the fifth node N5 through the seventh transistor T7, and the potential of the fifth node N5 will not be affected by the input signal SIN.

[0088] Continue to refer to Figure 7 , optionally, the second inverter 102 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is connected to the fifth node N5. The first pole of the eighth transistor T8 accesses the first potential signal VGH, and the second pole of the eighth transistor T8 is connected to the sixth node N6. The gate of the ninth transistor T9 is connected to the fifth node N5. The first pole of the ninth transistor T9 accesses the second potential signal VGL, and the second pole of the ninth transistor T9 is connected to the sixth node N6. Optionally, the eighth transistor T8 is a P-type transistor, and the ninth transistor T9 is an N-type transistor.

[0089] Specifically, when the fifth node N5 is at a low potential, at this time, the eighth transistor T8 (P-type transistor) is turned on, and the ninth transistor T9 (N-type transistor) is turned off. The first potential signal VGH is transmitted to the sixth node N6, and the sixth node N6 is at a high potential, realizing the inversion of the low potential of the fifth node N5. When the fifth node N5 is at a high potential, at this time, the eighth transistor T8 is turned off, and the ninth transistor T9 is turned on. The second potential signal VGL is transmitted to the sixth node N6, and the sixth node N6 is at a low potential, realizing the inversion of the high potential of the fifth node N5.

[0090] Continue to refer to Figure 7 , optionally, the second potential control unit 103 includes a tenth transistor T10. The gate of the tenth transistor T10 accesses the second clock signal CLK2. The first pole of the tenth transistor T10 is connected to the sixth node N6, and the second pole of the tenth transistor T10 is connected to the first node N1. Optionally, the tenth transistor T10 is a P-type transistor.

[0091] Specifically, when the second clock signal CLK2 is at a low level, the tenth transistor T10 is turned on. Once the tenth transistor T10 is turned on, the potential signal of the sixth node N6 can be smoothly transmitted to the first node N1 through the tenth transistor T10. For example, if the sixth node N6 is in a high potential state, then the first node N1 will also become a high potential; if the sixth node N6 is at a low potential, the first node N1 will also become a low potential. When the second clock signal CLK2 is at a high level, the tenth transistor T10 is turned off. In the off state, the potential signal of the sixth node N6 cannot be transmitted to the first node N1 through the tenth transistor T10. At this time, the potential of the first node N1 remains in the previous state, or is determined by other relevant circuits, and is not affected by the potential of the sixth node N6.

[0092] Figure 8 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 8 , optionally, the input module 10 further includes a third inverter 104 and a third potential control unit 105.

[0093] The third inverter 104 is connected between the sixth node N6 and the seventh node N7, and is configured to invert the potential of the sixth node N6 and then transmit it to the seventh node N7.

[0094] The control terminal of the third potential control unit 105 is connected to the first clock signal CLK1. The first terminal of the third potential control unit 105 is connected to the fifth node N5, and the second terminal of the third potential control unit 105 is connected to the seventh node N7. The third potential control unit 105 is configured to respond to the first clock signal CLK1 and transmit the potential of the seventh node N7 to the fifth node N5.

[0095] Specifically, without this feedback loop, in some cases, the sixth node N6 may be in a floating state because there is no stable potential driving. Exemplarily, when the first potential control unit 101 is turned off, the second inverter 102 has no signal source and is in a cut-off state, and at this time, the sixth node N6 is in a floating state. When the gate of a transistor is in a floating state, its potential will randomly change due to factors such as electromagnetic interference and stray capacitance in the surrounding environment, resulting in unstable on and off states of the transistor. The entire circuit of the input module 10 provided in this embodiment forms a signal feedback loop. The potential of the sixth node N6 is inverted by the third inverter 104 to obtain the potential of the seventh node N7, and then under the control of the first clock signal CLK1, the potential of the seventh node N7 is fed back to the fifth node N5 through the third potential control unit 105. And the potential of the fifth node N5 will affect the operation of the second inverter 102 connected to the sixth node N6, thus forming a self-loop that can maintain the stability of the potential of the sixth node N6, so that the potential of the sixth node N6 is not in a floating state, ensuring the stable operation of the circuit.

[0096] Figure 9 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 9 , optionally, the third inverter 104 includes an eleventh transistor T11 and a twelfth transistor T12. The gate of the eleventh transistor T11 is connected to the sixth node N6, the first pole of the eleventh transistor T11 is connected to the first potential signal VGH, and the second pole of the eleventh transistor T11 is connected to the seventh node N7.

[0097] The gate of the twelfth transistor T12 is connected to the sixth node N6, the first pole of the twelfth transistor T12 is connected to the second potential signal VGL, and the second pole of the twelfth transistor T12 is connected to the seventh node N7. Optionally, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor.

[0098] Specifically, when the sixth node N6 is at a low potential, the eleventh transistor T11 (P-type transistor) is turned on, and the twelfth transistor T12 (N-type transistor) is turned off. At this time, the first potential signal VGH is transmitted to the seventh node N7, and the seventh node N7 is at a high potential, realizing the inversion of the low potential of the sixth node N6. When the sixth node N6 is at a high potential, the eleventh transistor T11 is turned off, and the twelfth transistor T12 is turned on. At this time, the second potential signal VGL is transmitted to the seventh node N7, and the seventh node N7 is at a low potential, realizing the inversion of the high potential of the sixth node N6.

[0099] Continue to refer to Figure 9 , optionally, the third potential control unit 105 includes a thirteenth transistor T13. The gate of the thirteenth transistor T13 serves as the control end of the third potential control unit 105, the first pole of the thirteenth transistor T13 serves as the first end of the third potential control unit 105, and the second pole of the thirteenth transistor T13 serves as the second end of the third potential control unit 105. Optionally, the thirteenth transistor T13 is an N-type transistor.

[0100] Specifically, when the first clock signal CLK1 is at a high level, the thirteenth transistor T13 is turned on. Once turned on, the potential signal of the seventh node N7 is transmitted to the fifth node N5 through the thirteenth transistor T13. For example, if the seventh node N7 is in a high potential state, then when the thirteenth transistor T13 is turned on, the fifth node N5 will also become high potential; if the seventh node N7 is at a low potential, the fifth node N5 will also become low potential.

[0101] When the first clock signal CLK1 is at a low level, the thirteenth transistor T13 is turned off. In the off state, the potential signal of the seventh node N7 cannot be transmitted to the fifth node N5 through the thirteenth transistor T13. At this time, the potential of the fifth node N5 may remain in the previous state, or be determined by other related circuits, and will not be affected by the potential of the seventh node N7.

[0102] Figure 10 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 10 , the first output module 40 includes: a first output unit 401 and a second output unit 402.

[0103] The first output unit 401 is connected to the second node N2, and is configured to output the first potential signal VGH as the first scan signal S1 according to the potential of the second node N2.

[0104] The second output unit 402 is connected to the third node N3, and is configured to output the second potential signal VGL as the first scan signal S1 according to the potential of the third node N3.

[0105] As a preferred implementation provided by the embodiments of the present invention, optionally, the first output unit 401 includes: a twenty-first transistor T21, the gate of the twenty-first transistor T21 is connected to the second node N2, the first pole of the twenty-first transistor T21 accesses the first potential signal VGH, and the second pole of the twenty-first transistor T21 serves as the output terminal of the first output unit 401.

[0106] The second output unit 402 includes: a twenty-second transistor T22 and a second capacitor C2. The gate of the twenty-second transistor T22 is respectively connected to the third node N3 and the first end of the second capacitor C2. The first pole of the twenty-second transistor T22 is connected to the second end of the second capacitor C2 and serves as the output terminal of the second output unit 402. The second pole of the twenty-second transistor T22 accesses the second potential signal VGL. Optionally, both the twenty-first transistor T21 and the twenty-second transistor T22 are P-type transistors.

[0107] Figure 11 It is a schematic structural diagram of another shift register provided by the embodiments of the present invention. Refer to Figure 11 , optionally, the second control module 30 is respectively connected to the fifth node N5 and the third node N3. The second control module 30 also accesses the first clock signal CLK1. The second control module 30 is used to control the potential of the third node N3 according to the potential of the fifth node N5 and the first clock signal CLK1, so that the potential of the third node N3 is negatively correlated with the potential of the fifth node N5.

[0108] Specifically, the meaning of negatively correlated potential: when the potential of the fifth node N5 rises, the second control module 30 will lower the potential of the third node N3; conversely, when the potential of the fifth node N5 drops, the second control module 30 will raise the potential of the third node N3.

[0109] Optionally, the potentials of the first node N1 and the third node N3 simultaneously change from a low potential to a high potential, and / or, the potentials of the first node N1 and the third node N3 simultaneously change from a high potential to a low potential. The change from a low potential to a high potential can be a rising edge, and the change from a high potential to a low potential can be a falling edge.

[0110] Optionally, the potential of the third node N3 includes a first level signal and a third level signal, and the voltage of the third level signal VGL2 is lower than the voltage of the first level signal.

[0111] Optionally, the absolute value of the voltage difference between the third-level signal VGL2 and the first-level signal VGH is greater than the absolute value of the voltage difference between the second-level signal VGL and the first-level signal VGH. In this way, it can be ensured that when the potential of the third node N3 is the third-level signal VGL2, the twenty-first transistor T21 can be fully turned on, further ensuring that when the twenty-first transistor T21 is turned on, the second-level signal VGL can be transmitted to the output terminal OUT of the shift register with equal amplitude, thereby improving the display effect.

[0112] Optionally, the potential of the third node N3 is negatively correlated with the potential of the fifth node N5, and thus the potential of the third node N3 is positively correlated with the potential of the first node N1. That is, when the fifth node N5 is at a high potential, the third node N3 and the first node N1 are at low potentials; when the fifth node N5 is at a low potential, the third node N3 and the first node N1 are at high potentials.

[0113] Figure 12 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 12 , optionally, the second control module 30 includes a charge-discharge control unit 310, a coupling unit 320, and a unidirectional conduction unit 330.

[0114] The charge-discharge control unit 310 is respectively connected to the fifth node N5, the first end of the coupling unit 320, and the second end of the coupling unit 320. The second end of the coupling unit 320 is connected to the first end of the unidirectional conduction unit 330, and the second end of the unidirectional conduction unit 330 is connected to the third node N3.

[0115] The charge-discharge control unit 310 is configured to charge and / or discharge the coupling unit 320 according to the potential of the fifth node N5 and the first clock signal CLK1. The coupling unit 320 is configured to couple the potential change of its first end to the second end. The unidirectional conduction unit 330 is configured to conduct when the potential of the first end of the unidirectional conduction unit 320 is lower than the potential of the third node N3.

[0116] Among them, the first clock signal CLK1 is a periodic signal, and the first clock signal includes a first potential signal VGH and a second potential signal VGL that are alternately set. Specifically, when the potential of the fifth node N5 is the second potential signal VGL, the charge-discharge control unit 310 transmits the first potential signal VGH to the first end of the coupling unit 320, causing the potential of the first end of the coupling unit 320 to rise. Due to the coupling effect of the coupling unit 320 itself, the potential of the second end of the coupling unit 320 is pulled up, and the unidirectional conduction unit 330 is turned off. When the potential of the fifth node N5 is the first potential signal VGH, the charge-discharge control unit 310 alternately charges and discharges the coupling unit 320 according to the high and low potential transitions of the first clock signal CLK1. Exemplarily, when the potential of the fifth node N5 is the first potential signal VGH and the first clock signal CLK1 jumps from a high level to a low level, the coupling unit 320 discharges, and the potential of the first end of the coupling unit 320 decreases. Due to the coupling effect of the coupling unit 320 itself, the potential of the second end of the coupling unit 320 is pulled down, the unidirectional conduction unit 330 conducts, and the potential of the third node N3 is pulled down, causing the potential of the third node N3 to be lower than the second potential signal VGL, and the second output unit 402 conducts, transmitting the first potential signal VGL to the output end OUT of the shift register with equal amplitude. When the potential of the fifth node N5 is the first potential signal VGH and the first clock signal CLK1 jumps from a low level to a high level, the coupling unit 320 is charged, and the potential of the first end of the coupling unit 320 increases. Due to the coupling effect of the coupling unit 320 itself, the potential of the second end of the coupling unit 320 increases, the unidirectional conduction unit 330 is turned off, and the third node N3 still maintains a low potential, causing the potential of the third node N3 to be lower than the second potential signal VGL, and the second output unit 402 conducts, transmitting the second potential signal VGL to the output end OUT of the shift register with equal amplitude.

[0117] Figure 13 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 13 , optionally, the charge-discharge control unit 310 includes a fourteenth transistor T14 and a fifteenth transistor T15. The gate of the fourteenth transistor T14 is connected to the fifth node N5, the first pole of the fourteenth transistor T14 accesses the first potential signal VGH, and the second pole of the fourteenth transistor T14 is connected to the first end of the coupling unit 320. The gate of the fifteenth transistor T15 is connected to the second end of the coupling unit 320, the first pole of the fifteenth transistor T15 accesses the first clock signal CLK1, and the second pole of the fifteenth transistor T15 is connected to the first end of the coupling unit 320. Optionally, both the fourteenth transistor T14 and the fifteenth transistor T15 are P-type transistors.

[0118] Optionally, the coupling unit 320 includes a first capacitor C1. The first electrode plate of the first capacitor C1 serves as the first end of the coupling unit 320, and the second electrode plate of the first capacitor C1 serves as the second end of the coupling unit 320. Optionally, the unidirectional conduction unit 330 includes a sixteenth transistor T16. The gate of the sixteenth transistor T16 is connected to the first pole of the sixteenth transistor T16. The gate of the sixteenth transistor T16 is connected to the second end of the coupling unit 320, and the second pole of the sixteenth transistor T16 is connected to the third node N3. Optionally, the sixteenth transistor T16 is a P-type transistor.

[0119] Figure 14 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 14 Optionally, the second control module 30 further includes a second control unit 340.

[0120] The control terminal of the second control unit 340 is connected to the first clock signal CLK1. The second end of the second control unit 340 is connected to the first node N1. The second end of the second control unit 340 is connected to the first end of the unidirectional conduction unit 330. The second control unit 340 is configured to transfer the potential of the first node N1 to the first end of the unidirectional conduction unit 330 according to the first clock signal CLK1.

[0121] Continue to refer to Figure 14 Optionally, the second control unit 340 includes a seventeenth transistor T17. The gate of the seventeenth transistor T17 serves as the control terminal of the second control unit 340. The first pole of the seventeenth transistor T17 serves as the first end of the second control unit 340. The second pole of the seventeenth transistor T17 serves as the second end of the second control unit 340. Optionally, the seventeenth transistor T17 is an N-type transistor.

[0122] Specifically, when the shift register starts to operate, the initial level state of the first clock signal CLK1 determines the conduction or cutoff of T17. When the first clock signal CLK1 turns on the seventeenth transistor T17, the potential of the first node N1 is transferred to the first end of the unidirectional conduction unit 330. This potential transfer provides the starting potential condition for the unidirectional conduction unit 330 where the sixteenth transistor T16 is located. Since the conduction or cutoff of the unidirectional conduction unit 330 is closely related to the gate potential of the sixteenth transistor T16, and the potential transferred by the seventeenth transistor T17 affects the gate potential of the sixteenth transistor T16, the conduction or cutoff state of the seventeenth transistor T17 determines the starting working state of the sixteenth transistor T16, thereby affecting the conduction characteristics of the unidirectional conduction unit 330 at the initial stage of the shift register operation.

[0123] Figure 15 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer toFigure 15 , optionally, the second control module further includes a third control unit 350. The control terminal of the third control unit 350 is connected to the second potential signal VGL. The second control unit 340 is connected to the first end of the unidirectional conduction unit 330 through the third control unit 350. The third control unit 350 is configured to conduct or cut off according to the potential difference between the second potential signal VGL and the potential at the second end of the second control unit 340.

[0124] With this arrangement in this embodiment, it is possible to block the transmission of the extremely low potential generated by the coupling effect of the first capacitor C1 at the gate of the sixteenth transistor T16 to the second pole of the seventeenth transistor T17, and avoid the impact of this extremely low potential on the seventeenth transistor T17. Specifically, when the second pole of the seventeenth transistor T17 is at a low potential, since the second potential signal VGL is also at a low potential, the potential difference between the control terminal and the first end of the third control unit 350 is basically 0, making the third control unit 350 in a critical cut-off state. Then, when the first capacitor C1 pulls the gate of the sixteenth transistor T16 down to an extremely low potential, due to the critical cut-off of the third control unit 350, this extremely low potential cannot be transmitted to the second pole of the seventeenth transistor T17 and will not cause an impact on the seventeenth transistor T17. When the gate of the sixteenth transistor T16 is at a high potential, the potential difference between the control terminal and the first end of the third control unit 350 is greater than 0, making the third control unit 350 conduct, and effectively transmitting the high potential at the gate of the sixteenth transistor T16 to the second pole of the seventeenth transistor T17. Therefore, the third control unit 350 only cuts off the transmission path of the extremely low voltage to the second pole of the seventeenth transistor T17, without affecting the normal transmission of the high potential.

[0125] , optionally, the third control unit 350 includes an eighteenth transistor T18. The gate of the eighteenth transistor T18 serves as the control terminal of the third control unit 350. The first pole of the eighteenth transistor T18 is connected to the first end of the third control unit 350. The second pole of the eighteenth transistor T18 is connected to the first end of the unidirectional conduction unit 340.

[0126] Figure 16 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 16 , optionally, the second control module further includes a fourth control unit 360. The control terminal of the fourth control unit 360 is connected to the second potential signal VGL. The first end of the fourth control unit 360 is connected to the first node N1. The second end of the fourth control unit 360 is connected to the third node N3. The fourth control unit 360 is configured to conduct or cut off according to the potential difference between the second potential signal VGL and the potential at the first node N1.

[0127] With this arrangement in this embodiment, the transmission of the extremely low potential generated by the third node N3 due to the coupling effect of the second capacitor C2 to the first node N1 can be blocked, avoiding the impact of this extremely low potential on the transistors connected to the first node N1. Specifically, when the first node N1 is at a low potential, since the second potential signal VGL is also at a low potential, the potential difference between the control terminal and the first terminal of the fourth control unit 360 is basically 0, causing the fourth control unit 360 to be in a critical off state. Then, when the second capacitor C2 in the output module 40 pulls the third node N3 down to an extremely low potential, due to the critical off state of the fourth control unit 360, this extremely low potential cannot be transmitted to the first node N1 and will not impact the transistors in the first control module 20, etc. When the first node N1 is at a high potential, the potential difference between the control terminal and the first terminal of the fourth control unit 360 is greater than 0, causing the fourth control unit 360 to conduct, and effectively transmitting the high potential of the first node N1 to the third node N3. Therefore, the fourth control unit 360 only cuts off the transmission path of the extremely low voltage to the first node N1 without affecting the normal transmission of the high potential.

[0128] Optionally, the fourth control unit 360 includes a nineteenth transistor T19. The gate of the nineteenth transistor T19 serves as the control terminal of the fourth control unit 360, the first pole of the nineteenth transistor T19 serves as the first terminal of the fourth control unit 360, and the second pole of the nineteenth transistor T19 serves as the second terminal of the fourth control unit 360. Optionally, the nineteenth transistor T19 is a P-type transistor.

[0129] Figure 17 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 17 , optionally, the second control module 30 further includes a reset unit 370. The control terminal of the reset unit 370 is connected to a reset signal RST, the first terminal of the reset unit 370 is connected to a first potential signal VGH, and the second terminal of the reset unit 370 is connected to the first node N1 and the first terminal of the fourth control unit 360. The reset unit 370 is configured to transmit the first potential signal VGH to the first node N1 according to the reset signal RST.

[0130] Continue to refer to Figure 17 , optionally, the reset unit 370 includes a twentieth transistor T20. The gate of the twentieth transistor T20 serves as the control terminal of the reset unit 370, the first pole of the twentieth transistor T20 serves as the first terminal of the reset unit 370, and the second pole of the twentieth transistor T20 serves as the second terminal of the reset unit 370. Optionally, the twentieth transistor T20 is a P-type transistor.

[0131] When the display panel is working, the shift register may deviate from the normal working state due to factors such as noise and signal interference. Under the action of the reset signal, the reset unit 370 restores the potential of the first node N1 to the first potential signal VGH, which is equivalent to restoring some key states of the shift register to the initial set values. In this way, the shift register can start working again from a stable initial state, avoid driving errors in the pixel circuit caused by accumulated abnormal states, effectively prevent the occurrence of the flash screen phenomenon, and ensure the stable and normal display of images on the display panel.

[0132] Figure 18 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 18 Optionally, the first control module 20 includes a fourth inverter 201.

[0133] The fourth inverter 201 is connected between the first node N1 and the second node N2, and is configured to respond to the potential of the first node N1 and transmit the first potential signal VGH or the second potential signal VGL to the second node N2.

[0134] Optionally, the fourth inverter 201 includes a twenty-third transistor T23 and a twenty-fourth transistor T24. The gate of the twenty-third transistor T23 is connected to the first node N1. The first pole of the twenty-third transistor T23 is connected to the first potential signal VGH, and the second pole of the twenty-third transistor T23 is connected to the second node N2. The gate of the twenty-fourth transistor T14 is connected to the first node N1. The first pole of the twenty-fourth transistor T24 is connected to the second potential signal VGL, and the second pole of the twenty-fourth transistor T24 is connected to the second node N2. Optionally, the twenty-third transistor T23 is a P-type transistor, and the twenty-fourth transistor T24 is an N-type transistor.

[0135] Figure 19 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 19 Optionally, the first control module 20 further includes a fifth inverter 202 and a fourth potential control unit 203.

[0136] The fifth inverter 202 is connected between the second node N2 and the eighth node N8, and is configured to invert the potential of the second node N2 and transmit it to the eighth node N8.

[0137] The control terminal of the fourth potential control unit 203 is connected to the second clock signal CLK2. The first terminal of the fourth potential control unit 203 is connected to the first node N1, and the second terminal of the fourth potential control unit 203 is connected to the eighth node N8. The fourth potential control unit 203 is configured to respond to the second clock signal CLK2 and transmit the potential of the eighth node N8 to the first node N1.

[0138] Optionally, the fifth inverter 202 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. The gate of the twenty-fifth transistor T25 is connected to the second node N2. The first pole of the twenty-fifth transistor T25 receives the first potential signal VGH. The second pole of the twenty-fifth transistor T25 is connected to the eighth node N8.

[0139] The gate of the twenty-sixth transistor T26 is connected to the second node N2. The first pole of the twenty-sixth transistor T26 receives the second potential signal VGL. The second pole of the twenty-sixth transistor T26 is connected to the eighth node N8. Optionally, the twenty-fifth transistor is a P-type transistor, and the twenty-sixth transistor is an N-type transistor.

[0140] Optionally, the fourth potential control unit 203 includes a twenty-seventh transistor T27. The gate of the twenty-seventh transistor T27 serves as the control end of the fourth potential control unit 203. The first pole of the twenty-seventh transistor T27 serves as the first end of the fourth potential control unit 203. The second pole of the twenty-seventh transistor T27 serves as the second end of the fourth potential control unit 203. Optionally, the twenty-seventh transistor T27 is an N-type transistor.

[0141] Figure 20 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 20 and, optionally, the shift register includes: an input module 10, a first control module 20, a second control module 30, and a first output module 40.

[0142] Optionally, the input module 10 includes a first potential control unit 101, a second inverter 102, and a second potential control unit 103. Optionally, the first potential control unit 101 includes a seventh transistor T7. Optionally, the second inverter 102 includes an eighth transistor T8 and a ninth transistor T9. Optionally, the second potential control unit 103 includes a tenth transistor T10.

[0143] Optionally, the first output module 40 includes: a first output unit 401 and a second output unit 402. Optionally, the first output unit 401 includes: a twenty-first transistor T21, and the second output unit 402 includes: a twenty-second transistor T22 and a second capacitor C2.

[0144] Optionally, the first control module 20 includes a fourth inverter 201. The fourth inverter 201 includes a twenty-third transistor T23 and a twenty-fourth transistor T24. Optionally, the first control module 20 further includes a fifth inverter 202 and a fourth potential control unit 203. Optionally, the fifth inverter 202 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. Optionally, the fourth potential control unit 203 includes a twenty-seventh transistor T27.

[0145] Optionally, the second control module 30 is respectively connected to the first node N1 and the third node N3, and is configured to respond to the potential of the first node N1 and transmit the first potential signal VGH or the third potential signal VGL2 to the third node N3. The second control module 30 includes a first inverter 301 and a first control unit 302. Optionally, the first inverter 301 includes a first transistor T1 and a second transistor T2. Optionally, the first control unit 302 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0146] Figure 21 is another driving timing diagram of the shift register provided by the embodiments of the present invention and can be used to drive Figure 20 the shift register shown in Figure 20 and Figure 21 . The driving timing of the shift register includes five stages, namely a first stage P1, a second stage P2, a third stage P3, a fourth stage P4, and a fifth stage P5. Taking the signal input by the first potential signal VGH as a high-level signal and the second potential signal VGL as a low-level signal as an example.

[0147] In the first stage P1, the input signal SIN and the first clock signal CLK1 are at low levels, and the second clock signal CLK2 is at a high level. The seventh transistor T7 is turned on in response to the low level of the first clock signal CLK1, and transmits the low level of the input signal SIN to the fifth node N5. The eighth transistor T8 is turned on in response to the low level of the fifth node N5, and transmits the first potential signal VGH to the sixth node N6. The tenth transistor T10 is turned off, and the potential of the first node N1 remains at a low level. The twenty-third transistor T23 is turned on in response to the low level of the first node N1, and transmits the first potential signal VGH to the second node N2, thereby controlling the potential of the second node N2 to be at a high level. The twenty-sixth transistor T26 is turned on in response to the high level of the second node N2, and transmits the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 is turned on, and transmits the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from being floating. The first transistor T1 and the third transistor T3 are turned on in response to the low level of the first node N1. The first transistor T1 transmits the first potential signal VGH to the fourth node N4. The fifth transistor T5 is turned off. The third transistor T3 transmits the first potential signal VGH to the gate of the sixth transistor T6. The sixth transistor T6 is turned on, and transmits the third potential signal VGL2 to the third node N3. The fourth transistor T4 is turned off. The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the first stage P1, the first scan signal S1 output by the first output module 40 is a low level signal.

[0148] In the second stage P2, the input signal SIN and the first clock signal CLK1 transition to a high level, and the second clock signal CLK2 transitions to a low level. The seventh transistor T7 is turned off, and the fifth node N5 maintains the low level of the first stage P1. The eighth transistor T8 is turned on in response to the low level of the fifth node N5, and transmits the first potential signal VGH to the sixth node N6. The tenth transistor T10 is turned on in response to the low level of the second clock signal CLK2, and transmits the high level of the sixth node N6 to the first node N1. The twenty-fourth transistor T24 is turned on in response to the high level of the first node N1, and transmits the second potential signal VGL to the second node N2, thereby controlling the potential of the second node N2 to be low. The twenty-fifth transistor T25 is turned on in response to the low level of the second node N2, and transmits the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is at a low level at this time, the twenty-seventh transistor T27 is turned off. The second transistor T2 is turned on in response to the high level of the first node N1, and transmits the second potential signal VGL to the fourth node N4. The fifth transistor T5 is turned on and transmits the first potential signal VGH to the gate of the fourth transistor T4 and the third node N3. The fourth transistor T4 is turned on, and the twenty-second transistor T22 is turned off, and transmits the third potential signal VGL2 to the first pole of the third transistor T3. The twenty-first transistor T21 is turned on in response to the low potential of the second node N2, and outputs the first potential signal VGH as the first scan signal S1. That is, in the second stage P2, the first scan signal S1 output by the first output module 40 is a high-level signal.

[0149] In the third stage P3, the input signal SIN remains at a high level, the first clock signal CLK1 transitions to a low level, and the second clock signal CLK2 transitions to a high level. The tenth transistor T10 is turned off, and the first node N1 maintains the high level of the second stage P2. The twenty-fourth transistor T24 conducts in response to the high level of the first node N1, transmitting the second potential signal VGL to the second node N2, thereby controlling the potential of the second node N2 to be at a low level. The twenty-fifth transistor T25 conducts in response to the low level of the second node N2, transmitting the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 conducts, transmitting the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from being in a floating state. The second transistor T2 conducts in response to the high level of the first node N1, transmitting the second potential signal VGL to the fourth node N4. The fifth transistor T5 conducts, transmitting the first potential signal VGH to the gate of the fourth transistor T4 and the third node N3. The fourth transistor T4 conducts, and the twenty-second transistor T22 is turned off, transmitting the third potential signal VGL2 to the first pole of the third transistor T3. The twenty-first transistor T21 conducts in response to the low potential of the second node N2, outputting the first potential signal VGH as the first scan signal S1. That is, in the third stage P3, the first scan signal S1 output by the first output module 40 is a high-level signal.

[0150] In the fourth stage P4, the input signal SIN remains high, the first clock signal CLK1 transitions to high, and the second clock signal CLK2 transitions to low. The seventh transistor T7 turns off, and the fifth node N5 maintains the high level of the third stage P3. The ninth transistor T9 turns on in response to the high level of the fifth node N5, transmitting the second potential signal VGL to the sixth node N6. The tenth transistor T10 turns on in response to the low level of the second clock signal CLK2, transmitting the low potential of the sixth node N6 to the first node N1. The twenty-third transistor T23 turns on in response to the low level of the first node N1, transmitting the first potential signal VGH to the second node N2, thereby controlling the potential of the second node N2 to be high. The twenty-sixth transistor T26 turns on in response to the high level of the second node N2, transmitting the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is high at this time, the twenty-seventh transistor T27 turns on, transmitting the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from floating. The first transistor T1 and the third transistor T3 turn on in response to the low level of the first node N1. The first transistor T1 transmits the first potential signal VGH to the fourth node N4. The fifth transistor T5 turns off. The third transistor T3 transmits the first potential signal VGH to the gate of the sixth transistor T6. The sixth transistor T6 turns on, transmitting the third potential signal VGL2 to the third node N3. The fourth transistor T4 turns off. The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the fourth stage P4, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0151] In the fifth stage P5, the input signal SIN remains at a high level, the first clock signal CLK1 transitions to a low level, and the second clock signal CLK2 transitions to a high level. The seventh transistor T7 conducts in response to the low level of the first clock signal CLK1, transmitting the high level of the input signal SIN to the fifth node N5. The ninth transistor T9 conducts in response to the high level of the fifth node N5, transmitting the second potential signal VGL to the sixth node N6. The tenth transistor T10 is turned off, and the first node N1 maintains the low level of the fourth stage P4. The twenty-third transistor T23 conducts in response to the low level of the first node N1, transmitting the first potential signal VGH to the second node N2, thereby controlling the potential of the second node N2 to be high. The twenty-sixth transistor T26 conducts in response to the high level of the second node N2, transmitting the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 conducts, transmitting the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from floating. The first transistor T1 and the third transistor T3 conduct in response to the low level of the first node N1. The first transistor T1 transmits the first potential signal VGH to the fourth node N4. The fifth transistor T5 is turned off. The third transistor T3 transmits the first potential signal VGH to the gate of the sixth transistor T6. The sixth transistor T6 conducts, transmitting the third potential signal VGL2 to the third node N3. The fourth transistor T4 is turned off. The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the fifth stage P5, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0152] Figure 22 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 22 , optionally, the shift register includes: an input module 10, a first control module 20, a second control module 30, and a first output module 40.

[0153] Optionally, the input module 10 includes a first potential control unit 101, a second inverter 102, and a second potential control unit 103. Optionally, the first potential control unit 101 includes a seventh transistor T7. Optionally, the second inverter 102 includes an eighth transistor T8 and a ninth transistor T9. Optionally, the second potential control unit 103 includes a tenth transistor T10.

[0154] Optionally, the first output module 40 includes: a first output unit 401 and a second output unit 402. Optionally, the first output unit 401 includes: a twenty-first transistor T21, and the second output unit 402 includes: a twenty-second transistor T22 and a second capacitor C2.

[0155] Optionally, the first control module 20 includes a fourth inverter 201. The fourth inverter 201 includes a twenty-third transistor T23 and a twenty-fourth transistor T24. Optionally, the first control module 20 further includes a fifth inverter 202 and a fourth potential control unit 203. Optionally, the fifth inverter 202 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. Optionally, the fourth potential control unit 203 includes a twenty-seventh transistor T27.

[0156] Optionally, the second control module 30 is respectively connected to the fifth node N5 and the third node N3. Optionally, the second control module 30 includes a charge and discharge control unit 310, a coupling unit 320, and a unidirectional conduction unit 330. Optionally, the charge and discharge control unit 310 includes a fourteenth transistor T14 and a fifteenth transistor T15. Optionally, the coupling unit 320 includes a first capacitor C1. Optionally, the unidirectional conduction unit 330 includes a sixteenth transistor T16.

[0157] Optionally, the second control module 30 further includes a second control unit 340. Optionally, the second control module further includes a third control unit 350. Optionally, the third control unit 350 includes an eighteenth transistor T18. Optionally, the second control module further includes a fourth control unit 360, and the fourth control unit 360 includes a nineteenth transistor T19. Optionally, the second control module 30 further includes a reset unit 370, and the reset unit 370 includes a twentieth transistor T20.

[0158] Reference Figure 20 and Figure 22 , the driving timing of the shift register includes five stages, namely a first stage P1, a second stage P2, a third stage P3, a fourth stage P4, and a fifth stage P5. Taking the signal input by the first potential signal VGH as a high-level signal and the second potential signal VGL as a low-level signal as an example.

[0159] In the first stage P1, the input signal SIN and the first clock signal CLK1 are at low level, and the second clock signal CLK2 is at high level. The seventh transistor T7 is turned on in response to the low level of the first clock signal CLK1, and transmits the low level of the input signal SIN to the fifth node N5. The eighth transistor T8 is turned on in response to the low level of the fifth node N5, and transmits the first potential signal VGH to the sixth node N6. The tenth transistor T10 is turned off, and the potential of the first node N1 remains at low level. The twenty-third transistor T23 is turned on in response to the low level of the first node N1, and transmits the first potential signal VGH to the second node N2, thereby controlling the potential of the second node N2 to be at high level. The twenty-sixth transistor T26 is turned on in response to the high level of the second node N2, and transmits the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at high level at this time, the twenty-seventh transistor T27 is turned on, and transmits the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from floating. The fourteenth transistor T14 is turned on in response to the low level of the fifth node N5, and the fourteenth transistor T14 transmits the first potential signal VGH to the first end of the first capacitor C1. Due to the coupling effect of the first capacitor C1 itself, the potential of the second end of the first capacitor C1 is pulled up, and the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. Since the first clock signal CLK1 is at low level, the seventeenth transistor T17 is turned off, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the nineteenth transistor T19 transmits the low level to the gate of the twenty-second transistor T22 (i.e., the third node N3). The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the first stage P1, the first scan signal S1 output by the first output module 40 is a low level signal.

[0160] In the second stage P2, the input signal SIN and the first clock signal CLK1 transition to high level, and the second clock signal CLK2 transitions to low level. The seventh transistor T7 is turned off, the fifth node N5 maintains the low level of the first stage P1, the eighth transistor T8 is turned on in response to the low level of the fifth node N5, and transmits the first potential signal VGH to the sixth node N6. The tenth transistor T10 is turned on in response to the low level of the second clock signal CLK2, and transmits the high level of the sixth node N6 to the first node N1. The twenty-fourth transistor T24 is turned on in response to the high level of the first node N1, and transmits the second potential signal VGL to the second node N2, thereby controlling the potential of the second node N2 to be low. The twenty-fifth transistor T25 is turned on in response to the low level of the second node N2, and transmits the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is low at this time, the twenty-seventh transistor T27 is turned off. The fourteenth transistor T14 is turned on in response to the low level of the fifth node N5, and transmits the first potential signal VGH to the first end of the first capacitor C1. Due to the coupling effect of the first capacitor C1 itself, the potential of the second end of the first capacitor C1 is pulled up, and the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. Since the first clock signal CLK1 is high, the seventeenth transistor T17 is turned on, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on. The seventeenth transistor T17 and the eighteenth transistor T18 transmit the high level of the first node N1 to the gate of the sixteenth transistor T16. The nineteenth transistor T19 transmits the high level of the first node N1 to the gate of the twenty-second transistor T22 (i.e., the third node N3). The twenty-first transistor T21 outputs the first potential signal VGH as the first scan signal S1 in response to the potential of the second node N2. That is, in the second stage P2, the first scan signal S1 output by the first output module 40 is a high level signal.

[0161] In the third stage P3, the input signal SIN remains at a high level, the first clock signal CLK1 transitions from a high level to a low level, and the second clock signal CLK2 transitions to a high level. The seventh transistor T7 turns on in response to the low level of the first clock signal CLK1 and transmits the high level of the input signal SIN to the fifth node N5. The tenth transistor T10 turns off, and the first node N1 maintains the high level of the second stage P2. The twenty-fourth transistor T24 turns on in response to the high level of the first node N1 and transmits the second potential signal VGL to the second node N2, thereby controlling the potential of the second node N2 to be at a low level. The twenty-fifth transistor T25 turns on in response to the low level of the second node N2 and transmits the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 turns on and transmits the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from being floating. Since the potential of the fifth node N5 is at a high level, the fourteenth transistor T14 turns off. The seventeenth transistor T17 turns off, the gate of the sixteenth transistor T16 maintains the high level of the second stage P2, and the sixteenth transistor T16 turns off. The nineteenth transistor T19 transmits the high level of the first node N1 to the twenty-second transistor T22, and the twenty-second transistor T22 turns off. The twenty-first transistor T21 turns on in response to the low potential of the second node N2 and outputs the first potential signal VGH as the first scan signal S1. That is, in the third stage P3, the first scan signal S1 output by the first output module 40 is a high-level signal.

[0162] In the fourth stage P4, the input signal SIN remains at a high level, the first clock signal CLK1 transitions from a low level to a high level, and the second clock signal CLK2 transitions to a low level. The seventh transistor T7 is turned off, and the fifth node N5 remains at the high level of the third stage P3. The ninth transistor T9 is turned on in response to the high level of the fifth node N5, transmitting the second potential signal VGL to the sixth node N6. The tenth transistor T10 is turned on in response to the low level of the second clock signal CLK2, transmitting the low potential of the sixth node N6 to the first node N1. The twenty-third transistor T23 is turned on in response to the low level of the first node N1, transmitting the first potential signal VGH to the second node N2, thereby controlling the potential of the second node N2 to be high, causing the twenty-first transistor T21 to turn off. The twenty-sixth transistor T26 is turned on in response to the high level of the second node N2, transmitting the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 is turned on, transmitting the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from floating. Since the potential of the fifth node N5 is high, the fourteenth transistor T14 is turned off. Since the first clock signal CLK1 transitions from a low level to a high level, the first capacitor C1 is charged, and the potential of the first end of the first capacitor C1 increases. Due to the coupling effect of the first capacitor C1 itself, the potential of the second end of the first capacitor C1 increases, and the sixteenth transistor T16 is turned off. The third node N3 remains at a low potential, making the potential of the third node N3 lower than the second potential signal VGL. The twenty-second transistor T22 is turned on, transmitting the second potential signal VGL with an equal amplitude to the output terminal OUT of the shift register. That is, in the fourth stage P4, the first scan signal S1 output by the first output module 40 is a low level signal.

[0163] In the fifth stage P5, the input signal SIN remains at a high level, the first clock signal CLK1 transitions to a low level, and the second clock signal CLK2 transitions to a high level. The seventh transistor T7 conducts in response to the low level of the first clock signal CLK1, transmitting the high level of the input signal SIN to the fifth node N5. The ninth transistor T9 conducts in response to the high level of the fifth node N5, transmitting the second potential signal VGL to the sixth node N6. The tenth transistor T10 is turned off, and the first node N1 maintains the low level of the fourth stage P4. The twenty-third transistor T23 conducts in response to the low level of the first node N1, transmitting the first potential signal VGH to the second node N2, thereby controlling the potential of the second node N2 to be high. The twenty-sixth transistor T26 conducts in response to the high level of the second node N2, transmitting the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 conducts, transmitting the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the second node N2 from floating. Since the first clock signal CLK1 transitions from a high level to a low level, the first capacitor C1 discharges, and the potential of the first end of the first capacitor C1 decreases. Due to the coupling effect of the first capacitor C1 itself, the potential of the second end of the first capacitor C1 is pulled down, the sixteenth transistor T16 conducts, and the potential of the third node N3 is pulled down, making the potential of the third node N3 lower than the second potential signal VGL. The twenty-second transistor T22 conducts, transmitting the second potential signal VGL to the output terminal OUT of the shift register with equal amplitude. That is, in the fifth stage P5, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0164] Figure 23 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 23 , optionally, the shift register includes: an input module 10, a first control module 20, a second control module 30, and a first output module 40.

[0165] Optionally, the input module 10 includes a first potential control unit 101, a second inverter 102, and a second potential control unit 103. Optionally, the first potential control unit 101 includes a seventh transistor T7. Optionally, the second inverter 102 includes an eighth transistor T8 and a ninth transistor T9. Optionally, the second potential control unit 103 includes a tenth transistor T10.

[0166] Optionally, the first output module 40 includes: a first output unit 401 and a second output unit 402. Optionally, the first output unit 401 includes: a twenty-first transistor T21, and the second output unit 402 includes: a twenty-second transistor T22 and a second capacitor C2.

[0167] Optionally, the first control module 20 includes a fourth inverter 201. The fourth inverter 201 includes a twenty-third transistor T23 and a twenty-fourth transistor T24. Optionally, the first control module 20 further includes a fifth inverter 202 and a fourth potential control unit 203. Optionally, the fifth inverter 202 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. Optionally, the fourth potential control unit 203 includes a twenty-seventh transistor T27.

[0168] Optionally, the first control module 20 further includes a fifth inverter 202 and a fourth potential control unit 203. Optionally, the fifth inverter 202 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. Optionally, the fourth potential control unit 203 includes a twenty-seventh transistor T27.

[0169] Optionally, the second control module 40 includes a twenty-eighth transistor T28, a twenty-ninth transistor T29, a thirtieth transistor T30, and a thirty-first transistor T31.

[0170] The gate of the twenty-eighth transistor T28 is connected to the gate of the twenty-fifth transistor T25. The first pole of the twenty-eighth transistor T28 receives the first potential signal VGH. The second pole of the twenty-eighth transistor T28 is connected to the gate of the thirty-first transistor T31 and the first pole of the twenty-ninth transistor T29.

[0171] The gate of the thirtieth transistor T30 is connected to the eighth node N8 and the second node N2. The first pole of the thirtieth transistor T30 receives the first potential signal VGH. The second pole of the thirtieth transistor T30 is connected to the gate of the twenty-ninth transistor T29 and the first pole of the thirty-first transistor T31.

[0172] The second poles of both the twenty-ninth transistor T29 and the thirty-first transistor T31 receive the third potential signal VGL2.

[0173] Figure 24 is another driving timing diagram of the shift register provided by the embodiments of the present invention and can be used to drive Figure 23 the shift register shown in Figure 23 and Figure 24 . The driving timing of the shift register includes five stages, namely a first stage P1, a second stage P2, a third stage P3, a fourth stage P4, and a fifth stage P5. Taking the signal input by the first potential signal VGH as a high-level signal and the second potential signal VGL as a low-level signal as an example.

[0174] In the first stage P1, the first clock signal CLK1 is at a low level, the input signal SIN and the second clock signal CLK2 are at high levels. The seventh transistor T7 conducts in response to the low level of the first clock signal CLK1, transmits the high level of the input signal SIN to the fifth node N5. The ninth transistor T9 conducts in response to the high level of the fifth node N5, transmits the second potential signal VGL to the sixth node N6. The eleventh transistor T11 conducts in response to the low potential of the sixth node N6, transmits the first potential signal VGH to the seventh node N7. Since the first clock signal CLK1 is at a low level, the thirteenth transistor T13 conducts, transmits the high potential of the seventh node N7 to the fifth node N5, thus forming a self-loop to prevent the sixth node N6 from being in a floating state. Since the second clock signal CLK2 is at a high level, the tenth transistor T10 is turned off, and the potential of the first node N1 remains at a high level. The twenty-fourth transistor T24 conducts in response to the high level of the first node N1, transmits the second potential signal VGL to the gate Ng of the twenty-eighth transistor T28, thereby controlling the potential of the gate Ng of the twenty-eighth transistor T28 to be at a low level. The twenty-fifth transistor T25 conducts in response to the low level of the gate Ng of the twenty-eighth transistor T28, transmits the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 conducts, transmits the first potential signal VGH to the first node N1, thus forming a self-loop to prevent the gate Ng of the twenty-eighth transistor T28 from being in a floating state. Since the eighth node N8 is at a high potential, the thirtieth transistor T30 is turned off, and the twenty-ninth transistor T29 is turned off. The twenty-eighth transistor T28 conducts, the twenty-eighth transistor T28 transmits the first potential signal VGH to the gate of the thirty-first transistor T31, the thirty-first transistor T31 conducts, transmits the third potential signal VGL2 to the third node N3. The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the first stage P1, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0175] In the second stage P2, the first clock signal CLK1 transitions to a high level, and the input signal SIN and the second clock signal CLK2 transition to a low level. The seventh transistor T7 is turned off, and the fifth node N5 maintains the high level of the first stage P1. The ninth transistor T9 turns on in response to the high level of the fifth node N5, transmitting the second potential signal VGL to the sixth node N6. The eleventh transistor T11 turns on in response to the low potential of the sixth node N6, transmitting the first potential signal VGH to the seventh node N7. Since the first clock signal CLK1 is at a high level, the thirteenth transistor T13 turns on, transmitting the high potential of the seventh node N7 to the fifth node N5, thus forming a self-loop to prevent the sixth node N6 from being in a floating state. The tenth transistor T10 turns on in response to the low level of the second clock signal CLK2, transmitting the low level of the sixth node N6 to the first node N1. The twenty-third transistor T23 turns on in response to the low level of the first node N1, transmitting the first potential signal VGH to the gate Ng of the twenty-eighth transistor T28, thereby controlling the potential of the gate Ng of the twenty-eighth transistor T28 to be at a high level. The twenty-sixth transistor T26 turns on in response to the high level of the gate Ng of the twenty-eighth transistor T28, transmitting the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at a low level at this time, the twenty-seventh transistor T27 is turned off. The twenty-eighth transistor T28 is turned off, and the thirtieth transistor T30 turns on in response to the low potential of the eighth node N8, transmitting the first potential signal VGH to the gate of the twenty-ninth transistor T9. The twenty-ninth transistor T29 turns on, transmitting the third potential signal VGL2 to the second pole of the twenty-eighth transistor T28. In addition, the twenty-first transistor T21 turns on in response to the low potential of the second node N2, outputting the first potential signal VGH as the first scan signal S1. That is, in the second stage P2, the first scan signal S1 output by the first output module 40 is a high-level signal.

[0176] In the third stage P3, the input signal SIN remains at a low level, the first clock signal CLK1 transitions to a low level, and the second clock signal CLK2 transitions to a high level. The tenth transistor T10 is turned off, and the first node N1 maintains the low level of the second stage P2. The twenty-third transistor T23 is turned on in response to the low level of the first node N1, and transmits the first potential signal VGH to the gate Ng of the twenty-eighth transistor T28, thereby controlling the potential of the gate Ng of the twenty-eighth transistor T28 to be at a high level. The twenty-sixth transistor T26 is turned on in response to the high level of the gate Ng of the twenty-eighth transistor T28, and transmits the second potential signal VGL to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 is turned on, and transmits the second potential signal VGL to the first node N1, thus forming a self-loop to prevent the potential of the gate Ng of the twenty-eighth transistor T28 from floating. Since the eighth node N8 is at a low potential, the thirtieth transistor T30 is turned on, and transmits the first potential signal VGH to the gate of the twenty-ninth transistor T29, and the twenty-ninth transistor T29 is turned on, and transmits the third potential signal VGL2 to the second pole of the twenty-eighth transistor T28. In addition, the twenty-first transistor T21 is turned on in response to the low potential of the second node N2, and outputs the first potential signal VGH as the first scan signal S1. That is, in the third stage P3, the first scan signal S1 output by the first output module 40 is a high-level signal.

[0177] In the fourth stage P4, the input signal SIN remains at a low level, the first clock signal CLK1 transitions to a high level, and the second clock signal CLK2 transitions to a low level. The seventh transistor T7 is turned off, the fifth node N5 remains at the low level of the third stage P3, the eighth transistor T8 turns on in response to the low level of the fifth node N5, and transmits the first potential signal VGH to the sixth node N6. The tenth transistor T10 turns on in response to the low level of the second clock signal CLK2, and transmits the high potential of the sixth node N6 to the first node N1. The twenty-fourth transistor T24 turns on in response to the high level of the first node N1, and transmits the second potential signal VGL to the gate Ng of the twenty-eighth transistor T28, thereby controlling the potential of the gate Ng of the twenty-eighth transistor T28 to be at a low level. The twenty-fifth transistor T25 turns on in response to the low level of the gate Ng of the twenty-eighth transistor T28, and transmits the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is at a low level at this time, the twenty-seventh transistor T27 is turned off. Since the eighth node N8 is at a high potential, the thirtieth transistor T30 is turned off, and the twenty-ninth transistor T29 is turned off. The twenty-eighth transistor T28 is turned on, and the twenty-eighth transistor T28 transmits the first potential signal VGH to the gate of the thirty-first transistor T31. The thirty-first transistor T31 is turned on and transmits the third potential signal VGL2 to the third node N3. The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the fourth stage P4, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0178] In the fifth stage P5, the input signal SIN remains at a low level, the first clock signal CLK1 transitions to a low level, and the second clock signal CLK2 transitions to a high level. The seventh transistor T7 conducts in response to the low level of the first clock signal CLK1, transmitting the low level of the input signal SIN to the fifth node N5. The eighth transistor T8 conducts in response to the low level of the fifth node N5, transmitting the first potential signal VGH to the sixth node N6. The tenth transistor T10 is turned off, and the first node N1 maintains the high level of the fourth stage P4. The twenty-fourth transistor T24 conducts in response to the high level of the first node N1, transmitting the second potential signal VGL to the gate Ng of the twenty-eighth transistor T28, thereby controlling the potential of the gate Ng of the twenty-eighth transistor T28 to be at a low level. The twenty-fifth transistor T25 conducts in response to the low level of the gate Ng of the twenty-eighth transistor T28, transmitting the first potential signal VGH to the eighth node N8. Since the second clock signal CLK2 is at a high level at this time, the twenty-seventh transistor T27 conducts, transmitting the first potential signal VGH to the first node N1, thus forming a self-loop to prevent the potential of the gate Ng of the twenty-eighth transistor T28 from being in a floating state. Since the eighth node N8 is at a high potential, the thirtieth transistor T30 is turned off, and the twenty-ninth transistor T29 is turned off. The twenty-eighth transistor T28 conducts, and the twenty-eighth transistor T28 transmits the first potential signal VGH to the gate of the thirty-first transistor T31. The thirty-first transistor T31 conducts, transmitting the third potential signal VGL2 to the third node N3. The twenty-second transistor T22 outputs the second potential signal VGL as the first scan signal S1 in response to the potential of the third node N3. That is, in the fifth stage P5, the first scan signal S1 output by the first output module 40 is a low-level signal.

[0179] Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit. Figure 25 FIG. is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention. Referring to Figure 25 , the gate driving circuit includes a plurality of shift registers 11, wherein the shift register 11 is the shift register 11 of any of the above embodiments of the present invention. The output end of the previous-stage shift register 11 is connected to the input end of the input module 10 of the next-stage shift register 11 (the input signal SIN can be connected).

[0180] The gate driving circuit of this embodiment includes the shift register of any of the above embodiments of the present invention and has the beneficial effects of the shift register of any of the above embodiments of the present invention, which will not be elaborated here.

[0181] The gate driving circuit can be connected to a first clock line and a second clock line. The first clock line can be used to provide a first clock signal to the odd-stage shift register, and the second clock line can be used to provide a second clock signal to the odd-stage shift register. The first clock line can be used to provide a second clock signal to the even-stage shift register, and the second clock line can be used to provide a first clock signal to the even-stage shift register.

[0182] Figure 26 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. Refer to Figure 26 , including the Figure 23 shift register as the starting shift register 11; it also includes a multi-stage output shift register 13; in the starting shift register 11, the first control module 20 is used to output a shift signal CIN.

[0183] The output shift register 13 includes: a driving control module 131, a stage transmission output module 132, a transmission control module 133, and a second output module 134.

[0184] The output end of the driving control module 131 is connected to the ninth node N9, and is used to transmit the shift signal CIN to the ninth node N9 in response to the first clock signal CLK1;

[0185] The stage transmission output module 132 is connected to the ninth node N9, and is used to output a first potential signal VGH or a second potential signal VGL to the first output end of the stage transmission output module 132 according to the potential of the ninth node N9, and is used to output a first potential signal VGH or a second potential signal VGL to the second output end of the stage transmission output module 132 according to the potential of the first output end of the stage transmission output module 132.

[0186] The transmission control module 133 is connected to the first output end and the second output end, and is used to control the potential of the first control end Ctr1 of the second output module 134 according to the potentials of the first output end and the second output end.

[0187] The first control end Ctr1 of the second output module 134 is connected to the transmission control module 133, the second control end Ctr2 of the second output module 134 is connected to the first output end of the stage transmission output module 132, and the second output module 134 is used to output the first potential signal VGH as the second scan signal S2 in response to the potential of the second control end Ctr2, or output the second potential signal VGL as the second scan signal S2 in response to the potential of the first control end Ctr1.

[0188] Among them, the input end of the first-stage output shift register 13 is connected to the first control module 20 of the starting shift register 11, and the input end of the (i + 1)-th stage output shift register 13 is connected to the first output end of the stage transmission output module 132 of the i-th stage output shift register 13, where i is an integer greater than or equal to 1.

[0189] Figure 27 is a schematic structural diagram of an output shift register provided by an embodiment of the present invention. Refer to Figure 27 Optionally, the stage transmission output module 132 includes a sixth potential control unit 1321, a sixth inverter 1322, and a seventh inverter 1323.

[0190] The control end of the sixth potential control unit 1321 is connected to the first clock signal CLK1. The first end of the sixth potential control unit 1321 is connected to the ninth node N9. The second end of the sixth potential control unit 1321 serves as the second output end of the stage transmission output module 132. The sixth potential control unit 1321 is configured to respond to the first clock signal CLK1 and transmit the potential of the ninth node N9 to the second output end of the stage transmission output module 132.

[0191] The sixth inverter 1322 is connected between the ninth node N9 and the tenth node N10, and is configured to respond to the potential of the ninth node N9 and transmit the first potential signal VGH or the second potential signal VGL to the tenth node N10. The tenth node N10 serves as the first output end of the stage transmission output module 132.

[0192] The seventh inverter 1323 is connected between the tenth node N10 and the eleventh node N11, and is configured to respond to the potential of the tenth node N10 and transmit the first potential signal VGH or the second potential signal VGL to the eleventh node N11; the eleventh node N11 serves as the second output end of the stage transmission output module 1323.

[0193] Optionally, the sixth potential control unit 1321 includes a thirty-second transistor T32. The gate of the thirty-second transistor T32 serves as the control end of the sixth potential control unit 1321. The first pole of the thirty-second transistor T32 serves as the first end of the sixth potential control unit 1321. The second pole of the thirty-second transistor T32 serves as the second end of the sixth potential control unit 1321.

[0194] Specifically, when the first clock signal CLK1 is at an effective level, the thirty-second transistor T32 is turned on, and the potential of the ninth node N9 is transmitted to the second output end. Among them, the effective level is the level that enables the transistor to conduct. When the transistor is a P-type transistor, the effective level is a low level, and when the transistor is an N-type transistor, the effective level is a high level.

[0195] Optionally, the sixth inverter 1322 includes a thirty-third transistor T33 and a thirty-fourth transistor T34. The gate of the thirty-third transistor T33 is connected to the ninth node N9. The first pole of the thirty-third transistor T33 is connected to the first potential signal VGH. The second pole of the thirty-third transistor T33 is connected to the tenth node N10. The gate of the thirty-fourth transistor T34 is connected to the ninth node N9. The first pole of the thirty-fourth transistor T34 is connected to the second potential signal VGL. The second pole of the thirty-fourth transistor T34 is connected to the tenth node N10.

[0196] Optionally, the thirty-third transistor T33 is a P-type transistor, and the thirty-fourth transistor T34 is an N-type transistor. When the ninth node N9 is at a high potential, the thirty-fourth transistor T34 is turned on, and the second potential signal VGL is transmitted to the tenth node N10. When the ninth node N9 is at a low potential, the thirty-third transistor T33 is turned on, and the first potential signal VGH is transmitted to the tenth node N10.

[0197] Optionally, the seventh inverter 1323 includes a thirty-fifth transistor T35 and a thirty-sixth transistor T36. The gate of the thirty-fifth transistor T35 is connected to the tenth node N10. The first pole of the thirty-fifth transistor T35 is connected to the first potential signal VGH. The second pole of the thirty-fifth transistor T35 is connected to the tenth node N10. The gate of the thirty-sixth transistor T36 is connected to the eleventh node N11. The first pole of the thirty-sixth transistor T36 is connected to the second potential signal VGL. The second pole of the thirty-sixth transistor T36 is connected to the eleventh node N11.

[0198] Optionally, the thirty-fifth transistor T35 is a P-type transistor, and the thirty-sixth transistor T36 is an N-type transistor. When the tenth node N10 is at a high potential, the thirty-sixth transistor T36 is turned on, and the second potential signal VGL is transmitted to the eleventh node N11. When the tenth node N10 is at a low potential, the thirty-fifth transistor T35 is turned on, and the first potential signal VGH is transmitted to the eleventh node N11.

[0199] Continue to refer to Figure 27 , optionally, the drive control module 131 includes a thirty-seventh transistor T37. The gate of the thirty-seventh transistor T37 is connected to the first clock signal CLK1. The first pole of the thirty-seventh transistor T37 is connected to the shift signal CIN. The second pole of the thirty-seventh transistor T37 is connected to the ninth node N9.

[0200] Continue to refer to Figure 27 , optionally, the transmission control module 133 includes a thirty-eighth transistor T38, a thirty-ninth transistor T39, a fortieth transistor T40, and a forty-first transistor T41.

[0201] The gate of the thirty-eighth transistor T38 is connected to the gate of the twenty-fifth transistor T25. The first pole of the thirty-eighth transistor T38 receives the first potential signal VGH, and the second pole of the thirty-eighth transistor T38 is connected to the gate of the forty-first transistor T41 and the first pole of the thirty-ninth transistor T39.

[0202] The gate of the fortieth transistor T40 is connected to the eighth node N8 and the second node N2. The first pole of the fortieth transistor T40 receives the first potential signal VGH, and the second pole of the fortieth transistor T40 is connected to the gate of the thirty-ninth transistor T39 and the first pole of the forty-first transistor T41;

[0203] The second poles of the thirty-ninth transistor T39 and the forty-first transistor T41 both receive the third potential signal VGL2.

[0204] Optionally, the second output module 314 includes a third output unit and a fourth output unit. The third output unit is connected to the second control terminal Ctr2 and is configured to output the first potential signal VGH as the second scan signal S2 according to the potential of the second control terminal Ctr2. The fourth output unit is connected to the first control terminal Ctr1 and is configured to output the second potential signal VGL as the second scan signal S2 according to the potential of the first control terminal Ctr1.

[0205] Optionally, the third output unit includes: a forty-second transistor T42. The gate of the forty-second transistor T42 is connected to the second control terminal Ctr2. The first pole of the forty-second transistor T42 receives the first potential signal VGH, and the second pole of the forty-second transistor T42 serves as the output terminal of the third output unit;

[0206] The fourth output unit includes: a forty-third transistor T43 and a third capacitor C3. The gate of the forty-third transistor T43 is connected to the first control terminal Ctr1 and the first end of the third capacitor C3. The first stage of the forty-third transistor T43 receives the second potential signal VGL. The second pole of the forty-third transistor T43 is connected to the second end of the third capacitor C3 and serves as the output terminal of the fourth output unit.

[0207] Figure 28 is a driving timing diagram of an output shift register provided by an embodiment of the present invention and can be used to drive Figure 27 the output shift register shown, refer to Figure 27 and Figure 28 , the driving timing of the output shift register includes five stages, namely the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, and the fifth stage P5. Taking the signal input by the first potential signal VGH as a high-level signal and the second potential signal VGL as a low-level signal as an example.

[0208] In the first stage P1, the shift signal CIN and the first clock signal CLK1 are at high level, and the second clock signal CLK2 is at low level. The thirty-seventh transistor T37 is turned off, and the potential of the tenth node N10 remains at high potential. The thirty-sixth transistor T36 is turned on in response to the high potential of the tenth node N10, and transmits the second potential signal VGL to the eleventh node N11. Since the first clock signal CLK1 is at high level, the thirty-second transistor T32 is turned on, and transmits the low potential of the eleventh node N11 to the ninth node N9, thus forming a self-loop to prevent the tenth node N10 from being in a floating state. Since the potential of the tenth node N10 is at high level and the potential of the eleventh node N11 is at low level, the fortieth transistor T40 and the forty-second transistor T42 are turned off, and the thirty-eighth transistor T38 is turned on. The thirty-eighth transistor T38 is turned on, and transmits the first potential signal VGH to the gate of the forty-first transistor T41. The forty-first transistor T41 is turned on, and transmits the third potential signal VGL2 to the first control terminal Ctr1. The forty-third transistor T43 outputs the second potential signal VGL as the second scan signal S2 in response to the potential of the first control terminal Ctr1. That is, in the first stage P1, the second scan signal S2 output by the second output module 134 is a low-level signal.

[0209] In the second stage P2, the shift signal CIN remains at high level, the first clock signal CLK1 jumps to low level, and the second clock signal CLK2 jumps to high level. The thirty-seventh transistor T37 is turned on in response to the low level of the first clock signal CLK1, and transmits the high level of the shift signal CIN to the ninth node N9. The thirty-fourth transistor T34 is turned on in response to the high potential of the ninth node N9, and transmits the second potential signal VGL to the tenth node N10, causing the potential of the tenth node N10 to jump to low level. The thirty-fifth transistor T35 is turned on in response to the low potential of the tenth node N10, and transmits the first potential signal VGH to the eleventh node N11. Since the first clock signal CLK1 is at low level, the thirty-second transistor T32 is turned off. Since the potential of the tenth node N10 is at low level and the potential of the eleventh node N11 is at high level, the thirty-eighth transistor T38 is turned off, and the fortieth transistor T40 and the forty-second transistor T42 are turned on. The fortieth transistor T40 is turned on, and transmits the first potential signal VGH to the gate of the thirty-ninth transistor T39. The thirty-ninth transistor T39 is turned on, and transmits the third potential signal VGL2 to the second pole of the thirty-eighth transistor T38. The forty-second transistor T42 is turned on, and outputs the first potential signal VGH as the second scan signal S2. That is, in the second stage P2, the second scan signal S2 output by the second output module 134 is a high-level signal.

[0210] In the third stage P3, the shift signal CIN remains high, the first clock signal CLK1 transitions to high, and the second clock signal CLK2 transitions to low. The thirty-seventh transistor T37 turns off, and the potential of the tenth node N10 remains at the low potential of the second stage P2. The thirty-fifth transistor T35 turns on in response to the low potential of the tenth node N10, transmitting the first potential signal VGH to the eleventh node N11. Since the first clock signal CLK1 is high, the thirty-second transistor T32 turns on, transmitting the high potential of the eleventh node N11 to the ninth node N9, thus forming a self-loop to prevent the tenth node N10 from being in a floating state. Since the potential of the tenth node N10 is low and the potential of the eleventh node N11 is high, the thirty-eighth transistor T38 turns off, and the fortieth transistor T40 and the forty-second transistor T42 turn on. The fortieth transistor T40 turns on, transmitting the first potential signal VGH to the gate of the thirty-ninth transistor T39. The thirty-ninth transistor T39 turns on, transmitting the third potential signal VGL2 to the second pole of the thirty-eighth transistor T38. The forty-second transistor T42 turns on, outputting the first potential signal VGH as the second scan signal S2. That is, in the third stage P3, the second scan signal S2 output by the second output module 134 is a high-level signal.

[0211] In the fourth stage P4, the shift signal CIN transitions to low, the first clock signal CLK1 transitions to low, and the second clock signal CLK2 transitions to high. The thirty-seventh transistor T37 turns on in response to the low level of the first clock signal CLK1, transmitting the low level of the shift signal CIN to the ninth node N9. The thirty-third transistor T33 turns on in response to the low potential of the ninth node N9, transmitting the first potential signal VGH to the tenth node N10, causing the potential of the tenth node N10 to transition to high. The thirty-sixth transistor T36 turns on in response to the high potential of the tenth node N10, transmitting the second potential signal VGL to the eleventh node N11. Since the first clock signal CLK1 is low, the thirty-second transistor T32 turns off. Since the potential of the tenth node N10 is high and the potential of the eleventh node N11 is low, the fortieth transistor T40 and the forty-second transistor T42 turn off, and the thirty-eighth transistor T38 turns on. The thirty-eighth transistor T38 turns on, transmitting the first potential signal VGH to the gate of the forty-first transistor T41. The forty-first transistor T41 turns on, transmitting the third potential signal VGL2 to the first control terminal Ctr1. The forty-third transistor T43 outputs the second potential signal VGL as the second scan signal S2 in response to the potential of the first control terminal Ctr1. That is, in the fourth stage P4, the second scan signal S2 output by the second output module 134 is a low-level signal.

[0212] In the fifth stage P5, the shift signal CIN remains low, the first clock signal CLK1 transitions to high, and the second clock signal CLK2 transitions to low. The thirty-seventh transistor T37 is turned off, and the potential of the tenth node N10 remains high as in the fourth stage P4. The thirty-sixth transistor T36 turns on in response to the high potential of the tenth node N10, transmitting the second potential signal VGL to the eleventh node N11. Since the first clock signal CLK1 is high, the thirty-second transistor T32 is turned on. Since the potential of the tenth node N10 is high and the potential of the eleventh node N11 is low, the fortieth transistor T40 and the forty-second transistor T42 are turned off, and the thirty-eighth transistor T38 is turned on. The thirty-eighth transistor T38 being turned on transmits the first potential signal VGH to the gate of the forty-first transistor T41, and the forty-first transistor T41 is turned on, transmitting the third potential signal VGL2 to the first control terminal Ctr1. The forty-third transistor T43 outputs the second potential signal VGL as the second scan signal S2 in response to the potential of the first control terminal Ctr1. That is, in the fifth stage P5, the second scan signal S2 output by the second output module 134 is a low-level signal.

[0213] The above specific embodiments do not limit the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A shift register, characterized in that, Comprising: An input module, a first control module, a second control module, and a first output module; The output terminal of the input module is connected to a first node, and is used to control the potential of the first node according to a first clock signal, a second clock signal, and an input signal; The first control module is respectively connected to the first node and a second node, and is used to control the potential of the second node according to the potential of the first node; The second control module is connected to the input module and / or the first control module, and is used to control the potential of a third node to be positively or negatively correlated with the potential of the second node; The first output module is respectively connected to the second node and the third node, and is used to respond to the potential of the second node to output a first potential signal as a first scan signal, or respond to the potential of the third node to output a second potential signal as the first scan signal; Wherein, at least one of the input module, the first control module, and the second control module includes a P-type transistor and an N-type transistor.

2. The shift register according to claim 1, wherein The second control module is respectively connected to the first node and the third node, and is used to respond to the potential of the first node to transmit the first potential signal or a third potential signal to the third node; Preferably, the absolute value of the difference between the third potential signal and the first potential signal is greater than the absolute value of the difference between the second potential signal and the first potential signal; Preferably, the absolute value of the difference between the third potential signal and the second potential signal is less than the absolute value of the difference between the third potential signal and the first potential signal; Preferably, the second control module includes a first inverter and a first control unit; The first inverter is respectively connected to the first node and a fourth node, and is used to invert the potential of the first node and output it to the fourth node; The first control unit is respectively connected to the first node, the third node, and the fourth node, and is used to transmit the first potential signal or the third potential signal to the third node according to the potentials of the first node and the fourth node; Preferably, the first inverter includes a first transistor and a second transistor; The gate of the first transistor is connected to the first node, the first pole of the first transistor accesses the first potential signal, and the second pole of the first transistor is connected to the fourth node; The gate of the second transistor is connected to the first node, the first pole of the second transistor accesses the second potential signal, and the second pole of the second transistor is connected to the fourth node; Preferably, the first transistor is a P-type transistor, and the second transistor is an N-type transistor; Preferably, the first control unit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The gate of the third transistor is connected to the first node, the first pole of the third transistor accesses the first potential signal, and the second pole of the third transistor is connected to the gate of the sixth transistor and the first pole of the fifth transistor; The gate of the fourth transistor is connected to the fourth node, the first pole of the fourth transistor accesses the first potential signal, and the second pole of the fourth transistor is connected to the gate of the fifth transistor and the first pole of the sixth transistor; The gate of the sixth transistor is connected to the third node, and the second poles of the fifth transistor and the sixth transistor both access the third potential signal; Preferably, the third transistor and the fourth transistor are P-type transistors, and the fifth transistor and the sixth transistor are N-type transistors.

3. The shift register according to claim 1, characterized in that, The input module includes a first potential control unit, a second inverter, and a second potential control unit; The output terminal of the first potential control unit is connected to the fifth node, and is used to respond to the first clock signal and transmit the input signal to the fifth node; The second inverter is connected between the fifth node and the sixth node, and is used to invert the potential of the fifth node and then transmit it to the sixth node; The second potential control unit is connected between the sixth node and the first node, and is used to respond to the second clock signal and transmit the potential of the sixth node to the first node; Preferably, the first potential control unit includes a seventh transistor, the gate of the seventh transistor accesses the first clock signal, the first pole of the seventh transistor accesses the input signal, and the second pole of the seventh transistor is connected to the fifth node; Preferably, the second inverter includes an eighth transistor and a ninth transistor; the gate of the eighth transistor is connected to the fifth node, the first pole of the eighth transistor accesses the first potential signal, and the second pole of the eighth transistor is connected to the sixth node; The gate of the ninth transistor is connected to the fifth node, the first pole of the ninth transistor accesses the second potential signal, and the second pole of the ninth transistor is connected to the sixth node; Preferably, the eighth transistor is a P-type transistor and the ninth transistor is an N-type transistor; Preferably, the second potential control unit includes a tenth transistor, the gate of the tenth transistor accesses the second clock signal, the first pole of the tenth transistor is connected to the sixth node, and the second pole of the tenth transistor is connected to the first node; Optionally, the input module further includes a third inverter and a third potential control unit; The third inverter is connected between the sixth node and the seventh node, and is used to invert the potential of the sixth node and then transmit it to the seventh node; The control terminal of the third potential control unit accesses the first clock signal, the first end of the third potential control unit is connected to the fifth node, the second end of the third potential control unit is connected to the seventh node, and the third potential control unit is used to respond to the first clock signal and transmit the potential of the seventh node to the fifth node; Preferably, the third inverter includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is connected to the sixth node. The first pole of the eleventh transistor receives the first potential signal. The second pole of the eleventh transistor is connected to the seventh node. The gate of the twelfth transistor is connected to the sixth node. The first pole of the twelfth transistor receives the second potential signal. The second pole of the twelfth transistor is connected to the seventh node. Preferably, the eleventh transistor is a P-type transistor and the twelfth transistor is an N-type transistor. Preferably, the third potential control unit includes a thirteenth transistor. The gate of the thirteenth transistor serves as the control end of the third potential control unit. The first pole of the thirteenth transistor serves as the first end of the third potential control unit. The second pole of the thirteenth transistor serves as the second end of the third potential control unit. Preferably, the thirteenth transistor is an N-type transistor.

4. The shift register according to claim 3, characterized in that The second control module is respectively connected to the fifth node and the third node. The second control module also receives the first clock signal. The second control module is configured to control the potential of the third node according to the potential of the fifth node and the first clock signal, so that the potential of the third node is negatively correlated with the potential of the fifth node. Preferably, the potentials of the first node and the third node simultaneously change from a low potential to a high potential, and / or the potentials of the first node and the third node simultaneously change from a high potential to a low potential. Preferably, the potential of the third node includes a first level signal and a third level signal, and the voltage of the third level signal is lower than the voltage of the first level signal. Preferably, the absolute value of the voltage difference between the third level signal and the first level signal is greater than the absolute value of the voltage difference between the second level signal and the first level signal. Preferably, the potential of the third node is negatively correlated with the potential of the fifth node, and thus the potential of the third node is positively correlated with the potential of the first node.

5. The shift register according to claim 4, characterized in that, The second control module includes a charge and discharge control unit, a coupling unit, and a unidirectional conduction unit. The charge and discharge control unit is respectively connected to the fifth node, the first end of the coupling unit, and the second end of the coupling unit. The second end of the coupling unit is connected to the first end of the unidirectional conduction unit. The second end of the unidirectional conduction unit is connected to the third node. The charge and discharge control unit is configured to charge and / or discharge the coupling unit according to the potential of the fifth node and the first clock signal. The coupling unit is configured to couple the potential change of its first end to the second end. The unidirectional conduction unit is configured to conduct when the potential of the first end of the unidirectional conduction unit is lower than the potential of the third node. Preferably, the charge and discharge control unit includes a fourteenth transistor and a fifteenth transistor. The gate of the fourteenth transistor is connected to the fifth node, the first pole of the fourteenth transistor accesses the first potential signal, and the second pole of the fourteenth transistor is connected to the first end of the coupling unit; the gate of the fifteenth transistor is connected to the second end of the coupling unit, the first pole of the fifteenth transistor accesses the first clock signal, and the second pole of the fifteenth transistor is connected to the first end of the coupling unit; Preferably, both the fourteenth transistor and the fifteenth transistor are P-type transistors; Preferably, the coupling unit includes a first capacitor. The first plate of the first capacitor serves as the first end of the coupling unit, and the second plate of the first capacitor serves as the second end of the coupling unit; Preferably, the unidirectional conduction unit includes a sixteenth transistor. The gate of the sixteenth transistor is connected to the first pole of the sixteenth transistor, the gate of the sixteenth transistor is connected to the second end of the coupling unit, and the second pole of the sixteenth transistor is connected to the third node; Preferably, the sixteenth transistor is a P-type transistor; Preferably, the second control module further includes a second control unit; The control terminal of the second control unit accesses the first clock signal. The second end of the second control unit is connected to the first node, and the second end of the second control unit is connected to the first end of the unidirectional conduction unit. The second control unit is configured to transmit the potential of the first node to the first end of the unidirectional conduction unit according to the first clock signal; Preferably, the second control unit includes a seventeenth transistor. The gate of the seventeenth transistor serves as the control terminal of the second control unit, the first pole of the seventeenth transistor serves as the first end of the second control unit, and the second pole of the seventeenth transistor serves as the second end of the second control unit; Preferably, the seventeenth transistor is an N-type transistor; Preferably, the second control module further includes a third control unit. The control terminal of the third control unit accesses the second potential signal. The second control unit is connected to the first end of the unidirectional conduction unit through the third control unit. The third control unit is configured to conduct or turn off according to the potential difference between the second potential signal and the second end of the second control unit; Preferably, the third control unit includes an eighteenth transistor. The gate of the eighteenth transistor serves as the control terminal of the third control unit, the first pole of the eighteenth transistor is connected to the second end of the second control unit, and the second pole of the eighteenth transistor is connected to the first end of the unidirectional conduction unit; Preferably, the eighteenth transistor is a P-type transistor; Preferably, the second control module further includes a fourth control unit. The control terminal of the fourth control unit is connected to the second potential signal. The first terminal of the fourth control unit is connected to the first node. The second terminal of the fourth control unit is connected to the third node. The fourth control unit is configured to conduct or turn off according to the potential difference between the second potential signal and the first node. Preferably, the fourth control unit includes a nineteenth transistor. The gate of the nineteenth transistor serves as the control terminal of the fourth control unit. The first pole of the nineteenth transistor serves as the first terminal of the fourth control unit. The second pole of the nineteenth transistor serves as the second terminal of the fourth control unit. Preferably, the nineteenth transistor is a P-type transistor. Preferably, the second control module further includes a reset unit. The control terminal of the reset unit is connected to a reset signal. The first terminal of the reset unit is connected to the first potential signal. The second terminal of the reset unit is connected to the first node and the first terminal of the fourth control unit. The reset unit is configured to transmit the first potential signal to the first node according to the reset signal. Preferably, the reset unit includes a twentieth transistor. The gate of the twentieth transistor serves as the control terminal of the reset unit. The first pole of the twentieth transistor serves as the first terminal of the reset unit. The second pole of the twentieth transistor serves as the second terminal of the reset unit. Preferably, the twentieth transistor is a P-type transistor.

6. The shift register according to claim 1, characterized in that The first output module includes: a first output unit and a second output unit. The first output unit is connected to the second node and is configured to output the first potential signal as the first scan signal according to the potential of the second node. The second output unit is connected to the third node and is configured to output the second potential signal as the first scan signal according to the potential of the third node. Preferably, the first output unit includes: a twenty-first transistor. The gate of the twenty-first transistor is connected to the second node. The first pole of the twenty-first transistor is connected to the first potential signal. The second pole of the twenty-first transistor serves as the output terminal of the first output unit. The second output unit includes: a twenty-second transistor and a second capacitor. The gate of the twenty-second transistor is connected to the third node and the first end of the second capacitor respectively. The first pole of the twenty-second transistor is connected to the second end of the second capacitor and serves as the output terminal of the second output unit. The second pole of the twenty-second transistor is connected to the second potential signal. Preferably, both the twenty-first transistor and the twenty-second transistor are P-type transistors.

7. The shift register according to claim 1, characterized in that, The first control module includes a fourth inverter. The fourth inverter is connected between the first node and the second node and is configured to transmit the first potential signal or the second potential signal to the second node in response to the potential of the first node. Preferably, the fourth inverter includes a twenty-third transistor and a twenty-fourth transistor. The gate of the twenty-third transistor is connected to the first node. The first pole of the twenty-third transistor receives the first potential signal. The second pole of the twenty-third transistor is connected to the second node; The gate of the twenty-fourth transistor is connected to the first node. The first pole of the twenty-fourth transistor receives the second potential signal. The second pole of the twenty-fourth transistor is connected to the second node; Preferably, the twenty-third transistor is a P-type transistor and the twenty-fourth transistor is an N-type transistor; Preferably, the first control module further includes a fifth inverter and a fourth potential control unit; The fifth inverter is connected between the second node and the eighth node and is used to invert the potential of the second node and transmit it to the eighth node; The control terminal of the fourth potential control unit receives the second clock signal. The first terminal of the fourth potential control unit is connected to the first node. The second terminal of the fourth potential control unit is connected to the eighth node. The fourth potential control unit is used to respond to the second clock signal and transmit the potential of the eighth node to the first node; Preferably, the fifth inverter includes a twenty-fifth transistor and a twenty-sixth transistor. The gate of the twenty-fifth transistor is connected to the second node. The first pole of the twenty-fifth transistor receives the first potential signal. The second pole of the twenty-fifth transistor is connected to the eighth node; The gate of the twenty-sixth transistor is connected to the second node. The first pole of the twenty-sixth transistor receives the second potential signal. The second pole of the twenty-sixth transistor is connected to the eighth node; Preferably, the twenty-fifth transistor is a P-type transistor and the twenty-sixth transistor is an N-type transistor; Preferably, the fourth potential control unit includes a twenty-seventh transistor. The gate of the twenty-seventh transistor serves as the control terminal of the fourth potential control unit. The first pole of the twenty-seventh transistor serves as the first terminal of the fourth potential control unit. The second pole of the twenty-seventh transistor serves as the second terminal of the fourth potential control unit; Preferably, the twenty-seventh transistor is an N-type transistor; Preferably, the second control module includes a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor; The gate of the twenty-eighth transistor is connected to the gate of the twenty-fifth transistor. The first pole of the twenty-eighth transistor receives the first potential signal. The second pole of the twenty-eighth transistor is connected to the gate of the thirty-first transistor and the first pole of the twenty-ninth transistor; The gate of the thirtieth transistor is connected to the eighth node and the second node. The first pole of the thirtieth transistor receives the first potential signal. The second pole of the thirtieth transistor is connected to the gate of the twenty-ninth transistor and the first pole of the thirty-first transistor; The second poles of the twenty-ninth transistor and the thirty-first transistor are both connected to a third potential signal.

8. A gate driving circuit, characterized in that, Comprising: Multiple shift registers as described in any one of claims 1-6; wherein the output end of the previous shift register is connected to the input end of the input module of the next shift register.

9. A gate driving circuit, characterized in that, Comprising: A shift register as described in claim 7 as a starting shift register; further comprising multiple output shift registers; In the starting shift register, the first control module is used to output a shift signal; The output shift register includes: a drive control module, a stage transmission output module, a transmission control module, and a second output module; The output end of the drive control module is connected to a ninth node, and is used to respond to a first clock signal and transmit the shift signal to the ninth node; The stage transmission output module is connected to the ninth node, and is used to output a first potential signal or a second potential signal to the first output end of the stage transmission output module according to the potential of the ninth node, and is used to output the first potential signal or the second potential signal to the second output end of the stage transmission output module according to the potential of the first output end of the stage transmission output module; The transmission control module is connected to the first output end and the second output end, and is used to control the potential of the first control end of the second output module according to the potentials of the first output end and the second output end; The first control end of the second output module is connected to the transmission control module, the second control end of the second output module is connected to the first output end of the stage transmission output module, and the second output module is used to respond to the potential of the second control end and output the first potential signal as a second scan signal, or respond to the potential of the first control end and output the second potential signal as the second scan signal; Wherein, the input end of the first-stage output shift register is connected to the first control module of the starting shift register, and the input end of the (i + 1)-th stage output shift register is connected to the first output end of the stage transmission output module of the i-th stage output shift register, and i is an integer greater than or equal to 1.

10. The gate driving circuit according to claim 9, wherein The stage transmission output module includes a sixth potential control unit, a sixth inverter, and a seventh inverter; The control end of the sixth potential control unit is connected to a first clock signal, the first end of the sixth potential control unit is connected to the ninth node, the second end of the sixth potential control unit is used as the second output end of the stage transmission output module, and the sixth potential control unit is used to respond to the first clock signal and transmit the potential of the ninth node to the second output end of the stage transmission output module; The sixth inverter is connected between the ninth node and a tenth node, and is used to respond to the potential of the ninth node and transmit the first potential signal or the second potential signal to the tenth node; The tenth node is used as the first output end of the stage transmission output module; The seventh inverter is connected between the tenth node and the eleventh node, and is configured to transmit the first potential signal or the second potential signal to the eleventh node in response to the potential of the tenth node; the eleventh node serves as the second output terminal of the stage transmission output module; Preferably, the sixth potential control unit includes a thirty-second transistor, the gate of the thirty-second transistor serves as the control terminal of the sixth potential control unit, the first pole of the thirty-second transistor serves as the first terminal of the sixth potential control unit, and the second pole of the thirty-second transistor serves as the second terminal of the sixth potential control unit; Preferably, the sixth inverter includes a thirty-third transistor and a thirty-fourth transistor, the gate of the thirty-third transistor is connected to the ninth node, the first pole of the thirty-third transistor is connected to the first potential signal, and the second pole of the thirty-third transistor is connected to the tenth node; The gate of the thirty-fourth transistor is connected to the ninth node, the first pole of the thirty-fourth transistor is connected to the second potential signal, and the second pole of the thirty-fourth transistor is connected to the tenth node; Preferably, the seventh inverter includes a thirty-fifth transistor and a thirty-sixth transistor, the gate of the thirty-fifth transistor is connected to the tenth node, the first pole of the thirty-fifth transistor is connected to the first potential signal, and the second pole of the thirty-fifth transistor is connected to the tenth node; The gate of the thirty-sixth transistor is connected to the eleventh node, the first pole of the thirty-sixth transistor is connected to the second potential signal, and the second pole of the thirty-sixth transistor is connected to the eleventh node.

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