Packaging method and packaging structure

Abstract

According to the packaging method and the packaging structure provided by the invention, a two-time scribing process is adopted to replace a traditional one-time scribing process, after first-time scribing is carried out, the hydrophobic glue layer is formed in the cutting groove, after second-time scribing is carried out, the independent chip is formed, the upper part of the side wall of the chip is covered with the hydrophobic glue layer, and the hydrophobic glue layer can disperse an adhesive material. In the formed packaging structure, the adhesive material can only climb along the surface, not covered by the hydrophobic glue layer, of the side wall of the chip, the climbing height of the adhesive material is limited, the formed packaging structure can meet the requirements of semiconductor packaging specifications, the yield of the packaging structure is improved, and the packaging cost is reduced. And the failure or poor contact between the packaging structure and the heat dissipation cover caused by the fact that the adhesive material climbs to the surface of the chip is effectively avoided. And meanwhile, the climbing height of the adhesive material is limited, so that the thickness of the adhesive material between the chip and the bearing structure can be increased, and the reliability of the packaging structure is further improved. Fool-proof is achieved from the process source, the packaging process can be implemented, the process operability is high, and application and popularization are facilitated.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and particularly to a packaging method and a packaging structure. Background Art

[0002] Semiconductor packaging refers to the process of processing a tested wafer into independent chips according to product models and functional requirements. In the semiconductor packaging process, the wafer from the front-end process of the wafer is cut into small chips through a dicing process, and the chips are fixed on a carrier such as a lead frame or a substrate through a die bonding process. In the die bonding process, an adhesive material is coated on the carrier, and the back surface of the chip is fixed on the carrier through the adhesive material, and finally cured after baking to form a die bond. In the die bonding process, the adhesive material on the back surface of the chip will climb along the side wall of the chip. In the semiconductor packaging specification, if the height of the adhesive material on the side wall of the chip exceeds 90% of the height of the chip side wall, the packaging structure is judged to be defective.

[0003] As Figure 1A shown, it is a schematic diagram after die bonding on a lead frame. In some packaging structures, the chip 100 is fixed on the base island 120 of the lead frame through the adhesive material 110. The adhesive material 110 climbs on the side wall of the chip 100, and the climbing height of the adhesive material 110 is greater than 90% of the height of the side wall of the chip 100. Then, according to the semiconductor packaging specification, this packaging structure is judged to be defective. As Figure 1B shown, it is another schematic diagram after die bonding on a lead frame. In some packaging structures, the adhesive material 110 climbs on the side wall of the chip 100 and turns up to the front surface of the chip 100, which will directly cause the product to fail.

[0004] Therefore, how to limit the climbing height of the adhesive material on the side of the chip has become the focus of current research. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a packaging method and a packaging structure, which can limit the climbing height of the adhesive material on the side of the chip, can improve the yield of the packaged product, and can effectively avoid the failure of the packaged product caused by the climbing of the adhesive material.

[0006] To solve the above problems, the present invention provides a packaging method, including: providing a wafer to be scribed, the wafer to be scribed including a plurality of chips, with a dicing channel between adjacent chips; performing a first scribing along the dicing channel to form a cutting groove, the depth of the cutting groove being less than the thickness of the chip; forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer being capable of separating the adhesive material; performing a second scribing along the cutting groove to form a plurality of independent chips, the width of the cutting tool used for the second scribing being less than the width of the cutting tool used for the first scribing; and mounting the chips on a carrier structure using an adhesive material.

[0007] In a specific embodiment, in the step of performing the first scribing along the dicing channel, the depth of the cutting groove is 1 / 3 to 1 / 2 of the thickness of the chip.

[0008] In a specific embodiment, in the step of performing the first scribing along the dicing channel, the side wall of the cutting groove is a ramp side wall.

[0009] In a specific embodiment, in the step of performing the first scribing along the dicing channel, the side wall of the cutting groove is a vertical side wall.

[0010] In a specific embodiment, in the step of forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer covers the entire surface of the cutting groove.

[0011] In a specific embodiment, in the step of forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer covers the entire side wall of the cutting groove, and the bottom of the cutting groove is not covered by the glue-repellent layer.

[0012] In a specific embodiment, in the step of forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer covers the upper part of the side wall of the cutting groove, and the bottom of the cutting groove and the lower part of the side wall of the cutting groove are not covered by the glue-repellent layer.

[0013] In a specific embodiment, the step of forming a glue-repellent layer on the surface of the cutting groove further includes spraying a glue-repellent material layer on the surface of the cutting groove; baking and curing the glue-repellent material layer to form the glue-repellent layer.

[0014] In a specific embodiment, in the step of performing the second scribing along the cutting groove, the cutting tool used for the second scribing cuts along the center line of the cutting groove.

[0015] In a specific embodiment, the step of mounting the chip on the carrier structure using an adhesive material further includes: coating the adhesive material on the carrier structure; fixing the chip on the adhesive material; performing reflow soldering, and the adhesive material can climb along the side wall of the chip and cover all or part of the surface of the area on the side wall of the chip where the glue-repellent layer is not provided.

[0016] In a specific embodiment, in the step of mounting the chip on the carrier structure using an adhesive material, the chip is mounted upright on the carrier structure, and the surface of the chip facing away from the carrier structure has solder pads, and the solder pads are electrically connected to the carrier structure through leads.

[0017] In a specific embodiment, the glue-repellent layer is a polyimide layer.

[0018] In a specific embodiment, after the step of mounting the chip on the carrier structure using an adhesive material, it further includes: encapsulating the chip to form an encapsulant, and the encapsulant covers the surface of the carrier structure and encapsulates the chip, the adhesive material and the leads.

[0019] In a specific embodiment, in the step of mounting the chip on the carrier structure using an adhesive material, the chip is mounted upside down on the carrier structure.

[0020] In a specific embodiment, the glue-repellent layer includes one or both of silicon oxide and silicon nitride.

[0021] In a specific embodiment, after the step of mounting the chip on the carrier structure using an adhesive material, it further includes: providing a heat dissipation cover, the heat dissipation cover is buckled on the carrier structure and forms a receiving cavity with the carrier structure, the chip is disposed in the receiving cavity, and the heat dissipation cover is in direct or indirect contact with at least the surface of the chip facing away from the carrier structure.

[0022] To solve the above problems, the present invention also provides a packaging structure, including: a carrier structure; a chip fixed on the carrier structure through an adhesive material, the side wall of the chip includes a first region and a second region disposed above the first region, and a glue-repellent layer covers all or part of the surface of the second region, and the adhesive material also covers all or part of the surface of the side wall of the chip where the glue-repellent layer is not provided, wherein the width of the chip in the second region is smaller than the width of the chip in the first region.

[0023] In a specific embodiment, the depth of the second region is 1 / 3 to 1 / 2 of the thickness of the chip.

[0024] In a specific embodiment, in the second region, the side wall of the chip is a sloped side wall.

[0025] In a specific embodiment, in the second region, the sidewall of the chip is a bent sidewall.

[0026] In a specific embodiment, the chip is face-up mounted on the carrier structure. The surface of the chip facing away from the carrier structure has solder pads, and the solder pads are electrically connected to the carrier structure through leads. The encapsulant covers the surface of the carrier structure and encapsulates the chip, the adhesive material, and the leads.

[0027] In a specific embodiment, the glue-repellent layer is a polyimide layer.

[0028] In a specific embodiment, the chip is flip-chip mounted on the carrier structure.

[0029] In a specific embodiment, the glue-repellent layer includes one or both of silicon oxide and silicon nitride.

[0030] In a specific embodiment, the packaging structure further includes a heat dissipation cover. The heat dissipation cover is snapped onto the carrier structure and forms a receiving cavity with the carrier structure. The chip is disposed in the receiving cavity, and the heat dissipation cover is in direct or indirect contact with at least the surface of the chip facing away from the carrier structure.

[0031] The packaging method provided by the specific embodiment of the present invention uses two dicing processes instead of the traditional single dicing process. After the first dicing, a glue-repellent layer is formed in the cutting groove. After the second dicing, independent chips are formed, and the upper part of the sidewall of the chip is covered with the glue-repellent layer, and the glue-repellent layer can separate the adhesive material. After the chip is mounted on the carrier structure using the adhesive material, the adhesive material can only climb along the surface of the sidewall of the chip that is not covered by the glue-repellent layer, which limits the climbing height of the adhesive material. The formed packaging structure can meet the requirements of semiconductor packaging specifications, improve the yield of the packaging structure, and effectively avoid the failure of the packaging structure caused by the adhesive material climbing onto the chip surface or the poor contact between the chip and the heat dissipation cover. At the same time, the limited climbing height of the adhesive material can also increase the thickness of the adhesive material between the chip and the carrier structure, further improving the reliability of the packaging structure. The packaging method provided by the specific embodiment of the present invention prevents mistakes from the source of the process, the packaging process is feasible, and the process is highly operable, which is conducive to popularization and application.

[0032] In the encapsulation structure provided by the specific embodiment of the present invention, a glue-repellent layer covers all or part of the surface of the upper region (i.e., the second region) of the sidewall of the chip. The glue-repellent layer can repel the adhesive material, thereby limiting the climbing height of the adhesive material on the sidewall of the chip by utilizing the glue-repellent property of the glue-repellent layer. The formed encapsulation structure can meet the requirements of semiconductor encapsulation specifications, improve the yield of the encapsulation structure, and effectively avoid the failure of the encapsulation structure caused by the adhesive material climbing to the surface of the chip facing away from the carrier structure or the poor contact between the chip and the heat sink cover. At the same time, the limited climbing height of the adhesive material can also increase the thickness of the adhesive material between the chip and the carrier structure, further improving the reliability of the encapsulation structure. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1A is a schematic diagram after mounting the chip on the lead frame;

[0035] Figure 1B is another schematic diagram after mounting the chip on the lead frame;

[0036] Figure 2 is a schematic diagram of the steps of the encapsulation method provided by a specific embodiment of the present invention;

[0037] Figures 3A to 3F is a process flow chart of the encapsulation method provided by a specific embodiment of the present invention;

[0038] Figure 4 is a schematic diagram after forming a cutting groove in the encapsulation method provided by another specific embodiment of the present invention;

[0039] Figure 5A is a schematic diagram after forming a glue-repellent layer in the encapsulation method provided by another specific embodiment of the present invention;

[0040] Figure 5B is a schematic diagram after forming a glue-repellent layer in the encapsulation method provided by another specific embodiment of the present invention;

[0041] Figure 6A is a schematic diagram after the second dicing in the encapsulation method provided by another specific embodiment of the present invention;

[0042] Figure 6B is a schematic diagram after the second dicing in the encapsulation method provided by another specific embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of a packaging structure formed by a packaging method provided in another specific embodiment of the present invention. DETAILED DESCRIPTION

[0044] The specific implementation manner of the packaging method and packaging structure provided by the present invention is described in detail below with reference to the accompanying drawings.

[0045] Figure 2 This is a schematic diagram of the steps of the packaging method provided by a specific embodiment of the present invention. Figure 2 The packaging method includes: step S20, providing a wafer to be diced, the wafer to be diced includes a plurality of chips, and there is a cutting path between adjacent chips; step S21, performing a first dicing along the cutting path to form a cutting groove, the depth of the cutting groove is less than the thickness of the chip; step S22, forming a repellent layer on the surface of the cutting groove, the repellent layer can be repelled from the adhesive material; step S23, performing a second dicing along the cutting groove to form a plurality of independent chips, the width of the cutting knife used for the second dicing is less than the width of the cutting knife used for the first dicing; step S24, mounting the chip on a supporting structure using an adhesive material.

[0046] The packaging method provided by the specific embodiment of the present invention adopts a two-slicing process to replace the traditional one-slicing process. After the first slicing, a thin glue layer is formed in the cutting groove. After the second slicing, an independent chip is formed, and the upper part of the side wall of the chip is covered with the thin glue layer, and the thin glue layer can be separated from the adhesive material. After the chip is mounted on the bearing structure using the adhesive material, the adhesive material can only climb along the surface of the chip side wall that is not covered by the thin glue layer, limiting the climbing height of the adhesive material, and the formed packaging structure can meet the requirements of the semiconductor packaging specification, improve the yield of the packaging structure, and effectively avoid the failure of the packaging structure caused by the adhesive material climbing to the surface of the chip away from the bearing structure or the poor contact between the chip and the heat dissipation cover. At the same time, the limited climbing height of the adhesive material can also increase the thickness of the adhesive material between the chip and the bearing structure, further improving the reliability of the packaging structure. The packaging method provided by the specific embodiment of the present invention is foolproof from the source of the process, the packaging process can be implemented, the process is highly operable, and it is conducive to popularization and application.

[0047] The packaging method provided by a specific embodiment of the present invention is further described below in conjunction with the accompanying drawings, wherein: Figures 3A to 3F It is a process flow chart of a packaging method provided by a specific embodiment of the present invention.

[0048] See also Figure 2 and Figure 3A ,in,Figure 3A It is a partial schematic diagram of the wafer to be scribed. In step S20, a wafer to be scribed is provided. The wafer to be scribed includes a plurality of chips 300, and there are scribing channels 320 between adjacent chips 300.

[0049] In Figure 3A order to simplify the illustration, only two of the chips 300 are schematically shown. In fact, a complete wafer may contain hundreds or even thousands of the chips 300, and these chips 300 are separated from each other by the scribing channels 320. The scribing channels 320 are thin lines on the wafer for separating each of the chips 300, and their main function is to provide guiding lines during wafer scribing to ensure the accuracy and consistency of the cutting process. There is a dielectric layer 310 between two adjacent chips 300, and the scribing channels 320 are located in the area where the dielectric layer 310 is located. The dielectric layer 310 is usually composed of an insulating material (such as silicon dioxide), and its main function is to provide electrical isolation to prevent electrical interference between adjacent chips 300.

[0050] Please refer to Figure 2 and Figure 3B , in step S21, a first scribing is performed along the scribing channels 320 to form cutting grooves 330, and the depth of the cutting grooves 330 is less than the thickness of the chips 300.

[0051] Scribing is the process of cutting a single wafer into multiple independent chips. In the first scribing process of the packaging method of the present invention, in the thickness direction of the chips 300, the cutting tool only performs partial cutting along the scribing channels 320, and the formed cutting grooves 330 do not penetrate the wafer, and the dielectric layer 310 at the bottom of the cutting grooves 330 is retained. After the first scribing, independent chips are not formed, but a wafer with the cutting grooves 330 is formed. In this step, the width of the cutting grooves 330 is less than the distance between two adjacent chips 300 to ensure that the functional areas of the chips 300 are not damaged during the cutting process and at the same time maintain the structural integrity of the chips 300.

[0052] In some specific embodiments, the depth of the cutting grooves 330 is 1 / 3 to 1 / 2 of the thickness of the chips 300. If the depth of the cutting grooves 330 is less than 1 / 3 of the thickness of the chips 300, then in the step of mounting the chips 300 on the carrier structure 350 (see Figure 3E ) using the adhesive material 340 (see Figure 3E ), the climbing height of the adhesive material 340 is too high, which may affect the performance of the packaging structure; if the depth of the cutting grooves 330 is greater than 1 / 2 of the thickness of the chips 300, the side walls of the chips 300 cover the glue-repellent layer 360 (see Figure 3E) If the area is too large, then in the step of mounting the chip 300 on the carrier structure 350 using the adhesive material 340, the climbing height of the adhesive material 340 is too low, which may affect the bonding strength between the chip 300 and the carrier structure 350. Setting the depth of the cutting groove 330 to 1 / 3 to 1 / 2 of the thickness of the chip 300 can take into account restricting the climbing height of the adhesive material 340 and ensuring the bonding strength between the chip 300 and the carrier structure. In this specific embodiment, the depth of the cutting groove 330 is 1 / 2 of the thickness of the chip 300.

[0053] In some specific embodiments, the side wall of the cutting groove 330 is a ramp side wall or a vertical side wall. As Figure 3B shown, in this specific embodiment, the cross-section of the cutting groove 330 is rectangular, and the side wall of the cutting groove 330 is a vertical side wall; as Figure 4 shown, in this specific embodiment, the cross-section of the cutting groove 330 is V-shaped, and the side wall of the cutting groove 330 is a ramp side wall. In some specific embodiments, with different cutting depths, the shape of the cross-section of the cutting groove 330 may also be different, thereby making the form of the side wall of the cutting groove 330 different. For example, in some specific embodiments, when the cutting depth is relatively shallow, the shape of the cross-section of the cutting groove 330 is V-shaped, and the side wall of the cutting groove 330 is a ramp side wall; when the cutting depth is relatively deep, the shape of the cross-section of the cutting groove 330 is rectangular, and the side wall of the cutting groove 330 is a vertical side wall.

[0054] Please refer to Figure 2 and Figure 3C , step S22, forming a glue-repellent layer 360 on the surface of the cutting groove 330, and the glue-repellent layer 360 can repel the adhesive material 340 (see Figure 3E ).

[0055] The glue-repellent layer 360 can repel the adhesive material 340 means that the adhesive material 340 has very low wettability or no wettability on the surface of the glue-repellent layer 360, the climbing height of the adhesive material 340 along the glue-repellent layer 360 is very low and can be ignored, or the adhesive material 340 will not climb along the glue-repellent layer 360. In this specific embodiment, the glue-repellent layer 360 is a polyimide (abbreviated as PI) layer, and the adhesive material 340 is a tin-containing solder. This kind of adhesive material has good wettability and mechanical strength and is widely used in fields such as electronic manufacturing, electrical connection, and pipe welding. The tin-containing adhesive material has very low wettability on the surface of the polyimide layer, thereby preventing the tin-containing adhesive material from climbing along the polyimide layer.

[0056] In some specific embodiments, the glue-repellent layer 360 extends from the top edge of the sidewall of the cutting groove 330 towards the bottom of the cutting groove 330, that is, the glue-repellent layer 360 covers the sidewall of the cutting groove 330 starting from the top edge of the sidewall of the cutting groove 330, so as to form an effective isolation in the top region of the sidewall of the chip 300 formed in subsequent steps, further restricting the upward climbing of the adhesive material 340 and avoiding the adhesive material 340 covering the surface of the chip 300 facing away from the carrier structure 350.

[0057] In some specific embodiments, the glue-repellent layer 360 covers all or part of the surface of the cutting groove 330. For example, as Figure 3C shown, in this specific embodiment, the glue-repellent layer 360 covers all the surface of the cutting groove 330, that is, the glue-repellent layer 360 covers the sidewall and the bottom of the cutting groove 330. For example, as Figure 5A shown, in another specific embodiment, the glue-repellent layer 360 covers all the sidewalls of the cutting groove 330, and the bottom of the cutting groove 330 is not covered by the glue-repellent layer 360. For example, as Figure 5B shown, in another specific embodiment, the glue-repellent layer 360 covers the upper part of the sidewall of the cutting groove 330, and the bottom of the cutting groove 330 and the lower part of the sidewall of the cutting groove 330 are not covered by the glue-repellent layer 360.

[0058] In a specific embodiment, the step of forming the glue-repellent layer 360 on the surface of the cutting groove 330 further includes: spraying a glue-repellent material layer on the surface of the cutting groove 330; baking and curing the glue-repellent material layer to form the glue-repellent layer 360. For example, spraying a polyimide material layer on the surface of the cutting groove 330; baking and curing the polyimide material layer to form a polyimide layer.

[0059] Please refer to Figure 2 and Figure 3D , step S23, perform a second dicing along the cutting groove 330 to form a plurality of independent chips 300, and the width of the cutting blade used in the second dicing is smaller than the width of the cutting blade used in the first dicing.

[0060] In this step, in the thickness direction of the chip 300, the cutting blade performs a complete cut to form an independent chip 300.

[0061] In this step, when performing the second dicing, a cutting blade with a smaller width is used for cutting, and the glue-removing layer 360 on the sidewall of the chip 300 is retained. Specifically, the width of the cutting blade for the second dicing is smaller than the distance between the glue-removing layers 360 covered by the two opposite sidewalls of the cutting groove 330. When performing the second dicing, the glue-removing layers 360 covered by the two opposite sidewalls of the cutting groove 330 are not cut off, thereby forming an area covered with the glue-removing layer 360 on the sidewall of the chip 300. In a specific embodiment, the cutting blade used for the second dicing cuts along the center line of the cutting groove 330 to ensure high consistency in the size and shape of the formed chips 300, minimize the cutting deviation, and improve the geometric accuracy of the chips.

[0062] The sidewall of the chip 300 formed by cutting in this step includes a first region 300A and a second region 300B provided above the first region 300A, and the glue-removing layer 360 covers all or part of the surface of the second region 300B.

[0063] For example, in this specific embodiment, if the glue-removing layer 360 covers the entire surface of the cutting groove 330, then on the sidewall of the formed chip 300, the entire surface of the second region 300B is covered with the glue-removing layer 360, as Figure 3D shown.

[0064] For example, in another specific embodiment, the glue-removing layer 360 covers all the sidewalls of the cutting groove 330, and the bottom of the cutting groove 330 is not covered by the glue-removing layer 360. Then on the sidewall of the formed chip 300, the vertical surface of the second region 300B is covered with the glue-removing layer 360, and the horizontal surface is not covered with the glue-removing layer 360, as Figure 6A shown. For another example, in another specific embodiment, the glue-removing layer 360 covers the upper part of the sidewall of the cutting groove 330, and the bottom of the cutting groove 330 and the lower part of the sidewall of the cutting groove 330 are not covered by the glue-removing layer 360. Then on the sidewall of the formed chip 300, only a partial area of the vertical surface of the second region 300B is covered with the glue-removing layer 360, as Figure 6B shown.

[0065] Please refer to Figure 2 and Figure 3E Step S24, mount the chip 300 on the carrier structure 350 using the adhesive material 340.

[0066] The carrier structure 350 includes, but is not limited to, structures used in packaging processes such as substrates, lead frames, etc. The carrier structure 350 can adopt existing ceramic substrates, or lead frames, or stacked substrates, or MIS (Molded Interconnect System) plastic-encapsulated interconnect substrates, or rewiring stacked layers, etc. These substrate materials and technologies have their own characteristics: Ceramic substrates have excellent thermal conductivity and mechanical strength, and are suitable for high-power and high-reliability scenarios; Lead frames have a lower cost and are suitable for traditional packaging requirements; Stacked substrates achieve high-density interconnection through multi-layer wiring and are suitable for complex circuit designs; MIS plastic-encapsulated interconnect substrates combine injection molding and interconnect technologies and have the advantages of high integration and low cost; Rewiring stacked layers achieve higher integration density and performance optimization through vertical stacking and rewiring technologies. The material selection and structural design of the carrier structure 350 can be adjusted according to the requirements of specific application scenarios. For example, low-dielectric-constant materials are used in high-frequency applications to reduce signal loss, or high-temperature-resistant materials are used in high-temperature environments to improve reliability.

[0067] The carrier structure 350 includes a top surface and a bottom surface that are relatively distributed. A circuit layer (not labeled in the drawings) is provided inside the carrier structure 350 for realizing the transmission and distribution of electrical signals. In some specific embodiments, a plurality of lead-out solder balls electrically connected to the circuit layer are provided on the bottom surface of the carrier structure 350. The lead-out solder balls not only provide electrical connection but also play a mechanical support role. In a specific embodiment, the carrier structure 350 is disposed on a printed circuit board through the lead-out solder balls and is electrically connected to the printed circuit board through the lead-out solder balls. This connection method is realized through a reflow soldering process to ensure a reliable electrical and mechanical connection between the lead-out solder balls and the pads on the printed circuit board.

[0068] In this step, the chip 300 is mounted on the carrier structure 350 using the adhesion material 340. To ensure the soldering and fixing effect of the adhesion material 340, the adhesion material 340 needs to climb a certain height along the side wall of the chip 300. However, if the climbing height of the adhesion material 340 on the side wall of the chip 300 is too high, it will not meet the requirements of semiconductor packaging specifications and may cause the chip 300 to fail.

[0069] In the encapsulation method of the present invention, after the chip 300 is mounted on the carrier structure 350 using the adhesive material 340, due to the characteristics of the glue-repellent layer 360, the adhesive material 340 can only climb along the surface of the sidewall of the chip 300 that is not covered by the glue-repellent layer 360, which limits the climbing height of the adhesive material 340. The formed encapsulation structure can meet the requirements of semiconductor encapsulation specifications, and effectively avoid the failure of the encapsulation structure caused by the adhesive material 340 climbing onto the surface of the chip 300 or affecting the heat dissipation effect of the heat sink cover on the chip 300. At the same time, the limited climbing height of the adhesive material 340 can also increase the thickness of the adhesive material 340 between the chip 300 and the carrier structure 350, further improving the reliability of the encapsulation structure.

[0070] In a specific embodiment, the step of mounting the chip 300 on the carrier structure 350 using the adhesive material 340 further includes the following main steps: Coating the adhesive material 340 on the carrier structure 350. For example, the adhesive material 340 is uniformly coated on the designated area of the carrier structure 350 by techniques such as screen printing, dispensing, or spraying. Fixing the chip 300 on the adhesive material 340. For example, using a high-precision chip mounter to accurately place the chip 300 on the adhesive material 340 of the carrier structure 350. Performing reflow soldering, the adhesive material 340 can climb along the sidewall of the chip 300 and cover all or part of the surface of the area on the sidewall of the chip 300 where the glue-repellent layer 360 is not provided. Setting the reflow soldering temperature curve according to the characteristics of the adhesive material 340, including preheating, reflow, and cooling stages, and precisely controlling the temperature and time of each stage to ensure that the adhesive material 340 is fully melted and wets the surfaces of the chip 300 and the carrier structure 350.

[0071] In this specific embodiment, the chip 300 is face-up mounted on the carrier structure 350. The surface of the chip 300 facing away from the carrier structure 350 has bonding pads 301, and the bonding pads 301 are electrically connected to the carrier structure 350 through leads 380. Specifically, after coating the adhesive material 340 on the carrier structure 350, the chip 300 is adhered to the adhesive material 340, and the bonding pads 301 are electrically connected to the carrier structure 350 through leads 380 by using a wire bonding process.

[0072] In one example, the chip 300 includes a back surface facing the carrier structure 350 and a front surface facing away from the carrier structure 350. An array of aluminum / copper pads 301 is disposed around the periphery of the front surface of the chip 300. The surface of the pads 301 can be treated by sputtering nickel / gold to enhance the bonding performance. The back surface of the chip 300 is mechanically and thermally conductively connected to the carrier structure 350 through the adhesive material 340. A lead bonding area is provided on the top surface of the carrier structure 350. One end of the lead 380 is bonded to the pad 301 of the chip 300 by a welding process such as thermal ultrasonic ball bonding, and the other end is connected to the corresponding lead bonding area of the carrier structure 350 by a welding process such as wedge bonding, forming the arc-shaped lead 380. The lead 380 can be a gold wire, a silver wire, a copper wire, an aluminum wire, or an alloy wire, etc.

[0073] In the above specific implementation, after the chip 300 is face-up mounted on the top surface of the carrier structure 350, if the adhesive material 340 climbs up to the surface of the chip 300 facing away from the carrier structure 350, it may contaminate the pad 301 on the surface of the chip 300, thereby affecting the welding between the pad 301 and the lead 380. The encapsulation method provided by the specific implementation of the present invention cleverly uses the glue repellent layer 360 to effectively control the climbing height of the adhesive material 340, avoiding the adhesive material 340 from climbing up to the surface of the chip 300 facing away from the carrier structure 350 and contaminating the pad 301, effectively ensuring the reliability of the encapsulation structure. Moreover, the encapsulation method of the present invention prevents mistakes from the source of the process, the encapsulation process is feasible, and the process operability is strong, which is conducive to popularization and application.

[0074] Further, in some specific implementations, after the step of face-up mounting the chip 300 on the carrier structure 350, it further includes: Please refer to Figure 3F , encapsulating the chip 300 to form an encapsulant 370, where the encapsulant 370 covers the surface of the carrier structure 350 and encapsulates the chip 300, the adhesive material 340, and the lead 380.

[0075] The encapsulant 370 is uniformly covered on the entire surface of the carrier structure 350 by an injection molding process using thermosetting materials such as epoxy resin. The encapsulant 370 not only tightly wraps the front side of the chip 300, but also completely wraps the adhesive material 340 and the side surfaces of the chip 300 to form a reliable physical protection layer. The encapsulant 370 has good mechanical strength, thermal stability, and moisture-proof performance, which can effectively protect the chip 300 from the influence of the external environment (such as moisture, dust, mechanical stress, etc.), and at the same time provide structural support for subsequent cutting, testing, and assembly processes. In addition, the thickness and shape of the encapsulant 370 can be precisely controlled according to the package type (such as QFN, BGA, etc.) to meet the requirements of different application scenarios for package size and heat dissipation performance.

[0076] In the above specific embodiments, the chip 300 is mounted face-up on the carrier structure 350. In some other specific embodiments, the chip 300 is mounted face-down on the carrier structure 350. Specifically, as Figure 7 shown, which is a schematic diagram of a package structure formed by a packaging method provided in another specific embodiment of the present invention. In this specific embodiment, the chip 300 is mounted face-down on the carrier structure 350.

[0077] The chip 300 includes a front side facing the carrier structure 350 and a back side facing away from the carrier structure 350. A plurality of conductive bumps 701 are provided on the front side of the chip 300. These conductive bumps 701 are usually made of conductive materials such as copper, nickel, or gold, and are soldered to the top surface of the carrier structure 350. During the soldering process, the solder melts at high temperature to form a reliable electrical and mechanical connection, ensuring that the conductive bumps 701 are in close contact with the circuit layer in the carrier structure 350. This connection method can not only achieve efficient signal transmission, but also withstand certain mechanical stress and thermal stress, improving the reliability of the package structure. Through the electrical connection between the conductive bumps 701 and the circuit layer in the carrier structure 350, control signals can be transmitted to the chip 300 or signals in the chip 300 can be led out. This design shortens the signal transmission path, reduces signal delay and loss, and is particularly suitable for high-frequency and high-performance application scenarios. In addition, the distribution and number of the conductive bumps 701 can be optimized according to the pin layout and signal requirements of the chip 300 to achieve higher connection density and more flexible wiring.

[0078] In this specific embodiment, the adhesive material 340 is filled in the gap between the chip 300 and the carrier structure 350 and completely fills the space between the conductive bumps 701. The material of the adhesive material 340 can be underfill, which is an epoxy resin material specifically used for flip-chip packaging, having excellent fluidity, bonding strength, and thermal stability, further enhancing the mechanical connection between the chip 300 and the carrier structure 350. The adhesive material 340 can also provide a certain degree of insulation protection to prevent short circuits or corrosion problems between the conductive bumps 701 caused by the external environment (such as moisture and dust). At the same time, the coefficient of thermal expansion of the underfill can be optimally selected according to the material properties of the chip 300 and the carrier structure 350 to reduce the stress generated during the thermal cycle and extend the service life of the packaging structure. The glue-repellent layer 360 includes one or both of silicon oxide and silicon nitride. As a barrier structure, the glue-repellent layer 360 can prevent the adhesive material 340 from climbing. During the operation of the semiconductor device, the chip 300 generates a large amount of heat due to the high-frequency switching and current conduction of the internal circuit. To avoid the influence of this heat on the performance of the chip 300, the heat needs to be dissipated in a timely manner. In some specific embodiments, the heat generated inside the chip 300 is dissipated by providing a heat sink cover.

[0079] Specifically, as Figure 7 shown, after the step of mounting the chip on the carrier structure using the adhesive material, the packaging method further includes: providing a heat sink cover 700, the heat sink cover 700 being snapped onto the carrier structure 350 and forming a receiving cavity 710 with the carrier structure 350, the chip 300 being disposed in the receiving cavity 710, and the heat sink cover 700 being in direct or indirect contact with at least the surface of the chip 300 facing away from the carrier structure 350. During the operation of the semiconductor device, the heat generated by the chip 300 is mainly transferred from the active region of the chip 300 to its back surface by heat conduction and then to the heat sink cover 700 through a thermal conductive adhesive.

[0080] The heat sink cover 700 is generally made of a material with a high thermal conductivity coefficient (such as copper, aluminum, or ceramic composite material). Its bottom is in close contact with the chip 300, and its top is designed with heat dissipation fins or connected to other heat dissipation structures (such as heat pipes or cooling fans) to increase the heat dissipation surface area. The heat sink cover 700 quickly dissipates the heat to the surrounding environment through heat convection and heat radiation, thereby effectively reducing the operating temperature of the chip 300 and ensuring its stability and reliability.

[0081] In this specific embodiment, the heat dissipation cover 700 has a concave configuration and is inverted on the top surface of the carrier structure 350, enclosing the accommodation cavity 710 with the carrier structure 350. This concave design not only provides sufficient installation space for the chip 300 and other electronic components, but also enhances the mechanical stability and sealing performance of the overall structure through the close fit between the side wall of the heat dissipation cover 700 and the carrier structure 350.

[0082] The side wall of the heat dissipation cover 700 is fixedly connected to the top surface of the carrier structure 350 through an adhesive layer 730. The adhesive layer 730 generally uses materials with high thermal conductivity and certain elasticity, such as epoxy resin or silica gel, to ensure a firm connection between the heat dissipation cover 700 and the carrier structure 350, and at the same time can relieve the stress caused by the difference in thermal expansion coefficients. In some specific embodiments, the thickness and material properties of the adhesive layer 730 can be optimized according to the heat dissipation requirements and mechanical strength requirements. For example, in high-power applications, the adhesive layer 730 can use epoxy resin enhanced with high thermal conductivity fillers (such as silver powder or ceramic particles) to improve the heat conduction efficiency; while in scenarios with higher requirements for mechanical strength, an adhesive material with high bonding strength and impact resistance can be selected. Through the setting of the adhesive layer 730, the sealing of the accommodation cavity 710 can also be achieved to prevent external dust, moisture or other pollutants from entering the accommodation cavity 710, improving the reliability and service life of the packaging structure.

[0083] In this specific embodiment, the heat dissipation cover 700 is fixed on the surface of the chip 300 facing away from the carrier structure 350 through a thermal interface material (TIM) 720, that is, the heat dissipation cover 700 is indirectly in contact with the surface of the chip 300 facing away from the carrier structure 350 through the thermal conductive adhesive 720. In some other specific embodiments, the heat dissipation cover 700 can also be directly attached to the surface of the chip 300 facing away from the carrier structure 350, that is, the heat dissipation cover 700 is directly in contact with the surface of the chip 300 facing away from the carrier structure 350.

[0084] A large amount of heat generated by the chip 300 during operation is transferred from the active area of the chip 300 to its back surface through heat conduction, and then directly transferred or transferred to the heat dissipation cover 700 through the thermal conductive adhesive and dissipated into the external environment. In the above specific embodiment, when the chip 300 is flip-chip mounted on the top surface of the carrier structure 350, the heat dissipation of the chip 300 is achieved by arranging the heat dissipation cover on the surface of the chip 300 facing away from the carrier structure 350 (such as Figure 7As shown, if the adhesive material 340 climbs up to the surface of the chip 300 facing away from the carrier structure 350, it will prevent the surface of the chip 300 facing away from the carrier structure 350 from contacting the heat dissipation cover, thereby affecting heat dissipation. The packaging method provided by the specific embodiment of the present invention cleverly uses the glue-repellent layer 360 to effectively control the climbing height of the adhesive material 340, preventing the adhesive material 340 from climbing up to the surface of the chip 300 facing away from the carrier structure 350, effectively ensuring the contact between the heat dissipation cover and the chip surface, and ensuring the heat dissipation performance of the packaging structure. The packaging method of the present invention prevents mistakes from the source of the process, the packaging process is feasible, and the process operability is strong, which is conducive to popularization and application.

[0085] The packaging method provided by the specific embodiment of the present invention utilizes the property of the glue-repellent layer to separate the adhesive material, restricting the climbing height of the adhesive material. The formed packaging structure can meet the requirements of semiconductor packaging specifications, improve the yield of the packaging structure, and effectively avoid the failure of the packaging structure or the poor contact between the chip and the heat dissipation cover caused by the adhesive material climbing up to the surface of the chip facing away from the carrier structure.

[0086] Based on the same inventive concept, the specific embodiment of the present invention also provides a packaging structure formed by the above packaging method. Please refer to Figures 3A to 3F , the packaging structure includes: a carrier structure 350; a chip 300 fixed on the carrier structure 350 through an adhesive material 340. The side wall of the chip 300 includes a first region 300A and a second region 300B disposed above the first region 300A. A glue-repellent layer 360 covers all or part of the surface of the second region 300B. The adhesive material 340 also covers all or part of the surface of the side wall of the chip 300 where the glue-repellent layer 360 is not provided. Among them, the width of the chip 300 in the second region 300B is smaller than the width of the chip 300 in the first region 300A. The first region 300A and the second region 300B are arranged along the thickness direction of the chip 300. The width of the chip 300 refers to the dimension of the chip 300 in the direction perpendicular to the thickness direction of the chip 300. In a specific embodiment, the glue-repellent layer 360 is a polyimide layer.

[0087] In the encapsulation structure provided by the specific embodiment of the present invention, the entire or part of the surface of the upper region (i.e., the second region 300B) of the sidewall of the chip 300 is covered with the glue-repellent layer 360. The glue-repellent layer 360 can repel the adhesive material 340. Furthermore, by using the glue-repellent property of the glue-repellent layer 360, the climbing height of the adhesive material 340 on the sidewall of the chip 300 is limited. The formed encapsulation structure can meet the requirements of semiconductor encapsulation specifications, improve the yield of the encapsulation structure, and effectively avoid the failure of the encapsulation structure caused by the adhesive material 340 climbing to the front surface of the chip 300. At the same time, the limitation of the climbing height of the adhesive material 340 can also increase the thickness of the adhesive material 340 between the chip 300 and the carrier structure 350, further improving the reliability of the encapsulation structure.

[0088] In a specific embodiment, the entire surface of the second region 300B is covered with the glue-repellent layer 360. Refer to Figure 3E ; in another specific embodiment, part of the surface of the second region 300B is covered with the glue-repellent layer 360. Refer to Figure 6A and Figure 6B . In a specific embodiment, the adhesive material 340 is filled between the chip 300 and the carrier structure 350 and covers the entire surface of the sidewall of the chip 300 where the glue-repellent layer 360 is not provided. Refer to Figure 3E . In another specific embodiment, the adhesive material 340 is filled between the chip 300 and the carrier structure 350 and covers part of the surface of the sidewall of the chip 300 where the glue-repellent layer 360 is not provided. Specifically, there is a distance between the highest point where the adhesive material 340 climbs on the sidewall of the chip 300 and the bottom edge of the glue-repellent layer 360.

[0089] In a specific embodiment, the depth of the second region 300B is 1 / 3 to 1 / 2 of the thickness of the chip 300. Specifically, the depth of the second region 300B in the thickness direction of the chip 300 is 1 / 3 to 1 / 2 of the thickness of the chip 300. If the depth of the second region 300B is less than 1 / 3 of the thickness of the chip 300, the climbing height of the adhesive material 340 is too high, which may affect the performance of the packaging structure; if the depth of the second region 300B is greater than 1 / 2 of the thickness of the chip 300, the area of the sidewall of the chip 300 covered by the non-adhesive layer 360 is too large, and the climbing height of the adhesive material 340 is too low, which may affect the bonding strength between the chip 300 and the carrier structure 350. Setting the depth of the second region 300B to 1 / 3 to 1 / 2 of the thickness of the chip 300 can balance the limitation of the climbing height of the adhesive material 340 and ensure the bonding strength of the chip 300. In this specific embodiment, the depth of the second region 300B is 1 / 2 of the thickness of the chip 300.

[0090] In a specific embodiment, in the second region 300B, the sidewall of the chip 300 is a sloped sidewall. Specifically, in the second region 300B, during the process of forming the packaging structure, the sidewall of the cutting groove 330 is a sloped sidewall, as can be seen in Figure 4 , and when the bottom of the cutting groove 330 is completely removed during the second dicing, the sidewall of the finally formed chip 300 is a sloped sidewall. In a specific embodiment, in the second region 300B, the sidewall of the chip 300 is a bent sidewall. Specifically, during the process of forming the packaging structure, the sidewall of the cutting groove 330 is a vertical sidewall or a sloped sidewall, and the bottom of the cutting groove 330 is a flat surface, as can be seen in Figure 3B , and when the bottom of the cutting groove 330 is partially removed during the second dicing, the sidewall of the finally formed chip 300 is a bent sidewall.

[0091] In some specific embodiments, as Figure 3F shown, the chip 300 is mounted on the carrier structure 350 in a face-up manner. The surface of the chip 300 facing away from the carrier structure 350 has bonding pads 301, and the bonding pads 301 are electrically connected to the carrier structure 350 through leads 380. The encapsulant 370 covers the surface of the carrier structure 350 and encapsulates the chip 300, the adhesive material 340, and the leads 380.

[0092] The surface of the chip 300 facing the carrier structure 350 is the back surface, and the surface facing away from the carrier structure 350 is the front surface. An array of aluminum / copper pads 301 is provided on the periphery of the front surface of the chip 300. The surface of the pads 301 can be treated by sputtering nickel / gold to enhance the bonding performance. The back surface of the chip 300 is mechanically and thermally conductively connected to the carrier structure 350 through the adhesive material 340. A wire bonding pad is provided on the top surface of the carrier structure 350. One end of the wire 380 is bonded to the pad 301 of the chip 300, and the other end is connected to the corresponding wire bonding pad of the carrier structure 350, forming the arcuate wire 380. The encapsulant 370 uniformly covers the entire surface of the carrier structure 350 and tightly wraps the front surface of the chip 300, and also completely wraps the adhesive material 340, the side surfaces of the chip 300, and the wire 380, forming a reliable physical protection layer.

[0093] In this specific embodiment, after the chip 300 is mounted face-up on the top surface of the carrier structure 350, if the adhesive material 340 climbs up to the surface of the chip 300 facing away from the carrier structure 350, it may contaminate the pads 301 on the surface of the chip 300, thus affecting the soldering of the pads 301 and the wire 380. The encapsulation method provided by the specific embodiment of the present invention cleverly uses the glue-repellent layer 360 to effectively control the climbing height of the adhesive material 340, preventing the adhesive material 340 from climbing up to the surface of the chip 300 facing away from the carrier structure 350 and contaminating the pads 301, effectively ensuring the reliability of the encapsulation structure.

[0094] In some specific embodiments, the chip 300 is mounted face-up on the carrier structure 350, for example, as Figure 3F shown, while in some specific embodiments, the chip 300 is mounted face-down on the carrier structure 350. For example, in a specific embodiment, as Figure 7As shown, the chip 300 is flip-chip mounted on the carrier structure 350. Specifically, the chip 300 includes a front face facing the carrier structure 350 and a back face facing away from the carrier structure 350. A plurality of conductive bumps 701 are provided on the front face of the chip 300, and the conductive bumps 701 are soldered to the top surface of the carrier structure 350. Through the electrical connection between the conductive bumps 701 and the circuit layer in the carrier structure 350, control signals can be transmitted to the chip 300 or signals in the chip 300 can be led out. The distribution and number of the conductive bumps 701 can be optimized according to the pin layout and signal requirements of the chip 300 to achieve higher connection density and more flexible wiring. In this specific embodiment, the adhesive material 340 fills the gap between the chip 300 and the carrier structure 350 and completely fills the space between the conductive bumps 701.

[0095] During the operation of the semiconductor device, the chip 300 generates a large amount of heat due to high-frequency switching and current conduction in its internal circuit. To prevent this heat from affecting the performance of the chip 300, the heat needs to be dissipated in a timely manner. In some specific embodiments, the heat dissipation of the chip 300 is achieved by providing a heat sink cover. Specifically, as Figure 7 shown, the package structure further includes a heat sink cover 700, which is snapped onto the carrier structure 350 and forms a receiving cavity 710 with the carrier structure 350. The chip 300 is disposed in the receiving cavity 710, and the heat sink cover 700 is in direct or indirect contact with at least the surface of the chip 300 facing away from the carrier structure 350. In this specific embodiment, the heat sink cover 700 is fixed to the surface of the chip 300 facing away from the carrier structure 350 by a thermal conductive adhesive 720, and the heat sink cover 700 is in indirect contact with the surface of the chip 300 facing away from the carrier structure 350 through the thermal conductive adhesive 720; in some other specific embodiments, the heat sink cover 700 can also be directly attached to the surface of the chip 300 facing away from the carrier structure 350, and the heat sink cover 700 is in direct contact with the surface of the chip 300 facing away from the carrier structure 350. During the operation of the semiconductor device, the heat generated by the chip 300 is mainly transferred from the active region of the chip 300 to its back face by heat conduction, and then transferred to the heat sink cover 700 through the thermal conductive adhesive.

[0096] The heat dissipation cover 700 is usually made of a material with a high thermal conductivity (such as copper, aluminum, or ceramic composite). Its bottom is in close contact with the chip 300, and heat dissipation fins are designed on the top or connected to other heat dissipation structures (such as heat pipes or heat dissipation fans) to increase the heat dissipation surface area. The heat dissipation cover 700 quickly dissipates heat to the surrounding environment through heat convection and heat radiation, thereby effectively reducing the operating temperature of the chip 300 and ensuring its stability and reliability.

[0097] In this specific embodiment, the heat dissipation cover 700 has a concave configuration, which not only provides sufficient installation space for the chip 300 and other electronic components, but also enhances the mechanical stability and sealing of the overall structure through the close fit between the side wall of the heat dissipation cover 700 and the carrier structure 350. The side wall of the heat dissipation cover 700 is fixedly connected to the top surface of the carrier structure 350 through an adhesive layer 730. Through the setting of the adhesive layer 730, not only the fixation of the heat dissipation cover 700 is realized, but also the sealing of the accommodation cavity 710 can be realized to prevent external dust, moisture, or other pollutants from entering the accommodation cavity 710, improving the reliability and service life of the packaging structure.

[0098] In the above specific embodiment, when the chip 300 is flip-chip mounted on the top surface of the carrier structure 350, heat dissipation of the chip 300 is achieved by providing the heat dissipation cover on the surface of the chip 300 facing away from the carrier structure 350. If the adhesive material 340 climbs up to the surface of the chip 300 facing away from the carrier structure 350, it will prevent the contact between the surface of the chip 300 facing away from the carrier structure 350 and the heat dissipation cover, thereby affecting heat dissipation. The packaging structure provided by the specific embodiment of the present invention cleverly uses the glue repellent layer 360 to effectively control the climbing height of the adhesive material 340, preventing the adhesive material 340 from climbing up to the surface of the chip 300 facing away from the carrier structure 350, effectively ensuring the contact between the heat dissipation cover and the chip surface, and ensuring the heat dissipation performance of the packaging structure.

[0099] The packaging structure provided by the specific embodiment of the present invention cleverly uses the characteristics of the glue repellent layer to effectively control the climbing height of the adhesive material. The packaging structure can meet the requirements of semiconductor packaging specifications, improve the yield of the packaging structure, and effectively avoid the failure of the packaging structure caused by the adhesive material climbing up to the surface of the chip facing away from the carrier structure. The packaging structure of the present invention prevents mistakes from the source of the process, the packaging process is feasible, and the process operability is strong, which is conducive to popularization and application.

[0100] It should be noted that the terms "including" and "having" and their variants in the documents of the present invention are intended to cover non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context and can be used to describe a feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or features in a plural sense. The term "based on" can be understood as not necessarily aiming to express a set of exclusive factors, but instead, and also at least in part depending on the context, allowing for the existence of other factors that are not necessarily explicitly described. Additionally, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessarily confusing the concepts of the present invention. In each of the above embodiments, the emphasis of each embodiment is on the differences from other embodiments. For the same / similar parts among the embodiments, reference can be made to each other.

[0101] The above is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A packaging method, characterized in that, Comprising: Providing a wafer to be diced, the wafer to be diced including a plurality of chips, with a dicing lane between adjacent chips; Performing a first dicing along the dicing lane to form a cutting groove, the depth of the cutting groove being less than the thickness of the chips; Forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer being capable of separating the adhesive material; Performing a second dicing along the cutting groove to form a plurality of independent chips, the width of the cutting tool used in the second dicing being less than the width of the cutting tool used in the first dicing; Mounting the chips on a carrier structure using an adhesive material.

2. The encapsulation method according to claim 1, wherein In the step of performing the first dicing along the dicing lane, the depth of the cutting groove is 1 / 3 to 1 / 2 of the thickness of the chips.

3. The encapsulation method according to claim 1, wherein In the step of performing the first dicing along the dicing lane, the side wall of the cutting groove is a sloped side wall.

4. The encapsulation method according to claim 1, characterized in that In the step of performing the first dicing along the dicing lane, the side wall of the cutting groove is a vertical side wall.

5. The encapsulation method according to claim 1, wherein In the step of forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer covers the entire surface of the cutting groove.

6. The encapsulation method according to claim 1, wherein In the step of forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer covers the entire side wall of the cutting groove, and the bottom of the cutting groove is not covered by the glue-repellent layer.

7. The encapsulation method according to claim 1, wherein In the step of forming a glue-repellent layer on the surface of the cutting groove, the glue-repellent layer covers the upper part of the side wall of the cutting groove, and the bottom of the cutting groove and the lower part of the side wall of the cutting groove are not covered by the glue-repellent layer.

8. The encapsulation method according to claim 1, wherein The step of forming a glue-repellent layer on the surface of the cutting groove further includes: Spraying a glue-repellent material layer on the surface of the cutting groove; Baking and curing the glue-repellent material layer to form the glue-repellent layer.

9. The encapsulation method according to claim 1, wherein In the step of performing the second dicing along the cutting groove, the cutting tool used in the second dicing cuts along the center line of the cutting groove.

10. The encapsulation method according to claim 1, characterized in that, The step of mounting the chips on a carrier structure using an adhesive material further includes: Coating an adhesive material on the carrier structure; Fixing the chips on the adhesive material, the adhesive material being capable of climbing along the side walls of the chips and covering all or part of the surface of the area on the side walls of the chips where no glue-repellent layer is provided.

11. The encapsulation method according to claim 1, wherein In the step of mounting the chips on a carrier structure using an adhesive material, the chips are mounted upright on the carrier structure, and the surface of the chips facing away from the carrier structure has bonding pads, and the bonding pads are electrically connected to the carrier structure through leads.

12. The encapsulation method according to claim 11, wherein, The glue-repellent layer is a polyimide layer.

13. The encapsulation method according to claim 11, wherein After the step of mounting the chips on a carrier structure using an adhesive material, it further includes: encapsulating the chips to form an encapsulant, the encapsulant covering the surface of the carrier structure and encapsulating the chips, the adhesive material, and the leads.

14. The encapsulation method according to claim 1, wherein In the step of mounting the chips on a carrier structure using an adhesive material, the chips are mounted upside down on the carrier structure.

15. The encapsulation method according to claim 14, wherein The glue-repellent layer includes one or both of silicon oxide and silicon nitride.

16. The encapsulation method according to claim 14, wherein After the step of mounting the chips on a carrier structure using an adhesive material, it further includes: providing a heat dissipation cover, the heat dissipation cover being buckled on the carrier structure and forming a receiving cavity with the carrier structure, the chips being disposed in the receiving cavity, and the heat dissipation cover being in direct or indirect contact with at least the surface of the chips facing away from the carrier structure.

17. An encapsulation structure, characterized in that, Comprising: A carrier structure; The chip is fixed on the carrier structure through an adhesive material. The side wall of the chip includes a first region and a second region disposed above the first region. A glue-repellent layer covers all or part of the surface of the second region. The adhesive material also covers all or part of the surface of the side wall of the chip where the glue-repellent layer is not provided. Wherein, the width of the chip in the second region is smaller than the width of the chip in the first region.

18. The encapsulation structure according to claim 17, characterized in that, The depth of the second region is 1 / 3 to 1 / 2 of the thickness of the chip.

19. The encapsulation structure according to claim 17, wherein, In the second region, the side wall of the chip is a sloped side wall.

20. The encapsulation structure according to claim 17, wherein In the second region, the side wall of the chip is a bent side wall.

21. The encapsulation structure according to claim 17, wherein, The chip is mounted upright on the carrier structure. The surface of the chip facing away from the carrier structure has bonding pads, and the bonding pads are electrically connected to the carrier structure through leads. A plastic package covers the surface of the carrier structure and encapsulates the chip, the adhesive material, and the leads.

22. The encapsulation structure according to claim 21, wherein, The glue-repellent layer is a polyimide layer.

23. The encapsulation structure according to claim 17, wherein, The chip is flip-chip mounted on the carrier structure.

24. The encapsulation structure according to claim 23, wherein The glue-repellent layer includes one or both of silicon oxide and silicon nitride.

25. The encapsulation structure according to claim 23, wherein The packaging structure further includes a heat dissipation cover. The heat dissipation cover is snapped onto the carrier structure and forms a receiving cavity with the carrier structure. The chip is disposed in the receiving cavity, and the heat dissipation cover is in direct or indirect contact with at least the surface of the chip facing away from the carrier structure.

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