Power amplifier circuit, integrated circuit and high-frequency signal transmitting equipment

Abstract

The invention discloses a power amplifier circuit. The circuit comprises a driving power splitting phase shift stage unit, a space-time modulation control logic unit and a multi-channel power output stage unit. The driving power-splitting phase-shifting stage unit is used for carrying out power distribution and phase shifting on an input signal and generating a plurality of signal outputs with different phases; the multi-channel power output stage unit is provided with a plurality of input ports which are connected with signal output of the driving power splitting and phase shifting stage unit, and after each path of input signal is subjected to multi-stage modulation and amplification, multiple paths of output signals are superposed and combined to form a signal wave beam; and the space-time modulation control logic unit is used for generating a multi-channel switching signal for carrying out space-time modulation on the multi-stage modulation amplifier in the multi-channel power output stage unit.

Description

Technical Field

[0001] The present invention belongs to the technical fields of high-frequency signal processing and communication technology, and particularly relates to a power amplifier circuit, an integrated circuit, and a high-frequency signal transmitting device. Background Art

[0002] With the development of 5G and higher-frequency communication technologies, the application of the millimeter-wave (mm-Wave) band has gradually become one of the core technologies in wireless communication and radar systems. The millimeter-wave communication system has a relatively high bandwidth and transmission speed, and is particularly suitable for high-performance applications such as large-scale data transmission and low-latency communication. However, existing millimeter-wave transmitting systems face the following main problems under higher-order channel or constellation modulation (such as OFDM, 64-QAM, 256-QAM, etc.):

[0003] 1. Low power back-off efficiency: In current millimeter-wave systems, especially in 5G and later systems, the power back-off efficiency (PBO) is usually low. Especially when the peak-to-average power ratio (PAPR) is 7 to 9.5 dB, the PBO performance of the existing technology is insufficient to meet the requirements of efficient communication.

[0004] 2. Complex and inefficient radio frequency beamforming technology: Traditional beamforming technology separately processes baseband beamforming and radio frequency beamforming, resulting in increased system complexity and large matching errors and insertion losses during radio frequency beamforming.

[0005] 3. Serious harmonic pollution problem: When existing technologies perform millimeter-wave transmission, they often cannot effectively suppress high-order harmonics, resulting in low energy efficiency and degraded system performance.

[0006] 4. Complex phase control and power back-off control: Traditional power amplifier (PA) systems separate phase control and power back-off control, resulting in increased hardware complexity and difficulty in effectively optimizing the coupling relationship between the two.

[0007] 5. Poor system scalability: Existing technologies are difficult to achieve efficient and low-cost expansion in high-frequency bands and large-scale arrays.

[0008] Among them, one of the main challenges faced by millimeter-wave technology is the power back-off efficiency (PBO) problem. Especially when using higher-order channels or constellation modulation (such as OFDM, 64-QAM, 256-QAM, etc.), the peak-to-average power ratio (PAPR) of the signal is usually relatively high, which will cause the efficiency of the power amplifier to decrease when operating in the low-power region, and even lead to a sharp degradation of the system performance.

[0009] In addition, beamforming technology is also a key issue in millimeter-wave systems. Traditional beamforming methods are generally divided into baseband beamforming and radio-frequency (RF) beamforming. Although baseband beamforming can achieve good beam control through digital signal processing, it increases the complexity of the system and has high requirements for computing power and power consumption. RF beamforming often relies on precise phase modulation in the high-frequency band. However, due to possible matching errors and insertion losses during the phase modulation process, and the fact that traditional high-frequency beamforming devices (such as phase shifters) are bulky and inefficient, it is difficult to improve the system performance.

[0010] In addition to power efficiency and beamforming, the problem of harmonic suppression is also becoming increasingly serious in millimeter-wave transmission. In traditional power amplifier (PA) designs, especially during high-power transmission, the generation of high-order harmonics affects the linearity of the system, reduces the spectral efficiency, and may cause spectral pollution and cross-channel interference. Currently, most power amplifier designs fail to effectively control and suppress these harmonics, so their usability in high-frequency and high-linearity scenarios is limited. Summary of the Invention

[0011] One embodiment of the present disclosure provides a spatio-temporal direct digital beamforming power amplifier chip, which includes a power amplifier circuit. The circuit includes a driving power splitting and phase shifting stage unit, a spatio-temporal modulation control logic unit, and a multi-channel power output stage unit.

[0012] The driving power splitting and phase shifting stage unit is configured to perform power distribution and phase shifting on an input signal to generate multiple signal outputs with different phases.

[0013] The multi-channel power output stage unit has multiple input ports connected to the signal outputs of the driving power splitting and phase shifting stage unit. After the input signals of each path are modulated and amplified through multiple stages, the multi-path output signals are superimposed and combined to form a signal beam.

[0014] The spatio-temporal modulation control logic unit is configured to generate multi-channel switching signals for spatio-temporal modulation of the multi-stage modulation amplifiers in the multi-channel power output stage unit. Here, spatio-temporal modulation, "time" refers to the modulation and control of signals in the time series, and "space" is related to the propagation and distribution of signals in the physical space. The spatio-temporal modulation method dynamically adjusts the signals in two dimensions of time and space to achieve flexible control of signal characteristics such as signal power and beam direction, so as to meet different communication and signal processing requirements. Brief Description of the Drawings

[0015] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present invention will become readily understood. In the drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, where:

[0016] Figure 1 Schematic diagram of the spatial - temporal direct digital beamforming power amplifier circuit according to one embodiment of the present invention.

[0017] Figure 2 Schematic diagram of the drive power splitter - phase shifter stage circuit according to one embodiment of the present invention.

[0018] Figure 3 Schematic diagram of the spatio - temporal modulation control logic unit according to one embodiment of the present invention.

[0019] Figure 4 Schematic diagram of the multi - channel power output stage circuit according to one embodiment of the present invention.

[0020] Figure 5 Schematic diagram of the spatio - temporal modulation waveform according to one embodiment of the present invention.

[0021] Figure 6 Schematic diagram of the power amplifier chip layout according to one embodiment of the present invention. Detailed implementation manners

[0022] Regarding how to solve the problems of millimeter - wave communication systems, the existing ideas mainly focus on how to solve the above - mentioned problems through different circuit architectures and modulation methods. The following is an explanation of some existing solutions. 1. Traditional power back - off technology.

[0023] Most traditional power degradation methods optimize the operating state of the power amplifier (PA) separately. For example, technologies such as Doherty amplifier, Envelope Tracking, and Outphasing are used to improve the power - back - off efficiency (PBO).

[0024] The Doherty amplifier is an efficient radio - frequency power amplifier architecture. Through dynamic load modulation technology, it significantly improves the efficiency of the power amplifier when processing non - constant envelope signals (such as signals with high peak - to - average power ratio). Its core consists of a carrier amplifier and a peaking amplifier. At low input power, only the carrier amplifier works and the peaking amplifier is turned off to reduce static power consumption. As the input power increases, the peaking amplifier is gradually activated, and the load impedance of the carrier amplifier is adjusted through a load - pulling network to keep it always working in the high - efficiency region. When the signal reaches the peak power, the carrier amplifier and the peaking amplifier jointly amplify the output power to ensure high efficiency and linearity. The Doherty amplifier is widely used in wireless communication base stations, broadcast systems, and other high - frequency fields that need to process signals with high peak - to - average power ratio, and is one of the key technologies in modern power amplifier design.

[0025] Envelope Tracking (ET) is a technology that optimizes the efficiency of a power amplifier (PA) by dynamically adjusting its supply voltage, especially suitable for processing signals with large power fluctuations such as high Peak-to-Average Power Ratio (PAPR) signals (e.g., OFDM). Its working principle is to extract the envelope information from the input signal. The envelope represents the power variation of the signal and tracks this change in real time. Based on the extracted envelope signal, the envelope tracking system adjusts the supply voltage of the power amplifier through a DC-DC converter, making the output power of the power amplifier consistent with the envelope of the input signal. Specifically, when the signal power is low, the supply voltage of the power amplifier is also reduced, thus reducing energy consumption; while when the signal power increases, the supply voltage is correspondingly increased to ensure sufficient output power.

[0026] Outphasing is a power amplification technology that decomposes the input signal into two signals with equal amplitude but opposite phase, which are respectively transmitted to two power amplifiers for independent amplification, and then the two amplified signals are recombined to generate the final output signal. The key of this technology is to use phase modulation so that the two power amplifiers can work simultaneously in the high-efficiency working range, thereby improving the overall efficiency of the system. Specifically, the two components after signal decomposition are opposite in phase. They are respectively processed by two amplifiers during the amplification process, and the output powers are finally combined. The outphasing technology can effectively reduce the energy waste of the power amplifier at low power output. Especially in the processing of high Peak-to-Average Power Ratio (PAPR) signals, it can improve the efficiency while weighing the signal linearity.

[0027] 2. Separate Phase and Power Control Technology.

[0028] Existing millimeter-wave systems generally adopt separate phase control and power degradation control. Specifically, phase control is achieved by using radio frequency components such as phase shifters, power dividers, and variable gain amplifiers, while power back-off control usually relies on adjusting the working range of the power amplifier or radio frequency gain to control efficiency. Under this technical architecture, the optimization of beamforming and power back-off is often carried out independently, resulting in a relatively high system complexity.

[0029] 3. Digital Beamforming (DBF) Technology.

[0030] This is a technology that independently controls the phase and amplitude of multiple antenna elements through Digital Signal Processing (DSP) to form a directional beam. Its basic principle is to digitally process the signals transmitted by each antenna element, precisely adjust the phase and amplitude of each signal, thereby controlling the direction and shape of the beam. The specific implementation process is as follows:

[0031] First, the received or transmitted signals are sampled and digitized, and the signals received by each antenna element are processed independently. Then, a digital signal processor (DSP) or other processing unit adjusts the amplitude and phase of the signals of each antenna element according to the preset beam direction and shape. In this way, the signals of all antenna elements are coherently superimposed in space to form a directional beam that can point to a specific receiver or coverage area. Different from traditional analog beamforming, digital beamforming does not rely on analog hardware circuits for phase adjustment, but precisely calculates through software algorithms, providing higher beam control accuracy and flexibility to adapt to various complex communication environments.

[0032] 4. Harmonic suppression technology.

[0033] Traditional power amplifier designs usually rely on radio frequency devices such as linearity optimization designs, filters, or resonator cavities to suppress harmonics. However, these devices not only occupy a large amount of layout area, which is not conducive to cost control, but also usually have large insertion losses when operating in the high-frequency band, and have limited suppression effects on high-order harmonics. These methods are usually complex and difficult to achieve large-scale integration.

[0034] To solve the above problems, the present disclosure proposes a spatial-time direct digital beamforming power amplifier chip design scheme.

[0035] According to one or more embodiments, as Figure 1 shown, the hardware principle architecture of the embodiments of the present disclosure is as Figure 1 shown. The entire chip consists of three parts: a driving power splitting and phase shifting stage, a spatio-temporal modulation control logic unit, and a multi-channel power output stage. Among them,

[0036] Driving power splitting and phase shifting stage: Differential amplifies the input high-frequency signal and preliminarily amplifies it, and generates multiple driving channel outputs with different phases through a passive or active power distribution and phase shifting network.

[0037] Spatio-temporal modulation control logic unit: According to the input specific modulation code pattern signal and control signal, generates multi-channel switch signals for spatio-temporal modulation ([[]] Figure 1 taking four channels as an example in [[[]]), and determines the power back-off and beamforming of the entire array.

[0038] Multi-channel power output stage: Includes multiple amplification channels ([[]] Figure 1 taking four channels as an example in [[[]]). The input ends of each branch receive the driving output high-frequency signals with different phases from the driving power splitting and phase shifting stage, and increase the modulation switch ratio through multi-stage modulated power amplifiers ([[]] Figure 1 taking N stages as an example in [[[]]) in each branch, and finally realizes the modulated amplification output of the high-frequency signal.

[0039] Bias circuit: In the drive power splitter phase shifter stage and the multi-channel power output stage, the bias circuit unit is used to provide a suitable operating point for the transistors in the amplifier, ensuring the stability of the gain with respect to temperature.

[0040] The signal flow when the chip circuit of the present disclosure embodiment operates is as follows:

[0041] Millimeter-wave or terahertz signals are input into the chip from the left drive input port of the drive power splitter phase shifter stage, converted into differential signals by the input matching network and enter the drive differential amplifier. Under the action of the power splitting and phase shifting network, multiple channel drive output high-frequency signals with different phases are generated. Each channel drive output signal is respectively input into the input ports of each branch of the multi-channel power output stage, enters the multi-stage modulation power amplifier through the drive matching network, is amplified, and time-space modulation is applied by the modulation switches of each stage of the amplifier. Finally, the waveform signal is output from the output ports of each branch through the output matching network. The modulation switch signals of each stage of the amplifier in each channel branch are provided by the time-space modulation control logic unit. The specific modulation code pattern signals that determine the power back-off and beamforming are input serially from the modulation waveform serial input port. The modulation mode control signal generates corresponding chip select and enable signals inside the logic unit, and cooperates with the input clock signal to generate multi-channel switch signals for time-space modulation. These signals are distributed to the modulation switches of the multi-stage modulation power amplifiers in the multi-channel power output stage.

[0042] In the present disclosure embodiment,

[0043] The drive power splitter phase shifter stage unit first converts the input millimeter-wave or terahertz signal into a differential signal through the input matching network, and then enters the drive differential amplifier. Under the action of the power splitting and phase shifting network, multiple channel drive output high-frequency signals with different phases are generated. Here, the comprehensive meaning of "drive power splitter phase shifter stage" can be understood as "drive power distribution and phase shifting stage". The main function of this stage is to perform preliminary amplification, power distribution, and phase adjustment on the input high-frequency signal for subsequent power amplification and signal modulation.

[0044] The spatio-temporal modulation control logic unit generates multi-channel switching signals for spatio-temporal modulation under the drive of a clock signal based on the input specific modulation pattern signal and control signal. These signals determine the power back-off and beamforming of the entire array. The modulation mode control signal generates corresponding chip select and enable signals inside the logic unit, and cooperates with the input clock signal to generate multi-channel switching signals for spatio-temporal modulation. The specific modulation pattern signal mentioned here can adopt the form of square-wave switching modulation: the power back-off control is determined by the duty cycle of the periodic square-wave signal; the multi-channel harmonic suppression is determined by the phase difference between the modulation waveforms of channels; the signal phase shift and beamforming are determined by the relative time delay of the overall modulation signal. Therefore, the meaning of the specific modulation pattern signal is a set of modulation patterns with a duty cycle corresponding to the required power back-off, the phase difference between channels satisfying the harmonic suppression relationship, and an overall time delay corresponding to the required phase shift and beamforming angle.

[0045] Here, spatio-temporal modulation is to modulate the signal in two dimensions of time and space and is used in a digital beamforming system, that is, to affect the formation of the beam and the transmission characteristics of the signal by controlling the distribution of the signal in time and space. Specifically, the multi-channel switching signals generated by the spatio-temporal modulation control logic unit are distributed to the modulation switches of the multi-stage modulation power amplifiers in the multi-channel power output stage, so as to realize the modulated amplification output of the signal. In this way, precise control of the signal can be achieved, including the direction, shape, and intensity of the beam, etc., to adapt to different communication requirements and environmental conditions.

[0046] In the multi-channel power output stage unit, the drive output signals of each channel are respectively input into the input ports of each branch of the multi-channel power output stage, enter the multi-stage modulation power amplifier through the drive matching network and are amplified. The modulation switches of each stage of the amplifier apply spatio-temporal modulation, and the final waveform signal is output from the output ports of each branch through the output matching network. The modulation switch signals of each stage of the amplifier in each channel branch are provided by the spatio-temporal modulation control logic unit.

[0047] According to one or more embodiments, a spatial-time direct digital beamforming power amplifier chip circuit architecture includes: a drive power splitting and phase shifting stage unit, a spatio-temporal modulation control logic unit, and a multi-channel power output stage unit. Among them,

[0048] 1. The drive power splitting and phase shifting stage unit sequentially includes an input matching circuit, a drive differential amplifier, a bias circuit, a drive power splitting circuit, and a phase shift network circuit.

[0049] Input matching circuit: responsible for impedance matching of the input high-frequency signal to maximize the power transmission efficiency and minimize reflection.

[0050] Bias circuit: provides a suitable DC bias voltage for the drive differential amplifier.

[0051] Drive power splitter circuit: preliminarily amplify the input high-frequency signal to provide sufficient drive level for subsequent power amplification.

[0052] Phase shift network circuit: used to adjust the phase of the signal to achieve phase synchronization between different channels or a specific phase difference.

[0053] 2. Space-time modulation control logic unit, including a digital control logic unit, which generates multi-channel modulation switch signals for space-time modulation according to the input modulation waveform serial input, clock signal, and modulation mode control signal.

[0054] 3. Multi-channel power output stage unit, including multiple branch input-output circuits, and each branch input-output circuit includes a drive matching circuit, a first modulation switch, a multi-stage modulation power amplifier, a bias circuit, a second modulation switch, and an output matching circuit.

[0055] Drive matching circuit: match the signal from the drive power splitter and phase shift stage to meet the input requirements of the subsequent power amplifier. Here, the drive matching can adopt balun matching.

[0056] Bias circuit: provide a suitable DC bias voltage for the modulation power amplifier.

[0057] Output matching circuit: ensure that the amplified signal can be effectively coupled to the transmission line to minimize transmission loss.

[0058] The signal enters the drive power splitter and phase shift stage from the left, is converted into a differential signal by the input matching network, and enters the drive differential amplifier. Under the action of the drive power splitter and phase shift network, multiple-channel drive output high-frequency signals with different phases are generated. These signals are respectively input to the input ports of each branch of the multi-channel power output stage, enter the multi-stage modulation power amplifier through the drive matching network, are amplified and subjected to space-time modulation, and finally the waveform signal is output from the output ports of each branch by the output matching network.

[0059] The modulation switch signals of each stage of the amplifier in each channel branch are provided by the space-time modulation control logic unit. The specific modulation code pattern signals that determine power back-off and beamforming are input serially from the modulation waveform serial input port. The modulation mode control signal generates corresponding chip select and enable signals inside the logic unit, and cooperates with the input clock signal to generate multi-channel switch signals for space-time modulation. These signals are distributed to the modulation switches of the multi-stage modulation power amplifiers in the multi-channel power output stage.

[0060] Such as Figure 2The shown driving power splitting and phase shifting stage circuit. The input port RFin of the driving power splitting and phase shifting stage is the driving input terminal, and the input matching structure is a balun matching structure that can provide a center-tapped bias. The differential driving amplifier is a differential structure with an adjustable emitter current source bias, and there is a cross-connected neutralizing capacitor structure between the collector and the base. The amplified signals RF + and RF - enter the matching phase shifting network in a fully differential form to generate four quadrature phase driving branch channels of 0°, 90°, 180°, and 270°. The matching phase shifting network adopts the form of a coupler. The driving power splitting and phase shifting stage circuit includes,

[0061] Input matching structure: This input matching structure circuit is located at the very front end of the driving power splitting and phase shifting stage. Its main function is to achieve impedance matching between the input port RFin and the subsequent circuit. The input port Rfin is connected to this input matching structure. The input matching structure adopts a balun matching structure. Balun matching is a commonly used matching network that can provide a center-tapped bias, optimize impedance matching, reduce signal reflection, and improve power transmission efficiency.

[0062] Differential driving amplifier: It includes a pair of bipolar transistors M2 that form a differential structure. The two output terminals of the input matching structure circuit are respectively connected to the bases of this pair of differential bipolar transistors through a resistor R1. The two emitters of this pair of differential bipolar transistors are short-circuited and then connected to a bias current source. The bias current source is composed of a pair of transistors. The bases of these two transistors M1 are connected in parallel, the emitters are connected in parallel and then grounded, and the collectors are connected in parallel and then connected to the emitter of the differential driving amplifier. After the collectors of the differential driving amplifier are respectively cross-connected with a capacitor C1, these two capacitors C1 are respectively connected to the bases of the opposite bipolar transistors in the differential bipolar transistor pair.

[0063] Matching phase shifting network circuit: It is connected to a pair of collector output terminals of the differential driving amplifier to adjust the phase of the amplified radio frequency signal and generate multiple driving branch channels with different phases (0°, 90°, 180°, 270°). The signals RF+ and RF- enter the matching phase shifting network in a fully differential form, which helps to maintain the integrity and anti-interference ability of the signal. The matching phase shifting network adopts the form of a coupler and includes a differential transformer matching structure arranged between the differential driving amplifier and the coupler. In the matching phase shifting network, the functions of the coupler include: signal distribution and phase control, impedance matching, and enhanced anti-interference ability. Through the fully differential signal input (RF+ and RF-), the coupler can effectively suppress common-mode interference while maintaining the integrity and stability of the signal.

[0064] Output port circuit: The signals that have been amplified and phase-shifted are output from each output port to drive the subsequent power amplification stage.

[0065] As shown Figure 3 in the figure, it is the single-channel schematic diagram in the spatio-temporal modulation control logic unit. The input modulation waveform is serially input from the DATAin port and stored in the 24-bit register. The combinational logic part is responsible for controlling the reading and output of the waveform and the switching of the working state. The clock signal is input from the Clk port, driving the clock tree and pushing the shift register to output the starting modulation signal from the SW data out port. The calculation method of the spatio-temporal modulation waveform is as follows:

[0066] The mathematical expression of the switching modulation waveform adopted by each channel is: a periodic square wave function with a minimum value of 0, a maximum value of 1, a waveform width of τ, a period of T, and an initial time delay of t n , where n is the serial number of the channel. The exponential Fourier series expansion of this switching modulation signal is:

[0067]

[0068] In this expansion, m represents the harmonic order. In this expansion, the power of each harmonic is determined by the duty cycle τ / T of the waveform width, and the power back-off can be accurately adjusted by changing τ. In this expansion, the phase factor of each harmonic of each channel is determined by the initial time delay t n of the modulation waveform of the channel. By changing t n , the phase difference between different channels can be controlled, and the elimination of irrelevant harmonics and the retention of the first-order main harmonic can be achieved. After the eight-channel harmonic suppression modulation, the complex amplitude of the retained first-order main harmonic can be expressed as:

[0069]

[0070] In this expansion, the overall phase factor of the first-order main harmonic of the nth channel is determined by the overall time delay t n of the modulation waveform of this channel. By changing t n , phase shift, phased array formation, and beamforming can be performed.

[0071] The principle of the above spatio-temporal modulation waveform calculation method is explained as follows.

[0072] 1. A periodic square wave signal with a certain duty cycle can be Fourier decomposed. The fundamental harmonic coefficient determines the power back-off and is controlled and adjusted by the duty cycle;

[0073] 2. Multi-channel modulation signals with phase differences can generate high-order harmonics with different phases. Modulating them to high frequencies and then adding them together can eliminate harmonic interference and retain the first-order main signal. The phase difference between channels is related to the order of harmonic elimination and the number of channels;

[0074] 3. Phase and beamforming control are determined by the overall time delay of the modulation waveform.

[0075] In terms of the implementation principle of the hardware circuit:

[0076] 1. The control signal controls the combinational logic circuit and the register bank to work in the read-in gear, and serially inputs the 24-bit pre-adjusted code type that meets the above three conditions from the Data In port into the on-chip register;

[0077] 2. After the read-in is completed, the control signal controls the combinational logic and the register bank to work in the output state. The Clk port inputs the clock, which reaches each register port under the distribution of the clock tree. Every time the clock flips, the cyclic shift register bank moves 1 bit and generates 1 bit of output;

[0078] 3. The output signal passes through the output driver and goes to the modulation switches of each modulation channel.

[0079] Figure 3 The Chinese explanations of the English terms involved are as follows.

[0080] Combinational Logic - Combinational Logic

[0081] Clock Tree - Clock Tree

[0082] Output Driver - Output Driver

[0083] Data In - Data Input

[0084] Control - Control

[0085] Clk - Clock

[0086] SW data out - Serial waveform data output.

[0087] Figure 3 The circuit in realizes precise signal modulation and output through a series of logic components and timing controls. Among them, the combinational logic circuit part is responsible for controlling the logical operations of the entire modulation process, including waveform read-in, output, and working state switching. The clock tree is responsible for distributing the clock signal (Clk) to each part of the circuit to ensure that all operations are synchronized. The output driver is responsible for driving the processed signal from the data output port (SW data out) to the external load or subsequent circuit.

[0088] As Figure 4 shown, it is the schematic diagram of a single-channel power amplifier link in the multi-channel power output stage. Multistage modulation amplifier( Figure 4Taking two - stage as an example, the inter - stage matching adopts the form of a transformer (Transformer), and the drive - stage matching and output matching adopt the form of a balun. This schematic diagram takes a two - stage modulated power amplifier as an example. Both of them adopt a differential structure with a switched emitter current - source bias, and there is a cross - connected neutralizing capacitor structure between the collector and the base. The switched modulation signal is input from the base of the current source.

[0089] The single - channel power amplifier link in the multi - channel power output stage includes multiple - stage modulated amplifiers. Figure 4 The multi - stage differential time - modulation amplifier in it consists of two stages. The inter - stage matching adopts the form of a transformer (Transformer). The transformer not only plays the role of impedance matching but also can realize power transfer and isolation between different amplification stages. The drive - stage matching and output matching adopt the form of a balun (Balun).

[0090] Each stage of the differential time - modulation amplifier also adopts an amplifier with a differential structure. Both of the two - stage amplifiers adopt a differential structure with a switched emitter current - source bias. The transistor pair of the differential amplifier has a cross - connected neutralizing capacitor structure between the collector and the base. This structure helps to realize the cross - coupling of signals, improve the bandwidth and efficiency of the amplifier. And the switched modulation signal is input from the base of the current source.

[0091] Differential time - modulation power amplifier: It includes a pair of transistors M2 forming a differential structure. The two output terminals of the input - matching structure circuit are respectively connected to the bases of this pair of differential transistors through a resistor R1. The two emitters of this pair of differential transistors are short - circuited and then connected to a bias current source. The bias current source consists of a pair of transistors. The bases of these two transistors M1 are connected in parallel and then connected to the modulation switch. The emitters are connected in parallel and then grounded. The collectors are connected in parallel and then connected to the emitter of the differential drive amplifier. After the collectors of the differential drive amplifier are respectively cross - connected with a capacitor C1, these two capacitors C1 are respectively connected to the bases of the opposite transistors in the differential transistor pair. The bases of the two transistors M1 of the first - stage amplifier are connected in parallel and then connected to the first modulation switch. The bases of the two transistors M1 of the second - stage amplifier are connected in parallel and then connected to the second modulation switch.

[0092] The input high - frequency signal is first amplified by the first - stage amplifier and then transmitted to the second - stage amplifier through a transformer for further amplification. In each stage of the amplifier, the switched modulation signal controls the current of the emitter to realize the modulation of the input signal. The signal after two - stage amplification and modulation is finally transmitted to the load or antenna through the output - matching network.

[0093] As Figure 5 shown, it is the design of the spatio - temporal modulation waveform for each channel of the multi - channel power output stage generated by the spatio - temporal modulation control logic unit. Among them,

[0094] Sub - figure (a) shows the spatio - temporal modulation waveform required to achieve harmonic suppression for a total of eight channels (two transmitting groups) with a duty cycle of τ.

[0095] Sub - figure (b) shows the spatio - temporal modulation waveform required to maintain harmonic suppression in a 3 dB power - back - off state with a duty cycle of τ / 2.

[0096] Sub - figure (c) shows the spatio - temporal modulation waveform required to achieve 0° beamforming and maintain harmonic suppression for two transmitting groups with a duty cycle of τ.

[0097] Sub - figure (d) shows the spatio - temporal modulation waveform required to achieve 30° beamforming and maintain harmonic suppression for two transmitting groups with a duty cycle of τ.

[0098] When different channels in the multi - channel power output stage are applied with Figure 5 the modulation waveforms shown for each channel, the relative time delay between channels can make the modulated high - frequency signals carry different phases, achieving harmonic cancellation of the corresponding order. The higher the duty cycle of the switching waveform for each channel, the higher the average output power, so power back - off can be controlled. Taking a group of 4 channels as an example, the relative time delay between groups can control the relative phase between different groups, achieving phase control and beamforming.

[0099] This series of waveforms can be generated by the on - chip spatio - temporal modulation control logic unit or injected externally. Its design principle is to control the duty cycle and time delay, and the waveform design under corresponding conditions is marked in each sub - figure.

[0100] Figure 5 Shown are the spatio - temporal modulation waveforms for each channel designed by the spatio - temporal modulation control logic unit for the multi - channel power output stage. These waveforms are used to achieve harmonic suppression and power back - off in a multi - channel system to optimize the signal transmission quality and efficiency. In the multi - channel power output stage, by applying different spatio - temporal modulation waveforms, the relative time delay between channels is achieved, making the modulated high - frequency signals carry different phases, thus achieving harmonic cancellation of the corresponding order.

[0101] As Figure 6 shown, the layout of the space - time direct digital beamforming power amplifier chip in the millimeter - wave band constructed in this disclosure integrates a driver power - dividing phase - shifting stage, a spatio - temporal modulation control logic unit, a multi - channel power output stage (four channels), and an on - chip PTAT bias circuit on a single chip. Figure 6 The Chinese explanations of the English terms in

[0102] Driver Amplifier - - Driver amplifier

[0103] Passive Phase Network - - Passive phase - shift network

[0104] Digital Unit - Digital Unit

[0105] 4-Channel Tx TMAPA - 4-Channel Transmit (Tx) Time Modulated Array (TMA) Power Amplifier (PA)

[0106] Figure 6 It is a layout design of a space-time direct digital beamforming (STDBF) power amplifier chip in the millimeter-wave band. This chip integrates multiple key functional modules for efficient millimeter-wave signal transmission and beamforming. The driver amplifier is used to amplify the input high-frequency signal, and the passive phase-shift network is used to adjust the phase of the signal to ensure the correct phase relationship between signals in different channels. The digital unit includes digital control logic and signal processing circuits for generating control signals and processing input signals to achieve spatio-temporal modulation functions, including generating modulation waveforms and controlling the switching states of power amplifiers. The 4-Channel Transmit Time Modulated Array Power Amplifier (4-Channel Tx TMAPA) includes four independent power amplification channels, and each channel is responsible for amplifying one signal. The time modulation array (TMA) technology is adopted to achieve precise beamforming and beam shaping. The on-chip PTAT (Phase Truth Table) bias circuit is used to precisely control the phase and achieve fine-tuning of the phase inside the chip.

[0107] Summarizing the embodiments of the present disclosure, the space-time direct digital beamforming power amplifier circuit involved in the present disclosure has the following technical characteristics:

[0108] 1. The present disclosure creates a new degree of freedom for back-off efficiency optimization, which can be combined with existing mature high back-off efficiency technologies for further improvement on the basis of existing technologies, and has strong scalability. Specifically:

[0109] Digital switching modulation of multi-channel amplifiers is one of the key features of the present disclosure. Achieving power back-off through duty cycle adjustment is the key method of the solution of the present disclosure, and the present disclosure does not limit the type of power amplifier. Engineers with relevant industry experience can perform digital switching modulation on various types of amplifiers based on the same principle as the present disclosure and achieve power back-off through duty cycle adjustment.

[0110] 2. The present disclosure has made theoretical innovations in digital spatio-temporal modulation for full functions of power back-off, harmonic elimination, phase adjustment, and beam shaping. While integrating various functions, it simplifies the digital modulation scheme and improves the modulation depth. Specifically,

[0111] One of the key features of the present disclosure is a multi-channel power output stage for power back-off, harmonic cancellation, phase adjustment, and beamforming. The key method of the present disclosure is to achieve harmonic cancellation, phase adjustment, and beamforming through the adjustment of relative time delays between channels or between channel groups. Inter-channel harmonic cancellation and duty cycle adjustment for power back-off are two independent design dimensions, which are respectively two steps in the modulation waveform design. The present disclosure does not limit the number of channels of the multi-channel power output stage. Engineers with relevant industry experience can increase or decrease the number of channels of the multi-channel power output stage, but all may rely on the power back-off, harmonic cancellation, phase adjustment, and beamforming principles proposed by the present disclosure.

[0112] 3. The present disclosure adopts a specific digital waveform design of spatio-temporal modulation. This series of waveforms can be generated by an on-chip spatio-temporal modulation control logic unit or injected externally. Its design principle is to control the duty cycle and relative time delay.

[0113] 4. The combination of the digital control unit and the power transmission unit in the present disclosure simplifies the system structure and reduces the chip cost.

[0114] Therefore, by deeply analyzing the defects of the existing solutions, the beneficial effects of the present disclosure can be further understood, including:

[0115] 1. Analyzing the power back-off technology, most traditional power degradation methods improve the power back-off efficiency (PBO) by separately optimizing the operating state of the power amplifier (PA), such as using technologies like Doherty amplifiers, Envelope Tracking, and Outphasing. Specifically:

[0116] The impedance tuning of Doherty amplifiers is complex, with limited bandwidth and linearity, and it is difficult to guarantee the beamforming phase error. Envelope Tracking is bulky and not convenient for integration, and the synchronization of envelope detection and power supply regulation is poor. Outphasing technology poses high requirements for high-frequency phase adjustment and error control, and there are great challenges in optimizing high-frequency linearity and bandwidth. Generally speaking, although these methods are effective, they usually can only solve a single problem (such as PBO efficiency), and it is difficult to balance various requirements in the system, such as beamforming and harmonic suppression. The integration ability between different technologies is poor, and functional expansion brings greater hardware overhead.

[0117] In response to this, the present disclosure constructs a new degree of freedom for power back-off, which is compatible with existing mature technologies and further improves the power back-off efficiency of existing technologies. While achieving power back-off, it ensures the consistency of the amplifier operating state, and can balance phase adjustment, beamforming, and harmonic suppression through waveform design.

[0118] 2. Existing millimeter-wave systems generally adopt discrete phase control and power degradation control. Specifically, phase control is achieved by using radio frequency components such as phase shifters, power dividers, variable gain amplifiers, etc., while power back-off control usually relies on adjusting the operating range of the power amplifier or radio frequency gain to control efficiency. Under this technical architecture, the optimization of beamforming and power back-off is often carried out independently, resulting in a relatively high system complexity.

[0119] In response to this, the present disclosure enables the high-frequency array to get rid of the limitations of high-frequency phase shifters and digital phase shifters, and can be directly completed by the transmit power amplifier, realizing the integration of phase and power control technologies. It greatly simplifies the transmitter architecture and improves scalability and robustness.

[0120] 3. For digital control beamforming technology, existing research attempts to optimize beamforming through direct digital control. For example, digital beamforming can reduce the complexity of radio frequency control hardware to achieve digital control of phase. The advantage of this type of method is that it optimizes the phase control scheme and improves flexibility and applicability, but the digital control architecture is too complex, the control unit is separated from the power unit, the structure is large, and there are problems such as harmonic pollution and low power back-off efficiency, especially in applications in high-frequency (such as 24 GHz, 77 GHz, 94 GHz, and terahertz) frequency bands.

[0121] In response to this, the present disclosure enables the high-frequency beamforming array to get rid of the limitations of complex digital control logic and separate power modules, and can directly complete the spatio-temporal modulation of digital control by the transmit power amplifier, realizing all-digital phase and power control technology.

[0122] 4. Traditional power amplifier designs usually rely on linearity optimization designs, radio frequency devices such as filters or resonator cavities to suppress harmonics, but these devices not only occupy a large amount of layout area, which is not conducive to cost control, but also usually have large insertion losses when operating in high-frequency bands, and the suppression effect on high-order harmonics is limited. These methods are usually complex and difficult to achieve large-scale integration.

[0123] The present disclosure effectively suppresses high-order harmonic pollution through the design of digital modulation waveforms, thus providing a new and efficient solution for high-frequency millimeter-wave communication systems.

[0124] In summary, the spatio-temporal direct digital beamforming power amplifier chip proposed in the present disclosure integrates phase control and power degradation control in the same system, and uses time as an additional degree of freedom for adjustment, thereby overcoming the defects of existing solutions. The present disclosure realizes high power back-off efficiency, effective harmonic suppression, simplified beamforming operation, and phase adjustment through direct digital control, thereby reducing system complexity and improving overall performance and scalability. Specifically, it realizes:

[0125] 1. The combination of the digital control unit and the power transmission unit simplifies the system structure and reduces the chip cost; 2. An innovation in the digital spatio-temporal modulation theory with full functions of power back-off, harmonic elimination, phase adjustment, and beamforming is carried out. While integrating various functions, the digital modulation scheme is simplified and the modulation depth is improved; 3. The present disclosure creates a new degree of freedom for optimizing the back-off efficiency, which can be combined with existing mature high-back-off efficiency technologies to further improve on the existing technology, and has strong scalability.

[0126] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0127] It is worth noting that although the foregoing has described the spirit and principle of the present invention with reference to several specific embodiments, it should be understood that the present invention is not limited to the specific embodiments disclosed, and the division of each aspect does not mean that the features in these aspects cannot be combined. This division is only for the convenience of expression. The present invention aims to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A power amplifier circuit, characterized in that, The circuit includes a driving power dividing and phase shifting stage unit, a spatio-temporal modulation control logic unit, and a multi-channel power output stage unit. The driving power dividing and phase shifting stage unit is used to perform power distribution and phase shifting on the input signal, and generate multiple signal outputs with different phases. The multi-channel power output stage unit has multiple input ports connected to the signal outputs of the driving power dividing and phase shifting stage unit. After the input signals of each path are amplified through multiple stages of modulation, the multi-path output signals are superimposed and combined to form a signal beam. The spatio-temporal modulation control logic unit is used to generate multi-channel switching signals for spatio-temporal modulation of the multi-stage modulation amplifiers in the multi-channel power output stage unit.

2. The power amplifier circuit according to claim 1, wherein The driving power dividing and phase shifting stage unit sequentially includes an input matching circuit, a driving differential amplifier, a first bias circuit, a driving power dividing circuit, and a phase shift network circuit. The input matching circuit performs impedance matching on the input signal. The first bias circuit provides a DC bias voltage or current for the driving differential amplifier, and the driving power dividing circuit preliminarily amplifies the input signal. The phase shift network circuit is used to adjust the phase of the signal.

3. The power amplifier circuit according to claim 1, wherein The spatio-temporal modulation control logic unit, through a digital control logic circuit, generates multi-channel modulation switching signals for spatio-temporal modulation according to the input modulation waveform serial input, clock signal, and modulation mode control signal.

4. The power amplifier circuit according to claim 3, wherein, The multi-channel power output stage unit includes multiple branch input-output circuits. Each branch input-output circuit includes a driving matching circuit, a multi-stage modulation power amplifier, a multi-stage modulation switch, an inter-stage matching circuit, a second bias circuit, and an output matching circuit connected in sequence. Among them, The driving matching circuit matches the signal from the driving power dividing and phase shifting stage, and the multi-stage modulation switch is connected to the corresponding modulation power amplifier. The inter-stage matching circuit connects the outputs and inputs of the modulation power amplifiers at each stage. The second bias circuit provides a DC bias voltage or current for the modulation power amplifier, and the output matching circuit capacitively couples the amplified signal to the transmission line antenna unit.

5. The power amplifier circuit according to claim 4, wherein The spatio-temporal modulation control logic unit realizes the switching modulation of the multi-stage and multi-channel power amplifiers through an array of switches composed of multi-stage modulation switches by adjusting the duty cycle of the input signal.

6. The power amplifier circuit according to claim 5, wherein The spatio-temporal modulation control logic unit adjusts to achieve harmonic cancellation, phase adjustment, and / or beamforming of the output signal through the relative time delay between different branch channels or within the same branch channel group.

7. An integrated circuit, characterized in that, It includes a power amplifier circuit, which includes a driving power dividing and phase shifting stage unit, a spatio-temporal modulation control logic unit. The driving power dividing and phase shifting stage unit is used to perform power distribution and phase shifting on the input signal, and generate multiple signal outputs with different phases. The multi-channel power output stage unit has multiple input ports connected to the signal outputs of the driving power dividing and phase shifting stage unit. After the input signals of each path are amplified through multiple stages of modulation, the multi-path output signals are superimposed and combined to form a signal beam.

8. The integrated circuit according to claim 7, characterized in that, The power amplifier circuit further includes a spatio-temporal modulation control logic unit. The spatio-temporal modulation control logic unit is configured to generate multi-channel switching signals for spatio-temporal modulation of the multi-stage modulation amplifiers in the multi-channel power output stage unit.

9. A high-frequency signal transmitting device, characterized in that, The device includes the integrated circuit as claimed in claim 7.

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