Clock synchronization method and device, communication equipment and storage medium

Abstract

The invention discloses a clock synchronization method and device, communication equipment and a storage medium. The method comprises the following steps: a first node sends a first synchronization signal, the first synchronization signal is received by a second node, and the first synchronization signal is used for the second node to obtain a first propagation time delay; the first node receives a second synchronization signal from the second node, obtains a second propagation time delay based on the second synchronization signal, and sends the second propagation time delay to network equipment, and the first synchronization signal and the second synchronization signal are reflected by a target in the transmission process.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to a clock synchronization method, apparatus, communication device, and storage medium based on base stations. Background Art

[0002] Integrated communication and sensing is mainly divided into independent sensing and cooperative sensing. Cooperative sensing refers to a working mode in which the sensing signals sent by sensing nodes are received by one or more other sensing nodes after being reflected by a target, and then through further information processing and information interaction between nodes, etc., the environmental sensing between the sending and receiving nodes is completed. The core of cooperative sensing is to maintain clock synchronization and frequency synchronization between multiple nodes.

[0003] Current clock synchronization often adopts methods such as satellite synchronization or clock synchronization protocols (such as IEEE 1588V2). However, the satellite synchronization method has an error of 4.5 - 9 meters (m) (equivalent to 50 - 100 nanoseconds (ns)), and the clock synchronization protocol method has an error of 300 m (equivalent to 1 microsecond (μs)). The above methods cannot meet the high-precision sensing requirements of current application scenarios such as communication and sensing drones and vehicles. Summary of the Invention

[0004] To solve the existing technical problems, embodiments of the present invention provide a clock synchronization method, apparatus, communication device, and storage medium.

[0005] To achieve the above object, the technical solution of the embodiments of the present invention is implemented as follows:

[0006] Embodiments of the present invention provide a clock synchronization method, the method including: a first node sending a first synchronization signal, wherein the first synchronization signal is received by a second node, and the first synchronization signal is used for the second node to obtain a first propagation delay;

[0007] The first node receives a second synchronization signal from the second node, obtains a second propagation delay based on the second synchronization signal, and sends the second propagation delay to a network device, wherein both the first synchronization signal and the second synchronization signal are reflected by a target during the transmission process.

[0008] In the above solution, the first synchronization signal and the second synchronization signal are in the same time slot; or, the first synchronization signal and the second synchronization signal are in different time slots.

[0009] In the above solution, when the first synchronization signal and the second synchronization signal are in the same time slot, the first synchronization signal is transmitted in the first symbol within the time slot, and the first symbol is N symbols starting from the last downlink symbol within the time slot and moving from right to left, where N is a positive integer; and / or, the second synchronization signal is transmitted in the second symbol within the time slot, and the second symbol is M symbols starting from the first uplink symbol within the time slot and moving from left to right, where M is a positive integer.

[0010] In the above solution, when the first synchronization signal and the second synchronization signal are in different time slots, the first synchronization signal is transmitted in the first symbol within the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, where M is a positive integer;

[0011] and / or, the second synchronization signal is transmitted in the second symbol within the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, where M is a positive integer.

[0012] In the above solution, there is at least one time slot interval between the first time slot and the second time slot.

[0013] In the above solution, the values of M and / or N are related to the distance between the first node and the second node; and / or, the values of M and / or N are pre-configured.

[0014] In the above solution, after the last symbol for transmitting the first synchronization signal, there are at least one first reserved symbol, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, after the last symbol for transmitting the second synchronization signal, there are at least one second reserved symbol, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

[0015] An embodiment of the present invention further provides a clock synchronization method, and the method includes: the second node receives a first synchronization signal from the first node, obtains a first propagation delay based on the first synchronization signal, and sends the first propagation delay to the network device;

[0016] The second node sends a second synchronization signal, and the second synchronization signal is received by the first node, and the second synchronization signal is used for the first node to obtain a second propagation delay; wherein, both the first synchronization signal and the second synchronization signal are reflected by the target during the transmission process.

[0017] In the above solution, the first synchronization signal and the second synchronization signal are in the same time slot; or, the first synchronization signal and the second synchronization signal are in different time slots.

[0018] In the above solution, when the first synchronization signal and the second synchronization signal are in the same time slot, the first synchronization signal is transmitted in the first symbol within the time slot, and the first symbol is N symbols starting from the last downlink symbol within the time slot and moving from right to left, where N is a positive integer; and / or,

[0019] The second synchronization signal is transmitted in the second symbol within the time slot, and the second symbol is M symbols starting from the first uplink symbol within the time slot and moving from left to right, where M is a positive integer.

[0020] In the above solution, when the first synchronization signal and the second synchronization signal are in different time slots, the first synchronization signal is transmitted in the first symbol within the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, where M is a positive integer;

[0021] and / or, the second synchronization signal is transmitted in the second symbol within the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, where M is a positive integer.

[0022] In the above solution, there is at least one time slot interval between the first time slot and the second time slot.

[0023] In the above solution, the values of M and / or N are related to the distance between the first node and the second node; and / or, the values of M and / or N are pre-configured.

[0024] In the above solution, after the last symbol for transmitting the first synchronization signal, there are at least one first reserved symbol, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, after the last symbol for transmitting the second synchronization signal, there are at least one second reserved symbol, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

[0025] An embodiment of the present invention further provides a clock synchronization method, and the method includes: a network device respectively receives a first propagation delay sent by a first node and a second propagation delay sent by a second node;

[0026] The network device obtains the path propagation delay based on the first propagation delay and the second propagation delay to eliminate the synchronization error.

[0027] In the above solution, the network device obtains the path propagation delay based on the first propagation delay and the second propagation delay, including: the network device performs a summation and averaging process on the first propagation delay and the second propagation delay to obtain the path propagation delay.

[0028] In the above solution, the network device obtains the path propagation delay based on the first propagation delay and the second propagation delay, including: the network device obtains multiple first time delays based on the first propagation delay and the second propagation delay received multiple times, and determines the path propagation delay based on the first time delays.

[0029] An embodiment of the present invention further provides a clock synchronization device, which is applied to a first node. The device includes: a first sending unit, a first receiving unit, and a first processing unit; wherein,

[0030] The first sending unit is configured to send a first synchronization signal, wherein the first synchronization signal is received by a second node, and the first synchronization signal is used for the second node to obtain a first propagation delay;

[0031] The first receiving unit is configured to receive a second synchronization signal from the second node;

[0032] The first processing unit is configured to obtain a second propagation delay based on the second synchronization signal;

[0033] The first sending unit is further configured to send the second propagation delay to a network device, wherein both the first synchronization signal and the second synchronization signal are reflected by a target during the transmission process.

[0034] An embodiment of the present invention further provides a clock synchronization device, which is applied to a second node. The device includes: a second receiving unit, a second sending unit, and a second processing unit; wherein,

[0035] The second receiving unit is configured to receive a first synchronization signal from the first node;

[0036] The second processing unit is configured to obtain a first propagation delay based on the first synchronization signal;

[0037] The second sending unit is configured to send the first propagation delay to a network device; and is further configured to send a second synchronization signal, which is received by the first node and is used for the first node to obtain a second propagation delay; wherein, both the first synchronization signal and the second synchronization signal are reflected by a target during transmission.

[0038] An embodiment of the present invention further provides a clock synchronization device, which is applied to a network device and includes: a communication unit and a third processing unit; wherein,

[0039] The communication unit is configured to respectively receive a first propagation delay sent by a first node and a second propagation delay sent by a second node;

[0040] The third processing unit is configured to obtain a path propagation delay based on the first propagation delay and the second propagation delay to eliminate a synchronization error.

[0041] An embodiment of the present invention further provides a communication device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the clock synchronization method applied to the first node, the second node, or the network device in the embodiments of the present invention are implemented.

[0042] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of the clock synchronization method applied to the first node, the second node, or the network device in the embodiments of the present invention are implemented.

[0043] The clock synchronization method, device, communication device, and storage medium provided by the embodiments of the present invention enable a second node that receives a first synchronization signal to obtain a first propagation delay by the first node sending the first synchronization signal, and enable a first node that receives a second synchronization signal to obtain a second propagation delay by the second node sending the second synchronization signal. By sending the first propagation delay and the second propagation delay to a network device, the network device can obtain a path propagation delay based on the first propagation delay and the second propagation delay to eliminate a synchronization error, ensuring clock synchronization between sensing nodes while guaranteeing communication performance, improving the collaborative sensing efficiency, and increasing the communication rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of a frame structure with a 5-ms period;

[0045] Figure 2 It is a schematic diagram of a frame structure in which a flexible time slot is applied to sensing;

[0046] Figure 3 It is a flowchart of the clock synchronization method according to the embodiment of the present inventionFigure 1 ;

[0047] Figure 4 Schematic diagram of the multi - target collaborative sensing scenario of the embodiment of the present invention;

[0048] Figure 5A Schematic diagram of the first synchronization signal transmission scenario of the embodiment of the present invention;

[0049] Figure 5B Schematic diagram of the frame structure configuration of the first synchronization signal of the embodiment of the present invention Figure 1 ;

[0050] Figure 5C Schematic diagram of the second synchronization signal transmission scenario of the embodiment of the present invention;

[0051] Figure 5D Schematic diagram of the frame structure configuration of the second synchronization signal of the embodiment of the present invention Figure 1 ;

[0052] Figure 5E Schematic diagram of the frame structure configuration of the first synchronization signal of the embodiment of the present invention Figure 2 ;

[0053] Figure 5F Schematic diagram of the frame structure configuration of the second synchronization signal of the embodiment of the present invention Figure 2 ;

[0054] Figure 6 Schematic diagram of the flow of the clock synchronization method of the embodiment of the present invention Figure 2 ;

[0055] Figure 7 Schematic diagram of the flow of the clock synchronization method of the embodiment of the present invention Figure 3 ;

[0056] Figure 8 Schematic diagram of the interaction flow of the clock synchronization method of the embodiment of the present invention;

[0057] Figure 9 Schematic diagram of the composition structure of the clock synchronization device provided by the embodiment of the present invention Figure 1 ;

[0058] Figure 10 Schematic diagram of the composition structure of the clock synchronization device provided by the embodiment of the present invention Figure 2 ;

[0059] Figure 11 Schematic diagram of the composition structure of the clock synchronization device provided by the embodiment of the present invention Figure 3 ;

[0060] Figure 12 Schematic diagram of the hardware composition structure of the communication device provided by the embodiment of the present invention. Detailed implementation manners

[0061] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0062] The technical solutions of the embodiments of the present invention can be applied to various communication systems, such as: Global System of Mobile communication (GSM) system, Long Term Evolution (LTE) system, or 5G system, etc. Optionally, the 5G system or 5G network can also be referred to as a New Radio (NR) system or NR network.

[0063] Exemplarily, the communication system to which the embodiments of the present invention are applied may include a network device and a terminal device (which may also be referred to as a terminal, a communication terminal, etc.); the network device may be a device that communicates with the terminal device. Among them, the network device can provide communication coverage within a certain area range and can communicate with terminals located in that area. Optionally, the network device may be a base station in each communication system, such as an Evolutional Node B (eNB) in the LTE system, or a base station (gNB) in the 5G system or NR system.

[0064] It should be understood that in the embodiments of the present application, a device with communication functions in the network / system may be referred to as a communication device. The communication device may include a network device and a terminal with communication functions. The network device and the terminal device may be the specific devices described above, which will not be elaborated here; the communication device may also include other devices in the communication system, such as other network entities such as a network controller and a mobility management entity, which are not limited in the embodiments of the present invention.

[0065] It should be understood that the terms "system" and "network" are often used interchangeably in this article. The term " / and" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the front and rear associated objects.

[0066] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0067] Before further elaborating on the embodiments of the present invention, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are subject to the following explanations.

[0068] 1) Time slot, which is the smallest time unit in a communication system and is used to transmit data or control information. Generally, each time slot contains 14 OFDM symbols.

[0069] 2) Flexible time slot, which serves as the transition point between communication downlink and communication uplink, and its composition structure is: downlink symbol + guard interval + uplink symbol.

[0070] 3) Orthogonal Frequency Division Multiplexing (OFDM), which is a modulation technique used in digital communication. It divides the data stream into multiple subcarriers, and the OFDM symbol is the basic unit for transmitting information on the subcarriers.

[0071] 4) Guard Period (GP), which is the protection time for switching between uplink and downlink. The longer the time, the larger the coverage radius, and it is used to prevent mutual interference between uplink and downlink signals.

[0072] Cooperative sensing (or collaborative sensing) is one of the main working modes of communication and sensing integration. As a potential enabling key technology for 6G, communication and sensing integration can endow mobile cellular networks with new sensing capabilities such as speed measurement, ranging, positioning, target imaging, and recognition, enabling the network to meet the new requirements of intelligent scenarios such as intelligent transportation, drone monitoring, autonomous driving environment perception, and robot interaction.

[0073] The clock synchronization method provided by the embodiments of the present invention enables each base station to obtain the propagation delay through the way of bidirectionally sending synchronization signals between cooperative sensing base stations, and eliminates the synchronization error based on the propagation delay obtained by each base station. In this way, while ensuring communication performance, clock synchronization between base stations is ensured.

[0074] When configuring synchronization signals (such as clock synchronization signals), the uplink and downlink transmission direction configuration of the semi-static frame structure can be achieved through cell-specific uplink and downlink configurations and user equipment (UE)-specific uplink and downlink configurations. Taking a frame structure with a subcarrier spacing of 30 kHz and a period of 5 milliseconds (ms) as an example, as Figure 1 shown, D represents downlink, U represents uplink, and F represents flexible. Within one period, the composition structure of the frame structure from front to back can be: downlink time slot (downlink subframe) + flexible time slot (special subframe) + uplink time slot (uplink subframe). Through cell-specific uplink and downlink configurations, 3 downlink time slots (nrofDownlinkSlots) and 2 uplink time slots (nrofUplinkSlots) have been configured. The slot after all downlink time slots includes 14 symbols, among which the number of downlink symbols (nrofDownlinkSymbols) is 10. The slot before all uplink time slots includes 6 uplink symbols (nrofUplinkSymbols). For the middle flexible time slot, UE-specific uplink and downlink configurations can be performed.

[0075] In addition, when performing inter-station cooperation awareness, the traditional time-domain configuration method may have the problem of multiple uplink and downlink handovers. Taking the positioning reference signal (PRS) as the clock synchronization signal as an example, its time-domain starting position is configured by high-layer parameters, and the starting position of the sensing resource may appear in any symbol of any time slot. Figure 2 It is a schematic diagram of a frame structure in which a flexible time slot is applied to sensing, as Figure 2 shown. The sensing resource is located in the downlink symbols in the first half of the flexible time slot. For the transmitting node, the clock synchronization signal occupies 4 OFDM symbols; relative to the transmitting end, this OFDM symbol can be equivalent to a sensing downlink symbol (CS D ); for the receiving node, due to cooperative reception, it is necessary to ensure the same time-domain position as the transmitting node for receiving the clock synchronization signal. Therefore, the clock synchronization signal also occupies 4 OFDM symbols; relative to the receiving end, this OFDM symbol can also be equivalent to a sensing uplink symbol (CS U ). It should be noted that Figure 2 This is only an example of applying the flexible time slot to the sensing service. The downlink time slot or the uplink time slot can also be applied to the sensing service, and the embodiments of the present invention will not elaborate on this.

[0076] The clock synchronization methods provided by the embodiments of the present invention can all be implemented in the Figure 1 semi-static frame structure, and specifically, the configuration of the flexible time slot can all be implemented in the Figure 2 configuration of the uplink time slot and the downlink time slot.

[0077] Based on this, an embodiment of the present invention provides a clock synchronization method. Figure 3 It is a schematic flow chart of the clock synchronization method according to the embodiment of the present invention. Figure 1 As shown in Figure 3 the figure, the method includes:

[0078] Step 101: The first node sends a first synchronization signal, where the first synchronization signal is received by the second node, and the first synchronization signal is used for the second node to obtain a first propagation delay.

[0079] Step 102: The first node receives a second synchronization signal from the second node, obtains a second propagation delay based on the second synchronization signal, and sends the second propagation delay to the network device, where both the first synchronization signal and the second synchronization signal are reflected by the target during transmission.

[0080] In this embodiment, the first node and the second node are sending nodes or receiving nodes in cooperative sensing. When the first node is the sending node, the second node is the receiving node; when the second node is the sending node, the first node is the receiving node. In some alternative embodiments, the first node and the second node may be node devices in the access network, such as base stations. In other alternative embodiments, the first node and the second node may also be other node devices.

[0081] In this embodiment, synchronization signals are sent bidirectionally between the first node and the second node. For the sake of distinction, the synchronization signal sent by the first node is denoted as the first synchronization signal, and the synchronization signal sent by the second node is denoted as the second synchronization signal. Exemplarily, the above synchronization signals (such as the first synchronization signal and the second synchronization signal) may be clock synchronization signals.

[0082] In some alternative embodiments, in order to achieve cooperative sensing, the first node sends a first synchronization signal. The first synchronization signal is reflected by the target, and the first synchronization signal is reflected to the second node, that is, the second node receives the first synchronization signal, or the first synchronization signal is reflected by the target and received by the first node. The embodiment of the present invention mainly focuses on the above first case, that is, the case where the first synchronization signal is received by the second node. Similarly, the second node sends a second synchronization signal. The second synchronization signal is reflected by the target, and the second synchronization signal is reflected to the first node, that is, the first node receives the second synchronization signal, or the second synchronization signal is reflected by the target and received by the second node. The embodiment of the present invention mainly focuses on the above first case, that is, the case where the second synchronization signal is received by the first node.

[0083] Figure 4 As a schematic diagram of a multi-target cooperative sensing scenario provided by the embodiment of the present invention, as shown in Figure 4As shown in the figure, node A can send a sensing signal. The sensing signal is reflected by target 1 and target 2 and sends back an echo signal, which is received by node B. In addition, node A can also receive the echo signal reflected by target 1 and / or target 2. It should be noted that the echo signal is the sensing signal after being reflected by the target, that is, the echo signal is equivalent to the sensing signal.

[0084] In this embodiment, due to the transmission distance and clock synchronization error between the first node and the second node, there is a propagation delay in the transmission of the synchronization signal. The propagation delay includes: the path propagation delay caused by the transmission distance and the synchronization error delay caused by the clock synchronization error. On the one hand, the first node sends a first synchronization signal, so that the second node receives the first synchronization signal and calculates the first propagation delay based on the received first synchronization signal. On the other hand, the second node sends a second synchronization signal, so that the first node receives the second synchronization signal and calculates the second propagation delay based on the second synchronization signal. By reporting the first propagation delay and the second propagation delay to the network device respectively, the network device obtains the accurate path propagation delay according to the second propagation delay and the first propagation delay, and eliminates the synchronization error.

[0085] In some alternative embodiments, obtaining the second propagation delay based on the second synchronization signal includes: the first node determines the second propagation delay based on the transmission time in the second synchronization signal and the reception time of the second synchronization signal. Among them, as an example, the transmission time of the second synchronization signal can be a time pre-agreed between the second node and the first node; as another example, the second synchronization signal includes a timestamp, which can represent the transmission time of the second synchronization signal. Further, the first node sends the calculated second propagation delay to the network device, so that the network device obtains the accurate path propagation delay according to the second propagation delay and the first propagation delay reported by the second node, and eliminates the synchronization error.

[0086] In other alternative embodiments, the specific method for the second node to calculate the first propagation delay is similar to the specific method for the first node to calculate the second propagation delay, which will not be elaborated here.

[0087] In some embodiments, the first synchronization signal and the second synchronization signal are in the same time slot; or, the first synchronization signal and the second synchronization signal are in different time slots.

[0088] In this embodiment, the first synchronization signal and the second synchronization signal can be transmitted within the same time slot or within different time slots. In some alternative embodiments, the symbols for transmitting the first synchronization signal and the second synchronization signal can be the symbols in the sensing time slot, and the sensing time slot can be a flexible time slot. In other alternative embodiments, the sensing time slot can also be a downlink time slot or an uplink time slot. In the embodiments of the present invention, the case where the sensing time slot is a flexible time slot is taken as an example for description.

[0089] Exemplarily, when the first synchronization signal and the second synchronization signal are within the same time slot, the first node transmits the first synchronization signal and receives the second synchronization signal from the second node within the same time slot; when the first synchronization signal and the second synchronization signal are in different time slots, the first node transmits the first synchronization signal in one time slot and receives the second synchronization signal from the second node in another time slot.

[0090] In this embodiment, there are different transmission configuration methods for the first synchronization signal and the second synchronization signal when they are in the same time slot and in different time slots.

[0091] In some embodiments, when the first synchronization signal and the second synchronization signal are within the same time slot, the first synchronization signal is transmitted in the first symbol within the time slot, and the first symbol is N symbols from the last downlink symbol within the time slot, starting from the right and moving left, where N is a positive integer; and / or, the second synchronization signal starts to be transmitted in the second symbol within the time slot, and the second symbol is M symbols from the first uplink symbol within the time slot, starting from the left and moving right, where M is a positive integer. It can be considered that the first synchronization signal is transmitted in the downlink symbols within the time slot and starts to be transmitted from the Nth symbol from the last downlink symbol, starting from the right and moving left. The second synchronization signal is transmitted in the uplink symbols within the time slot and starts to be transmitted from the Mth symbol from the first uplink symbol within the time slot, starting from the left and moving right.

[0092] In this embodiment, the first symbol and the second symbol can be orthogonal frequency division multiplexing (OFDM) symbols in the flexible time slot, which are respectively used to transmit the first synchronization signal and the second synchronization signal.

[0093] As an example, Figure 5A is a schematic diagram of the first synchronization signal transmission scenario of the embodiment of the present invention. As Figure 5A shown, when the first node transmits the first synchronization signal (see Figure 5A the solid arrow part), after the first synchronization signal is reflected by Target 1, the transmission direction of the first synchronization signal is changed, and the first synchronization signal is received by the second node (see Figure 5AThe dashed arrow part). The first synchronization signal is transmitted in the first symbol within the time slot. The first symbol is N symbols starting from the last downlink symbol and moving from right to left within the flexible time slot, where N is a positive integer. Figure 5B Schematic diagram of the frame structure configuration of the first synchronization signal according to an embodiment of the present invention Figure 1 , as Figure 5B shown, in the frame structure configuration corresponding to the first node, among the 10 downlink symbols of the 14 OFDM symbols in the flexible time slot, the first synchronization signal is transmitted starting from the Nth symbol starting from the last downlink symbol within the time slot and moving from right to left (or from back to front); for example, when N is 2, the first symbol is 2 symbols starting from the last downlink symbol and moving from right to left (or from back to front), that is, the 10th and 9th downlink symbols, and starting from the 9th downlink symbol to the last downlink symbol (i.e., the 10th downlink symbol) are all used to transmit the first synchronization signal.

[0094] As another example, Figure 5C Schematic diagram of the transmission scenario of the second synchronization signal according to an embodiment of the present invention, as Figure 5C shown, when the second node transmits the second synchronization signal (see Figure 5C the solid arrow part), after the second synchronization signal is reflected by target 1, the transmission direction of the second synchronization signal is changed, and the second synchronization signal is received by the first node (see Figure 5C the dashed arrow part). The second synchronization signal starts to be transmitted in the second symbol within the time slot. The second symbol is M symbols starting from the first uplink symbol and moving from left to right (or from front to back) within the flexible time slot, where M is a positive integer. Figure 5D Schematic diagram of the frame structure configuration of the second synchronization signal according to an embodiment of the present invention Figure 1 , as Figure 5D shown, in the frame structure configuration corresponding to the first node, among the 2 uplink symbols of the 14 OFDM symbols in the flexible time slot, the second synchronization signal starts to be transmitted starting from the first uplink symbol within the time slot and lasts for M symbols; for example, when M is 2, the second symbol is 2 symbols starting from the first uplink symbol, that is, the 1st and 2nd uplink symbols (the 13th and 14th symbols) are both used to receive the second synchronization signal transmitted by the second node.

[0095] In this embodiment, the first synchronization signal and the second synchronization signal are within the same time slot, that is, Figure 5B and Figure 5D in, the frame structure configuration corresponding to the first node is the frame structure configuration within the same time slot. Similarly, the frame structure configuration corresponding to the second node is the frame structure configuration within the same time slot, that is, Syn D and Syn U are within the same time slot.

[0096] In some embodiments, when the first synchronization signal and the second synchronization signal are in different time slots, the first synchronization signal is transmitted in the first symbol of the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol in the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol in the first time slot and moving from left to right, where M is a positive integer.

[0097] And / or, the second synchronization signal is transmitted in the second symbol of the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol in the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol in the second time slot and moving from left to right, where M is a positive integer.

[0098] Exemplarily, when the first synchronization signal and the second synchronization signal are in different time slots, when performing the scenario where the first node as shown in Figure 5A sends the first synchronization signal (see the solid arrow part in Figure 5A ), there are two methods to send the first synchronization signal.

[0099] The first method is that the first symbol is N symbols starting from the last downlink symbol in the first time slot and moving from right to left (or from back to front), where N is a positive integer. As shown in Figure 5B , for the frame structure configuration corresponding to the first node, among the 10 downlink symbols of the 14 OFDM symbols in the flexible time slot, the first synchronization signal is transmitted starting from the Nth symbol starting from the last downlink symbol in the time slot and moving from right to left (or from back to front); for example, when N is 2, the first symbol is 2 symbols starting from the last downlink symbol and moving from right to left (or from back to front), that is, the 10th and 9th downlink symbols are both used to send the first synchronization signal.

[0100] The second method is that the first symbol is M symbols starting from the first uplink symbol in the first time slot and moving from left to right (or from front to back), where M is a positive integer. Figure 5E Schematic diagram of the frame structure of the first synchronization signal according to the embodiment of the present invention Figure 2 , as shown in Figure 5E , for the frame structure configuration corresponding to the first node, among the 2 uplink symbols of the 14 OFDM symbols in the flexible time slot, the first synchronization signal is transmitted starting from the first uplink symbol in the time slot and lasting for M symbols; for example, when M is 2, the first symbol is 2 symbols starting from the first uplink symbol, that is, the 1st and 2nd uplink symbols (the 13th and 14th symbols) are both used to send the first synchronization signal.

[0101] Exemplarily, in the case where the first synchronization signal and the second synchronization signal are in different time slots, when the first node as shown in Figure 5C receives the second synchronization signal from the second node (see the Figure 5C dashed arrow part), there are two methods for receiving the second synchronization signal.

[0102] The first method is that the second symbol is N symbols starting from the last downlink symbol in the second time slot and moving from right to left (or from back to front), where N is a positive integer. Figure 5F Schematic diagram of the frame structure of the second synchronization signal according to an embodiment of the present invention Figure 2 , as Figure 5F shown, for the frame structure configuration corresponding to the first node, among the 10 downlink symbols of the 14 OFDM symbols in the flexible time slot, the second synchronization signal is transmitted starting from the Nth symbol starting from the last downlink symbol in the time slot and moving from right to left (or from back to front); for example, when N is 2, the second symbol is 2 symbols starting from the last downlink symbol and moving from right to left (or from back to front), that is, the 10th and 9th downlink symbols are both used to receive the second synchronization signal transmitted by the second node.

[0103] Optionally, since some OFDM symbols in the downlink symbols are used as the second symbol for receiving the second synchronization signal, an OFDM symbol is set as a guard period (GP, Guard Period) between the second symbol and the remaining downlink symbols to prevent the downlink symbols originally used for transmitting the clock synchronization signal from interfering with each other when receiving the second synchronization signal.

[0104] In this embodiment, before the uplink symbol for receiving the second synchronization signal, the number of OFDM symbols constituting the guard period can be determined according to requirements. For example, when the uplink-downlink switching speed is slow, the number of OFDM symbols in the guard period can be appropriately increased, and vice versa. The number of OFDM symbols constituting the guard period is at least 1.

[0105] The second method is that the second symbol is M symbols starting from the first uplink symbol in the second time slot and moving from left to right (or from front to back), where M is a positive integer. As Figure 5D shown, for the frame structure configuration corresponding to the first node, among the 2 uplink symbols of the 14 OFDM symbols in the flexible time slot, the second synchronization signal is transmitted starting from the first uplink symbol in the time slot and lasting for M symbols; for example, when M is 2, the second symbol is 2 symbols starting from the first uplink symbol, that is, the 1st and 2nd uplink symbols (the 13th and 14th symbols) are both used to receive the second synchronization signal transmitted by the second node.

[0106] In some embodiments, there is at least one time slot interval between the first time slot and the second time slot.

[0107] In this embodiment, the interval length between the first time slot and the second time slot can be pre-configured by the network based on the out-of-step change rate of the base station. Base station out-of-step refers to the phenomenon that the clocks between base stations are out of sync due to various reasons.

[0108] In some embodiments, the value of M and / or N is related to the distance between the first node and the second node; and / or, the value of M and / or N is pre-configured.

[0109] In this embodiment, the value of the number N of OFDM symbols occupied by the first symbol in the flexible time slot and the value of the number M of OFDM symbols occupied by the second symbol in the flexible time slot can be pre-set or dynamically updated based on the distance between the first node and the second node. For example, the requirement for synchronous signal energy accumulation. If the distance between the first node and the second node is far, the number of N and / or M can be increased to extend the time slot for transmitting and / or receiving the clock synchronization signal, avoiding incomplete transmission and / or reception of the clock synchronization signal; if the distance between the first node and the second node is close, the number of N and / or M can be reduced to shorten the time slot for transmitting and / or receiving the clock synchronization signal, avoiding wasting resources and increasing overhead.

[0110] In some embodiments, after the last symbol for transmitting the first synchronization signal, there are at least one first reserved symbol, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, after the last symbol for transmitting the second synchronization signal, there are at least one second reserved symbol, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

[0111] In this embodiment, the first reserved symbol and the second reserved symbol can be OFDM symbols in the flexible time slot, which are respectively used to continue receiving the first synchronization signal and the second synchronization signal, and the number of OFDM symbols occupied by the first reserved symbol and the second reserved symbol can be determined according to requirements.

[0112] Exemplarily, when transmitting the synchronization signal between the first node and the second node, although the lengths of the first symbol and / or the second symbol for receiving the synchronization signal will be dynamically changed, due to the clock synchronization error between the receiving node and the transmitting node and the time delay generated during the transmission of the synchronization signal, there will still be a situation where the received synchronization signal is incomplete. Therefore, at least one OFDM symbol needs to be reserved after the last symbol for receiving the first synchronization signal and / or the second synchronization signal for continuing to receive the first synchronization signal and / or the second synchronization signal.

[0113] In this embodiment, asFigure 5D As shown, in the frame structure configuration corresponding to the first node, in the uplink symbol, the Syn behind the second symbol (the 14th OFDM symbol from left to right) that is the last one for receiving the second synchronization signal from the second node U is the second reserved symbol for continuously receiving the second synchronization signal; as Figure 5F shown, in the frame structure configuration corresponding to the first node, in the downlink symbol, the Syn behind the second symbol (the 10th OFDM symbol from left to right) that is the last one for receiving the second synchronization signal from the second node U is the second reserved symbol for continuously receiving the second synchronization signal.

[0114] Figure 6 is a flowchart of the clock synchronization method according to an embodiment of the present invention Figure 2 ; as Figure 6 shown, the method includes:

[0115] Step 201: The second node receives the first synchronization signal from the first node, obtains the first propagation delay based on the first synchronization signal, and sends the first propagation delay to the network device.

[0116] Step 202: The second node sends the second synchronization signal, and the second synchronization signal is received by the first node. The second synchronization signal is used for the first node to obtain the second propagation delay; wherein, both the first synchronization signal and the second synchronization signal are reflected by the target during transmission.

[0117] In this embodiment, the first node and the second node are the sending node or the receiving node in cooperative sensing. When the first node is the sending node, the second node is the receiving node; when the second node is the sending node, the first node is the receiving node. In some optional embodiments, the first node and the second node may be node devices in the access network, such as base stations. In other optional embodiments, the first node and the second node may also be other node devices.

[0118] In this embodiment, synchronization signals are sent bidirectionally between the first node and the second node. For the sake of distinction, the synchronization signal sent by the first node is denoted as the first synchronization signal, and the synchronization signal sent by the second node is denoted as the second synchronization signal. Exemplarily, the above synchronization signals (such as the first synchronization signal, the second synchronization signal) may be clock synchronization signals.

[0119] In some optional embodiments, in order to achieve collaborative perception, the second node sends a second synchronization signal, and the second synchronization signal is reflected by the target and then reflected to the first node, that is, the first node receives the second synchronization signal, or the second synchronization signal is reflected by the target and then received by the second node. The embodiments of the present invention are mainly aimed at the first case mentioned above, that is, the case where the second synchronization signal is received by the first node. Similarly, the first node sends a first synchronization signal, and the first synchronization signal is reflected by the target and then reflected to the second node, that is, the second node receives the first synchronization signal, or the first synchronization signal is reflected by the target and then received by the first node. The embodiments of the present invention are mainly aimed at the first case mentioned above, that is, the case where the first synchronization signal is received by the second node.

[0120] As an example, the cooperative sensing scenario of synchronized signal transmission between nodes through target reflection has been described above. For details, please refer to Figure 4 And related descriptions, I will not go into details here.

[0121] In this embodiment, due to the transmission distance and clock synchronization error between the first node and the second node, there is a propagation delay in the transmission of the synchronization signal, and the propagation delay includes: the path propagation delay caused by the transmission distance and the synchronization error delay caused by the clock synchronization error. On the one hand, the first synchronization signal is sent by the first node, so that the second node receives the first synchronization signal, and calculates the first propagation delay based on the received first synchronization signal. On the other hand, the second synchronization signal is sent by the second node, so that the first node receives the second synchronization signal, and calculates the second propagation delay based on the second synchronization signal. By reporting the first propagation delay and the second propagation delay to the network device respectively, the network device obtains the accurate path propagation delay based on the second propagation delay and the first propagation delay, thereby eliminating the synchronization error.

[0122] In some optional embodiments, obtaining the first propagation delay based on the first synchronization signal includes: the second node determines the first propagation delay based on the sending time in the first synchronization signal and the receiving time of the first synchronization signal. As an example, the sending time of the first synchronization signal may be a time pre-agreed by the first node and the second node; as another example, the first synchronization signal includes a timestamp, which may indicate the sending time of the first synchronization signal. Furthermore, the second node sends the calculated first propagation delay to the network device, so that the network device obtains an accurate path propagation delay based on the first propagation delay and the second propagation delay reported by the first node, thereby eliminating synchronization errors.

[0123] In other alternative embodiments, the specific manner in which the first node calculates the second propagation delay is similar to the specific manner in which the second node calculates the first propagation delay, which will not be elaborated here.

[0124] In some embodiments, the first synchronization signal and the second synchronization signal are within the same time slot; or, the first synchronization signal and the second synchronization signal are in different time slots.

[0125] In this embodiment, the second synchronization signal and the first synchronization signal can be transmitted within the same time slot or in different time slots. In some alternative embodiments, the symbols for transmitting the first synchronization signal and the second synchronization signal are the symbols in the sensing time slot, and the sensing time slot can be a flexible time slot in the subcarrier frame structure. In other alternative embodiments, the sensing time slot can also be a downlink time slot or an uplink time slot. In the embodiments of the present invention, the flexible time slot is taken as an example for illustration.

[0126] Exemplarily, when the second synchronization signal and the first synchronization signal are in the same time slot, the second node transmits the second synchronization signal and receives the first synchronization signal from the first node within the same time slot; when the second synchronization signal and the first synchronization signal are in different time slots, the second node transmits the second synchronization signal within one time slot and receives the first synchronization signal from the first node within another time slot.

[0127] In this embodiment, there are different transmission configuration methods for the second synchronization signal and the first synchronization signal in the same time slot and in different time slots.

[0128] In some embodiments, when the first synchronization signal and the second synchronization signal are in the same time slot, the first synchronization signal is transmitted in the first symbol within the time slot, and the first symbol is N symbols starting from the last downlink symbol within the time slot and moving from right to left, where N is a positive integer; and / or, the second synchronization signal is transmitted in the second symbol within the time slot, and the second symbol is M symbols starting from the first uplink symbol within the time slot and moving from left to right, where M is a positive integer. It can be considered that the first synchronization signal is transmitted in the downlink symbols within the time slot and starts from the Nth symbol starting from the last downlink symbol and moving from right to left. The second synchronization signal is transmitted in the uplink symbols within the time slot and starts from the Mth symbol starting from the first uplink symbol within the time slot and moving from left to right.

[0129] In this embodiment, the first symbol and the second symbol can be OFDM symbols in the flexible time slot, which are respectively used to transmit the first synchronization signal and the second synchronization signal.

[0130] As an example, such as Figure 5AAs shown, when the first node sends the first synchronization signal (see Figure 5A the solid arrow part), the first synchronization signal is reflected by Target 1, changing the transmission direction of the first synchronization signal, and the first synchronization signal is received by the second node (see Figure 5A the dashed arrow part). The first synchronization signal is transmitted in the first symbol within the time slot. The first symbol is N symbols starting from the last downlink symbol and moving from right to left within the flexible time slot, where N is a positive integer. As Figure 5B shown, in the frame structure configuration corresponding to the second node, among the 10 downlink symbols of the 14 OFDM symbols in the flexible time slot, the first synchronization signal starts to be transmitted from the Nth symbol starting from the last downlink symbol in the time slot and moving from right to left (or from back to front); for example, when N is 2, the first symbol is 2 symbols starting from the last downlink symbol and moving from right to left (or from back to front), that is, the 10th and 9th downlink symbols. Then, from the 9th downlink symbol to the last downlink symbol (i.e., the 10th downlink symbol) are all used to receive the first synchronization signal transmitted from the first node.

[0131] Optionally, since the last N OFDM symbols in the downlink symbol are used as the first symbol for receiving the first synchronization signal, an OFDM symbol is set as the guard interval (F) between the first symbol and the remaining downlink symbols to prevent the downlink symbols originally used for transmitting the clock synchronization signal from interfering with each other when receiving the first synchronization signal.

[0132] In this embodiment, the number of OFDM symbols used as the guard interval can be pre-configured according to requirements. For example, when the uplink-downlink switching speed is slow, the number of OFDM symbols in the guard interval can be appropriately increased, and vice versa. The number of OFDM symbols forming the guard interval is at least 1.

[0133] As another example, as Figure 5C shown, when the second node sends the second synchronization signal (see Figure 5C the solid arrow part), the second synchronization signal is reflected by Target 1, changing the transmission direction of the second synchronization signal, and the second synchronization signal is received by the first node (see Figure 5C the dashed arrow part). The second synchronization signal starts to be transmitted in the second symbol within the time slot. The second symbol is M symbols starting from the first uplink symbol in the flexible time slot and moving from left to right (or from front to back), where M is a positive integer. As Figure 5DAs shown, in the frame structure configuration corresponding to the second node, among the 2 uplink symbols of the 14 OFDM symbols in the flexible time slot, the second synchronization signal is transmitted starting from the first uplink symbol within the time slot, lasting for M symbols; for example, when M is 2, the second symbol is 2 symbols starting from the first uplink symbol, that is, the 1st and 2nd uplink symbols (the 13th and 14th symbols) are both used to transmit the second synchronization signal.

[0134] In this embodiment, the first synchronization signal and the second synchronization signal are within the same time slot, that is Figure 5B and Figure 5D in, the frame structure configuration corresponding to the first node is the frame structure configuration in the same time slot. Similarly, the frame structure configuration corresponding to the second node is the frame structure configuration in the same time slot, that is Syn D and Syn U are in the same time slot.

[0135] In some embodiments, when the first synchronization signal and the second synchronization signal are in different time slots, the first synchronization signal is transmitted in the first symbol within the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, where M is a positive integer;

[0136] and / or, the second synchronization signal is transmitted in the second symbol within the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, where M is a positive integer.

[0137] Exemplarily, when the first synchronization signal and the second synchronization signal are in different time slots, when performing as Figure 5A shown in the scenario where the second node receives the first synchronization signal from the first node (see Figure 5A the dotted arrow part), there are two methods to receive the first synchronization signal.

[0138] The first method is that the first symbol is N symbols starting from the last downlink symbol within the first time slot and moving from right to left (or from back to front), where N is a positive integer, as Figure 5BAs shown, in the frame structure configuration corresponding to the second node, among the 10 downlink symbols of the 14 OFDM symbols in the flexible time slot, the first synchronization signal is transmitted starting from the Nth symbol from the right (or from the back) to the left with the last downlink symbol in the time slot as the starting point; for example, when N is 2, the first symbol is 2 symbols from the right (or from the back) to the left with the last downlink symbol as the starting point, that is, the 10th and 9th downlink symbols, which are used to receive the first synchronization signal from the first node.

[0139] Optionally, since some of the OFDM symbols in the downlink symbols are used as the first symbols for receiving the first synchronization signal, an OFDM symbol is set as a guard interval between the first symbol and the remaining downlink symbols to prevent the downlink symbols originally used for transmitting the clock synchronization signal from interfering with each other when receiving the first synchronization signal.

[0140] The second method is that the first symbol is M symbols from the left (or from the front) to the right with the first uplink symbol in the first time slot as the starting point, where M is a positive integer. As Figure 5E shown, in the frame structure configuration corresponding to the second node, among the 2 uplink symbols of the 14 OFDM symbols in the flexible time slot, the first synchronization signal is transmitted starting from the first uplink symbol in the time slot and lasting for M symbols; for example, when M is 2, the first symbol is 2 symbols with the first uplink symbol as the starting point, that is, both the 1st and 2nd uplink symbols (the 13th and 14th symbols) are used to receive the first synchronization signal.

[0141] Exemplarily, in the case where the first synchronization signal and the second synchronization signal are in different time slots, when performing the scenario of the second node transmitting the second synchronization signal as shown in Figure 5C (see the solid arrow part in Figure 5C ), there are two methods for transmitting the second synchronization signal.

[0142] The first method is that the second symbol is N symbols from the right (or from the back) to the left with the last downlink symbol in the second time slot as the starting point, where N is a positive integer. As Figure 5F shown, in the frame structure configuration corresponding to the second node, among the 10 downlink symbols of the 14 OFDM symbols in the flexible time slot, the second synchronization signal is transmitted starting from the Nth symbol from the right (or from the back) to the left with the last downlink symbol in the time slot as the starting point; for example, when N is 2, the second symbol is 2 symbols from the right (or from the back) to the left with the last downlink symbol as the starting point, that is, both the 10th and 9th downlink symbols are used for the second node to transmit the second synchronization signal.

[0143] Optionally, since some OFDM symbols in the downlink symbols are used as the second symbols for receiving the second synchronization signal, an OFDM symbol is set as a guard interval between the second symbol and the remaining downlink symbols, so as to prevent the downlink symbols originally used for transmitting the clock synchronization signal from interfering with each other when receiving the second synchronization signal.

[0144] The second method is that the second symbol is M symbols starting from the first uplink symbol in the second time slot and going from left to right (or from front to back), where M is a positive integer. For example, Figure 5D As shown, in the frame structure configuration corresponding to the second node, in 2 uplink symbols of 14 OFDM symbols in the flexible time slot, the second synchronization signal is transmitted starting from the first uplink symbol in the time slot, lasting for M symbols. For example, when M is 2, the second symbol is 2 symbols starting from the first uplink symbol, that is, the 1st and 2nd uplink symbols (the 13th and 14th symbols) are both used for the second node to transmit the second synchronization signal.

[0145] In some embodiments, there is at least one time slot interval between the first time slot and the second time slot.

[0146] In this embodiment, the interval length between the first time slot and the second time slot can be pre-configured by the network based on the out-of-step change rate of the base station. Base station out-of-step refers to the phenomenon that the clocks between base stations are not synchronized due to various reasons.

[0147] In some embodiments, the value of M and / or N is related to the distance between the first node and the second node; and / or, the value of M and / or N is pre-configured.

[0148] In this embodiment, the value of N, the number of OFDM symbols occupied by the first symbol in the flexible time slot, and the value of M, the number of OFDM symbols occupied by the second symbol in the flexible time slot, can be pre-set or dynamically updated based on the distance between the first node and the second node. For example, the requirement for the accumulation of synchronization signal energy. If the distance between the first node and the second node is far, the number of N and / or M can be increased to extend the time slot for transmitting and / or receiving the clock synchronization signal, avoiding incomplete transmission and / or reception of the clock synchronization signal; if the distance between the first node and the second node is close, the number of N and / or M can be reduced to shorten the time slot for transmitting and / or receiving the clock synchronization signal, avoiding wasting resources and increasing overhead.

[0149] In some embodiments, after the last symbol for transmitting the first synchronization signal, there are at least one first reserved symbol, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, after the last symbol for transmitting the second synchronization signal, there are at least one second reserved symbol, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

[0150] In this embodiment, the first reserved symbol and the second reserved symbol may be OFDM symbols in flexible time slots, which are respectively used to continue receiving the first synchronization signal and the second synchronization signal, and the number of OFDM symbols occupied by the first reserved symbol and the second reserved symbol can be determined according to requirements.

[0151] Exemplarily, when transmitting synchronization signals between the first node and the second node, although the lengths of the first symbol and / or the second symbol for receiving the synchronization signal will be dynamically changed, due to the clock synchronization error between the receiving node and the transmitting node, and the time delay generated during the transmission of the synchronization signal, there will still be a situation where the received synchronization signal is incomplete. Therefore, at least one OFDM symbol needs to be reserved after the last symbol for receiving the first synchronization signal and / or the second synchronization signal, for continuing to receive the first synchronization signal and / or the second synchronization signal.

[0152] In this embodiment, as Figure 5B shown, for the frame structure configuration corresponding to the second node, in the downlink symbols, the Syn U after the last first symbol (the 10th OFDM symbol from left to right) for receiving the first synchronization signal from the first node is the first reserved symbol, which is used to continue receiving the first synchronization signal; as Figure 5E shown, for the frame structure configuration corresponding to the second node, in the uplink symbols, the Syn U after the last first symbol (the 14th OFDM symbol from left to right) for receiving the first synchronization signal from the first node is the first reserved symbol, which is used to continue receiving the first synchronization signal.

[0153] Figure 7 is a schematic flow chart of the clock synchronization method according to an embodiment of the present invention Figure 3 ; as Figure 7 shown, the method includes:

[0154] Step 301: The network device respectively receives the first propagation delay sent by the first node and the second propagation delay sent by the second node.

[0155] In an embodiment of the present invention, the network device may be an electronic device with communication and computing functions. Exemplarily, the network device may be a server (such as a positioning server), a device with a central processing unit and network functions, etc.

[0156] In some embodiments, the first propagation delay represents the propagation delay generated during the transmission process of the first synchronization signal when the first synchronization signal is sent by the first node and reflected by the target and then transmitted to the second node.

[0157] In this embodiment, the first propagation delay includes: the path propagation delay caused by the transmission distance and the synchronization error delay caused by the clock synchronization error. Exemplarily, the first propagation delay can be expressed by the following formula:

[0158] L1 = T1 + ΔT (1)

[0159] Where L1 is the first propagation delay, T1 is the path propagation delay, that is, the true echo path delay, and ΔT is the delay caused by the synchronization error. The synchronization error is the clock synchronization error between the first node and the second node.

[0160] In some embodiments, the second propagation delay identifies the propagation delay generated during the transmission process of the second synchronization signal when the second synchronization signal is sent by the second node and reflected by the target and then transmitted to the first node.

[0161] In this embodiment, the second propagation delay includes: the path propagation delay caused by the transmission distance and the synchronization error delay caused by the clock synchronization error. Exemplarily, the second propagation delay can be expressed by the following formula:

[0162] L2 = T2 - ΔT (2)

[0163] Where L2 is the second propagation delay, T2 is the path propagation delay, that is, the true echo path delay, and ΔT is the delay caused by the synchronization error. The synchronization error is the clock synchronization error between the second node and the first node, which has the same meaning as the synchronization error ΔT in formula (1). However, since the first synchronization signal is generated during the transmission process from the first node to the second node, and the second synchronization signal is generated during the transmission process from the second node to the first node, therefore, during the calculation of the propagation delay, formula (1) uses “+ΔT”, while formula (2) uses “-ΔT”.

[0164] In this embodiment, Formulas (1) and (2) are not affected by whether the first synchronization signal and the second synchronization signal are in the same time slot. It can be understood that whether the first synchronization signal and the second synchronization signal are in the same time slot or not, Formulas (1) and (2) can be used to express the first propagation delay and the second propagation delay.

[0165] Step 302: The network device obtains a path propagation delay based on the first propagation delay and the second propagation delay to eliminate the synchronization error.

[0166] In some embodiments, in Step 302, the network device obtaining the path propagation delay based on the first propagation delay and the second propagation delay includes: The network device performs a summation and averaging process on the first propagation delay and the second propagation delay to obtain the path propagation delay.

[0167] In this embodiment, after the network device receives the second delay and the first delay uploaded by the first node and the second node respectively, by performing a summation and averaging process on the first propagation delay and the second propagation delay to obtain the path propagation delay, the corresponding path propagation delay calculation process is as follows:

[0168]

[0169] Wherein, L is the path propagation delay. By performing a summation and averaging process on Formula (1) representing the first propagation delay and Formula (2) representing the second propagation delay, the synchronization error ΔT can be eliminated to obtain the path propagation delay L without synchronization error.

[0170] In some embodiments, in Step 302, the network device obtaining the path propagation delay based on the first propagation delay and the second propagation delay includes: The network device obtains multiple first delays based on the first propagation delay and the second propagation delay received multiple times, and determines the path propagation delay based on the first delays.

[0171] In this embodiment, in order to further improve the accuracy, multiple sets of propagation delays can be obtained through repeated bidirectional transceiver in multiple time slots, and a more accurate path propagation delay can be obtained after weighted averaging. The time interval P of the bidirectional transceiver and the number K of repeated transceiver of the clock synchronization signal can be pre-configured through the network based on the out-of-step change rate of the base station. Base station out-of-step refers to the phenomenon that the clocks between base stations are not synchronized due to various reasons; The period P of the bidirectional transceiver and the number K of repeated transceiver of the clock synchronization signal can also be calculated with two transceiver time slots as the minimum unit.

[0172] The clock synchronization method of the embodiments of the present invention will be described below with specific embodiments.

[0173] Figure 8 Schematic diagram of the interaction process of the clock synchronization method according to an embodiment of the present invention; as Figure 8 shown, the method includes:

[0174] Step 401: The first node sends a first synchronization signal; the first synchronization signal is received by the second node after being reflected by the target;

[0175] Step 402: The second node obtains a first propagation delay based on the first synchronization signal and sends the first propagation delay to the network device;

[0176] Step 403: The second node sends a second synchronization signal; the second synchronization signal is received by the first node after being reflected by the target;

[0177] Step 404: The first node obtains a second propagation delay based on the second synchronization signal and sends the second propagation delay to the network device;

[0178] Step 405: The network device obtains a path propagation delay based on the first propagation delay and the second propagation delay to eliminate the synchronization error.

[0179] In some embodiments, the first synchronization signal and the second synchronization signal can be transmitted within the same time slot or in different time slots. In this embodiment, there are different transmission configuration methods for the first synchronization signal and the second synchronization signal within the same time slot and in different time slots.

[0180] In some embodiments, when the first synchronization signal and the second synchronization signal are within the same time slot, the first synchronization signal is transmitted in the downlink symbols within the time slot, and is transmitted as N symbols from the last downlink symbol as the starting point and from right to left. The second synchronization signal is transmitted in the uplink symbols within the time slot, and is transmitted as M symbols from the first uplink symbol within the time slot as the starting point and from left to right.

[0181] As an example, when performing the transmission of the first synchronization signal as Figure 5A shown, the first synchronization signal starts to be transmitted from the first symbol within the time slot. The first symbol is N symbols from the last downlink symbol as the starting point and from right to left within the flexible time slot, and N is a positive integer. When Figure 5C the second node and the first node perform the transmission of the second synchronization signal in

[0182] As an example, Figure 5B with Figure 5DTogether completed the transmission and reception of the first synchronization signal and the second synchronization signal between the first node and the second node within the same flexible time slot.

[0183] As Figure 5B shown, among the 10 downlink symbols of the 14 OFDM symbols in the same flexible time slot, the first synchronization signal is transmitted starting from the Nth symbol from the right (or from the back) to the left, with the last downlink symbol in the time slot as the starting point; for example, when N is 2, the first symbol is 2 symbols from the right (or from the back) to the left with the last downlink symbol as the starting point, that is, the 9th and 10th OFDM symbols. Then, starting from the 9th downlink symbol to the last downlink symbol (i.e., the 10th downlink symbol) are used for the first node to transmit the first synchronization signal and the second node to receive the first synchronization signal; when the second node receives the first synchronization signal through the first symbol, the 8th OFDM symbol is set as the guard interval to prevent mutual interference; the 11th OFDM symbol is set as the first reserved symbol to continue receiving the first synchronization signal.

[0184] As Figure 5D shown, among the 2 uplink symbols of the 14 OFDM symbols in the same flexible time slot, the second synchronization signal is transmitted starting from the first uplink symbol in the time slot and lasts for M symbols; for example, when M is 2, the second symbol is 2 symbols starting from the first uplink symbol, that is, the 1st and 2nd uplink symbols (the 13th and 14th OFDM symbols) are both used for the second node to transmit the second synchronization signal and the first node to receive the second synchronization signal; the Syn U behind the 14th OFDM symbol is the second reserved symbol to continue receiving the second synchronization signal.

[0185] In some embodiments, when the first synchronization signal and the second synchronization signal are in different time slots, the first synchronization signal can be transmitted in the downlink symbols of the first time slot and transmitted from the Nth symbol from the right to the left with the last downlink symbol as the starting point, or the first synchronization signal can be transmitted in the uplink symbols of the first time slot and transmitted from the Mth symbol from the left to the right with the first uplink symbol in the time slot as the starting point. Correspondingly, the second synchronization signal can be transmitted in the uplink symbols of the second time slot different from the first time slot and transmitted from the Mth symbol from the left to the right with the first uplink symbol in the time slot as the starting point, or the second synchronization signal can be transmitted in the downlink symbols of the second time slot and transmitted from the Nth symbol from the right to the left with the last downlink symbol as the starting point. Specific descriptions will be given separately below.

[0186] Exemplarily, when the first synchronization signal and the second synchronization signal are in different time slots, when performing as Figure 5AThe scenario where the first node transmits the first synchronization signal and the scenario where the second node transmits the second synchronization signal as shown can have four transmission configuration methods. Figure 5C When the second node transmits the second synchronization signal as shown, there can be four transmission configuration methods.

[0187] The first method is that the first symbol is N symbols starting from the last downlink symbol in the first time slot and moving from right to left (or from back to front), where N is a positive integer; and the second symbol is M symbols starting from the first uplink symbol in the second time slot and moving from left to right (or from front to back), where M is a positive integer. As Figure 5B and Figure 5D shown, Figure 5B Together with Figure 5D accomplish the transmission and reception of the first synchronization signal and the second synchronization signal between the first node and the second node. For the specific description of Figure 5B and Figure 5D is the same as the method where the first node and the second node are in the same time slot as described above, so it will not be elaborated here.

[0188] The second method is that the first symbol is N symbols starting from the last downlink symbol in the first time slot and moving from right to left (or from back to front), where N is a positive integer; and the second symbol is N symbols starting from the last downlink symbol in the second time slot and moving from right to left (or from back to front), where N is a positive integer. As Figure 5B and Figure 5F shown, Figure 5B Together with Figure 5F accomplish the transmission and reception of the first synchronization signal and the second synchronization signal between the first node and the second node. The specific description of the frame structures of the first node and the second node in Figure 5B and Figure 5D has been described above, so it will not be elaborated here.

[0189] The third method is that the first symbol is M symbols starting from the first uplink symbol in the first time slot and moving from left to right (or from front to back), where M is a positive integer; and the second symbol is M symbols starting from the first uplink symbol in the second time slot and moving from left to right (or from front to back), where M is a positive integer. As Figure 5E and Figure 5D shown, Figure 5E Together with Figure 5D accomplish the transmission and reception of the first synchronization signal and the second synchronization signal between the first node and the second node. The specific description of the frame structures of the first node and the second node in Figure 5E and Figure 5D has been described above, so it will not be elaborated here.

[0190] The fourth way is that the first symbol is M symbols starting from the first uplink symbol in the first time slot and going from left to right (or from front to back), where M is a positive integer; and the second symbol is N symbols starting from the last downlink symbol in the second time slot and going from right to left (or from back to front), where N is a positive integer. As Figure 5E and Figure 5F shown, Figure 5E together with Figure 5F have jointly completed the transmission and reception of the first synchronization signal and the second synchronization signal between the first node and the second node. For the specific descriptions of the frame structures of the first node and the second node in Figure 5E and Figure 5F have been described above and will not be elaborated here.

[0191] Based on the above embodiments, an embodiment of the present invention further provides a clock synchronization device applied to the first node. Figure 9 is a schematic diagram of the composition structure of the clock synchronization device provided by the embodiment of the present invention. Figure 1 As Figure 9 shown, the device includes: a first sending unit 51, a first receiving unit 52, and a first processing unit 53; where

[0192] The first sending unit 51 is configured to send a first synchronization signal, where the first synchronization signal is received by the second node, and the first synchronization signal is used for the second node to obtain a first propagation delay;

[0193] The first receiving unit 52 is configured to receive a second synchronization signal from the second node;

[0194] The first processing unit 53 is configured to obtain a second propagation delay based on the second synchronization signal;

[0195] The first sending unit 51 is further configured to send the second propagation delay to a network device, where both the first synchronization signal and the second synchronization signal are reflected by a target during transmission.

[0196] In an alternative embodiment of the present invention, the first synchronization signal and the second synchronization signal are in the same time slot; or, the first synchronization signal and the second synchronization signal are in different time slots.

[0197] In an alternative embodiment of the present invention, when the first synchronization signal and the second synchronization signal are in the same time slot, the first transmitting unit 51 is configured to transmit the first synchronization signal in the first symbol within the time slot, where the first symbol is N symbols starting from the last downlink symbol within the time slot and moving from right to left, and N is a positive integer; and / or, the first receiving unit 52 is configured to transmit the second synchronization signal in the second symbol within the time slot, where the second symbol is M symbols starting from the first uplink symbol within the time slot and moving from left to right, and M is a positive integer.

[0198] In an alternative embodiment of the present invention, when the first synchronization signal and the second synchronization signal are in different time slots, the first transmitting unit 51 is configured to transmit the first synchronization signal in the first symbol within the first time slot, where the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, and N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, and M is a positive integer; and / or, the first receiving unit 52 is configured to transmit the second synchronization signal in the second symbol within the second time slot, where the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, and N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, and M is a positive integer.

[0199] In an alternative embodiment of the present invention, there is at least one time slot interval between the first time slot and the second time slot.

[0200] In an alternative embodiment of the present invention, the value of M and / or N is related to the distance between the first node and the second node; and / or, the value of M and / or N is pre-configured.

[0201] In an alternative embodiment of the present invention, there is at least one first reserved symbol after the last symbol for transmitting the first synchronization signal, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, there is at least one second reserved symbol after the last symbol for transmitting the second synchronization signal, and the at least one second reserved symbol is used for the first receiving unit 52 to continue receiving the second synchronization signal.

[0202] In an embodiment of the present invention, the first processing unit 53 in the device can be implemented by a central processing unit (CPU, Central Processing Unit), a digital signal processor (DSP, Digital Signal Processor), a microcontroller unit (MCU, Microcontroller Unit), or a field-programmable gate array (FPGA, Field-Programmable Gate Array) in practical applications; the first sending unit 51 and the first receiving unit 52 in the device can be implemented by a communication module (including: basic communication suite, operating system, communication module, standardized interface and protocol, etc.) and a transceiver antenna in practical applications.

[0203] An embodiment of the present invention also provides a clock synchronization device applied to a second node. Figure 10 It is a schematic diagram of the composition structure of the clock synchronization device provided by the embodiment of the present invention. Figure 2 ; As Figure 10 shown, the device includes: the second receiving unit 61, the second processing unit 63, and the second sending unit 62; wherein,

[0204] The second receiving unit 61 is configured to receive a first synchronization signal from a first node.

[0205] The second processing unit 63 is configured to obtain a first propagation delay based on the first synchronization signal.

[0206] The second sending unit 62 is configured to send the first propagation delay to a network device; and is further configured to send a second synchronization signal, the second synchronization signal is received by the first node, and the second synchronization signal is used for the first node to obtain a second propagation delay; wherein, both the first synchronization signal and the second synchronization signal are reflected by a target during transmission.

[0207] In an alternative embodiment of the present invention, the first synchronization signal and the second synchronization signal are within the same time slot; or, the first synchronization signal and the second synchronization signal are within different time slots.

[0208] In an alternative embodiment of the present invention, when the first synchronization signal and the second synchronization signal are within the same time slot, the second receiving unit 61 is configured to transmit the first synchronization signal in the first symbol within the time slot, the first symbol is N symbols from the last downlink symbol within the time slot as the starting point and from right to left, and N is a positive integer; and / or, the second sending unit 62 is configured to transmit the second synchronization signal in the second symbol within the time slot, the second symbol is M symbols from the first uplink symbol within the time slot as the starting point and from left to right, and M is a positive integer.

[0209] In an alternative embodiment of the present invention, when the first synchronization signal and the second synchronization signal are in different time slots, the second receiving unit 61 is configured to transmit the first synchronization signal in the first symbol within the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, where M is a positive integer; and / or, the second transmitting unit 62 is configured to transmit the second synchronization signal in the second symbol within the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, where M is a positive integer.

[0210] In an alternative embodiment of the present invention, there is at least one time slot interval between the first time slot and the second time slot.

[0211] In an alternative embodiment of the present invention, the values of M and / or N are related to the distance between the first node and the second node; and / or, the values of M and / or N are pre-configured.

[0212] In an alternative embodiment of the present invention, at least one first reserved symbol is further included after the last symbol for transmitting the first synchronization signal, and the at least one first reserved symbol is used for the second receiving unit 61 to continue receiving the first synchronization signal; and / or, at least one second reserved symbol is further included after the last symbol for transmitting the second synchronization signal, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

[0213] In the embodiment of the present invention, the second processing unit 63 in the device can be implemented by a CPU, a DSP, an MCU, or an FPGA in practical applications; the second receiving unit 61 and the second transmitting unit 62 in the device can be implemented by a communication module (including: a basic communication suite, an operating system, a communication module, a standardized interface, and a protocol, etc.) and a transceiver antenna in practical applications.

[0214] The embodiment of the present invention further provides a clock synchronization device applied to a network device. Figure 11 It is a schematic diagram of the composition structure of the clock synchronization device provided by the embodiment of the present invention. Figure 3 ; As Figure 11 shown, the device includes: a communication unit 71 and a third processing unit 72; where

[0215] The communication unit 71 is configured to receive the first transmission delay sent by the first node and the second propagation delay sent by the second node respectively.

[0216] The third processing unit 72 is configured to obtain a path propagation delay based on the first propagation delay and the second propagation delay, so as to eliminate the synchronization error.

[0217] In an alternative embodiment of the present invention, the third processing unit 72 is configured to perform a summing and averaging process on the first propagation delay and the second propagation delay to obtain the path propagation delay.

[0218] In an alternative embodiment of the present invention, the third processing unit 72 is configured to obtain a plurality of first time delays based on the first propagation delay and the second propagation delay received by the communication unit 71 multiple times, and determine the path propagation delay based on the first time delays.

[0219] In the embodiments of the present invention, the third processing unit 72 in the device can be implemented by a CPU, a DSP, an MCU, or an FPGA in practical applications; the communication unit 71 in the device can be implemented by a communication module (including: a basic communication suite, an operating system, a communication module, a standardized interface, and a protocol, etc.) and a transceiver antenna in practical applications.

[0220] It should be noted that: when the above clock synchronization device performs clock synchronization, only the above division of each program module is used as an example for illustration. In practical applications, the above processing can be allocated to different program modules according to needs, that is, the internal structure of the device is divided into different program modules to complete all or part of the above-described processing. In addition, the above-described clock synchronization device provided in the embodiment and the embodiment of the clock synchronization method belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be elaborated here.

[0221] Embodiments of the present invention further provide a communication device, Figure 12 which is a schematic diagram of the hardware composition structure of the communication device provided in the embodiments of the present invention. As Figure 12 shown, the communication device includes a memory 82, a processor 81, and a computer program stored on the memory 82 and executable on the processor 81.

[0222] Optionally, the communication device may specifically be the first node, the second node, or the network device in the embodiments of the present invention; when the processor 81 executes the program, it implements the steps of the clock synchronization method applied to the first node, the second node, or the network device in the embodiments of the present invention.

[0223] Optionally, the communication device further includes at least one communication component 84. Among them, each component in the communication device can be coupled together through a bus system 83. It can be understood that the bus system 83 is used to realize the connection and communication between these components. In addition to including a data bus, the bus system 83 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 12 all kinds of buses are labeled as the bus system 83.

[0224] It can be understood that the memory 82 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), an erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory), an electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), a ferromagnetic random access memory (FRAM, ferromagnetic random access memory), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM, Compact Disc Read-Only Memory); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM, Random Access Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as a static random access memory (SRAM, Static Random Access Memory), a synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory), a dynamic random access memory (DRAM, Dynamic Random Access Memory), a synchronous dynamic random access memory (SDRAM, Synchronous Dynamic Random Access Memory), a double data rate synchronous dynamic random access memory (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), an enhanced synchronous dynamic random access memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), a sync link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), a direct rambus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 82 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memories.

[0225] The methods disclosed in the embodiments of the present invention described above can be applied to or implemented by the processor 81. The processor 81 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above methods can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 81. The above-mentioned processor 81 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 81 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the methods disclosed in the embodiments of the present invention, it can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory 82. The processor 81 reads the information in the memory 82 and combines its hardware to complete the steps of the foregoing methods.

[0226] In an exemplary embodiment, the communication device may be implemented by one or more application-specific integrated circuits (ASICs, Application Specific Integrated Circuits), DSPs, programmable logic devices (PLDs, Programmable Logic Devices), complex programmable logic devices (CPLDs, Complex Programmable Logic Devices), FPGAs, general-purpose processors, controllers, MCUs, microprocessors, or other electronic components, and is used to execute the foregoing methods.

[0227] The embodiments of the present invention also provide a computer-readable storage medium, on which a computer program is stored.

[0228] Optionally, the computer-readable storage medium can be applied to the clock synchronization device in the embodiments of the present invention; then when the program is executed by the processor, it implements the steps of the clock synchronization method of the embodiments of the present invention applied to the first node, the second node, or the network device.

[0229] The methods disclosed in several method embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0230] The features disclosed in several product embodiments provided in the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0231] The features disclosed in several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0232] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed with each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0233] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0234] In addition, in each embodiment of the present invention, each functional unit can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in a unit; the above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0235] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: various media such as removable storage devices, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0236] Alternatively, if the above integrated units of the present invention are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present invention essentially or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as removable storage devices, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0237] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A clock synchronization method, characterized in that, The method includes: The first node sends a first synchronization signal, where the first synchronization signal is received by the second node, and the first synchronization signal is used for the second node to obtain a first propagation delay; The first node receives a second synchronization signal from the second node, obtains a second propagation delay based on the second synchronization signal, and sends the second propagation delay to the network device, where both the first synchronization signal and the second synchronization signal are reflected by the target during transmission.

2. The method according to claim 1, wherein The first synchronization signal and the second synchronization signal are in the same time slot; or, The first synchronization signal and the second synchronization signal are in different time slots.

3. The method according to claim 2, wherein In the case where the first synchronization signal and the second synchronization signal are in the same time slot, The first synchronization signal is transmitted in the first symbol within the time slot, and the first symbol is N symbols starting from the last downlink symbol within the time slot and moving from right to left, where N is a positive integer; and / or, The second synchronization signal is transmitted in the second symbol within the time slot, and the second symbol is M symbols starting from the first uplink symbol within the time slot and moving from left to right, where M is a positive integer.

4. The method according to claim 2, wherein In the case where the first synchronization signal and the second synchronization signal are in different time slots, The first synchronization signal is transmitted in the first symbol within the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, where M is a positive integer; and / or, the second synchronization signal is transmitted in the second symbol within the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, where M is a positive integer.

5. The method according to claim 4, wherein There is at least one time slot interval between the first time slot and the second time slot.

6. The method according to claim 3 or 4, characterized in that, The values of M and / or N are related to the distance between the first node and the second node; and / or, The values of M and / or N are pre-configured.

7. The method according to claim 3 or 4, characterized in that, After the last symbol for transmitting the first synchronization signal, there are at least one first reserved symbol, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, After the last symbol for transmitting the second synchronization signal, there are at least one second reserved symbol, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

8. A clock synchronization method, characterized in that, The method includes: The second node receives a first synchronization signal from the first node, obtains a first propagation delay based on the first synchronization signal, and sends the first propagation delay to the network device; The second node sends a second synchronization signal, and the second synchronization signal is received by the first node, and the second synchronization signal is used for the first node to obtain a second propagation delay; where both the first synchronization signal and the second synchronization signal are reflected by the target during transmission.

9. The method according to claim 8, wherein The first synchronization signal and the second synchronization signal are within the same time slot; or, The first synchronization signal and the second synchronization signal are within different time slots.

10. The method according to claim 9, characterized in that, In the case where the first synchronization signal and the second synchronization signal are within the same time slot, The first synchronization signal is transmitted in the first symbol within the time slot, and the first symbol is N symbols starting from the last downlink symbol within the time slot and moving from right to left, where N is a positive integer; and / or, The second synchronization signal is transmitted in the second symbol within the time slot, and the second symbol is M symbols starting from the first uplink symbol within the time slot and moving from left to right, where M is a positive integer.

11. The method according to claim 9, characterized in that, In the case where the first synchronization signal and the second synchronization signal are within different time slots, The first synchronization signal is transmitted in the first symbol within the first time slot, and the first symbol is one of the following: N symbols starting from the last downlink symbol within the first time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the first time slot and moving from left to right, where M is a positive integer; and / or, the second synchronization signal is transmitted in the second symbol within the second time slot, and the second symbol is one of the following: N symbols starting from the last downlink symbol within the second time slot and moving from right to left, where N is a positive integer; M symbols starting from the first uplink symbol within the second time slot and moving from left to right, where M is a positive integer.

12. The method according to claim 11, characterized in that There is at least one time slot interval between the first time slot and the second time slot.

13. The method according to claim 10 or 11, characterized in that, The value of M and / or N is related to the distance between the first node and the second node; and / or, The value of M and / or N is pre-configured.

14. The method according to claim 10 or 11, characterized in that, After the last symbol for transmitting the first synchronization signal, there are at least one first reserved symbol, and the at least one first reserved symbol is used for the second node to continue receiving the first synchronization signal; and / or, After the last symbol for transmitting the second synchronization signal, there are at least one second reserved symbol, and the at least one second reserved symbol is used for the first node to continue receiving the second synchronization signal.

15. A clock synchronization method, characterized in that, The method includes: The network device respectively receives the first propagation delay sent by the first node and the second propagation delay sent by the second node; The network device obtains the path propagation delay based on the first propagation delay and the second propagation delay to eliminate the synchronization error.

16. The method according to claim 15, characterized in that, The network device obtaining the path propagation delay based on the first propagation delay and the second propagation delay includes: The network device performs a summation and averaging process on the first propagation delay and the second propagation delay to obtain the path propagation delay.

17. The method according to claim 15, wherein The network device obtaining the path propagation delay based on the first propagation delay and the second propagation delay includes: The network device obtains multiple first time delays based on the first propagation delay and the second propagation delay received multiple times, and determines the path propagation delay based on the first time delays.

18. A clock synchronization device, characterized in that, The apparatus is applied to the first node, and the apparatus includes: a first sending unit, a first receiving unit, and a first processing unit; where, The first sending unit is configured to send a first synchronization signal, where the first synchronization signal is received by a second node, and the first synchronization signal is used for the second node to obtain a first propagation delay; The first receiving unit is configured to receive a second synchronization signal from the second node; The first processing unit is configured to obtain a second propagation delay based on the second synchronization signal; The first sending unit is further configured to send the second propagation delay to a network device, where both the first synchronization signal and the second synchronization signal are reflected by a target during transmission.

19. A clock synchronization device, characterized in that, The apparatus is applied to a second node, and the apparatus includes: a second receiving unit, a second processing unit, and a second sending unit; where The second receiving unit is configured to receive a first synchronization signal from a first node; The second processing unit is configured to obtain a first propagation delay based on the first synchronization signal; The second sending unit is configured to send the first propagation delay to a network device; and is further configured to send a second synchronization signal, where the second synchronization signal is received by the first node, and the second synchronization signal is used for the first node to obtain a second propagation delay; where both the first synchronization signal and the second synchronization signal are reflected by a target during transmission.

20. A clock synchronization device, characterized in that, The apparatus is applied to a network device, and the apparatus includes: a communication unit and a third processing unit; where The communication unit is configured to respectively receive a first propagation delay sent by a first node and a second propagation delay sent by a second node; The third processing unit is configured to obtain a path propagation delay based on the first propagation delay and the second propagation delay to eliminate a synchronization error.

21. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7, or; When the processor executes the program, it implements the steps of the method according to any one of claims 8 to 14, or; When the processor executes the program, it implements the steps of the method according to any one of claims 15 to 17.

22. A communication device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 7, or; When the processor executes the program, it implements the steps of the method according to any one of claims 8 to 14, or; When the processor executes the program, it implements the steps of the method according to any one of claims 15 to 17.

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