MIM capacitor, manufacturing method thereof, and semiconductor device

Abstract

The present invention discloses an MIM capacitor, a manufacturing method thereof, and a semiconductor device, and relates to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, and sequentially forming a first electrode layer, a first insulating layer, a second electrode layer, and a second insulating layer on the substrate; using a mask layer having a first electrode pattern as a mask, etching the first electrode layer, the first insulating layer, the second electrode layer, and the second insulating layer to form a first electrode in the first electrode layer; etching back the second insulating layer to remove an edge portion of the second insulating layer so that the second insulating layer exposes an edge portion of the second electrode layer; using the etched-back second insulating layer as a mask, etching the second electrode layer to remove an edge portion of the second electrode layer so that the second electrode layer forms a second electrode. Thus, only one photomask is needed to form the mask layer having the first electrode pattern, thereby reducing the manufacturing cost of the MIM capacitor and improving the manufacturing efficiency of the MIM capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MIM capacitor, a manufacturing method thereof, and a semiconductor device. Background Art

[0002] Capacitors are a common passive electronic component used in integrated circuits. They typically include metal oxide semiconductor capacitors, polysilicon-insulator-polysilicon capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors are widely used due to their low parasitic capacitance, low contact resistance, and relatively precise capacitance values.

[0003] Typically, MIM capacitors are manufactured in the back-end process of integrated circuits and consist of a first electrode, a second electrode, and an insulating layer located between the two. Current MIM capacitor manufacturing methods all involve first sequentially forming a first electrode layer, an insulating layer, and a second electrode layer. A first mask having a second electrode pattern is then formed to etch the second electrode layer to form the second electrode. Finally, a second mask having a first electrode pattern is then formed to etch the first electrode layer to form the first electrode. However, this requires the use of two different photomasks to form the first and second masks, respectively, resulting in higher manufacturing costs for MIM capacitors. Summary of the Invention

[0004] The present invention discloses a MIM capacitor, a manufacturing method thereof, and a semiconductor device, so as to solve the problem of high manufacturing cost of the MIM capacitor.

[0005] In a first aspect, the present invention discloses a method for manufacturing a MIM capacitor, comprising: providing a substrate, and sequentially forming a first electrode layer, a first insulating layer, a second electrode layer, and a second insulating layer on the substrate; using a mask layer having a first electrode pattern as a mask, etching the first electrode layer, the first insulating layer, the second electrode layer, and the second insulating layer to form a first electrode in the first electrode layer, and making the patterns of the first insulating layer, the second electrode layer, and the second insulating layer the same as the pattern of the first electrode; etching back the second insulating layer to remove an edge portion of the second insulating layer so that the second insulating layer exposes an edge portion of the second electrode layer; using the etched back second insulating layer as a mask, etching the second electrode layer to remove an edge portion of the second electrode layer so that the second electrode layer forms a second electrode.

[0006] In some embodiments of the present invention, the first insulating layer and the second insulating layer are made of the same material, and etching back the second insulating layer includes: etching back the first insulating layer and the second insulating layer using a wet etching process to remove edge portions of the second insulating layer and edge portions of the first insulating layer.

[0007] In some embodiments of the present invention, the material of the first insulating layer and the second insulating layer includes silicon nitride.

[0008] In some embodiments of the present invention, the first insulating layer and the second insulating layer are made of different materials, and etching the second electrode layer includes etching the second electrode layer and the first insulating layer using a dry etching process to remove edge portions of the second electrode layer and the first insulating layer. In some embodiments of the present invention, the thickness of the second insulating layer is greater than or equal to 1500 angstroms. In some embodiments of the present invention, the first electrode layer and the second electrode layer are made of the same material; the material of the first electrode layer and the second electrode layer includes titanium nitride.

[0009] In some embodiments of the present invention, the first electrode layer and the second electrode layer are made of different materials; the first electrode layer and the second electrode layer are made of different metals or metal compounds.

[0010] In some embodiments of the present invention, the base includes a semiconductor substrate, a circuit layer located on the semiconductor substrate, and a third insulating layer, and the third insulating layer includes a silicon carbonitride layer.

[0011] In a second aspect, the present invention discloses a MIM capacitor, which is manufactured using any of the manufacturing methods described above.

[0012] In a third aspect, the present invention discloses a semiconductor device comprising the MIM capacitor as described above.

[0013] The MIM capacitor, its manufacturing method and semiconductor device disclosed in the present invention include providing a substrate and sequentially forming a first electrode layer, a first insulating layer, a second electrode layer and a second insulating layer on the substrate; using a mask layer having a first electrode pattern as a mask, etching the first electrode layer, the first insulating layer, the second electrode layer and the second insulating layer so that the first electrode layer forms a first electrode, and the patterns of the first insulating layer, the second electrode layer and the second insulating layer are the same as the pattern of the first electrode; then etching back the second insulating layer to remove the edge portion of the second insulating layer so that the second insulating layer exposes the edge portion of the second electrode layer; then etching the second electrode layer using the etched back second insulating layer as a mask to remove the edge portion of the second electrode layer so that the second electrode layer forms a second electrode, so that only one mask is needed to form the mask layer having the first electrode pattern, thereby reducing the manufacturing cost of the MIM capacitor and improving the manufacturing efficiency of the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0015] Figures 1 to 6 Schematic diagram of the cross-sectional structure of a MIM capacitor in each step of a current method for manufacturing a MIM capacitor.

[0016] Figure 7 This is a flow chart of a method for manufacturing a MIM capacitor disclosed in an embodiment of the present invention.

[0017] Figures 8 to 15 Schematic diagram of the cross-sectional structure of the MIM capacitor in each step of the manufacturing method of the MIM capacitor disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, the current method for manufacturing a MIM capacitor is to first form a first electrode layer 11, a first insulating layer 12, a second electrode layer 13 and a second insulating layer 14 on a substrate 10, and then Figure 2 As shown, a first mask 15 having a second electrode pattern is formed on the second insulating layer 14, and then Figure 3 As shown, the second electrode layer 13 is etched to form a second electrode, and then as shown Figure 4 As shown, a protective layer 16 is formed on the second electrode, and then Figure 5As shown in FIG, a second mask 17 having a first electrode pattern is formed on the protective layer 16, and then as shown in FIG. Figure 6 As shown, the first electrode layer 11 and the first insulating layer 12 are etched to form the first electrode and the insulating layer. However, this requires the use of two different masks to respectively form the first mask 15 having the second electrode pattern and the second mask 17 having the first electrode pattern, resulting in a higher production cost of the MIM capacitor.

[0020] Based on this, the present invention discloses a manufacturing scheme for an MIM capacitor, wherein a mask layer having a first electrode pattern is first used as a mask to etch the first electrode layer, the first insulating layer, the second electrode layer, and the second insulating layer so that the first electrode layer forms a first electrode, and then the second insulating layer is etched so that the second insulating layer exposes the peripheral area of the second electrode layer, and then the second insulating layer is used as a mask to etch the second electrode layer so that the second electrode layer forms a second electrode, so that the MIM capacitor can be manufactured using only one mask, thereby reducing the manufacturing cost of the MIM capacitor.

[0021] As an optional implementation of the present disclosure, an embodiment of the present invention discloses a method for manufacturing a MIM capacitor, such as Figure 7 As shown, the method includes:

[0022] S101: providing a substrate, and sequentially forming a first electrode layer, a first insulating layer, a second electrode layer, and a second insulating layer on the substrate.

[0023] In some embodiments of the present invention, Figure 8 As shown, a substrate 10 is provided, which includes a semiconductor substrate 101, a circuit layer 102 located on the semiconductor substrate 101, and a third insulating layer 103. A first electrode layer 11, a first insulating layer 12, a second electrode layer 13, and a second insulating layer 14 are sequentially formed on the substrate 10. The deposition method of the first electrode layer 11, the first insulating layer 12, the second electrode layer 13, and the second insulating layer 14 can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the present invention is not limited to this. In other embodiments, the substrate 10 can also include only the semiconductor substrate 101, that is, the first electrode layer 11, the first insulating layer 12, the second electrode layer 13, and the second insulating layer 14 can also be sequentially formed on the semiconductor substrate 101.

[0024] The semiconductor substrate 101 includes at least one of a Si substrate, a Ge substrate, a SiGe substrate, a SiC substrate, a SiGeC substrate, an InAs substrate, a GaAs substrate, an InP substrate, or an InGaAs substrate. Furthermore, the semiconductor substrate 101 can be a single-layer structure formed by the above substrates, or a multi-layer structure formed by the above substrates. The circuit layer 102 includes multiple metal layers and a dielectric layer located between any two metal layers. Each metal layer includes traces or conductive planes, etc. The traces or conductive planes between different metal layers are electrically connected via vias penetrating the dielectric layer between the two metal layers. The metal layers include copper layers. The third insulating layer 103 includes a silicon carbonitride layer or a silicon dioxide layer, etc.

[0025] S102: Using the mask layer having the first electrode pattern as a mask, the first electrode layer, the first insulating layer, the second electrode layer and the second insulating layer are etched to form the first electrode in the first electrode layer, and the patterns of the first insulating layer, the second electrode layer and the second insulating layer are the same as the pattern of the first electrode.

[0026] In the embodiment of the present invention, a mask layer can be formed on the second insulating layer 14, and the mask layer is a photoresist layer. Then, a photomask having a first electrode pattern is used to expose and develop the photoresist layer to transfer the first electrode pattern to the photoresist layer, i.e., the mask layer. Then, Figure 9 As shown, the mask layer 20 having the first electrode pattern is used as a mask to etch the first electrode layer 11, the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14. After etching, the first electrode layer 11, the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14 are as shown in FIG. Figure 10 As shown, the first electrode layer 11 forms a first electrode, and the patterns of the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14 are the same as the pattern of the first electrode.

[0027] It should be noted that, in some embodiments of the present invention, a wet etching process can be used to etch the first electrode layer 11, the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14. Of course, the present invention is not limited to this. In other embodiments, a dry etching process can also be used to etch the first electrode layer 11, the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14.

[0028] S103: etching back the second insulating layer to remove an edge portion of the second insulating layer, so that the second insulating layer exposes an edge portion of the second electrode layer.

[0029] In some embodiments of the present invention, the second insulating layer 14 may be etched back using a wet etching process, such as Figure 11As shown, the second insulating layer 14 after etching back exposes the edge portion of the second electrode layer 13. On this basis, in some embodiments of the present invention, the materials of the first insulating layer 12 and the second insulating layer 14 can be the same, for example, the materials of the first insulating layer 12 and the second insulating layer 14 are both silicon nitride or silicon dioxide, etc., and when the second insulating layer 14 is etched back using a wet etching process, the first insulating layer 12 will also be etched back. Figure 11 As shown, the first insulating layer 12 after etching back also exposes the edge portion of the second electrode layer 13. Of course, the present invention is not limited to this, and in other embodiments, the second insulating layer 14 can also be etched using a dry etching process.

[0030] It should be noted that because the wet etching process is isotropic, the second insulating layer 14 needs to have a certain thickness to prevent the second insulating layer 14 from being completely etched. In some embodiments of the present invention, the thickness of the second insulating layer 14 ranges from greater than or equal to 1500 angstroms. Of course, the present invention is not limited to this. In other embodiments, the thickness of the second insulating layer 14 can be set according to actual needs, which will not be detailed here.

[0031] S104: using the etched-back second insulating layer as a mask, etching the second electrode layer to remove an edge portion of the second electrode layer, so that the second electrode layer forms a second electrode.

[0032] In the embodiment of the present invention, the second insulating layer 14 that exposes the edge portion of the second electrode layer 13 can be used as a mask to etch the second electrode layer 13 to remove the edge portion of the second electrode layer 13, so that the second electrode layer 13 is formed. Figure 12 The second electrode is shown, wherein the length of the second electrode in the direction parallel to the substrate 10 is smaller than the length of the first electrode in the direction parallel to the substrate 10 .

[0033] It should be noted that, during the dry etching of the second electrode layer 13, the second insulating layer 14 will also be etched. Therefore, after the dry etching of the second electrode layer 13, the second insulating layer 14 will be completely etched or Figure 12 As shown, a small amount of film layer remains.

[0034] In the embodiment of the present invention, by etching the first electrode first and then the second electrode from bottom to top, two masks are no longer needed to form the masks for the first and second electrodes. Only one mask is needed to form the mask for the first electrode, thereby reducing the production cost of the MIM capacitor. In addition, the production process of the MIM capacitor in the embodiment of the present invention is relatively simple, and the production efficiency of the MIM capacitor is relatively high.

[0035] In other embodiments of the present invention, the materials of the first insulating layer 12 and the second insulating layer 14 may also be different, for example, the materials of the first insulating layer 12 and the second insulating layer 14 are silicon nitride and silicon dioxide, respectively. Figure 13 As shown, the second insulating layer 14 can be etched back by a wet etching process or a dry etching process to remove the edge portion of the second insulating layer 14, so that the second insulating layer 14 exposes the edge portion of the second electrode layer 13. Then, the second insulating layer 14 after the etching back is used as a mask, and the second electrode layer 13 and the first insulating layer 12 are simultaneously etched by a dry etching process to remove the edge portion of the second electrode layer 13 and the edge portion of the first insulating layer 12, forming a structure as shown in FIG. Figure 12 The second electrode is shown.

[0036] Of course, the present invention is not limited to this. In other embodiments, Figure 13 The second insulating layer 14 after etching back is used as a mask. The second electrode layer 13 is etched by a wet etching process or a dry etching process to remove the edge portion of the second electrode layer 13 to form a Figure 14 The second electrode is formed by etching the first insulating layer 12 by a wet etching process or a dry etching process to remove the edge portion of the first insulating layer 12, thereby forming a second electrode as shown in FIG. Figure 12 The structure shown.

[0037] In some embodiments of the present invention, the first electrode layer 11 and the second electrode layer 13 are made of the same material. For example, the first electrode layer 11 and the second electrode layer 13 are both made of titanium nitride. Therefore, to avoid etching the first electrode layer 11 during etching of the second electrode layer 13, a dry etching process is preferably used to etch the second electrode layer 13. Of course, the present invention is not limited to this. In other embodiments, the first electrode layer 11 and the second electrode layer 13 may be made of different materials. For example, the first electrode layer 11 and the second electrode layer 13 may be made of different metals or metal compounds, such as copper, silver, and aluminum.

[0038] It should be noted that if Figure 15 As shown, because the conductive layer 30 on the top of the MIM capacitor needs to be electrically connected to the first electrode and the second electrode respectively through multiple vias 301, and the via 301 electrically connected to the first electrode cannot be electrically connected to the second electrode, the length of the second electrode in the direction parallel to the substrate 10 is smaller than the length of the first electrode in the direction parallel to the substrate 10.

[0039] It should also be noted that if Figure 15 As shown, after the second electrode layer 13 is etched to form the MIM capacitor, a protective layer 16 and a planarization layer 50 may be formed on the side of the MIM capacitor away from the substrate 10 , which will not be described in detail here.

[0040] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a MIM capacitor, which is manufactured using the manufacturing method of the MIM capacitor disclosed in any of the above embodiments.

[0041] As an optional implementation of the present disclosure, an embodiment of the present disclosure discloses a semiconductor device, which includes a MIM capacitor as disclosed in any of the above embodiments. The semiconductor device may include a device such as a radio frequency power supply or a filter.

[0042] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0043] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the scope of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be subject to the appended claims.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that: include: Providing a substrate, and sequentially forming a first electrode layer, a first insulating layer, a second electrode layer, and a second insulating layer on the substrate; Using the mask layer having the first electrode pattern as a mask, etching the first electrode layer, the first insulating layer, the second electrode layer, and the second insulating layer so that the first electrode layer forms a first electrode, and the patterns of the first insulating layer, the second electrode layer, and the second insulating layer are the same as the pattern of the first electrode; etching back the second insulating layer to remove an edge portion of the second insulating layer, so that the second insulating layer exposes an edge portion of the second electrode layer; The second electrode layer is etched using the etched-back second insulating layer as a mask to remove an edge portion of the second electrode layer, so that the second electrode layer forms a second electrode.

2. The method for manufacturing a MIM capacitor according to claim 1, wherein: The first insulating layer and the second insulating layer are made of the same material, and etching back the second insulating layer includes etching back the first insulating layer and the second insulating layer using a wet etching process to remove edge portions of the second insulating layer and the first insulating layer.

3. The method for manufacturing a MIM capacitor according to claim 2, wherein: The materials of the first insulating layer and the second insulating layer include silicon nitride; The thickness of the second insulating layer is greater than or equal to 1500 angstroms.

4. The method for manufacturing a MIM capacitor according to claim 1, wherein: The first insulating layer and the second insulating layer are made of different materials, and etching the second electrode layer includes etching the second electrode layer and the first insulating layer using a dry etching process to remove edge portions of the second electrode layer and the first insulating layer.

5. The method for manufacturing a MIM capacitor according to claim 1, wherein: The first insulating layer and the second insulating layer are made of different materials. After etching the second electrode layer, the method further includes: etching the first insulating layer to remove an edge portion of the first insulating layer.

6. The method for manufacturing a MIM capacitor according to claim 1, wherein: The first electrode layer and the second electrode layer are made of the same material; the first electrode layer and the second electrode layer are made of titanium nitride.

7. The method for manufacturing a MIM capacitor according to claim 1, wherein: The materials of the first electrode layer and the second electrode layer are different; the materials of the first electrode layer and the second electrode layer are different metals or metal compounds.

8. The method for manufacturing a MIM capacitor according to claim 1, wherein: The base includes a semiconductor substrate, a circuit layer located on the semiconductor substrate, and a third insulating layer, wherein the third insulating layer includes a silicon carbonitride layer.

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