Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a substrate and a driving signal line located on one side of the substrate, the display panel further comprises a first side face and a second side face which are oppositely arranged in the first direction, the first side face is provided with a plurality of first side edge wires, and the first side edge wires are correspondingly and electrically connected with the driving signal line; wherein the plurality of driving signal lines comprise a first signal line, and the first signal line extends to the second side surface. In the preparation process of the display panel, the first signal line can be led out from the second side surface to the outer side of the display panel, so that needle insertion detection can be performed on the first signal line on the outer side of the display panel, mechanical damage to the to-be-detected panel is avoided, probe abrasion is reduced, and detection comprehensiveness is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] In the field of display technologies, array testing is a crucial step in the manufacturing process of display panels. It can not only detect and repair potential quality problems, but also help optimize the production process through data analysis, thereby improving the yield rate, reducing production costs, and ultimately ensuring the quality and user experience of products.

[0003] In the prior art, for some specific display panels (such as borderless splicing display panels), currently, only the method of inserting needles on the back of the display panel can be used for array testing, but this is prone to problems such as panel damage, pin wear, and difficult probe contact. Therefore, a solution is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including a substrate and driving signal lines located on one side of the substrate. The display panel further includes a first side surface and a second side surface oppositely arranged along a first direction. A plurality of first side-walking lines are provided on the first side surface, and the first side-walking lines are correspondingly electrically connected to the driving signal lines; among them, among the plurality of driving signal lines, there is a first signal line that extends to the second side surface.

[0006] In a second aspect, an embodiment of the present application provides a display device, including the display panel provided in the first aspect.

[0007] In the embodiments of the present application, by setting the first signal line to extend to the second side surface, during the preparation process of the display panel, the first signal line can be led out to the outside of the display panel from the second side surface. In this way, when performing array testing on the display panel, the first signal line can be inserted with a needle on the outside of the display panel. Even if the pressure applied to the probe is too large, it will not cause mechanical damage to the display panel. Moreover, the first signal line can also be electrically connected to the test pads on the back side of the display panel that are not easily accessible, which is beneficial to improving the comprehensiveness of detection by inserting a needle into the first signal line.

[0008] In addition, after leading the first signal line to the outside of the display panel, a shorting bar can be provided on the outside of the display panel to short-circuit the first signal lines with the same potential, simplifying the test process, which is beneficial to improving the test efficiency, reducing the usage frequency of the probes, and further beneficial to reducing the wear of the probes and the manufacturing cost of the display panel. Description of the Drawings

[0009] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0010] Figure 1 It is a simplified structural schematic diagram of a display panel provided by an embodiment of the present application; Figure 2 It is a plan schematic diagram of a display panel provided by an embodiment of the present application; Figure 3 It is a partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 4 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 5 It is Figure 3 a cross-sectional schematic diagram along the tangent line NN' in Figure 6 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 7 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 8 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 9 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 10A It is Figure 9 a cross-sectional schematic diagram along the tangent line MM' in Figure 10B It is a structural schematic diagram of a display panel provided by an embodiment of the present application; Figure 11 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 12 It is Figure 11 a comparison schematic diagram of the first electrostatic discharge unit and the second electrostatic discharge unit in Figure 13 It is a schematic diagram of a pixel circuit provided by an embodiment of the present application; Figure 14 It is another partial enlarged schematic diagram of a display panel provided by an embodiment of the present application; Figure 15 It is a schematic diagram of a display device provided by an embodiment of the present application. Specific embodiments

[0011] To better understand the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0012] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0013] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0014] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A / and B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0015] In the field of display technology, array test is a crucial step in the manufacturing process of display panels. It can not only detect and repair potential quality problems, but also help optimize the production process through data analysis, thereby improving the yield rate, reducing production costs, and ultimately ensuring the quality of products and the user experience.

[0016] During the array test process, a test head with fine probes is usually used to contact specific pads or contacts on the substrate to be tested. A preset voltage or current signal is applied to the circuit to be tested through the probes to simulate the charge transfer situation under actual working conditions. Then, the actual output signal of the circuit is compared with the preset standard value to check whether there are defects in the circuit.

[0017] In the prior art, for some specific display panels, such as borderless splicing display panels, due to their lack of a lower step design, there is usually no fan-out line structure and shorting bar arranged on the lower step. Therefore, only the method of needle insertion on the back of the display panel can be used for array test.

[0018] The inventors of the present application have found through research that during the process of array test by needle insertion on the back of the display panel, the probes need to apply a certain pressure to ensure good electrical contact. Once the pressure is too large, it may cause mechanical damage to the substrate to be tested, such as scratches and depressions, which is likely to affect the subsequent processes.

[0019] Moreover, since there is no shorting bar designed, during the testing process, the number of times the probe is used will be very large, which is likely to cause wear of the probe. The worn probe may not be able to provide stable contact quality, easily affecting the accuracy of the test results. If the probe is replaced in a timely manner, it will also increase the test cost.

[0020] In addition, if the result of the display panel is relatively complex, there may also be a situation where the probe cannot reach the pad to be tested, easily affecting the comprehensiveness of the test.

[0021] In view of this, the embodiments of the present application provide a solution to solve the problems existing in the prior art.

[0022] Figure 1 It is a schematic diagram of a simplified structure of a display panel provided by an embodiment of the present application.

[0023] As Figure 1 shown, the embodiment of the present application provides a display panel 01. The display panel 01 includes a substrate 10 and a plurality of driving signal lines 20 located on one side of the substrate 10. The driving signal lines 20 can be used to transmit display signals, such as data signals, scan signals, clock signals, power supply signals, etc.

[0024] The display panel 01 further includes a first side C1 and a second side C2 oppositely arranged along the first direction Y. The first side C1 can be the "lower" edge of the display panel 01, and the second side C2 can be the "upper" edge of the display panel 01. A plurality of first side traces 30 are arranged on the first side C1, and the first side traces 30 are electrically connected to the driving signal lines 20 correspondingly.

[0025] The back surface of the display panel 01 can be bonded with a driving chip IC. The first side traces 30 can be used to transmit the display signals provided by the driving chip IC to the driving signal lines 20.

[0026] Exemplarily, in the direction Z perpendicular to the plane where the substrate 10 is located, the substrate 10 includes a first surface S1 and a second surface S2 arranged oppositely. The first side C1 and the second side C2 can connect the first surface S1 and the second surface S2.

[0027] Optionally, the driving signal lines 20 are located on the side of the first surface S1, and the driving chip IC is located on the side of the second surface S2.

[0028] On the first surface S1 side, a first pad B1 is provided. The distance between the first pad B1 and the first side surface C1 is less than the distance between it and the second side surface C2. That is, on the first surface S1 side, the first pad B1 is close to the first side surface C1. On the second surface S2 side, a second pad B2 is provided. The distance between the second pad B2 and the first side surface C1 is less than the distance between it and the second side surface C2. That is, on the second surface S2 side, the second pad B2 is close to the first side surface C1. The first side-walk routing 30 is used to connect the first pad B1 and the second pad B2. The first side-walk routing 30 can be electrically connected to the driving signal line 20 through the first pad B1 and electrically connected to the driving chip IC through the second pad B2.

[0029] Combined Figure 2 as shown Figure 2 is a schematic plan view of a display panel provided by an embodiment of the present application. Among the multiple driving signal lines 20, there is a first signal line 21, and the first signal line 21 extends to the second side surface C2. Of course, the first signal line 21 can be used to transmit display signals.

[0030] Exemplarily, the first signal line 21 extends along the first direction Y in the display panel 01.

[0031] In the embodiment of the present application, by setting the first signal line 21 to extend to the second side surface C2, during the preparation process of the display panel 01, the first signal line 21 can be led out from the second side surface C2 to the outside of the display panel 01. In this way, when performing array detection on the display panel 01, relevant tests can be performed on the outside of the display panel 01, and needles can be inserted on the outside pads connected to the first signal line 21. Even if the pressure applied to the probe is too large, it will not cause mechanical damage to the display panel 01. Moreover, the first signal line 21 can also be electrically connected to the pads to be tested on the second surface S2 side that are not easily accessible, which is beneficial to improving the comprehensiveness of detection by inserting needles into the first signal line 21.

[0032] In addition, after leading the first signal line 21 to the outside of the display panel 01, a shorting bar can be provided on the outside of the display panel 01 to short-circuit the first signal lines 21 with the same potential, simplifying the test process. Thereby, it is beneficial to improve the test efficiency, reduce the usage frequency of the probes, and further beneficial to reducing the wear of the probes and lowering the manufacturing cost of the display panel 01.

[0033] It should be noted that after the detection of the display panel 01 is completed, cutting can be performed at the second side surface C2 to remove the part outside the second side surface C2 of the display panel 01.

[0034] Figure 3 is a partial enlarged schematic view of a display panel provided by an embodiment of the present application.

[0035] In one embodiment of the present application, in combination with Figure 2 and Figure 3 As shown, the first signal line 21 extends along the first direction Y. The same first signal line 21 includes an electrically connected first segment 21A and a second segment 21B. The second segment 21B is located on the side of the first segment 21A close to the second side C2.

[0036] Among them, the first segment 21A and the second segment 21B are located in different film layers.

[0037] Exemplarily, in the display panel 01, the first signal line 21 can extend from the first side C1 to the second side C2. The part of the first signal line 21 close to the second side C2 is the second segment 21B, and the part close to the first side C1 is the first segment 21A.

[0038] In the embodiment of the present application, by setting the first segment 21A and the second segment 21B in different film layers, when the first signal line 21 is extended to the second side C2, the film layer of the second segment 21B can be flexibly set to avoid interference between the second segment 21B and other signal lines close to the second side C2 in the display panel 01, thereby facilitating the avoidance of short - circuit when the first signal line 21 crosses other signal lines close to the second side C2.

[0039] Optionally, please continue to refer to Figure 3 , the display panel 01 includes multiple rows of pixel circuits XD and multiple electrostatic discharge units ESD. Among the multiple rows of pixel circuits XD, there is a first - row pixel circuit XD1 adjacent to the second side C2, and there are no other pixel circuits XD between the first - row pixel circuit XD1 and the second side C2. The electrostatic discharge unit ESD is located on the side of the first - row pixel circuit XD1 close to the second side C2.

[0040] In the first signal line 21, the first segment 21A and the second segment 21B are connected through a first via K1, and the first via K1 is located on the side of the electrostatic discharge unit ESD close to the second side C2.

[0041] Based on this setting method, in the first signal line 21, the first segment 21A can extend through the pixel circuit XD and the electrostatic discharge unit ESD and then be electrically connected to the second segment 21B through the first via K1. In this way, it is beneficial to reduce the number of vias between the first segment 21A and the second segment 21B and reduce the setting difficulty of the first signal line 21.

[0042] In addition, the first signal line 21 can also be electrically connected to the pixel circuit XD and the electrostatic discharge unit ESD. If the first via K1 is located on the side of the electrostatic discharge unit ESD close to the second side C2, then the first segment 21A in the first signal line 21 can be set to be electrically connected to the pixel circuit XD and the electrostatic discharge unit ESD, which is beneficial to overall arranging the film layer where the first segment 21A is located according to the film layers of the pixel circuit XD and the electrostatic discharge unit ESD, so as to reduce the difficulty of electrically connecting the first segment 21A to the pixel circuit XD and the electrostatic discharge unit ESD while reasonably utilizing the space of the display panel 01.

[0043] Optionally, as Figure 4 shown, Figure 4 is a partially enlarged schematic diagram of another display panel provided by an embodiment of the present application. The display panel 01 further includes a plurality of light-emitting devices FG, and the light-emitting devices FG are correspondingly electrically connected to the pixel circuit XD (not shown in the figure), and the pixel circuit XD is used to drive the light-emitting devices FG to emit light. Among the plurality of light-emitting devices FG, there is a first row of light-emitting devices FG1, and the first row of light-emitting devices FG1 is adjacent to the second side C2, and no other light-emitting devices are provided between the first row of light-emitting devices FG1 and the second side C2.

[0044] The light-emitting devices FG can be located on the side of the electrostatic discharge unit ESD and the first signal line 20 away from the substrate 10. Optionally, the first row of light-emitting devices FG1 is located in the area where the electrostatic discharge unit ESD is located, or on the side of the electrostatic discharge unit ESD close to the second side C2. In this way, it is beneficial to increase the display area of the display panel 01, reduce the border area of the display panel 01, and thus is beneficial to realizing the narrow border of the display panel 01.

[0045] It should be noted that Figure 4 only shows that the first row of light-emitting devices FG1 is located on the side of the electrostatic discharge unit ESD close to the second side C2.

[0046] Optionally, as Figure 5 shown, Figure 5 is Figure 3 a cross-sectional schematic diagram along the tangent line NN' in. In the first signal line 21, the second segment 21B is located on the side of the first segment 21A close to the substrate 10.

[0047] Based on this setting method, the second segment 21B can be arranged by using the film layer between the first segment 21A and the substrate 10, which is beneficial to conveniently arranging the light-emitting devices FG in the area where the second segment 21B is located and improving the possibility of realizing the narrow border of the display panel 01.

[0048] Figure 6 is a partially enlarged schematic diagram of another display panel provided by an embodiment of the present application.

[0049] As shown Figure 6 In an embodiment of the present application, the display panel 01 includes a plurality of second signal lines 40. The second signal line 40 includes a first portion 41 extending along a second direction X, and the second direction X intersects with a first direction Y.

[0050] Exemplarily, the first direction Y is the column direction in the display panel 01, and the second direction X is the row direction in the display panel 01.

[0051] The first portion 41 includes a connected first sub-portion 411 and a second sub-portion 412. The first sub-portion 411 and the second sub-portion 412 are arranged along the second direction X. In a direction perpendicular to the plane of the substrate 10, the second sub-portion 412 overlaps with the second segment 21B. That is, the first portion 41 in the second signal line 40 can be located on a side of the electrostatic discharge unit ESD close to the second side surface C2, and the first portion 41 intersects with the second segment 21B in the first signal line 21.

[0052] Optionally, the second signal line 40 is on the same layer as the first segment 21A in the first signal line 21. In this way, both short circuits can be avoided, and the second signal line 40 and the first segment 21A can be fabricated using the same process, which is beneficial to simplifying the fabrication process of the display panel 01 and saving costs.

[0053] Exemplarily, the second signal line 40 includes at least one of a trigger signal line and a common potential signal line. The trigger signal line can be used to provide a trigger signal to a scan circuit in the display panel 01, and the common potential signal line can be used for anti-static.

[0054] Among them, in the first direction Y, the width W1 of the first sub-portion 411 is greater than the width W2 of the second sub-portion 412.

[0055] The inventors of the present application have found through research that in a direction perpendicular to the plane of the substrate 10, the parasitic capacitance generated by the overlap of the first signal line 21 and the second signal line 40 easily causes signal fluctuations on the first signal line 21. During the array detection process, the signal fluctuations on the first signal line 21 will affect the detection accuracy.

[0056] In view of this, in the embodiment of the present application, the width of the second sub-portion 412 in the second signal line 40 is set to be smaller, so that the area of the second sub-portion 412 can be smaller, which is beneficial to reducing the overlapping area between the second sub-portion 412 and the second segment 21B in a direction perpendicular to the plane of the substrate 10, thereby being beneficial to reducing the parasitic capacitance between the second sub-portion 412 and the second segment 21B and improving the accuracy of the signal on the first signal line 21.

[0057] Optionally, as Figure 6As shown, the second sub - part 412 includes a first connecting part 412A and a second connecting part 412B connected to the first sub - part 411. In the first direction Y, the first connecting part 412A is adjacent to the second connecting part 412B. That is, in the first direction Y, there is no hollow area between the first connecting part 412A and the second connecting part 412B, and the second sub - part 412 is a continuous structure.

[0058] Among them, the sum of the widths of the first connecting part 412A and the second connecting part 412B in the first direction Y can be the width W2 of the second sub - part 412 in the first direction Y. Of course, in the first direction Y, the width W1 of the first sub - part 411 is greater than the sum of the widths of the first connecting part 412A and the second connecting part 412B, that is, W2.

[0059] In this way, the second sub - part 412 is designed with a "necking - down" relative to the first sub - part 411, thereby reducing the overlapping area between the second sub - part 412 and the second section 21B of the second segment, and further reducing the parasitic capacitance between the first signal line 21 and the second signal line 40.

[0060] Optionally, as Figure 7 shown, Figure 7 is a partially enlarged schematic diagram of another display panel provided by an embodiment of the present application. The second sub - part 412 includes a first connecting part 412A and a second connecting part 412B connected to the first sub - part 411, and the first connecting part 412A and the second connecting part 412B are arranged along the first direction Y.

[0061] Among them, a first hollow part LK1 is provided between the first connecting part 412A and the second connecting part 412B. In the direction perpendicular to the plane where the substrate 10 is located, the first hollow part LK1 overlaps with the second section 21B of the first signal line 21. That is, in the first direction Y, the second sub - part 412 is a discontinuous structure.

[0062] Among them, the width of the first connecting part 412A in the first direction Y is W21, the width of the second connecting part 412B in the first direction Y is W22, and the sum of the widths of the first connecting part 412A and the second connecting part 412B in the first direction Y can be the width W2 of the second sub - part 412 in the first direction Y. Of course, in the first direction Y, the width W1 of the first sub - part 411 is greater than the sum of the widths of the first connecting part 412A and the second connecting part 412B, that is, W2. That is, W1 > W21 + W22.

[0063] In this way, by providing the first hollow part LK1 between the first connecting part 412A and the second connecting part 412B, the overlapping area between the second sub - part 412 and the second section 21B is reduced, and the parasitic capacitance between the first signal line 21 and the second signal line 40 is reduced.

[0064] Further, asFigure 7 As shown, in the second direction X, the width of the first hollow portion LK1 is not less than the width of the second segment 21B. In this way, the overlapping area between the first hollow portion LK1 and the second segment 21B can be increased to a large extent, so that the overlapping area between the second sub-portion 412 and the second segment 21B can be reduced to a large extent, and further the parasitic capacitance between the first signal line 21 and the second signal line 40 can be reduced.

[0065] Figure 8 It is a partially enlarged schematic diagram of another display panel provided by an embodiment of the present application.

[0066] In an embodiment of the present application, as Figure 8 shown, among the multiple second signal lines 40, there are a first type of signal line 401 and a second type of signal line 402. In the first direction Y, the width D1 of the first sub-portion 411 in the first type of signal line 401 is less than the width D2 of the first sub-portion 411 in the second type of signal line 402.

[0067] The second sub-portion 412 includes a first connection portion 412A and a second connection portion 412B connected to the first sub-portion 411, and the first connection portion 412A and the second connection portion 412B are arranged along the first direction Y.

[0068] Among them, in the second sub-portion 412 of the first type of signal line 401, the first connection portion 412A and the second connection portion 412B are connected in the first direction Y. That is, in the first direction Y, in the first type of signal line 401, there is no hollow area between the first connection portion 412A and the second connection portion 412B, and the second sub-portion 412 is a continuous structure, and the second sub-portion 412 is designed with a "necking down" relative to the first sub-portion 411.

[0069] Exemplarily, the first type of signal line 401 may be a trigger signal line STV in the display panel 01, and the trigger signal line STV is used to transmit a trigger signal to the scanning circuit in the display panel 01. The trigger signal line STV may include a portion extending along the first direction Y (not shown in the figure) and a portion extending along the second direction X (i.e., the first portion 41). The first portion 41 in the trigger signal line STV generally does not need to be set wide. Therefore, in the first portion 41 of the trigger signal line STV, the second sub-portion 412 is designed with a "necking down" relative to the first sub-portion 411 to reduce the parasitic capacitance between the trigger signal line STV and the first signal line 41.

[0070] In the second sub-portion 412 of the second type of signal line 402, a first hollow portion LK1 is provided between the first connection portion 412A and the second connection portion 412B. That is, in the first direction Y, in the second type of signal line 402, the second sub-portion 412 is a discontinuous structure, thereby reducing the overlapping area between the second sub-portion 412 and the first signal line 21.

[0071] Exemplarily, the second type of signal line 402 may be the common potential signal line COM in the display panel 01, and the common potential signal line COM may be circular (only a part extending along the second direction X near the second side C2 is schematically shown in the figure). Since the common potential signal line COM can be used to prevent external static electricity from entering the interior of the display panel 01, the common potential signal line COM can be set wider. Therefore, in the first part 41 of the common potential signal line COM, a first hollow portion LK1 can be provided to reduce the parasitic capacitance between the common potential signal line COM and the first signal line 41. In the embodiment of the present application, while reducing the overlapping area between the second sub-part 412 in the second signal line 40 and the second segment 21B in the first signal line 21, it is beneficial to increase the structural diversity of the display panel 01.

[0072] Figure 9 It is a partially enlarged schematic diagram of another display panel provided by the embodiment of the present application.

[0073] In an embodiment of the present application, as Figure 9 shown, the display panel 01 includes a plurality of second signal lines 40, and the second signal lines 40 include a first part 41 extending along the second direction X, and the second direction X intersects with the first direction Y.

[0074] Exemplarily, the first direction Y is the column direction in the display panel 01, and the second direction X is the row direction in the display panel 01.

[0075] Along the direction perpendicular to the plane where the substrate 10 is located, the first part 41 overlaps with the second segment 21B in the first signal line 21. That is, the first part 41 in the second signal line 40 can be located on the side of the electrostatic discharge unit ESD close to the second side C2, and the first part 41 intersects with the second segment 21B in the first signal line 21.

[0076] Exemplarily, the second signal line 40 includes at least one of a trigger signal line and a common potential signal line. The trigger signal line can be used to provide a trigger signal to the scan circuit in the display panel 01, and the common potential signal line can be used for anti-static to protect the electronic devices located away from the second side C2 of the common potential signal line.

[0077] The second segment 21B includes a first sub-segment 21B1, and the first sub-segment 21B1 is located on the side of the first part 41 of the second signal line 41 close to the second side C2, and the first sub-segment 21B1 can extend to the second side C2.

[0078] Combined with Figure 10A shown, Figure 10A For Figure 9A schematic cross-sectional view along the tangent line MM'. Along the direction Z perpendicular to the plane where the substrate 10 is located, the first sub-segment 21B1 overlaps with the conductive pad 50.

[0079] Exemplarily, as Figure 10A shown, the conductive pad 50 is located on the side of the second segment 21B close to the substrate 10, and a first insulating layer JC1 is provided between the conductive pad 50 and the first sub-segment 21B1. During the preparation of the display panel 01, the first insulating layer JC1 is prepared after the conductive pad 50 is prepared, and the first sub-segment 21B1 is prepared after the first insulating layer JC1 is completed.

[0080] Since the first insulating layer JC1 is prepared after the conductive pad 50, when the first insulating layer JC1 is prepared, the first insulating layer JC1 shows a phenomenon similar to climbing at the side wall position of the conductive pad 50, resulting in a reduction in the thickness of the part of the first insulating layer JC1 located at the side wall position and near the side wall of the conductive pad 50. For example, relative to the thickness of the first insulating layer JC1 at the flat position, as Figure 10A shown, the thickness of the part of the first insulating layer JC1 located on the side wall of the conductive pad 50 is reduced, and the thickness of the part of the first insulating layer JC1 located near the edge of the upper surface of the conductive pad 50 is also reduced. The place where the thickness of the first insulating layer JC1 is reduced at the side wall position and near the side wall of the conductive pad 50 is called the weak point P1.

[0081] As can be seen from the foregoing analysis, during the preparation of the display panel 01, after the array detection of the display panel 01 is completed, cutting will be performed at the second side C2, and cutting is likely to generate frictional static electricity.

[0082] In the embodiment of the present application, the first sub-segment 21B1 close to the second side C2 is set to overlap with the conductive pad 50. Then, after the frictional static electricity generated by cutting at the second side C2 enters the first sub-segment 21B1, it is easy to break down the weak point P1 in the first insulating layer JC1 and be released through the conductive pad 50, which is beneficial to avoiding the static electricity generated by cutting from being transmitted to the inside of the display panel 01 through the first signal line 21 and damaging the electronic devices inside the display panel 01.

[0083] Optionally, the conductive pad 50 is of a U-shaped structure, and the U-shaped opening faces the second direction X. In this way, in the direction Z perpendicular to the plane where the substrate 10 is located, the first sub-segment 21B1 can overlap with multiple side walls of the conductive pad 50, and there are more weak points where the first insulating layer JC1 is located between the first sub-segment 21B1 and the conductive pad 50, which is beneficial to realizing the release of static electricity in the first sub-segment 21B1 through the conductive pad 50.

[0084] Optionally, as Figure 10B shown, Figure 10BSchematic structural diagram of a display panel provided by an embodiment of the present application. The display panel 01 includes a substrate 10, an array layer 11 on one side of the substrate 10, and a light-emitting device layer 12. The light-emitting device layer 12 is located on the side of the array layer 11 away from the substrate 10. The array layer 11 includes a plurality of transistors T, and the plurality of transistors T form a pixel circuit XD (only one transistor in the pixel circuit is schematically shown in the figure). The transistor T includes a semiconductor layer GD, a gate Ga, and source-drain electrodes SD. The conductive pad 50 can be disposed on the same layer as the semiconductor layer GD of the transistor T, the second segment 21B can be disposed on the same layer as the gate GD of the transistor T, and the first segment 21A can be disposed on the same layer as the source-drain electrodes SD of the transistor T, so as to simplify the manufacturing process of the display panel 01 and reduce costs. Figure 11 Partial enlarged schematic diagram of another display panel provided by an embodiment of the present application. Figure 12 is Figure 11 A comparison schematic diagram between the first electrostatic discharge unit and the second electrostatic discharge unit in

[0085] In an embodiment of the present application, as shown in combination with Figure 11 and Figure 12 , the first signal line 21 includes a first data voltage signal line 211 and a second data voltage signal line 212. The electrostatic discharge unit ESD includes a discharge transistor Td. The plurality of electrostatic discharge units ESD include a first electrostatic discharge unit ESD1 and a second electrostatic discharge unit ESD2. The first data voltage signal line 211 is electrically connected to the first electrostatic discharge unit ESD1, and the second data voltage signal line 212 is electrically connected to the second electrostatic discharge unit ESD2.

[0086] Exemplarily, as shown in Figure 12 , the first electrostatic discharge unit ESD1 includes a discharge transistor Td1 and a discharge transistor Td2. The first pole of the discharge transistor Td1 is electrically connected to the first high-level signal line VGH1, the second pole is electrically connected to the first pole of the discharge transistor Td2 and the first data voltage signal line 211, and the gate is electrically connected to the first high-level signal line VGH1. The second pole of the discharge transistor Td2 is electrically connected to the first low-level signal line VGL1, and the gate is electrically connected to the first data voltage signal line 211.

[0087] The second electrostatic discharge unit ESD2 includes a discharge transistor Td3 and a discharge transistor Td4. The first pole of the discharge transistor Td3 is electrically connected to the second high-level signal line VGH2, the second pole is electrically connected to the first pole of the discharge transistor Td4 and the second data voltage signal line 212, and the gate is electrically connected to the second high-level signal line VGH2. The second pole of the discharge transistor Td4 is electrically connected to the second low-level signal line VGL2, and the gate is electrically connected to the second data voltage signal line 212.

[0088] Among them, the channel width R1 of the discharge transistor Td in the first electrostatic discharge unit ESD1 is not less than the channel width R2 of the discharge transistor Td in the second electrostatic discharge unit ESD2. That is, R1 > R2, or R1 = R2.

[0089] In the embodiment of the present application, setting the channel width R1 of the discharge transistor Td in the first electrostatic discharge unit ESD1 to be not less than the channel width R2 of the discharge transistor Td in the second electrostatic discharge unit ESD2 is beneficial to flexibly setting the positions of the first electrostatic discharge unit ESD1 and the second electrostatic discharge unit ESD according to the layout space of the display panel 01, which can not only increase the structural diversity of the display panel 01, but also improve the utilization rate of the layout space of the display panel 01.

[0090] In addition, as Figure 12 shown, along the arrangement direction of the first data voltage signal line 211 and the second data voltage signal line 212, the first electrostatic discharge unit ESD1 and the second electrostatic discharge unit ESD are staggered from each other, which is beneficial to making the discharge transistor Td in the first electrostatic discharge unit ESD1 closer to the first high-level signal line VGH1 and the first low-level signal line VGL1 to which it is electrically connected, and the discharge transistor Td in the second electrostatic discharge unit ESD2 closer to the second high-level signal line VGH2 and the second low-level signal line VGL2 to which it is electrically connected, which is beneficial to reducing the electrical connection difficulty between each discharge transistor Td and the high-level signal line or the low-level signal line.

[0091] Exemplarily, as Figure 13 shown, Figure 13 is a schematic diagram of a pixel circuit provided by an embodiment of the present application. The pixel circuit XD includes an amplitude modulation module 11 and a pulse width modulation module 12 that are electrically connected. The pixel circuit XD generates a driving current under the control of the amplitude modulation module 11 and the pulse width modulation module 12. The amplitude modulation module 11 can be used to control the amplitude of the driving current, and the pulse width modulation module 12 can be used to adjust the pulse width of the voltage applied to the first pole of the light-emitting device FG.

[0092] The amplitude modulation module 11 includes an amplitude driving transistor T11, an amplitude reset transistor T12, an amplitude data writing transistor T13, an anode reset transistor T14, a first compensation transistor T15, a first light-emitting control transistor T16, a second light-emitting control transistor T17, and a first capacitor C1. The amplitude reset transistor T12 and the first compensation transistor T15 can be double-gate transistors.

[0093] The first pole of the amplitude reset transistor T12 receives the first reset signal PAM_REF, the second pole is electrically connected to the gate of the amplitude driving transistor T11, and the gate is electrically connected to the scan line PAM_S1. The first pole of the amplitude data writing transistor T13 receives the amplitude data voltage PAM_Data, the second pole is electrically connected to the first pole of the amplitude driving transistor T11, and the gate is electrically connected to the scan line PAM_S2. The first pole of the anode reset transistor T14 receives the anode reset signal VREF, the second pole is electrically connected to the first pole of the light emitting device FG, and the gate is electrically connected to the scan line PAM_S2. The first pole of the light emitting device FG may be its anode, and the second pole of the light emitting device FG receives the power supply signal PVEE.

[0094] The first pole of the first compensation transistor T15 is electrically connected to the second pole of the amplitude driving transistor T11, the second pole is electrically connected to the gate of the amplitude driving transistor T11, and the gate is electrically connected to the scan line PAM_S2. The first pole of the first light control transistor T16 receives the power supply signal PVDD1, the second pole is electrically connected to the first pole of the amplitude driving transistor T11, and the gate is electrically connected to the first light control signal line PAM_EM. The first pole of the second light control transistor T17 is electrically connected to the second pole of the amplitude driving transistor T11, the second pole is electrically connected to the first pole of the light emitting device FG, and the gate is electrically connected to the first light control signal line PAM_EM. One plate of the first capacitor C1 is electrically connected to the gate of the amplitude driving transistor T11, and the other plate receives the power supply signal PVDD1.

[0095] The pulse width modulation module 12 includes a pulse width driving transistor T21, a pulse width reset transistor T22, a pulse width data writing transistor T23, a second compensation transistor T25, a third light control transistor T26, a fourth light control transistor T27, and a second capacitor C2. The pulse width reset transistor T22 and the second compensation transistor T25 may be double-gate transistors.

[0096] The first pole of the pulse width reset transistor T22 receives the second reset signal PWM_REF, the second pole is electrically connected to the gate of the pulse width driving transistor T21, and the gate is electrically connected to the scan line PWM_S1. The first pole of the pulse width data writing transistor T23 receives the pulse width data voltage PWM_Data, the second pole is electrically connected to the first pole of the pulse width driving transistor T21, and the gate is electrically connected to the scan line PWM_S2.

[0097] The first pole of the second compensation transistor T25 is electrically connected to the second pole of the pulse width driving transistor T21, the second pole is electrically connected to the gate of the pulse width driving transistor T21, the gate is electrically connected to the scanning line PWM_S2, the first pole of the third light-emitting control transistor T26 receives the power supply signal PVDD2, the second pole is electrically connected to the first pole of the pulse width driving transistor T21, and the gate is electrically connected to the second light-emitting control signal line PWM_EM. The first pole of the fourth light-emitting control transistor T27 is electrically connected to the second pole of the pulse width driving transistor T21, the second pole is electrically connected to the gate of the amplitude driving transistor T11, and the gate is electrically connected to the second light-emitting control signal line PWM_EM. One plate of the second capacitor C2 is electrically connected to the gate of the pulse width driving transistor T21, and the other plate receives the sweep signal SWEEP.

[0098] In the embodiment of the present application, the first data voltage signal line 211 can be used to transmit the pulse width data voltage PWM_Data, and the second data voltage signal line 212 is used to transmit the amplitude data voltage PAM_Data. That is, the first data voltage signal line 211 can be electrically connected to the first pole of the pulse width data writing transistor T23, and the second data voltage signal line 212 is electrically connected to the first pole of the amplitude data writing transistor T13.

[0099] Figure 14 It is a partial enlarged schematic diagram of another display panel provided by the embodiment of the present application.

[0100] In an embodiment of the present application, as Figure 14 shown, the display panel 01 includes sub-pixels 60 and a scanning circuit 70. The sub-pixels 60 include a pixel circuit XD and a light-emitting device (not shown in the figure) that are electrically connected. The scanning circuit 70 is used to transmit a scanning signal to the pixel circuit XD in the sub-pixels 60.

[0101] The first signal line 21 includes a first type of signal line 2101 and a second type of signal line 2102. The first type of signal line 2101 is electrically connected to the sub-pixels 60, and the second type of signal line 2102 is electrically connected to the scanning circuit 70.

[0102] Optionally, the first type of signal line 2101 is used to transmit a data voltage signal to the pixel circuit XD. The first type of signal line 2101 includes at least one of a signal line for transmitting the pulse width data voltage PWM_Data and a signal line for transmitting the amplitude data voltage PAM_Data. The second type of signal line 2102 can transmit a driving signal to the scanning circuit 70, such as a clock signal, a power supply signal, a reset signal, a trigger signal, etc.

[0103] Among them, the width L1 of the second segment 21B in the first type of signal line 2101 is smaller than the width L2 of the second segment 21B in the second type of signal line 2102.

[0104] In the embodiment of the present application, the width L2 of the second segment 21B in the second type of signal line 2102 is set to be relatively large. While reasonably utilizing the layout space of the display panel 01, the voltage drop of the second type of signal line 2102 can be reduced, which is beneficial to improving the accuracy of the signal on the second type of signal line 2102.

[0105] Figure 15 It is a schematic diagram of a display device provided by an embodiment of the present application.

[0106] An embodiment of the present application provides a display device 02, as Figure 15 shown. The display device 02 includes the display panel 01 provided in the above embodiment. The display device 02 provided by the embodiment of the present invention can be a tiled display device, such as a borderless tiled display device. The tiled display device includes at least two of the above display panels 01 to be applicable to a large-screen display device with a display function.

[0107] Exemplarily, as Figure 15 shown, at least two display panels 01 can be arranged along the second direction X, or at least two display panels 01 can be arranged along the first direction Y, but it is not limited thereto. The embodiment of the present invention does not make specific limitations in this regard.

[0108] In the display device 02, the first signal line 21 is set to extend to the second side C2. Then, during the preparation process of the display panel 01, the first signal line 21 can be led out from the second side C2 to the outside of the display panel 01. In this way, during the array detection of the display panel 01, the first signal line 21 can be probed on the outside of the display panel 01. Even if the pressure applied to the probe is too large, it will not cause mechanical damage to the display panel 01. Moreover, the first signal line 21 can also be electrically connected to a test pad that is not easily accessible on the second surface S2 side, which is beneficial to improving the comprehensiveness of detection by probing the first signal line 21.

[0109] In addition, after leading the first signal line 21 to the outside of the display panel 01, a shorting bar can be provided on the outside of the display panel 01 to short-circuit the first signal lines 21 with the same potential, simplifying the test process. Thereby, it is beneficial to improve the test efficiency, reduce the usage frequency of the probe, and further beneficial to reducing the wear of the probe and the manufacturing cost of the display device 02.

[0110] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A display panel, characterized in that, Comprising: A substrate; Multiple driving signal lines located on one side of the substrate; The display panel includes a first side and a second side oppositely arranged in a first direction. Multiple first side-walk lines are provided on the first side, and the first side-walk lines are correspondingly electrically connected to the driving signal lines; Among them, multiple driving signal lines include a first signal line, and the first signal line extends to the second side.

2. The display panel according to claim 1, wherein The first signal line extends in the first direction. The first signal line includes a first section and a second section that are electrically connected. The second section is located on the side of the first section closer to the second side; Among them, the first section and the second section are located in different film layers.

3. The display panel according to claim 2, wherein The second section is located on the side of the first section closer to the substrate.

4. The display panel according to claim 2, wherein The display panel includes multiple rows of pixel circuits and multiple electrostatic discharge units. Among the multiple rows of pixel circuits, there is a first row of pixel circuits adjacent to the second side. The electrostatic discharge unit is located on the side of the first row of pixel circuits closer to the second side; The first section and the second section are connected by a first via hole, and the first via hole is located on the side of the electrostatic discharge unit closer to the second side.

5. The display panel according to claim 2, wherein The display panel includes multiple second signal lines. The second signal line includes a first part extending in a second direction, and the second direction intersects with the first direction; The first part includes a first sub-part and a second sub-part that are connected. In a direction perpendicular to the plane where the substrate is located, the second sub-part overlaps with the second section; In the first direction, the width of the first sub-part is greater than the width of the second sub-part.

6. The display panel according to claim 5, characterized in that, The second sub-part includes a first connection part and a second connection part connected to the first sub-part. In the first direction, the first connection part is adjacent to the second connection part.

7. The display panel according to claim 5, wherein The second sub-part includes a first connection part and a second connection part connected to the first sub-part. The first connection part and the second connection part are arranged along the first direction; Among them, a first hollow part is provided between the first connection part and the second connection part. In a direction perpendicular to the plane where the substrate is located, the first hollow part overlaps with the second section.

8. The display panel according to claim 7, wherein In the second direction, the width of the first hollow part is not less than the width of the second section.

9. The display panel according to claim 5, characterized in that, Multiple second signal lines include a first type of signal line and a second type of signal line. In the first direction, the width of the first sub-part in the first type of signal line is less than the width of the first sub-part in the second type of signal line; The second sub-part includes a first connection part and a second connection part connected to the first sub-part. The first connection part and the second connection part are arranged along the first direction; Among them, in the second sub-part of the first type of signal line, the first connection part is adjacent to the second connection part in the first direction; in the second sub-part of the second type of signal line, a first hollow part is provided between the first connection part and the second connection part.

10. The display panel according to claim 5, characterized in that, The first part of the second signal line is on the same layer as the first section of the first signal line.

11. The display panel according to claim 2, wherein, The display panel includes a plurality of second signal lines. The second signal lines include a first portion extending in a second direction, and the second direction intersects with the first direction. Along a direction perpendicular to the plane of the substrate, the first portion overlaps with the second segment. The second segment includes a first sub-segment. The first sub-segment is located on a side of the first portion close to the second side surface. Along a direction perpendicular to the plane of the substrate, the first sub-segment overlaps with the conductive pad.

12. The display panel according to claim 11, wherein The conductive pad is located on a side of the second segment close to the substrate.

13. The display panel according to claim 4, wherein The first signal lines include a first data voltage signal line and a second data voltage signal line. The electrostatic discharge unit includes a discharge transistor. Among the plurality of electrostatic discharge units, there are a first electrostatic discharge unit and a second electrostatic discharge unit. The first data voltage signal line is electrically connected to the first electrostatic discharge unit, and the second data voltage signal line is electrically connected to the second electrostatic discharge unit. Wherein, the channel width of the discharge transistor in the first electrostatic discharge unit is not less than the channel width of the discharge transistor in the second electrostatic discharge unit.

14. The display panel according to claim 1, wherein The display panel includes sub-pixels and a scanning circuit. The scanning circuit is configured to transmit a scanning signal to the sub-pixels. The first signal lines include a first type of signal line and a second type of signal line. The first type of signal line is electrically connected to the sub-pixels, and the second type of signal line is electrically connected to the scanning circuit. Wherein, the line width of the second segment in the first type of signal line is less than the line width of the second segment in the second type of signal line.

15. A display device, characterized in that, Comprising the display panel according to any one of claims 1-14.

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