Heterojunction battery structure and preparation method

Abstract

The invention provides a heterojunction cell structure and a preparation method, and relates to the technical field of solar cells. The heterojunction cell structure comprises a silicon substrate with a pyramid suede formed on the surface; wherein the height of a pyramid in the pyramid suede is 0.6 mu m-1. 2 mu m, the width of the pyramid is 0.8 mu m-1. 5 mu m, the reflectivity of the silicon substrate surface forming the pyramid suede is 9%-12%, and the problems that an existing heterojunction battery is high in amorphous passivation parasitic absorption, the current density of the battery is low, and the passivation is low when a polycrystalline silicon passivation structure is introduced are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a heterojunction cell structure and a preparation method thereof. Background Art

[0002] The theoretical limit efficiency of HJT cells reaches 28.12%. HJT cells benefit from their excellent passivation performance, especially the low J0 value achieved by using an amorphous silicon layer. However, the optical performance of HJT cells is poor, mainly due to the parasitic absorption of the amorphous silicon layer, which becomes an obstacle to further improving efficiency. Using a doped polysilicon / tunneling oxide passivation contact structure (TOPCON technology) on a velvety silicon substrate to replace hydrogenated amorphous silicon passivation is one of the ideas to solve the problem.

[0003] However, the existing velvet surface introduces a doped polysilicon / tunneling oxide layer passivation contact structure. The pyramid structure on the silicon-based velvet surface is relatively large. Due to the difference in the resistance of the tunneling oxide layer to phosphorus penetration at different positions, the top, side and bottom of the pyramid structure cannot obtain uniform high-quality tunneling oxide layer chemical passivation and N+ internal expansion field passivation, which will lead to the problem of increased battery current density but reduced passivation. Summary of the invention

[0004] In order to overcome the above technical defects, the purpose of the present invention is to provide a heterojunction battery structure and preparation method to solve the problems of high amorphous parasitic absorption and low battery current density of existing heterojunction batteries without losing battery passivation. The invention discloses a heterojunction battery structure, comprising a silicon base with a pyramid velvet surface formed on the surface; wherein the pyramids in the pyramid velvet surface are 0.6μm-1.2μm high and 0.8μm-1.5μm wide, and the surface reflectivity of the silicon base forming the pyramid velvet surface is 9%-12%.

[0005] Preferably, it also includes a front passivation structure located on the pyramid velvet surface; The front passivation structure includes an N+ inner expansion layer, a tunneling oxide layer, and a phosphorus-doped polycrystalline silicon oxide layer; The phosphorus-doped polycrystalline silicon oxide layer has gradient doping, wherein the side away from the silicon base is highly doped with phosphorus and low doped with oxygen, and the side close to the silicon base is low doped with phosphorus and high doped with oxygen.

[0006] Preferably, the phosphorus-doped polycrystalline silicon oxide layer is formed by annealing an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer, and a phosphorus-doped amorphous silicon layer deposited on a silicon substrate surface.

[0007] Preferably, it also includes a polishing surface located on the silicon base away from the pyramid velvet surface, and a back passivation structure formed on the polishing surface; The back passivation structure includes a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide silicon layer deposited on the surface of the silicon substrate.

[0008] The present invention also discloses a method for manufacturing a heterojunction battery, which manufactures the heterojunction battery structure described in any one of the above, and includes: Obtain a clean and polished silicon substrate, and texture the front surface of the silicon substrate to form a pyramid texture surface; Sequentially prepare a tunneling oxide layer, an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer, and a phosphorus-doped amorphous silicon layer on the front surface of the silicon substrate with a pyramid texture surface; anneal to activate the diffusion of phosphorus atoms into the silicon substrate to form a front passivation structure; Clean and remove the oxide layer generated by annealing on the surface of the silicon substrate, and sequentially prepare a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide silicon layer on the polished surface of the back of the silicon substrate to form a back passivation structure; Deposit transparent conductive films on the front and back surfaces of the silicon substrate respectively, and prepare metal electrodes to form a heterojunction battery.

[0009] Preferably, the front surface of the silicon substrate is textured and etched multiple times to form a pyramid texture surface, wherein the height of the pyramids in the pyramid texture surface is 0.6 μm - 1.2 μm, the width is 0.8 μm - 1.5 μm, and the reflectivity is 9% - 12%.

[0010] Preferably, a first texturing solution is used to perform the first texturing on the front surface of the silicon substrate, and the first to solution includes first potassium hydroxide and a first texturing additive; After cleaning, a second texturing solution is used to perform the second texturing on the front surface of the silicon substrate; wherein the second texturing solution includes second potassium hydroxide and a second texturing additive, and the second texturing solution has a high temperature, a high concentration of alkali, and a high concentration of additive compared with the first texturing solution; the concentration of the first texturing solution is 0.5% - 3%, and the concentration of the first potassium hydroxide is 1% - 5%; the concentration of the second texturing solution is 3% - 5%, and the concentration of the second potassium hydroxide is 5% - 10%; After cleaning, a weak etching system formed by hydrofluoric acid, hydrochloric acid, and ozone is used to etch the front surface of the silicon substrate to form the pyramid texture surface.

[0011] Preferably, a plate deposition method is used to prepare the tunneling oxide layer, the intrinsic amorphous silicon layer, the oxygen-doped amorphous silicon layer, the phosphorus-doped amorphous silicon layer, the hydrogenated intrinsic amorphous silicon layer, the boron-doped amorphous silicon layer, and / or the boron-doped microcrystalline carbon oxide silicon layer.

[0012] Preferably, an inert gas is used as a dilution gas when preparing the tunneling oxide layer.

[0013] Preferably, the transparent conductive film includes one or more combinations of ITO, IWO, TiO, TiN, AZO; the film thickness of the transparent conductive film is 50 nm - 150 nm; And / or, the metal electrode comprises one or more combinations of silver, copper, aluminum, and tin, the metal electrode width is 10um-50um, and the metal electrode height is 5um-20um; And / or, the silicon base is an N-type silicon base, including one of a Czochralski single crystal and a cast single crystal.

[0014] Compared with the prior art, the above technical solution has the following beneficial effects: 1. The heterojunction battery structure and preparation method thereof formed by the application of nano-scale small pyramid velvet morphology are limited to 0.6μm-1.2μm and 0.8μm-1.5μm in width, and the spatial distribution uniformity of the pyramid morphology is optimized, and the subsequent deposition and annealing uniformity of the film layer at the bottom of the pyramid spire and the edge of the pyramid are improved, the passivation is improved, and the parasitic absorption is reduced, so as to solve the problem of high amorphous parasitic absorption on the surface of the existing battery and low battery current density, and at the same time, the battery passivation is not affected; 2. After annealing on the front side of the heterojunction battery of the present application, a phosphorus-doped polycrystalline silicon oxide layer with gradient doping is formed, which slows down the internal expansion speed of phosphorus atoms, improves the uniformity of tunneling oxygen pinholes on the velvet surface and the internal expansion uniformity, and the introduction of oxygen by phosphorus-doped polycrystalline silicon further reduces the parasitic absorption of the film layer without affecting the contact resistance, thereby improving the battery current density; 3. Plate-type coating equipment is used to deposit each layer on one side, with fast deposition rate, easy in-situ doping, easy crystallization, no wrap-around plating, and improved preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the heterojunction battery structure of Embodiment 1 and Embodiment 2 of a heterojunction battery structure and a preparation method of the present invention; Figure 2 It is a schematic structural diagram of a silicon substrate with a pyramid velvet surface in a heterojunction battery according to Embodiment 1 and Embodiment 2 of a heterojunction battery structure and a preparation method of the present invention; Figure 3 It is a schematic diagram of the structure of the heterojunction battery before annealing according to Embodiment 1 and Embodiment 2 of a heterojunction battery structure and a preparation method of the present invention; Figure 4 It is a schematic diagram of the structure of the heterojunction battery after annealing according to Embodiment 1 and Embodiment 2 of a heterojunction battery structure and a preparation method of the present invention; Figure 5 This is a flow chart of the preparation method of Example 2 of a heterojunction battery structure and preparation method described in the present invention.

[0016] Reference numerals: 1 - Silicon substrate; 2 - N+ inner diffusion layer; 3 - Tunneling oxide layer; 4 - Phosphorus-doped polysilicon oxide layer; 41 - Intrinsic amorphous silicon layer; 42 - Oxygen-doped amorphous silicon layer; 43 - Phosphorus-doped amorphous silicon layer; 5 - Hydrogenated intrinsic amorphous silicon layer; 6 - Boron-doped amorphous silicon layer, boron-doped microcrystalline carbon oxide silicon layer; 7 - Transparent conductive film; 8 - Metal electrode; 9 - Oxide layer formed by annealing. Detailed implementation manners

[0017] The advantages of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

[0018] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0019] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "said" used in the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0020] Embodiment 1: This embodiment provides a heterojunction battery structure. Aiming at the problems of high amorphous parasitic absorption and low battery current density in HJT batteries, specifically, as Figures 1-4 , the heterojunction battery structure can include, from top to bottom: a front metal electrode, a transparent conductive film, phosphorus-doped polysilicon, a tunneling oxide layer, an N+ inner diffusion layer / region, a nanoscale small pyramid texture, a silicon substrate, a back alkaline-etched tower base texture, an intrinsic hydrogenated amorphous silicon, a boron-doped hydrogenated amorphous silicon, a transparent conductive film, and a back metal electrode. Specifically, the nanoscale small pyramid texture is the pyramid texture formed on the surface of the silicon substrate.

[0021] Specifically, the heterojunction battery structure includes a silicon substrate with a pyramid texture formed on its surface (see Figure 2); wherein the height of the pyramids in the pyramid texture is 0.6 μm - 1.2 μm, and the width is 0.8 μm - 1.5 μm, and the reflectivity of the silicon-based surface forming the pyramid texture is 9% - 12%. In the solution of this application, considering that the problems of high amorphous parasitic absorption and low battery current density in the battery are due to the introduction of the TOPCON passivation (doped polysilicon / tunneling oxide layer) contact structure by the texture. Since the pyramids on the texture are relatively large, the tips, edges, and bottoms of the pyramids occupy different spaces, and the tunneling oxide layers at different positions have different phosphorus penetration resistances. Especially, the tunneling oxide layers at the tips and bottoms are easily damaged by phosphorus atoms during high-temperature annealing, and the phosphorus penetration degree is uneven. Therefore, a nano-scale small pyramid texture morphology is prepared to optimize this problem. The formed pyramids are limited to be 0.6 μm - 1.2 μm in height and 0.8 μm - 1.5 μm in width. The distance from the tip to the bottom of the pyramid is nano-scale, optimizing the spatial distribution uniformity of the pyramid morphology, improving the deposition and annealing uniformity of the subsequent film layers at the tips, edges, and bottoms, enhancing passivation, and reducing parasitic absorption.

[0022] In this embodiment, the above-mentioned pyramid texture morphology is used to reduce the difference in phosphorus penetration resistance of the tunneling oxide layers at different positions on the silicon-based substrate and improve the phosphorus penetration uniformity; it can be understood that the above-mentioned limitation of the pyramid texture morphology can be formed by multiple texturing and etching, and / or by controlling the specific process parameters of texturing, as shown in the following preparation method.

[0023] In a preferred embodiment, the heterojunction battery structure further includes a front passivation structure (i.e., the above-mentioned phosphorus-doped polysilicon layer, tunneling oxide layer, N+ inner diffusion layer) located on the pyramid texture; the front passivation structure forms a phosphorus-doped polysilicon oxide layer with gradient doping, where the side far from the silicon-based substrate is highly doped with phosphorus and lowly doped with oxygen, and the side close to the silicon-based substrate is lowly doped with phosphorus and highly doped with oxygen. The introduction of oxygen by phosphorus-doped polysilicon further reduces the parasitic absorption of the film layer while not affecting the surface contact resistance, and improves the battery current density.

[0024] Specifically, the phosphorus-doped polysilicon oxide layer is formed by annealing an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer, and a phosphorus-doped amorphous silicon layer deposited on the silicon-based surface. It can be understood that high-temperature oxidation annealing is used to crystallize the intrinsic amorphous silicon, oxygen-doped amorphous silicon, and phosphorus-doped amorphous silicon into polysilicon, and at the same time activate the phosphorus atoms in the phosphorus-doped amorphous silicon to form phosphorus-doped polysilicon. The phosphorus atoms first advance to the polysilicon oxide layer (as a buffer layer to slow down the phosphorus advancement speed), then to the intrinsic polysilicon layer (further slowing down the phosphorus advancement speed), and finally to the tunneling oxide layer and enter the silicon-based substrate to form tunneling pinholes, forming an N+ inner diffusion layer. During this process, by slowing down the inner diffusion speed of phosphorus atoms multiple times, the uniformity of the tunneling oxygen pinholes at the "tips, valleys, and edges" on the texture and the inner diffusion uniformity of phosphorus atoms are improved, the passivation quality is enhanced, the parasitic absorption of the film layer is further reduced, and the battery current density is improved.

[0025] In a preferred embodiment, the phosphorus-doped polysilicon layer / tunneling oxide layer / N+ inner expansion layer formed by annealing, the phosphorus-doped polysilicon layer thickness: 15nm-300nm, the effective doping concentration: 5E19cm -3 -1E22cm -3 ; Tunneling oxide layer thickness: 0.5nm-3nm, tunneling silicon oxide & polysilicon thickness ratio 1:20-1:300, N+ inner expansion layer depth: 20nm-100nm.

[0026] In this embodiment, it also includes a polishing surface located on the silicon substrate away from the pyramid velvet surface, and a back passivation structure formed on the polishing surface (the intrinsic hydrogenated amorphous layer and the boron-doped hydrogenated amorphous silicon layer as described above); it can be understood that the "front" and "back" are only used to distinguish the surfaces on the silicon substrate that are opposite and used to deposit various layers. The back passivation structure includes a hydrogenated intrinsic amorphous silicon layer (i: a-Si), a boron-doped amorphous silicon layer (P: a-Si), and a boron-doped microcrystalline carbon oxide silicon layer (P-uc-SiO x C y ).

[0027] Specifically, the polishing surface has an alkali polishing tower base morphology. As a preferred embodiment, the surface reflectivity is 35%-45%, and the tower base size is 5um-15um. Further preferably, the boron-doped amorphous silicon layer includes a layer of boron-doped amorphous silicon and a layer of boron-doped carbon-oxidized silicon microcrystals. The intrinsic hydrogenated amorphous silicon thickness is 3nm-10nm, the boron-doped amorphous silicon thickness is 3nm-10nm, the boron-doped carbon-oxidized silicon microcrystal thickness is 10nm-30nm, and the doping concentration of the boron-doped amorphous silicon is 1E19. -3 -5E19 -3 , Boron-doped silicon oxycarbide microcrystal doping concentration: 5E19 -3 -2E20cm -3 .

[0028] In this embodiment, it also includes a transparent conductive film deposited on the front and back sides and a prepared electrode. The transparent conductive film can be one or more combinations of ITO (indium tin oxide), IWO (tungsten-doped indium oxide), TiO (titanium oxide), TiN (titanium nitride), AZO (aluminum-doped zinc oxide), etc., with a film thickness of 50nm-150nm and a square resistance of 40-200.

[0029] Optionally, the preparation of the metal electrode: the front metal electrode includes one or more combinations of silver, copper, aluminum, and tin, the metal electrode width is 10um-50um, and the metal electrode height is 5um-20um.

[0030] In this embodiment, the silicon substrate is an N-type silicon substrate, including one of a Czochralski single crystal and a cast single crystal, so as to realize the N+ inner expansion layer formed by the phosphorus atoms in the silicon substrate.

[0031] Example 2: This embodiment also provides a method for manufacturing a heterojunction battery, for manufacturing the heterojunction battery structure described in the first embodiment above, refer to Figure 5 , including the following steps: S10: Obtain a clean and polished silicon substrate, and texture the front surface of the silicon substrate to form a pyramid texture surface; Specifically, the silicon substrate can be an N-type silicon substrate, which can include one of Czochralski single crystal and ingot single crystal.

[0032] Specifically, first use wet cleaning to obtain a clean silicon wafer surface. Specific operation steps example: Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the silicon wafer surface to remove dirt on the silicon wafer surface. Process temperature: 55°C - 70°C, process time: 2 min - 5 min; Use water washing to remove surface chemical residues and dirt, washing time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (1%-10%) and additive (0.5%-5%) to polish the silicon wafer surface to form an alkaline polishing tower base morphology and remove cutting damage. Process temperature: 60°C - 85°C, process time: 3 min - 5 min; Use water washing to remove surface chemical residues and dirt, washing time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the silicon wafer surface to remove additive residues. Process temperature: 55°C - 70°C, process time: 2 min - 5 min; Use water washing to remove surface chemical residues and dirt, washing time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%) and O3 (10 ppm - 50 ppm) to clean the silicon wafer surface. At the same time, the weak etching system of O3 and HF lubricates the silicon wafer surface and reduces burr defects on the silicon wafer surface, (more conducive to amorphous silicon passivation). Process temperature: 15°C - 25°C, process time: 2 min - 3 min; Use water washing to remove surface chemical residues and dirt, washing time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) to clean the silicon wafer surface. Process temperature: room temperature, process time: 3 min - 5 min; Use water washing to remove surface chemical residues and dirt, washing time: 2 min - 3 min; Use slow lifting to remove dirt on the silicon wafer surface and dehydrate the silicon wafer, washing time 0.5 min - 1 min, washing temperature: 20°C - 70°C; Place the silicon wafer in a drying tank and blow dry the silicon wafer surface at high temperature. Blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min; Taking a 182.2-sized silicon wafer as an example, this cleaning process makes the silicon wafer lose weight: 0.3 g - 0.6 g; surface reflectivity: 35% - 45%; tower base size: 5 μm - 15 μm.

[0033] After the above operations, high-temperature gettering is used to improve the quality of N-type silicon wafers, reduce defective impurities, that is, improve the cleanliness of the silicon substrate. The specific steps are as follows: The polished silicon wafers are first printed with phosphorus paste, and then transferred to a high-temperature chain annealing furnace tube for annealing through a track. A PSG (a phosphorus-containing silicon dioxide layer formed on the silicon wafer surface) is formed on the silicon wafer surface, and at the same time, impurities in the silicon wafer are sucked into the PSG due to the difference in solid solubility; Annealing temperature: 850°C - 950°C, annealing time: 2 min - 10 min; PSG thickness: 30 nm - 100 nm. Specifically, this PSG will be washed off during the subsequent preparation of the pyramid texture.

[0034] Thus, a clean and polished silicon substrate is obtained.

[0035] Specifically, for the preparation of the pyramid texture, since the pyramids in the pyramid texture need to reach the nanoscale, the pyramid texture is formed by multiple texturing and etching on the front side of the silicon substrate. The pyramids in the pyramid texture have a height of 0.6 μm - 1.2 μm, a width of 0.8 μm - 1.5 μm, and a reflectivity of 9% - 12%.

[0036] In this step, the PSG on the front side of the silicon wafer is first removed by chain pickling and then textured and cleaned to prepare a positive / back-differentiated silicon substrate surface morphology with a textured front side and a polished back side. At the same time, the pyramids are secondarily textured and etched to prepare a nanoscale small pyramid texture.

[0037] The specific steps for preparing the nanoscale small pyramid texture are as follows: Single-sided chain pickling is carried out using a hydrofluoric acid (1% - 10%) solution to remove the annealing silicon oxide on the front side of the silicon wafer. Process temperature: room temperature, process time: 3 min - 5 min; Water washing is used to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; The silicon wafer is placed on a drying trough for transmission and high-temperature purging to dry the surface of the silicon wafer. Purging gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 2 min - 3 min; A mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) is used to clean the surface of the silicon wafer to remove the dirt on the surface of the silicon wafer. Process temperature: 55°C - 70°C, process time: 1 min - 3 min; Water washing is used to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min.

[0038] A mixed solution of potassium hydroxide (the first potassium hydroxide, 1% - 5%) and a texturing additive (the first texturing additive, 0.5% - 3%) is used to form a large pyramid texture on the front side of the silicon wafer. Process temperature: 70°C - 75°C, process time (3 min - 4 min); In this step, a low-temperature, low-concentration alkali and low-concentration additive are used to remove the cutting damage of the silicon wafer while preparing a large pyramid texture on the surface of the silicon wafer; In this step, the pyramids have a height of 3 - 4 μm, a width of 5 - 6 μm, and a reflectivity of 14% - 16%; Use water washing to remove the residual drugs and dirt on the surface, cleaning time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (the second potassium hydroxide, 5% - 10%) and texturing additive (the second texturing additive, 3% - 5%) to perform secondary texturing on the silicon wafer surface to form a small pyramid textured surface, process temperature: 75°C - 85°C, process time (3 min - 4 min); In this step, use high-temperature, high-concentration alkali and high-concentration additive to perform secondary texturing on the surface of the original large pyramid textured surface to prepare a small pyramid textured surface; In this step, the pyramid height is 0.8 μm - 1.4 μm, the pyramid width is 1 μm - 1.7 μm; Reflectivity: 8% - 11%; Use water washing to remove the residual drugs and dirt on the surface, cleaning time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to clean the silicon wafer surface to remove the dirt on the silicon wafer surface, process temperature: 55°C - 70°C, process time: 1 min - 3 min; Use water washing to remove the residual drugs and dirt on the surface, cleaning time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%) to clean the silicon wafer surface, process temperature: room temperature, process time: 3 min - 5 min; Use water washing to remove the residual drugs and dirt on the surface, cleaning time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (0.1% - 2%), hydrochloric acid (0.1% - 2%) and O3 (ozone, 10 ppm - 50 ppm) to clean the silicon wafer surface. At the same time, the weak etching system of O3 and HF corrodes the surface of the original smooth pyramid; Process temperature: 15°C - 25°C, process time: 3 min - 6 min; In this step, use the weak etching system of O3 and HF to weakly corrode the silicon substrate on the surface of the original small pyramid textured surface, and reduce the pyramid volume again to form a nano-scale pyramid textured surface; In this step, the pyramid height is 600 nm - 1200 nm, the pyramid width is 800 nm - 1500 nm, reflectivity: 9% - 12%; Use water washing to remove the residual drugs and dirt on the surface, cleaning time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%) to clean the silicon wafer surface, process temperature: room temperature, process time: 3 min - 5 min; Use water washing to remove the residual drugs and dirt on the surface, cleaning time: 2 min - 3 min; Use slow lifting to remove the dirt on the silicon wafer surface to dehydrate the silicon wafer, cleaning time 0.5 min - 1 min, cleaning temperature: 20°C - 70°C; Place the silicon wafer in a drying tank and blow it with high temperature to dry the silicon wafer surface, blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min; Taking a silicon wafer with a size of 182.2 as an example, the weight reduction of the above-prepared nanoscale small pyramid textured silicon wafer is 0.2 g - 0.5 g; the height of the pyramid is 600 nm - 1200 nm; the width of the pyramid is 800 nm - 1500 nm; the reflectivity is 9% - 12%; the formed nanoscale small pyramid texture is more conducive to improving the deposition and annealing uniformity of the subsequent film layer; At this time, the heterojunction battery includes a silicon substrate with a pyramid texture (such as Figure 2 ).

[0039] S20: Sequentially prepare a tunneling oxide layer, an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer, and a phosphorus-doped amorphous silicon layer on the front side of the silicon substrate with a pyramid texture; anneal to activate the diffusion of phosphorus atoms into the silicon substrate to form a front-side passivation structure; In this step, the tunneling oxide layer can be prepared by tube-type LP, PE, ALD, plate-type PE, PVD, ALD, or tank-type wet oxidation; the intrinsic amorphous silicon layer can be prepared by plate-type PVD, PE, or tube-type LP, PE; the doped amorphous silicon layer (buffer layer) can be prepared by plate-type PVD, PE, or tube-type PE; the phosphorus-doped amorphous silicon layer can be prepared by plate-type PVD, PE, or tube-type LP, PE.

[0040] Preferably, the tunneling oxide layer, the intrinsic amorphous silicon layer, the oxygen-doped amorphous silicon layer, and the phosphorus-doped amorphous silicon layer are prepared by plate-type deposition. Specifically, the tunneling oxide layer is prepared by plate-type PECVD, the intrinsic amorphous silicon layer is prepared by plate-type PVD, the doped amorphous silicon layer (buffer layer) is prepared by plate-type PVD, and the phosphorus-doped amorphous silicon layer is prepared by plate-type PVD. The film deposition under plate-type PVD has the characteristics of single-sided deposition without edge plating, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, the plate-type equipment has the advantage of integrated film deposition of different types of film layers, reducing equipment investment and the frequency of breaking the vacuum for battery coating, and improving the preparation efficiency.

[0041] Optionally, the doped amorphous silicon layer (buffer layer) can be doped with one or more of C, O, and N. Preferably, the doping gas of the doped amorphous silicon layer (buffer layer) is O2. The cost of O2 is relatively low, and the formed silicon oxide film layer can effectively slow down the advancing speed of phosphorus atoms. At the same time, the oxygen-doped polysilicon placed on the front side has less parasitic absorption, further optimizing the problems of high amorphous parasitic absorption and low battery current density. Specifically, the tunneling oxide layer is prepared by plate-type PECVD, and it can be prepared by using O2, O3, N2O, or a combination of one or more of the above gases with SiH4. Preferably, it is prepared by using O2 with low cost and high safety; the phosphorus doping source in this preparation step can be phosphine, phosphorus, a phosphorus-doped target, etc.; preferably, phosphine is used as the doping gas, and phosphine has the characteristics of high doping efficiency, easy decomposition, etc., and has a high matching degree with PVD coating.

[0042] In a preferred embodiment, an inert gas is used as a dilution gas for preparing the tunneling oxide layer, which is used to reduce the difference in the surface oxygen content of the "tips, edges, and valleys" on the surface of the silicon wafer, reduce the phenomenon of excessive oxygen content at the edges and too low oxygen content at the tips and valleys, and improve the uniformity of the oxide layer on the textured surface.

[0043] The steps for preparing the tunneling oxide layer include: The back surface of the singly-textured silicon wafer is oxidized by a planar PECVD method to prepare a tunneling oxide layer, and a layer of intrinsic amorphous silicon, a layer of oxygen-doped amorphous silicon, and a layer of phosphorus-doped amorphous silicon are deposited on the oxidized silicon wafer by a planar PVD method.

[0044] After texturing, the silicon wafer with the textured surface facing down is placed on a perforated carrier plate, and the carrier plate is transferred to the loading chamber 1. The chamber is evacuated, and the carrier plate is transferred to the PECVD1 reaction chamber 1. The O2 is ionized into plasma by the PECVD method, and the tunneling silicon oxide is prepared by oxidizing the surface of the silicon wafer from bottom to top through the perforated carrier plate. The carrier plate is transferred to the transition chamber, the chamber is evacuated, the carrier plate is transferred to the buffer chamber, and then transferred to the PVD1 reaction chamber 2. By the PVD method, through the perforated carrier plate, intrinsic amorphous silicon is deposited from bottom to top. Then it is transferred to the PVD2 reaction chamber 3. By the PVD method, through the perforated carrier plate, oxygen-doped amorphous silicon (buffer layer) is deposited from bottom to top. Then it is transferred to the PVD3 reaction chamber 4. By the PVD method, through the perforated carrier plate, phosphorus-doped amorphous silicon is deposited from bottom to top. Then it is transferred to the buffer chamber, the carrier plate is transferred to the cooling chamber, the carrier plate is transferred to the unloading chamber 1, the unloading chamber is backfilled with nitrogen to the atmospheric state, the carrier plate is transferred out of the chamber, and the silicon wafer is collected to complete the film layer preparation.

[0045] PECVD1 reaction chamber 1: When oxidizing to prepare the tunneling oxide layer by the PECVD method, oxygen is used as the process gas and argon is used as the dilution gas. Process pressure: 5 Pa - 20 Pa, process temperature: 150 °C - 350 °C, power: 50 W - 500 W, process belt speed: 10 cm / min - 500 cm / min; Thickness of the tunneling silicon oxide: 0.5 nm - 3 nm, which can be freely adjusted by power, belt speed, flow rate, and temperature to meet the process requirements.

[0046] PVD1 reaction chamber 2: When preparing intrinsic amorphous silicon by the PVD method, a silicon target is used as the silicon source, and argon is used as the working gas. Process pressure: 0.1 Pa - 1 Pa, process temperature: 200 °C - 500 °C, power: 10 kW - 40 kW, process belt speed: 10 cm / min - 500 cm / min; Thickness of the intrinsic amorphous silicon layer: 1 nm - 50 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements.

[0047] PVD2 Reaction Chamber 3: When preparing oxygen-doped amorphous silicon by PVD method, a silicon target is used as the silicon source, argon is used as the working gas, and O2 is used as the doping gas. Process pressure: 0.1 Pa - 1 Pa, process temperature: 200 °C - 500 °C, power: 1 kW - 40 KW, process belt speed: 10 cm / min - 500 cm / min, O2 flow rate: 5 sccm - 100 sccm; thickness of the oxygen-doped amorphous silicon layer (buffer layer): 1 nm - 50 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements; oxygen doping concentration of the oxygen-doped amorphous silicon layer (buffer layer): 1E+19 - 1E+21, which can be freely adjusted by the O2 flow rate; PVD3 Reaction Chamber 4: When preparing phosphorus-doped amorphous silicon by PVD method, a silicon target is used as the silicon source, argon is used as the working gas, and PH3 is used as the doping gas. Process pressure: 0.1 Pa - 1 Pa, process temperature: 200 °C - 500 °C, power: 10 kW - 40 KW, process belt speed: 10 cm / min - 500 cm / min, PH3 flow rate: 50 sccm - 500 sccm. Thickness of the phosphorus-doped amorphous silicon layer: 10 nm - 200 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements; carbon doping concentration of the phosphorus-doped amorphous silicon layer: 1E+19 - 1E+22, which can be freely adjusted by the PH3 flow rate; Among them, the thickness ratio of the intrinsic amorphous silicon layer, oxygen-doped amorphous silicon layer, and phosphorus-doped amorphous silicon layer is 1:1:10 - 50:50:200; the ratio of the number of targets in PVD1 reaction chamber, PVD2 reaction, and PVD3 reaction chamber is 1:1:1 - 1:1:3; the power ratio of PVD1 reaction chamber, PVD2 reaction chamber, and PVD3 reaction chamber is 1:1:200 - 50:50:600.

[0048] At this time, the heterojunction battery includes a silicon substrate with a pyramid texture, and sequentially deposited thereon are a tunneling oxide layer, an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer (amorphous silicon oxide layer), and a phosphorus-doped amorphous silicon layer (such as Figure 3 ).

[0049] As described above, high-temperature oxidation annealing is used to crystallize the front-side intrinsic amorphous silicon, oxygen-doped amorphous silicon, and phosphorus-doped amorphous silicon into polycrystalline silicon. At the same time, the phosphorus atoms in the phosphorus-doped amorphous silicon are activated to form phosphorus-doped polycrystalline silicon. The phosphorus atoms first advance to the silicon oxide polycrystalline layer (the buffer layer slows down the phosphorus advancement speed), then to the intrinsic polycrystalline silicon layer (slowing down the phosphorus advancement speed), and finally to the tunneling oxide layer and enter the silicon substrate to form tunneling pinholes, forming an N+ inner diffusion layer. The phosphorus-doped amorphous silicon layer serves as the phosphorus source, and amorphous silicon oxide serves as the oxygen source. Under the action of high-temperature annealing, all the amorphous layers are crystallized into phosphorus-doped polycrystalline silicon oxide, and show a trend of gradient doping (highly doped with phosphorus and lowly doped with oxygen in the surface metal contact area, and lowly doped with phosphorus and highly doped with oxygen in the bottom passivation area).

[0050] Introducing oxygen into phosphorus-doped polysilicon reduces the parasitic absorption of the film layer while not affecting the surface contact resistance, and improves the battery current density. Further, the design of the intrinsic layer + buffer layer + doped layer slows down the inward diffusion rate of phosphorus atoms, improves the uniformity of tunneling through oxygen pinholes on the "tips, valleys, and edges" of the textured surface and the inward diffusion uniformity, and improves the passivation quality.

[0051] The specific annealing steps include: inserting the silicon wafer with the front side coated into a quartz carrier, transporting it to a high-temperature annealing furnace tube, annealing, and completing the preparation of phosphorus-doped polycrystalline silicon oxide, tunneling oxide layer, and N+ inward diffusion layer. Among them, gradient heating is adopted to reduce the annealing process effect differences caused by the initial temperature differences at the furnace inlet - furnace middle - furnace tail due to opening the furnace door. The specific heating method is as follows: 800°C - 820°C - 840°C - 860°C - 880°C replaces the traditional 800°C - 840°C - 880°C; different annealing temperatures are used in different temperature zones to reduce the annealing process effect differences at different positions caused by the rapid cooling at the furnace inlet and tail due to water cooling of the furnace tube and the slow heating at the furnace inlet and fast heating at the furnace tail caused by opening the furnace door. The specific temperature setting method is as follows: furnace inlet - furnace middle - furnace tail: 890°C - 880°C - 885°C replaces the traditional furnace inlet - furnace middle - furnace tail: 880°C - 880°C - 880°C; oxidation annealing time: 30 min - 120 min; oxidation annealing temperature: 840°C - 950°C; oxidation annealing pressure: 600 mBar - 900 mBar; tunneling oxide layer thickness: 0.5 nm - 3 nm, which can be freely adjusted by power, belt speed, flow rate, and temperature to meet the process requirements; effective phosphorus doping concentration on the surface of phosphorus-doped polycrystalline silicon oxide: 5E19 -3 -1E22 -3 , which can be freely adjusted by phosphine flow rate, process pressure, and process time to meet the process requirements; thickness of phosphorus-doped polycrystalline silicon oxide: 20 nm - 300 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements; thickness of surface annealed silicon oxide: 20 nm - 50 nm, which can be freely adjusted by oxygen flow rate, annealing time, and annealing temperature to meet the process requirements; phosphorus inward diffusion depth: 20 nm - 100 nm; which can be freely adjusted by tunneling oxide layer thickness, annealing temperature and time, and doping concentration.

[0052] At this time, the heterojunction battery includes a silicon substrate with a pyramid-shaped textured surface on the front, an N+ inward diffusion layer, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon oxide layer, and an annealed oxide layer on the front; an annealed oxide layer is also deposited on the back (such as Figure 4 ).

[0053] S30: Clean and remove the oxide layer generated by annealing on the surface of the silicon substrate, and sequentially prepare a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide silicon layer on the polished surface of the back of the silicon substrate to form a back passivation structure. Specifically, pickling is used to remove the annealing oxide layer and dirt on the surface of the silicon wafer after annealing to obtain a clean silicon wafer surface. The specific steps are as follows: Wash the surface of the silicon wafer with water to remove dirt, and the cleaning time is 2 min - 3 min; Wash the surface of the silicon wafer with a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%), the process temperature is room temperature, and the process time is 3 min - 5 min; Wash the surface with water to remove the residual chemicals and dirt, and the cleaning time is 2 min - 3 min; Slowly lift the silicon wafer to remove the dirt on the surface, dehydrate the silicon wafer, and the cleaning time is 0.5 min - 1 min, and the cleaning temperature is 20°C - 70°C; Place the silicon wafer in a drying tank, blow it with high temperature, and dry the surface of the silicon wafer. The blowing gas is nitrogen or compressed air, the temperature is 80°C - 100°C, and the drying time is 5 min - 15 min.

[0054] At this time, the heterojunction battery includes a silicon substrate with a pyramid texture on the front, an N+ inner diffusion layer, a tunneling oxide layer, and a phosphorus-doped polysilicon oxide layer. The back is a polished surface with an alkaline polishing tower base morphology, the reflectivity is 35% - 45%, and the size of the tower base is 5 μm - 15 μm.

[0055] Deposit an intrinsic amorphous silicon layer doped with hydrogen, an amorphous silicon layer doped with boron, and a boron-doped microcrystalline carbon oxide silicon layer on the back. The specific steps are as follows: The deposition method is preferably plate-type PECVD or plate-type HWCVD; Specifically, if plate-type PECVD is used for deposition; For the boron-doped microcrystalline carbon oxide silicon layer, the carbon and oxygen sources can be one or more of CH4, CO2, TMB, and O2; It is preferred to use CO2 and TMB as the carbon and oxygen sources.

[0056] First, use the plate-type PECVD method to deposit a layer of i-a:Si on the back of the double-cleaned silicon wafer from top to bottom, then perform HPT cleaning (H ion cleaning) on the deposited surface, and finally use the plate-type PECVD method to deposit P-a:Si on the back of the silicon wafer from top to bottom. The deposition includes (a layer of P-a:Si and a layer of P-uc-SiOxCy); The silicon wafer after double-sided cleaning is placed on a perforated carrier plate, and the carrier plate is transferred to the loading chamber 2. The chamber is evacuated, the carrier plate is transferred to the preheating buffer chamber, and then transferred to the PECVD2 reaction chamber 5 to deposit a layer of i-a:Si from top to bottom. Then it is transferred to the HPT cleaning buffer chamber, and the deposited surface is cleaned with H ions to complete the preparation of i-a:Si; The carrier plate is first transferred to the transition chamber, then to the buffer chamber, and then to the PECVD3 reaction chamber 6 to deposit a layer of P-a:Si and a layer of P-uc-SiOxCy from top to bottom, and then transferred to the buffer chamber to complete the preparation of P-a:Si; The carrier plate is transferred to the unloading chamber 2, backfilled with nitrogen to the atmospheric state, the carrier plate is taken out, and the silicon wafer is collected to complete the preparation of the back passivation film layer; PECVD2 Reaction Chamber 5: Preparation of i-a:Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100°C - 250°C, process pressure: 10 Pa - 50 Pa, SiH4:H2 flow ratio: 1:10 - 1:30, power: 50 W - 300 W.

[0057] PECVD3 Reaction Chamber 6: Preparation of P-a:Si by PECVD method. P-a:Si is divided into two layers: conventional boron-doped (B) amorphous silicon (P-a:Si) and boron-doped microcrystalline carbon oxide layer (P-uc-SiOxCy). Preparation of conventional B-doped amorphous silicon (P-a:Si), using SiH4, H2, and B2H6 as process gases, process temperature: 100°C - 250°C, process pressure: 10 Pa - 50 Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5 - 1:30:15, power: 50 W - 300 W. Preparation of B-doped microcrystalline carbon oxide (P-uc-SiOxCy), using SiH4, H2, B2H6, CO2, and TMB as process gases, process temperature: 100°C - 250°C, process pressure: 50 Pa - 100 Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:30:10 - 1:60:30, CO2 and TMB as micro-doping gas flow: 5 sccm - 20 sccm, power: 300 w - 500 W; i:a-Si thickness: 2 nm - 10 nm, can be freely adjusted by power, belt speed, flow rate, temperature, and number of ion sources to meet process requirements; P:a-Si thickness: 10 nm - 20 nm, P-uc-SiOxCy thickness: 20 nm - 50 nm, can be freely adjusted by power, belt speed, flow rate, temperature, and number of ion sources to meet process requirements; P:a-Si doping concentration: 1E19 cm -3 -5E19 cm -3 : P-uc-SiOxCy doping concentration: 5E19 cm -3 -2E20 cm -3 , doping amount can be freely adjusted by belt speed, pressure, flow rate, and temperature to meet process requirements.

[0058] At this time, the heterojunction cell includes a silicon base with a pyramid-shaped texture on the front, an N+ inner diffusion layer, a tunneling oxide layer, and a phosphorus-doped polycrystalline oxide layer; a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide layer are also deposited on the back S40: Deposit transparent conductive films on the front and back of the silicon base and prepare metal electrodes to form a heterojunction cell.

[0059] Specifically, the metallization method can be electroplating or the method of curing screen-printed metal paste; preferably, the simple and environmentally friendly method of curing screen-printed metal paste is used; the metal paste can be one or a combination of silver paste, silver-coated copper paste, copper paste, aluminum paste, and tin paste, and silver-coated copper paste is preferably used; The specific steps are as follows: The silicon wafer after double-sided deposition of TCO is placed on a horizontal table. Through screen printing technology, silver-coated copper paste is printed on the front and back of the battery. After printing, the silicon wafer is transferred to a curing furnace for drying and curing to form an ohmic contact with TCO; the battery is transferred to an annealing furnace for annealing and light injection to excite H and improve passivation; the battery preparation is completed; Specifically, as an option, the transparent conductive film includes one or a combination of ITO, IWO, TiO, TiN, and AZO; the film thickness of the transparent conductive film is 50 nm - 150 nm; as an option, the metal electrode includes one or a combination of silver, copper, aluminum, and tin, the width of the metal electrode is 10 μm - 50 μm, and the height of the metal electrode is 5 μm - 20 μm; Finally, the above heterojunction battery is prepared (as Figure 1 shown). A TOPCON passivation contact structure is introduced on the front of the battery. By the above preparation method, the pyramid size in the pyramid texture is restricted, the difference in the thickness of the oxide layer at different positions of the pyramid is reduced, a nanoscale pyramid morphology is formed, the problem of parasitic absorption current loss on the front of the heterojunction battery is optimized, and at the same time, the above preparation method restricts the pyramid size in the pyramid texture, reduces the difference in the film preparation performance at different positions of the pyramid, and solves the problem of low passivation of the introduced Topcon structure.

[0060] Furthermore, based on the preparation of the above phosphorus-doped polysilicon, both the doping concentration of the polysilicon surface layer is increased and the penetration rate of phosphorus atoms through the tunneling oxide layer is slowed down, further optimizing the problems of high parasitic absorption and low battery current density on the front of the battery.

[0061] It should also be noted that in the above preparation method, during the processes of preparing the tunneling oxide layer, intrinsic amorphous silicon layer, oxygen-doped amorphous silicon layer, phosphorus-doped amorphous silicon layer, hydrogenated intrinsic amorphous silicon layer, boron-doped amorphous silicon layer, and / or boron-doped microcrystalline carbon oxide silicon layer by plate deposition, continuous vacuum coating technology is preferably applied, and the vacuum blocking technology of "transition - isolation - coating - isolation - transition" is adopted to meet the process pressures of different film layer preparations, while reducing the process abnormalities caused by "gas cross-talk" between the process gases of different film layer preparations, and a single machine can meet the preparations of different film layers; improving the preparation efficiency and preparation effect.

[0062] The above preparation method is also applicable to the preparation of P-type batteries.

[0063] It should be noted that the embodiments of the present invention have better implementability and do not impose any form of limitation on the present invention. Any person skilled in the art may use the technical content disclosed above to change or modify it into equivalent effective embodiments. However, as long as it does not depart from the content of the technical solution of the present invention, any modification, equivalent change or modification made to the above embodiments based on the technical essence of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A heterojunction battery structure, characterized in that: It comprises a silicon base with a pyramid velvet surface formed on the surface; wherein the pyramids in the pyramid velvet surface are 0.6μm-1.2μm high and 0.8μm-1.5μm wide, and the surface reflectivity of the silicon base forming the pyramid velvet surface is 9%-12%.

2. The heterojunction battery structure according to claim 1, characterized in that: Also included is a front passivation structure located on the pyramid velvet surface; The front passivation structure includes an N+ inner expansion layer, a tunneling oxide layer, and a phosphorus-doped polycrystalline silicon oxide layer; The phosphorus-doped polycrystalline silicon oxide layer has gradient doping, wherein the side away from the silicon base is highly doped with phosphorus and low doped with oxygen, and the side close to the silicon base is low doped with phosphorus and high doped with oxygen.

3. The heterojunction battery structure according to claim 1, characterized in that: The phosphorus-doped polycrystalline silicon oxide layer is formed by annealing an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer and a phosphorus-doped amorphous silicon layer which are deposited on the surface of a silicon substrate.

4. The heterojunction battery structure according to claim 1, characterized in that: It also includes a polishing surface located on the silicon base away from the pyramid velvet surface, and a back passivation structure formed on the polishing surface; The back passivation structure comprises a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide silicon layer deposited on the surface of the silicon substrate.

5. A method for preparing a heterojunction battery, characterized in that, The method of preparing the heterojunction battery structure according to any one of claims 1 to 4 comprises: Obtain a clean and polished silicon substrate, and texture the front side of the silicon substrate to form a pyramid texture surface; A tunneling oxide layer, an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer, and a phosphorus-doped amorphous silicon layer are sequentially prepared on the front side of the silicon substrate with a pyramid velvet surface; annealing is performed to activate phosphorus atoms to diffuse into the silicon substrate to form a front passivation structure; The oxide layer generated by annealing on the surface of the silicon substrate is cleaned and removed, and a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide silicon layer are sequentially prepared on the polished surface of the back side of the silicon substrate to form a back side passivation structure; A transparent conductive film is deposited on the front and back sides of the silicon substrate and metal electrodes are prepared to form a heterojunction battery.

6. The preparation method according to claim 5, characterized in that: The silicon-based front surface is repeatedly textured and etched to form a pyramid velvet surface, wherein the pyramids in the pyramid velvet surface are 0.6 μm-1.2 μm high, 0.8 μm-1.5 μm wide, and have a reflectivity of 9%-12%.

7. The preparation method according to claim 5, characterized in that: A first texturing solution is used to perform a first texturing on the front side of the silicon substrate, wherein the first solution includes a first potassium hydroxide and a first texturing additive; After cleaning, a second texturing liquid is used to perform a second texturing on the front side of the silicon substrate; wherein the second texturing liquid includes a second potassium hydroxide and a second texturing additive, and the second texturing liquid has a high temperature, a high concentration of alkali, and a high concentration of additives compared to the first texturing liquid; the concentration of the first texturing liquid is 0.5%-3%, and the concentration of the first potassium hydroxide is 1%-5%; the concentration of the second texturing liquid is 3%-5%, and the concentration of the second potassium hydroxide is 5%-10%; After cleaning, a weak etching system formed by hydrofluoric acid, hydrochloric acid and ozone is used to etch the front side of the silicon substrate to form the pyramid velvet surface.

8. The preparation method according to claim 5, wherein: A tunneling oxide layer, an intrinsic amorphous silicon layer, an oxygen-doped amorphous silicon layer, a phosphorus-doped amorphous silicon layer, a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and / or a boron-doped microcrystalline carbon oxide silicon layer are prepared by plate deposition.

9. The preparation method according to claim 5, wherein: An inert gas is used as a dilution gas for preparing the tunneling oxide layer.

10. The preparation method according to claim 5, wherein: The transparent conductive film includes one or a combination of more of ITO, IWO, TiO, TiN, and AZO; the film thickness of the transparent conductive film is 50 nm - 150 nm; and / or, the metal electrode includes one or a combination of more of silver, copper, aluminum, and tin, the width of the metal electrode is 10 um - 50 um, and the height of the metal electrode is 5 um - 20 um; and / or, the silicon substrate is an N-type silicon substrate, including one of Czochralski single crystal and ingot single crystal.

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