Display device and head mounted display device including the same

Abstract

A display device and a head-mounted display device including the same are provided. The display device includes: a substrate including a display area, a non-display area around the display area, and a plurality of transistors; a dam structure in the non-display area; a light emitting element layer including a plurality of light emitting elements in the display area; an encapsulation layer on the light emitting element layer; and a capping layer on the encapsulation layer. The dam structure includes a first dam including a plurality of first dam patterns spaced apart from each other and a second dam including a plurality of second dam patterns spaced apart from each other. A distance between the second dam and the display area is greater than a distance between the first dam and the display area.

Description

Technical Field

[0001] Aspects of one or more embodiments of the present disclosure relate to a display device and a head-mounted display device including the display device. Background Art

[0002] A head-mounted display device (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet to form an image in focus at a short distance in front of the user's eyes. The head-mounted display device can implement virtual reality (VR) or augmented reality (AR).

[0003] The head-mounted display device magnifies an image displayed on a small display device by using a plurality of lenses and displays the magnified image. Therefore, a display device applied to the head-mounted display device can provide a high-resolution image, such as an image having a resolution of 3000 PPI (pixels per inch) or higher. Accordingly, a silicon-based organic light-emitting diode (OLEDoS), which is a high-resolution small organic light-emitting display device, is used as the display device applied to the head-mounted display device. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are arranged on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0004] The above information disclosed in this background art section is used to enhance the understanding of the background of the present disclosure, and thus it may include information that does not constitute the prior art. Summary of the Invention

[0005] Embodiments of the present disclosure may relate to a display device including dams formed of patterns spaced apart from each other.

[0006] Embodiments of the present disclosure may relate to a display device capable of controlling an edge shape of an organic encapsulation layer.

[0007] However, aspects and features of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those of ordinary skill in the art through the following detailed description of the present disclosure with reference to the accompanying drawings.

[0008] According to one or more embodiments of the present disclosure, a display device includes a substrate including a display area, a non-display area around the display area, and a plurality of transistors; a dam structure in the non-display area; a light-emitting element layer including a plurality of light-emitting elements in the display area; an encapsulation layer on the light-emitting element layer; and a cover layer on the encapsulation layer. The dam structure includes a first dam including a plurality of first dam patterns spaced apart from each other and a second dam including a plurality of second dam patterns spaced apart from each other. A distance between the second dam and the display area is greater than a distance between the first dam and the display area.

[0009] In an embodiment, the encapsulation layer may include a first inorganic encapsulation layer extending beyond the second dam in the display area and the non-display area, an organic encapsulation layer on the first inorganic encapsulation layer and covering the first dam without covering the second dam, and a second inorganic encapsulation layer on the organic encapsulation layer and the first inorganic encapsulation layer.

[0010] In an embodiment, the first inorganic encapsulation layer and the second inorganic encapsulation layer may be in direct contact with each other outside the second dam.

[0011] In an embodiment, the interval between the first dam patterns spaced apart from each other may be 100 μm or less.

[0012] In an embodiment, the first dam pattern among the plurality of first dam patterns and the second dam pattern among the plurality of second dam patterns may be positioned side by side with each other.

[0013] In an embodiment, the display area may have a curved diagonal edge, the first dam may include a plurality of third dam patterns having side edges curved to correspond to the curved diagonal edge of the display area, and the second dam may include a plurality of fourth dam patterns having side edges curved to correspond to the curved diagonal edge of the display area.

[0014] In an embodiment, the first dam pattern and the second dam pattern may be positioned alternately with each other, and the second dam pattern among the plurality of second dam patterns may be positioned side by side with the area between adjacent first dam patterns among the plurality of first dam patterns.

[0015] In an embodiment, the display device may further include a plurality of pads in the non-display area, and the pads may be positioned outside the dam structure without overlapping with the encapsulation layer.

[0016] According to one or more embodiments of the present disclosure, a display device includes a substrate including a display area, a non-display area around the display area, and a plurality of transistors; a first insulating film on the substrate; a pixel defining film on the first insulating film in the display area; a plurality of light emitting elements respectively corresponding to a plurality of openings in the pixel defining film; a dam structure in the non-display area and including a plurality of dams having a trench shape penetrating the pixel defining film; an encapsulation layer on the light emitting elements in the display area and covering at least a part of the plurality of dams; and a cover layer on the encapsulation layer. The dam structure includes an innermost dam adjacent to the display area and an outermost dam outside the innermost dam. The encapsulation layer includes an organic encapsulation layer that at least covers the innermost dam among the plurality of dams without overlapping with the outermost dam and covers the light emitting elements.

[0017] In an embodiment, the plurality of dams may have the same depth as each other.

[0018] In an embodiment, the display device may further include a second insulating film between the pixel defining film and the first insulating film, and each of the plurality of dams may penetrate the pixel defining film and the second insulating film.

[0019] In an embodiment, the display device may further include a third insulating film between the pixel defining film and the second insulating film, and each of the plurality of dams may penetrate the pixel defining film, the third insulating film, and the second insulating film.

[0020] In an embodiment, the depth of the outermost dam among the plurality of dams may be greater than the depth of the innermost dam among the plurality of dams.

[0021] In an embodiment, the display device may further include a second insulating film and a third insulating film between the pixel defining film and the first insulating film. The innermost dam may penetrate the pixel defining film, and the outermost dam may penetrate the pixel defining film, the second insulating film, and the third insulating film.

[0022] In an embodiment, the outermost dam may include a recessed portion on the top surface of the first insulating film.

[0023] In an embodiment, the display device may further include a second insulating film and a third insulating film between the pixel defining film and the first insulating film. The plurality of dams may penetrate the pixel defining film, the second insulating film, and the third insulating film, and may have a width increasing in the downward direction.

[0024] In an embodiment, the width of the portion of the plurality of dams that penetrates the pixel defining film may be smaller than the width of the portion of the plurality of dams that penetrates the second insulating film and the third insulating film.

[0025] In an embodiment, the plurality of dams may include a recessed portion on the top surface of the first insulating film, and the width of the portion of the plurality of dams that penetrates the pixel defining film, the second insulating film, and the third insulating film may be smaller than the width of the portion of the plurality of dams that includes the recessed portion on the top surface of the first insulating film.

[0026] In an embodiment, the width of the portion of the plurality of dams that penetrates the second insulating film and the third insulating film may be smaller than the width of the portion of the plurality of dams that includes the recessed portion on the top surface of the first insulating film.

[0027] In an embodiment, the encapsulation layer may include a first inorganic encapsulation layer and a second inorganic encapsulation layer stacked on top of each other with an organic encapsulation layer therebetween, and the first inorganic encapsulation layer and the second inorganic encapsulation layer may be in direct contact with each other outside the outermost dam of the dam structure.

[0028] According to one or more embodiments of the present disclosure, a head-mounted display device includes a frame configured to be mounted on a user's body corresponding to the user's left and right eyes, a plurality of display devices in the frame, and eyepieces on each of the plurality of display devices. Each of the display devices includes a substrate including a display area, a non-display area around the display area, and a plurality of transistors; a dam structure in the non-display area; a light-emitting element layer including a plurality of light-emitting elements in the display area; a packaging layer on the light-emitting element layer; and a cover layer on the packaging layer. The dam structure includes a first dam including a plurality of first dam patterns spaced apart from each other and a second dam including a plurality of second dam patterns spaced apart from each other, the second dam having a groove shape and being positioned at a greater distance from the display area than the first dam. The packaging layer includes an organic packaging layer that covers the first dam without overlapping the second dam and covers the light-emitting elements.

[0029] In an embodiment, the first dam and the second dam may have the same depth as each other.

[0030] In an embodiment, the depth of the second dam may be greater than the depth of the first dam.

[0031] According to some embodiments of the present disclosure, the display device may include dams formed of dam patterns spaced apart from each other to control the flow of an organic material, thereby preventing or substantially preventing the bending of the edge shape of the organic packaging layer. Accordingly, the display device may improve brightness and light emission efficiency by reducing the thickness of the organic packaging layer, and may ensure product reliability by controlling the edge shape of the organic packaging layer.

[0032] However, aspects and features of the present disclosure are not limited to the above aspects and features, and various other aspects and features are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative non-limiting embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1 is an exploded perspective view of a display device according to an embodiment;

[0035] Figure 2 is a block diagram showing a display device according to an embodiment;

[0036] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment;

[0037] Figure 4 is a view showing a display panel according to an embodiment;

[0038] Figure 5 is a view showing arranged in Figure 4Plan view of the first electrode, emission region, and pixel defining film of a plurality of pixels in the display region;

[0039] Figure 6 Is a plan view showing the first electrode, emission region, and pixel defining film of a plurality of sub-pixels according to another embodiment;

[0040] Figure 7 Is along Figure 5 Schematic cross-sectional view taken along line A-A' of;

[0041] Figure 8 Is showing Figure 4 Enlarged view of region X of;

[0042] Figure 9 Is along Figure 8 Schematic cross-sectional view taken along line B-B' of;

[0043] Figure 10 Is showing Figure 4 Enlarged view of region Y of;

[0044] Figure 11 Is along Figure 10 Schematic cross-sectional view taken along line C-C' of;

[0045] Figure 12 And Figure 13 Is a plan view showing a schematic arrangement of the encapsulation layer and dam structure of a display device according to an embodiment;

[0046] Figure 14 Is a plan view showing a schematic arrangement of the encapsulation layer and dam structure of a display device according to another embodiment;

[0047] Figure 15 And Figure 16 Is a schematic cross-sectional view showing a part of the display device in which a dam structure is arranged according to one or more embodiments;

[0048] Figure 17 Is a schematic cross-sectional view showing a part of the display device in which a dam structure is arranged according to another embodiment;

[0049] Figure 18 Is showing in more detail Figure 17 Cross-sectional view of the dam of the display device of;

[0050] Figure 19 Is a schematic cross-sectional view showing the structure of the dam in a display device according to another embodiment;

[0051] Figures 20 to 22 Is a schematic cross-sectional view of the dam of a display device according to one or more embodiments;

[0052] Figure 23 is a perspective view showing a head-mounted display device according to an embodiment;

[0053] Figure 24 is showing Figure 23 an exploded perspective view of an example of the head-mounted display device; and

[0054] Figure 25 is a perspective view showing a head-mounted display device according to an embodiment. DETAILED DESCRIPTION

[0055] Aspects and features of embodiments of the present disclosure and methods of implementing the same can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand aspects and features of the present disclosure may not be described.

[0056] Unless otherwise noted, the same reference numerals, characters, or combinations thereof represent the same elements throughout the drawings and the written description, and thus, their description will not be repeated. Additionally, for the sake of clarity, parts that are not relevant to the description of one or more embodiments may not be shown.

[0057] In the drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, dimensions, ratios, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0058] In this document, various embodiments are described with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, for the purpose of describing embodiments according to the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Accordingly, the embodiments disclosed herein should not be construed as limited to the specific shapes of regions shown, but include deviations in shape caused by, for example, manufacturing.

[0059] For example, an implantation region shown as a rectangle may have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region located between the buried region and the surface through which the implantation is performed. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to be limiting. Additionally, as will be appreciated by those skilled in the art, the described embodiments can be modified in various different ways without departing from the scope of the present disclosure.

[0060] In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It will be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0061] Spatial relative terms, such as "beneath", "below", "lower", "under", "above", "upper", etc., may be used herein for ease of explanation to describe the relationship of one element or feature to another (or others) as shown in the figures. It is to be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "beneath" or "below" or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "beneath" and "below" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this indicates that the first part is disposed on the upper side or the lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0062] Furthermore, in this specification, the phrase "in a plane" or "in a plan view" means observing the target portion from the top, and the phrase "in a cross-section" means observing a cross-section formed by vertically cutting the target portion from the side.

[0063] It should be understood that when an element, layer, region or component is referred to as being "formed on", "located on", "connected to" or "coupled to" another element, layer, region or component, the element, layer, region or component can be directly formed on, directly located on, directly connected to or directly coupled to the other element, layer, region or component, or indirectly formed on, indirectly located on, indirectly connected to or indirectly coupled to the other element, layer, region or component such that there can be one or more intervening elements, layers, regions or components. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or coupled to the other layer, region or component, or there can be intervening layers, regions or components. However, "directly connected / directly coupled" means that a component is directly connected or coupled to another component without an intermediate component. Also, other expressions such as "between", "directly between", "adjacent to" and "directly adjacent to" describing the relationship between components can be similarly interpreted. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0064] For the purposes of the present disclosure, expressions such as "at least one of...", "one of...", and "select from..." when following a list of elements modify the entire list of elements, rather than individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z such as XYZ, XYY, XZ, YZ, and ZZ for example, or any variation thereof. Similarly, an expression such as "at least one of A and B" can include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, an expression such as "A and / or B" can include A, B, or A and B. Further, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure".

[0065] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion without departing from the scope of the present disclosure.

[0066] In an example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This also applies to the first direction, the second direction, and / or the third direction.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Unless the context clearly dictates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms. It should also be understood that the terms "comprises," "comprising," "has," "having," "includes," and "including" when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0068] As used herein, the terms "substantially", "about", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art. Taking into account the relevant measurements and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein includes the stated value and means within an acceptable deviation range for the particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0069] When one or more embodiments can be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0070] In addition, any numerical range disclosed and / or recited herein is intended to include all sub-ranges having the same numerical precision that fall within the recited range. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges between the stated minimum value of 1.0 and the stated maximum value of 10.0 (and including the stated minimum value of 1.0 and the stated maximum value of 10.0), e.g., all sub-ranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as by way of example 2.4 to 7.6. Any maximum numerical limitation stated herein is intended to include all lower numerical limitations that fall within it, and any minimum numerical limitation stated in this specification is intended to include all higher numerical limitations that fall within it. Accordingly, the applicant reserves the right to modify this specification (including the claims) to expressly recite any sub-ranges that fall within the ranges expressly stated herein. All such ranges are intended to be inherently described in this specification such that a modification for expressly stating any such sub-range will be compliant.

[0071] The electronic or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate multiple IC chips. Additionally, the various components of these devices may be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0072] Alternatively, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which may be implemented in the computing device using a standard memory device such as, by way of example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as, by way of example, CD-ROM, flash drive, etc. Additionally, those skilled in the art should recognize that the functions of the various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the present disclosure.

[0073] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly dogmatic sense unless expressly so defined herein.

[0074] Figure 1 is an exploded perspective view of a display device according to an embodiment.

[0075] Referring to Figure 1 , the display device 10 according to an embodiment is a device for displaying moving images or still images. The display device 10 according to an embodiment can be applied to various suitable portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile personal computers (UMPCs), or the like. For example, the display device 10 can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. As another example, the display device 10 can be applied to smart phones, watch phones, head-mounted display devices (HMDs) for realizing virtual reality and augmented reality, and the like.

[0076] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0077] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a short side extending in a first direction DR1 and a long side extending in a second direction DR2 that intersects or crosses the first direction DR1. In the display panel 100, the corners where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be right-angled or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape and may have other suitable shapes, such as a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0078] The heat dissipation layer 200 may overlap with the display panel 100 in a third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate the heat generated from the display panel 100. The heat dissipation layer 200 may include graphite having a high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0079] The circuit board 300 may be electrically connected to the pads PD of the pad portion PDA of the display panel 100 by using a conductive bonding member such as an anisotropic conductive film (for example, see Figure 4 ). The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Although the circuit board 300 is shown as being unfolded in Figure 1 , the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the opposite end of the other end of the circuit board 300 that is connected to the pads PD of the pad portion PDA of the display panel 100 by using a conductive bonding member (for example, see Figure 4 ).

[0080] The timing control circuit 400 may receive digital video data and timing signals input from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals (for example, see Figure 2 ). The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 (for example, see Figure 2 ), and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data and the data timing control signal DCS to the data driver 700 (for example, see Figure 2 ).

[0081] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT (for example, see Figure 2 ), and supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described in more detail below with reference to Figure 3 .

[0082] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0083] As another example, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100 (e.g., see Figure 2 ). In this case, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (e.g., see Figure 7 ) by a semiconductor process. For example, the plurality of timing transistors and the plurality of power transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be disposed between the data driver 700 and the pad portion PDA (e.g., see Figure 4 ).

[0084] Figure 2 is a block diagram showing a display device according to an embodiment.

[0085] Referring to Figure 2 , the display panel 100 may include a display area DAA and a non-display area NDA disposed around the display area DAA. In the display area DAA, a plurality of pixels PX are arranged to emit light or display an image. In the non-display area NDA, light may not be emitted or an image may not be displayed.

[0086] The display panel 100 may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL disposed in the display area DAA.

[0087] The plurality of pixels PX may be arranged along a first direction DR1 and a second direction DR2. The plurality of pixels PX may be arranged in a matrix in the display area DAA. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 and may be arranged at intervals from each other in the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 and may be arranged at intervals from each other in the first direction DR1.

[0088] A plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL includes a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0089] The plurality of pixels PX may include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include a plurality of pixel transistors as Figure 3 shown. The plurality of pixel transistors may be formed by a semiconductor process to be disposed on a semiconductor substrate SSUB (e.g., see Figure 7 ). For example, the plurality of pixel transistors may be formed of complementary metal oxide semiconductor (CMOS).

[0090] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to one write scan line GWL among the plurality of write scan lines GWL, one control scan line GCL among the plurality of control scan lines GCL, one bias scan line GBL among the plurality of bias scan lines GBL, one first emission control line EL1 among the plurality of first emission control lines EL1, one second emission control line EL2 among the plurality of second emission control lines EL2, and one data line DL among the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of the corresponding data line DL in response to a write scan signal of the corresponding write scan line GWL, and emit light from the corresponding light-emitting element according to the data voltage.

[0091] The display panel 100 may include a scan driver 610, an emission driver 620, and a data driver 700 disposed in a non-display area NDA.

[0092] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors may be formed by a semiconductor process on a semiconductor substrate SSUB (e.g., see Figure 7 ). For example, the plurality of scan transistors and the plurality of light-emitting transistors may be formed of CMOS. Although Figure 2 the scan driver 610 is shown disposed on the left side of the display area DAA, and the emission driver 620 is shown disposed on the right side of the display area DAA, the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0093] The scan driver 610 may include a write scan signal output unit (e.g., a write scan signal output circuit) 611, a control scan signal output unit (e.g., a control scan signal output circuit) 612, and a bias scan signal output unit (e.g., a bias scan signal output circuit) 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0094] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line EL2.

[0095] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (e.g., see Figure 7 ) by a semiconductor process. For example, the plurality of data transistors may be formed of CMOS.

[0096] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0097] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0098] Reference Figure 3 , the sub-pixel SP can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Additionally, the sub-pixel SP can be connected to the first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied (for example, see Figure 2 ), the second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied (for example, see Figure 2 ), and the third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied (for example, see Figure 2 ). In other words, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0099] The sub-pixel SP includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor C1, and a second capacitor C2.

[0100] The light-emitting element LE emits light in response to a driving current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the driving current Ids. The light-emitting element LE can be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element LE can be a micro light-emitting diode.

[0101] The first transistor T1 can be a driving transistor that controls a source-drain current Ids (hereinafter referred to as "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0102] The second transistor T2 may be arranged between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Accordingly, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0103] The third transistor T3 may be arranged between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Thus, since the gate electrode and the drain electrode of the first transistor T1 are connected to each other, the first transistor T1 can operate like a diode (for example, may be diode-connected). The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0104] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the drive current Ids of the first transistor T1 may be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0105] The fifth transistor T5 may be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Accordingly, the third drive voltage VINT of the third drive voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0106] The sixth transistor T6 may be arranged between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Accordingly, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0107] A first capacitor C1 is formed between a first node N1 and a drain electrode of a second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0108] A second capacitor C2 is formed between a gate electrode of a first transistor T1 and a second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0109] The first node N1 is a junction point among the gate electrode of the first transistor T1, the drain electrode of a third transistor T3, another electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction point among the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of a fourth transistor T4. The third node N3 is a junction point among the drain electrode of the fourth transistor T4, the source electrode of a fifth transistor T5, and a first electrode of a light-emitting element LE.

[0110] Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. As another example, each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. As another example, some of the first transistor T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0111] Although Figure 3 it is shown that the sub-pixel SP includes six transistors T1 to T6 and two capacitors C1 and C2, the present disclosure is not limited to Figure 3 the equivalent circuit diagram of the sub-pixel SP shown in Figure 3 For example, the number of transistors and the number of capacitors of the sub-pixel SP are not limited to

[0112] Figure 4 is a diagram showing a display panel according to an embodiment.

[0113] Referring to Figure 4, the display panel 100 according to an embodiment may include a plurality of pixels PX arranged in a matrix form in a display area DAA. The display panel 100 may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a pad portion PDA, a power connection portion PCA, and a dam structure DAM disposed in a non-display area NDA. In addition, the display panel 100 may further include an electrostatic protection portion, a moisture penetration prevention portion, and a crack prevention portion disposed outside the dam structure DAM.

[0114] The scan driver 610 may be disposed on a first side of the display area DAA, and the emission driver 620 may be disposed on a second side of the display area DAA. For example, the scan driver 610 may be disposed on one side of the display area DAA in a first direction DR1, and the emission driver 620 may be disposed on the other side of the display area DAA in the first direction DR1. In other words, the scan driver 610 may be disposed on the left side of the display area DAA, and the emission driver 620 may be disposed on the right side of the display area DAA. However, the present specification is not limited thereto, and the scan driver 610 and the emission driver 620 may be disposed on both the first side and the second side of the display area DAA.

[0115] The pad portion PDA may include a plurality of pads PD connected to pads or bumps of a circuit board 300 through a conductive bonding member. The pad portion PDA may be disposed on a third side of the display area DAA. For example, the pad portion PDA may be disposed on one side of the display area DAA in a second direction DR2. In other words, the pad portion PDA may be disposed on the lower side of the display area DAA. The pad portion PDA may be disposed outside the data driver 700 in the second direction DR2. In other words, the pad portion PDA may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0116] In some embodiments, the display panel 100 may further include inspection pads to check whether the display panel 100 is operating normally. The inspection pads may be connected to a jig or probe pins during an inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0117] The first distribution circuit 710 distributes data voltages applied through the pad portion PDA to a plurality of data lines DL (for example, see Figure 2)。For example, the first distribution circuit 710 may distribute data voltages applied through one pad PD of the pad portion PDA to P data lines DL (where P is a positive integer of 2 or greater), and as a result, the number of the plurality of pads PD may be reduced. The first distribution circuit 710 may be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be disposed on one side of the display area DAA in the second direction DR2. In other words, the first distribution circuit 710 may be disposed on the lower side of the display area DAA.

[0118] The second distribution circuit 720 distributes signals applied through the pad portion PDA to the scan driver 610, the emission driver 620, and the data lines DL. The second distribution circuit 720 may check operations of each of the pixels PX in the display area DAA. The second distribution circuit 720 may be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be disposed on the other side of the display area DAA in the second direction DR2. In other words, the second distribution circuit 720 may be disposed on the upper side of the display area DAA. However, the present disclosure is not limited thereto, and the second distribution circuit 720 may be omitted as needed or desired.

[0119] The power connection portion PCA refers to an area where a second electrode of a light-emitting element LE (e.g., see Figure 3 ) and a power connection electrode to which a first driving voltage VSS is applied (e.g., see Figure 2 ) are connected to each other to apply the first driving voltage VSS to the second electrode of the light-emitting element LE.

[0120] The power connection portion PCA may be disposed to surround the display area DAA (e.g., around the periphery of the display area DAA). Additionally, the power connection portion PCA may be disposed outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the power connection portion PCA may be disposed closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The power connection portion PCA may be disposed to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. However, the present disclosure is not limited thereto, and the power connection portion PCA may overlap at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0121] The dam structure DAM may be for preventing or substantially preventing an organic encapsulation layer TFE2 of an encapsulation layer TFE for encapsulating the light-emitting element LE (e.g., see Figure 3 ) (e.g., see Figure 7)The structure of the overflow to the pad portion PDA.

[0122] The dam structure DAM can be arranged to surround the display area DAA (e.g., around the periphery of the display area DAA). Additionally, the dam structure DAM can be arranged outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the dam structure DAM can be arranged closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The dam structure DAM can be arranged to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. However, the present disclosure is not limited thereto, and the dam structure DAM can overlap at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0123] Additionally, the dam structure DAM can be arranged outside the power connection portion PCA. For example, the dam structure DAM can be arranged closer to the edge of the display panel 100 than the power connection portion PCA. The dam structure DAM can be arranged to surround the power connection portion PCA (e.g., around the periphery of the power connection portion PCA).

[0124] According to an embodiment, the dam structure DAM can include a first dam DM1 surrounding the display area DAA (e.g., around the periphery of the display area DAA) and a second dam DM2 surrounding the first dam DM1 (e.g., around the periphery of the first dam DM1). In the display device 10 (e.g., see Figure 1 ), since the dam structure DAM can be formed by one dam or multiple dams DM1 and DM2, the overflow of the encapsulation layer can be smoothly controlled. Additionally, as will be described in more detail below, the dams DM1 and DM2 can each include a plurality of dam patterns DMP1 and DMP2 spaced apart from each other (e.g., see Figure 8 )(e.g., can be made of a plurality of dam patterns DMP1 and DMP2 spaced apart from each other), and the edge of the encapsulation layer can be formed more smoothly to improve product quality.

[0125] Figure 5 is a plan view showing the first electrode, the emission area, and the pixel defining film of a plurality of pixels arranged in the Figure 4 display area.

[0126] Referring to Figure 5 , a plurality of pixels PX (e.g., see Figure 2Each of them in

[0127] Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be a region defined by a pixel defining film PDL. For example, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be a region defined by a first pixel defining film PDL1.

[0128] The length of the third emission region EA3 in the first direction DR1 may be less than the length of the first emission region EA1 in the first direction DR1, and may be less than the length of the second emission region EA2 in the first direction DR1. The length of the first emission region EA1 in the first direction DR1 and the length of the second emission region EA2 in the first direction DR1 may be the same as or substantially the same as each other.

[0129] In each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The area of the first emission region EA1, the area of the second emission region EA2, and the area of the third emission region EA3 may be different from each other.

[0130] The first emission region EA1 may emit light of a first color, the second emission region EA2 may emit light of a second color, and the third emission region EA3 may emit light of a third color. The light of the first color may be light in a red wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a blue wavelength band. For example, the blue wavelength band may be a wavelength band of light having a peak wavelength in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light having a peak wavelength in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light having a peak wavelength in the range of about 600 nm to about 750 nm.

[0131] In a plan view, a first electrode AND of a light emitting element LE (for example, see Figure 3 ) (for example, see Figure 7) may have a rectangular shape. Among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the planar shape of the first electrode AND of the light-emitting element LE may be different. For example, the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2 may have a rectangular planar shape including a long side extending in the first direction DR1 and a short side extending in the second direction DR2. In a plan view, the first electrode AND of the third sub-pixel SP3 may have a rectangular shape including a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The length of the first electrode AND of the third sub-pixel SP3 in the first direction DR1 may be shorter than the length of the first electrode AND of each of the first sub-pixel SP1 and the second sub-pixel SP2 in the first direction DR1. The length of the first electrode AND of the first sub-pixel SP1 in the second direction DR2 may be longer than the length of the first electrode AND of the second sub-pixel SP2 in the second direction DR2.

[0132] The first electrode AND of the light-emitting element LE may be connected to the reflective electrode layer RL through the tenth via hole VA10 (for example, see Figure 7 ). The tenth via hole VA10 may overlap with the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 in the third direction DR3. Figure 7 )

[0133] At least one trench TRC may be a structure for disconnecting at least one charge generation layer of the light-emitting stack IL (for example, see Figure 7 ) between adjacent (e.g., neighboring) emission regions EA1, EA2, and EA3. At least one trench TRC may be disposed between the first emission region EA1 and the second emission region EA2, between the first emission region EA1 and the third emission region EA3, and between the second emission region EA2 and the third emission region EA3. More specifically, at least one trench TRC may be disposed between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0134] Figure 6 is a plan view showing the first electrodes, emission regions, and pixel defining films of a plurality of sub-pixels according to another embodiment.

[0135] Since the planar shapes of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from those described above with reference to Figure 5 and Figure 6The embodiments shown may be the same as or substantially the same as those described above with reference to Figure 5 and thus the redundant descriptions thereof may not be repeated.

[0136] With reference to Figure 6 , the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be arranged in a hexagonal structure having a hexagonal shape in a plan view. In this case, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in a first direction DR1. The second emission region EA2 and the third emission region EA3 may be adjacent to each other in a first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 may be adjacent to each other in a second diagonal direction DD2. The first diagonal direction DD1 may be a direction between the first direction DR1 and the second direction DR2, and may indicate a direction inclined 45 degrees with respect to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 may be a direction perpendicular or substantially perpendicular to the first diagonal direction DD1.

[0137] Although Figure 5 and Figure 6 show that each of the plurality of pixels PX includes three emission regions EA1, EA2, and EA3, the present disclosure is not limited thereto. In other words, each of the plurality of pixels PX may include four emission regions.

[0138] In addition, the arrangement of the emission regions EA1, EA2, and EA3 of the plurality of pixels PX is not limited to the arrangement shown in Figure 5 and Figure 6 . For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, an RGBG structure in which the emission regions are arranged in a diamond shape (e.g., structure, is a registered trademark of Samsung Display Co., Ltd.) or a similar shape.

[0139] Figure 7 is a schematic cross-sectional view taken along line A-A' of Figure 5 .

[0140] With reference to Figure 7 , the display panel 100 (e.g., see Figure 4 ) may include a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, a packaging layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens array layer LNS, and a cover layer DCL. In some embodiments, the display panel 100 may further include a polarizing plate disposed on the cover layer DCL.

[0141] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE respectively electrically connected to the plurality of pixel transistors PTR. The plurality of pixel transistors PTR may be the first transistor T1 to the sixth transistor T6 described above with reference to Figure 3 Description of the first transistor T1 to the sixth transistor T6.

[0142] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be disposed at the top surface (e.g., middle or upper) of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. As another example, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0143] Each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0144] The lower insulating film BINS may be disposed between the gate electrode GE and the well region WA. The side insulating film SINS may be disposed on the side surface of the gate electrode GE. The side insulating film SINS may be disposed on the lower insulating film BINS.

[0145] Each of the source region SA and the drain region DA may be a region doped with a first type of impurity. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the other side (e.g., opposite side) of the gate electrode GE.

[0146] Each of the plurality of well regions WA further includes a first lightly doped drain region LDD1 disposed between the channel region CH and the source region SA and a second lightly doped drain region LDD2 disposed between the channel region CH and the drain region DA. The first lightly doped drain region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the underlying insulating film BINS. The second lightly doped drain region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the underlying insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first lightly doped drain region LDD1 and the second lightly doped drain region LDD2. Accordingly, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby preventing or substantially preventing punch-through and hot carrier phenomena that may be caused by a short channel.

[0147] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed of a silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0148] The second semiconductor insulating film SINS2 may be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0149] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy including at least one of the above materials.

[0150] The third semiconductor insulating film SINS3 may be disposed on the second semiconductor insulating film SINS2. The third semiconductor insulating film SINS3 may also be disposed on side surfaces of each of some of the contact terminals CTE among the plurality of contact terminals CTE disposed on the second semiconductor insulating film SINS2. The top surface of each of the plurality of contact terminals CTE may be exposed and not covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0151] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors can be arranged on the glass substrate or the polymer resin substrate. The glass substrate can be a non-bendable rigid substrate, and the polymer resin substrate can be a flexible substrate capable of being bent or curved.

[0152] The light-emitting element backplane EBP includes a first metal layer ML1 to an eighth metal layer ML8, a reflective electrode layer RL, and a plurality of vias VA1 to VA10. In addition, the light-emitting element backplane EBP includes a plurality of interlayer insulating films INS1 to INS11 arranged between the semiconductor backplane SBP, the first metal layer ML1 to the eighth metal layer ML8, the reflective electrode layer RL, and the light-emitting element layer EML.

[0153] The first metal layer ML1 to the eighth metal layer ML8 can be connected to a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to form Figure 3 the circuit of the sub-pixel SP shown in. The first transistor T1 to the sixth transistor T6 (for example, see Figure 3 ) can be formed at (for example, in or on) the semiconductor backplane SBP, and the connection of the first transistor T1 to the sixth transistor T6 and the first capacitor C1 and the second capacitor C2 (for example, see Figure 3 ) can be achieved through the first metal layer ML1 to the eighth metal layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE can also be achieved through the first metal layer ML1 to the eighth metal layer ML8.

[0154] The first interlayer insulating film INS1 can be arranged on the semiconductor backplane SBP. Each of the first vias VA1 can penetrate the first interlayer insulating film INS1 to connect to the corresponding contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 can be arranged on the first interlayer insulating film INS1 and can be connected to the corresponding first via VA1.

[0155] The second interlayer insulating film INS2 can be arranged on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 can penetrate the second interlayer insulating film INS2 and connect to the corresponding exposed first metal layer ML1. Each of the second metal layers ML2 can be arranged on the second interlayer insulating film INS2 and can be connected to the corresponding second via VA2.

[0156] The third interlayer insulating film INS3 can be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 can penetrate the third interlayer insulating film INS3 and be connected to a corresponding exposed second metal layer ML2. Each of the third metal layers ML3 can be disposed on the third interlayer insulating film INS3 and be connected to a corresponding third via VA3.

[0157] The fourth interlayer insulating film INS4 can be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 can penetrate the fourth interlayer insulating film INS4 and be connected to a corresponding exposed third metal layer ML3. Each of the fourth metal layers ML4 can be disposed on the fourth interlayer insulating film INS4 and be connected to a corresponding fourth via VA4.

[0158] The fifth interlayer insulating film INS5 can be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 can penetrate the fifth interlayer insulating film INS5 and be connected to a corresponding exposed fourth metal layer ML4. Each of the fifth metal layers ML5 can be disposed on the fifth interlayer insulating film INS5 and can be connected to a corresponding fifth via VA5.

[0159] The sixth interlayer insulating film INS6 can be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 can penetrate the sixth interlayer insulating film INS6 and be connected to a corresponding exposed fifth metal layer ML5. Each of the sixth metal layers ML6 can be disposed on the sixth interlayer insulating film INS6 and can be connected to a corresponding sixth via VA6.

[0160] The seventh interlayer insulating film INS7 can be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 can penetrate the seventh interlayer insulating film INS7 and be connected to a corresponding exposed sixth metal layer ML6. Each of the seventh metal layers ML7 can be disposed on the seventh interlayer insulating film INS7 and can be connected to a corresponding seventh via VA7.

[0161] The eighth interlayer insulating film INS8 can be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 can penetrate the eighth interlayer insulating film INS8 and can be connected to a corresponding exposed seventh metal layer ML7. Each of the eighth metal layers ML8 can be disposed on the eighth interlayer insulating film INS8 and can be connected to a corresponding eighth via VA8.

[0162] The first metal layer ML1 to the eighth metal layer ML8 and the first vias VA1 to the eighth vias VA8 may be formed of the same or substantially the same material as each other. The first metal layer ML1 to the eighth metal layer ML8 and the first vias VA1 to the eighth vias VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. The first vias VA1 to the eighth vias VA8 may be made of the same or substantially the same material as each other. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0163] The thicknesses of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thicknesses of the first vias VA1, the second vias VA2, the third vias VA3, the fourth vias VA4, the fifth vias VA5, and the sixth vias VA6, respectively. The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be the same or substantially the same as each other. For example, the thickness of the first metal layer ML1 may be about The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be about And the thickness of each of the first vias VA1, the second vias VA2, the third vias VA3, the fourth vias VA4, the fifth vias VA5, and the sixth vias VA6 may be about

[0164] The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8. The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be greater than the thickness of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be the same as or substantially the same as each other. For example, the thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be about The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be about

[0165] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0166] Each of the ninth via holes VA9 may penetrate the ninth interlayer insulating film INS9 and be connected to the corresponding exposed eighth metal layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy including at least one of the above materials. The thickness of the ninth via hole VA9 may be about

[0167] The reflective electrode layer RL may be disposed on the ninth interlayer insulating film INS9. The reflective electrode layer RL may include at least one of the reflective electrodes RL1, RL2, RL3, and / or RL4. For example, as Figure 7 shown, the reflective electrode RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0168] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the corresponding ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy including at least one of the above materials. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0169] Each of the second reflective electrodes RL2 may be disposed on a corresponding first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. For example, the second reflective electrode RL2 may include aluminum (Al).

[0170] Each of the third reflective electrodes RL3 may be disposed on a corresponding second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0171] The fourth reflective electrodes RL4 may be respectively disposed on the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0172] Since the second reflective electrode RL2 is an electrode that reflects or substantially reflects light from the light-emitting element LE (for example, see Figure 3 ), the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be about and the thickness of the second reflective electrode RL2 may be

[0173] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 may be disposed between the reflective electrode layers RL adjacent to each other. The tenth interlayer insulating film INS10 may be disposed on the reflective electrode layer RL in the third sub-pixel SP3. The tenth interlayer insulating film INS10 may be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0174] The eleventh interlayer insulating film INS11 may be disposed on the tenth interlayer insulating film INS10 and the reflective electrode layer RL. The eleventh interlayer insulating film INS11 may be formed of a silicon oxide (SiO x)The base inorganic layer is formed, but the present disclosure is not limited thereto.

[0175] In at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, considering the resonance distance of the light emitted from the light-emitting element LE, the tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 may not be disposed under the first electrode AND.

[0176] For example, the first electrode AND of the first sub-pixel SP1 may be directly disposed on the fourth reflective electrode RL4, and the first electrode AND of the first sub-pixel SP1 may not overlap with the tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11. The first electrode AND of the second sub-pixel SP2 may be disposed on the eleventh interlayer insulating film INS11, and the eleventh interlayer insulating film INS11 may be directly disposed on the fourth reflective electrode RL4. In other words, the first electrode AND of the second sub-pixel SP2 may not overlap with the tenth interlayer insulating film INS10. The first electrode AND of the third sub-pixel SP3 may be disposed on the eleventh interlayer insulating film INS11 and may overlap with the tenth interlayer insulating film INS10.

[0177] In an embodiment, in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode AND and the reflective electrode layer RL may be different. In order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be set. For example, in Figure 7 the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. However, the present disclosure is not limited thereto. The distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3 may be variously modified and designed as needed or desired.

[0178] In addition, although the tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 are shown in Figure 7 the sub-pixel SP (for example, see Figure 3) The twelfth interlayer insulating film may also be disposed under the first electrode AND of (). In this case, the eleventh interlayer insulating film INS11 and the twelfth interlayer insulating film may be disposed under the first electrode AND of the second sub-pixel SP2, and the tenth interlayer insulating film INS10, the eleventh interlayer insulating film INS11, and the twelfth interlayer insulating film may be disposed under the first electrode AND of the third sub-pixel SP3. As another example, the eleventh interlayer insulating film INS11 may be omitted as needed or desired.

[0179] In the second sub-pixel SP2 and the third sub-pixel SP3, each of the tenth vias VA10 may penetrate the tenth interlayer insulating film INS10 and / or the eleventh interlayer insulating film INS11 and may be connected to the corresponding exposed fourth reflective electrode RL4. The tenth via VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. The thickness of the tenth via VA10 in the second sub-pixel SP2 may be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0180] The light-emitting element layer EML may be disposed on the light-emitting element backplane EBP. The light-emitting element layer EML may include light-emitting elements LE (for example, see Figure 3 ), a pixel defining film PDL, and a plurality of trenches TRC, each having a first electrode AND, a light-emitting stack IL (for example, an intermediate layer), and a second electrode CAT.

[0181] The first electrode AND of each of the light-emitting elements LE may be disposed on the tenth interlayer insulating film INS10 or the eleventh interlayer insulating film INS11 and may be connected to the corresponding tenth via hole VA10, or may be directly disposed on the fourth reflective electrode RL4. In the second sub-pixel SP2 and the third sub-pixel SP3, the first electrode AND of each of the light-emitting elements LE may be connected to the corresponding drain region DA or the corresponding source region SA of the corresponding pixel transistor PTR through the tenth via hole VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first via hole VA1 to the ninth via hole VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. In the first sub-pixel SP1, the first electrode AND of each of the light-emitting elements LE may be connected to the corresponding drain region DA or the corresponding source region SA of the corresponding pixel transistor PTR through the first reflective electrode RL1 to the fourth reflective electrode RL4, the first via hole VA1 to the ninth via hole VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. For example, the first electrode AND of each of the light-emitting elements LE may include (e.g., may be) titanium nitride (TiN).

[0182] The pixel defining film PDL may be disposed on a part of the first electrode AND of each of the light-emitting elements LE. The pixel defining film PDL may cover the edge of the first electrode AND of each of the light-emitting elements LE. The pixel defining film PDL may be used to separate the first emission region EA1, the second emission region EA2, and the third emission region EA3 from each other.

[0183] The first emission region EA1 may be defined as a region where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 may be defined as a region where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 may be defined as a region where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0184] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of a first electrode AND of each of the light emitting elements LE. The second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1. The third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about .

[0185] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as one pixel defining layer, the height of the one pixel defining layer increases, such that the first inorganic encapsulation layer TFE1 may be disconnected due to step coverage. Step coverage is the ratio of the degree to which a thin film is coated on an inclined portion to the degree to which the thin film is coated on a flat portion. The lower the step coverage, the greater the likelihood that the thin film will be disconnected at the inclined portion.

[0186] To prevent or substantially prevent the first inorganic encapsulation layer TFE1 from being disconnected due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a cross-sectional structure including a stepped portion. For example, the width of the first pixel defining layer PDL1 may be greater than the widths of the second pixel defining layer PDL2 and the third pixel defining layer PDL3. The width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined in a first direction DR1 and a second direction DR2 (e.g., see Figure 5 ).

[0187] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. In each of the plurality of trenches TRC, a part of the tenth interlayer insulating film INS10 may be dug out, and the eleventh interlayer insulating film INS11 may have a shape in which the eleventh interlayer insulating film INS11 is penetrated.

[0188] At least one trench TRC may be disposed between adjacent sub-pixels SP1, SP2, and SP3. Figure 7 Two trenches TRC are shown disposed between adjacent sub-pixels SP1, SP2, and SP3, but the present disclosure is not limited thereto.

[0189] The light-emitting stack IL may include a plurality of intermediate layers. Figure 7 The light-emitting stack IL is shown to have a three-tandem structure including a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3, but the present disclosure is not limited thereto. For example, the light-emitting stack IL may have a two-tandem structure including two intermediate layers.

[0190] In the three-tandem structure, the light-emitting stack IL may have a tandem structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit lights of different colors from each other. For example, the light-emitting stack IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0191] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are stacked in sequence. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are stacked in sequence. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are stacked in sequence.

[0192] A first charge generation layer for supplying charge to the second intermediate layer IL2 and for supplying electrons to the first intermediate layer IL1 may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first intermediate layer IL1 and a P-type charge generation layer that supplies holes to the second intermediate layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0193] A second charge generation layer for supplying charge to the third intermediate layer IL3 and for supplying electrons to the second intermediate layer IL2 may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second intermediate layer IL2 and a P-type charge generation layer that supplies holes to the third intermediate layer IL3.

[0194] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first intermediate layer IL1 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the trench TRC, the second intermediate layer IL2 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A gap or empty space ESS may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. The third intermediate layer IL3 may be disposed to cover the second intermediate layer IL2 in each of the trenches TRC without being disconnected by the trench TRC. In other words, in the three-series structure, each of the trenches TRC may be a structure for disconnecting the first charge generation layer, the second charge generation layer, and the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between adjacent sub-pixels SP1, SP2, and SP3. Additionally, in the two-series structure, each of the trenches TRC may be a structure for disconnecting the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0195] To stably disconnect the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each trench TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To disconnect the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light-emitting element layer EML between adjacent sub-pixels SP1, SP2, and SP3, there may be other structures instead of the trench TRC. For example, an inverted cone partition wall may be disposed on the pixel defining layer PDL instead of the trench TRC.

[0196] The number of the intermediate layers IL1, IL2, and IL3 that emit lights of different colors from each other is not limited to Figure 7 the number shown in. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be the same as or substantially the same as the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and for supplying charges to the other intermediate layer may be disposed between the two intermediate layers.

[0197] Additionally, Figure 7It is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but the present disclosure is not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first emission region EA1, but may not be disposed in the second emission region EA2 and the third emission region EA3. In addition, the second intermediate layer IL2 may be disposed in the second emission region EA2, but may not be disposed in the first emission region EA1 and the third emission region EA3. In addition, the third intermediate layer IL3 may be disposed in the third emission region EA3, but may not be disposed in the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer may be omitted.

[0198] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO that transmits light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity effect.

[0199] The encapsulation layer TFE may be disposed on the light-emitting element layer EML. The encapsulation layer TFE may include at least one inorganic encapsulation layer TFE1 and TFE3 to prevent or substantially prevent oxygen or moisture from penetrating into the light-emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic encapsulation layer TFE2 to protect the light-emitting element layer EML from foreign substances such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0200] The first inorganic encapsulation layer TFE1 may be disposed on the second electrode CAT. The organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed of a material in which a silicon nitride (SiN x ) layer, a silicon oxynitride (SiO x N y ) layer, a silicon oxide (SiO x ) layer, a titanium oxide (TiO x ) layer, and an aluminum oxide (AlO x) Formation of a multi-layer including one or more inorganic layers. The organic encapsulation layer TFE2 can be a monomer. As another example, the organic encapsulation layer TFE2 can be an organic layer including such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0201] The adhesive layer ADL can be disposed on the encapsulation layer TFE. The adhesive layer ADL can be a layer for bonding the encapsulation layer TFE to the layer disposed thereon. The adhesive layer ADL can be a double-sided adhesive member. Additionally, the adhesive layer ADL can be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0202] The color filter layer CFL, the lens array layer LNS, and the cover layer DCL can be disposed on the adhesive layer ADL. The color filter layer CFL, the lens array layer LNS, and the cover layer DCL can constitute the optical layer of the display panel 100 (for example, see Figure 4 ).

[0203] The color filter layer CFL can include a plurality of color filters CF1, CF2, and CF3, and can be disposed on the adhesive layer ADL. The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of the first color (for example, light in the red wavelength band). The first color filter CF1 can transmit light of the first color among the light emitted from the first emission region EA1.

[0204] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of the second color (for example, light in the green wavelength band). Thus, the second color filter CF2 can transmit light of the second color among the light emitted from the second emission region EA2.

[0205] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color (for example, light in the blue wavelength band). Thus, the third color filter CF3 can transmit light of the third color among the light emitted from the third emission region EA3.

[0206] The lens array layer LNS can be disposed on the color filter layer CFL in the display area DAA (for example, see Figure 4 ). The lens array layer LNS can include a plurality of lenses disposed in the display area DAA. The plurality of lenses can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses can be a structure for increasing the ratio of light directed towards the front of the display device 10 (for example, see Figure 1 ). Each of the plurality of lenses can have a cross-sectional shape that bulges in the upward direction.

[0207] The cover layer DCL can be arranged on the lens array layer LNS. The cover layer DCL can be directly arranged on multiple lenses of the lens array layer LNS. The cover layer DCL can have a desired refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at the interface between the multiple lenses and the cover layer DCL. Additionally, the cover layer DCL can be a planarization layer. The cover layer DCL can be an organic layer containing such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0208] In some embodiments, a polarizing plate can also be arranged on the cover layer DCL. The polarizing plate can be a structure for preventing or substantially preventing visibility degradation that may be caused by reflection of external light. The polarizing plate can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but the present disclosure is not limited thereto. However, when visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate can be omitted.

[0209] As Figure 7 shown, by forming the light-emitting element backplane EBP and the light-emitting element layer EML on a semiconductor substrate SSUB on which multiple transistors are formed (e.g., in or on), the size of multiple pixels PX (e.g., see Figure 2 ) can be reduced (e.g., can be significantly reduced), so that a display device 10 for displaying high-resolution images can be provided (e.g., see Figure 1 ).

[0210] Figure 8 is an enlarged view of the region X showing Figure 4 . Figure 9 is a schematic cross-sectional view taken along the line B-B' of Figure 8 .

[0211] Figure 4 The region X of Figure 8 and Figure 9 can be a region arranged on the lower side of one side in the second direction DR2 of the display area DAA.

[0212] Referring to Figure 8 and Figure 9, the first distribution circuit 710, the power connection part PCA, the dam structure DAM, the data driver 700, and the pad PD may be sequentially arranged along the second direction DR2 on the lower side of the display area DAA. However, the present disclosure is not limited thereto. In some embodiments, the power connection part PCA may overlap with the first distribution circuit 710 or the data driver 700 in the thickness direction, and the dam structure DAM may overlap with the first distribution circuit 710 or the data driver 700 in the thickness direction.

[0213] The first distribution circuit 710 may include a plurality of first distribution transistors DBTR1. Since each of the plurality of first distribution transistors DBTR1 may be formed in the same or substantially the same manner as the pixel transistor PTR described above with reference to Figure 7 description, its redundant description will not be repeated. Additionally, since the first metal layer ML1 to the eighth metal layer ML8 and the first vias VA1 to the eighth vias VA8 electrically connected to the plurality of first distribution transistors DBTR1 are also the same or substantially the same as those described above with reference to Figure 7 description, its redundant description will not be repeated.

[0214] The power connection part PCA includes a first power connection area PCAA1 of the semiconductor substrate SSUB, a first power connection electrode PCE1, and a second power connection electrode PCE2.

[0215] The first driving voltage VSS (for example, see Figure 2 ) may be applied to the first power connection area PCAA1 of the semiconductor substrate SSUB.

[0216] The first power connection electrode PCE1 may be disposed on the ninth interlayer insulating film INS9. The first power connection electrode PCE1 may be connected to the first power connection area PCAA1 of the semiconductor substrate SSUB through the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the ninth via VA9.

[0217] The first power connection electrode PCE1 may include a first sub - power connection electrode SPCE1 to a fourth sub - power connection electrode SPCE4. The first sub - power connection electrode SPCE1 to the fourth sub - power connection electrode SPCE4 of the first power connection electrode PCE1 may be the same or substantially the same as the first reflection electrode RL1 to the fourth reflection electrode RL4 of the reflection electrode layer RL (for example, see Figure 7 ). In other words, the first sub - power connection electrode SPCE1 may correspond to the first reflection electrode RL1, the second sub - power connection electrode SPCE2 may correspond to the second reflection electrode RL2, the third sub - power connection electrode SPCE3 may correspond to the third reflection electrode RL3, and the fourth sub - power connection electrode SPCE4 may correspond to the fourth reflection electrode RL4.

[0218] The second power connection electrode PCE2 may be disposed on the tenth interlayer insulating film INS10 or the eleventh interlayer insulating film INS11. The second power connection electrode PCE2 may be connected to the first power connection electrode PCE1 through the tenth through hole VA10. The second power connection electrode PCE2 may include a light emitting element LE (eg, Figure 3 ) of the first electrode AND (see, for example, Figure 7 ) or substantially the same material. The second power connection electrode PCE2 may be separated by the pixel definition film PDL. The second electrode CAT of the light emitting element LE may be connected to the second power connection electrode PCE2 exposed by the pixel definition film PDL without being covered.

[0219] The dam structure DAM may include a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 may be aligned with the trench TRC (eg, see Figure 7 ) are the same or substantially the same. Each of the first dam DM1 and the second dam DM2 may have a groove shape penetrating at least the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Each of the first dam DM1 and the second dam DM2 may penetrate the pixel defining film PDL and the eleventh interlayer insulating film INS11.

[0220] In the first dam DM1, the first inorganic encapsulation layer TFE1 may be arranged on the bottom surface thereof, the organic encapsulation layer TFE2 may be arranged on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be arranged on the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may be arranged to fill a portion of the first dam DM1. In the second dam DM2, the first inorganic encapsulation layer TFE1 may be arranged on the bottom surface thereof, and the second inorganic encapsulation layer TFE3 may be arranged on the first inorganic encapsulation layer TFE1. The organic encapsulation layer TFE2 may not be arranged in the second dam DM2. In the display device 10 (for example, see Figure 1 ), the dam structure DAM is composed of two or more dams DM1 and DM2, and the organic encapsulation layer TFE2 may be arranged in the innermost dam (for example, in the first dam DM1), and may cover the innermost dam. However, the organic encapsulation layer TFE2 may not be arranged in the outermost dam such as the second dam DM2, and may not cover the outermost dam. Due to the presence of the first dam DM1 and the second dam DM2, the organic encapsulation layer TFE2 may be prevented or substantially prevented from flowing to the pad portion PDA (for example, see Figure 4 ) to cover the pad PD. The organic encapsulation layer TFE2 can be prevented from covering the pad PD, and thus the pad PD is allowed to be electrically connected to the circuit board 300 (eg, see Figure 1 ).

[0221] According to an embodiment, in the display device 10, the plurality of dams DM1 and DM2 may include dam patterns DMP1 and DMP2 spaced apart from each other. The first dam DM1 may include a plurality of first dam patterns DMP1 spaced apart from each other, and the second dam DM2 may include a plurality of second dam patterns DMP2 spaced apart from each other. The first dam pattern DMP1 may be arranged to be spaced apart from each other while surrounding the display area DAA (e.g., see Figure 4 )(e.g., around the periphery of the display area DAA), and the second dam pattern DMP2 may be arranged to be spaced apart from each other while surrounding the first dam DM1 (e.g., around the periphery of the first dam DM1). For example, as shown in Figure 8 , the plurality of first dam patterns DMP1 may be arranged along the edge of the display area DAA and may be arranged to be spaced apart from each other in a first direction DR1 on the lower side of the display area DAA. The first dam pattern DMP1 may also be arranged to be spaced apart from each other in the first direction DR1 on the upper side of the display area DAA, and the first dam pattern DMP1 may be arranged to be spaced apart from each other in a second direction DR2 on the left and right sides of the display area DAA. The second dam pattern DMP2 may be arranged outside the first dam pattern DMP1 and may be arranged side by side with the first dam pattern DMP1. For example, the second dam pattern DMP2 may be arranged to be spaced apart from each other in the first direction DR1 on the upper and lower sides of the display area DAA, and may be arranged to be spaced apart from each other in the second direction DR2 on the left and right sides of the display area DAA. In the display device 10, the dams DM1 and DM2 of the dam structure DAM may include dam patterns DMP1 and DMP2 spaced apart from each other such that the organic material of the organic encapsulation layer TFE2 can be uniformly or substantially uniformly diffused.

[0222] The data driver 700 may include a plurality of data transistors DTR. Since each of the plurality of data transistors DTR may be formed to be the same as or substantially the same as the pixel transistor PTR described above with reference to Figure 7 , its redundant description will not be repeated. Additionally, since the first metal layer ML1 to the eighth metal layer ML8 and the first vias VA1 to the eighth vias VA8 electrically connected to the plurality of data transistors DTR may be the same as or substantially the same as those described above with reference to Figure 7 , their redundant descriptions will not be repeated.

[0223] Each of the pads PD may include a pad metal layer PML. The pad metal layer PML may include a first sub-pad metal layer SPML1 and a second sub-pad metal layer SPML2. The first sub-pad metal layer SPML1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. The second sub-pad metal layer SPML2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and a suitable alloy containing at least one of the above materials. For example, the first sub-pad metal layer SPML1 may be made of aluminum (Al) and may have a thickness of approximately . Additionally, the second sub-pad metal layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately . The thickness of the pad metal layer PML may be greater than the thickness of the reflective electrode layer RL (e.g., see Figure 7 ).

[0224] A part of the top surface of the pad metal layer PML of each pad PD may be exposed and not covered by the tenth interlayer insulating film INS10. The first sub-pad metal layer SPML1 may be connected to a ninth via hole VA9 that penetrates the ninth interlayer insulating film INS9 to connect to the eighth metal layer ML8.

[0225] The encapsulation layer TFE (e.g., see Figure 7 ) may also be disposed in a part of the non-display area NDA located on the lower side of the display area DAA. Although the organic encapsulation layer TFE2 of the encapsulation layer TFE is arranged up to the first dam DM1, the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE may be arranged up to the outside of the dam structure DAM to form an inorganic bonding region.

[0226] Figure 10 is an enlarged view of the region Y showing Figure 4 . Figure 11 is a schematic cross-sectional view taken along the line C-C' of Figure 10 .

[0227] Figure 4 The region Y of Figure 10 and Figure 11 may be a region arranged on the left side of the left side of the display area DAA in the first direction DR1.

[0228] Referring to Figure 10 and Figure 11, the scan driver 610, the power connection part PCA, and the dam structure DAM may be sequentially arranged along the first direction DR1 on the left side of the display area DAA. However, the present disclosure is not limited thereto, and the power connection part PCA may overlap with the scan driver 610 in the thickness direction, and the dam structure DAM may overlap with the scan driver 610 in the thickness direction.

[0229] The scan driver 610 may include a plurality of scan transistors STR. Since each of the plurality of scan transistors STR may be formed to be the same as or substantially the same as the pixel transistor PTR described above with reference to Figure 7 , its redundant description may not be repeated. Additionally, since the first metal layer ML1 to the eighth metal layer ML8 and the first vias VA1 to the eighth vias VA8 electrically connected to the plurality of scan transistors STR may be the same as or substantially the same as those described above with reference to Figure 7 , its redundant description may not be repeated.

[0230] Since the power connection part PCA and the dam structure DAM are the same as or substantially the same as those described above with reference to Figure 8 and Figure 9 , their redundant descriptions may not be repeated.

[0231] Additionally, since the area arranged on the second side of the display area DAA is the same as or substantially the same as that described above with reference to Figure 10 and Figure 11 except that the scan driver 610 is replaced with the emission driver 620, its redundant description may not be repeated.

[0232] The encapsulation layer TFE (for example, see Figure 7 ) may also be arranged in a part of the non-display area NDA located on the left side of the display area DAA. Although the organic encapsulation layer TFE2 of the encapsulation layer TFE is arranged up to the first dam DM1, the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE may be arranged up to the outside of the dam structure DAM to form an inorganic bonding area.

[0233] Figure 12 and Figure 13 are plan views showing the schematic arrangement of the encapsulation layer and the dam structure of the display device according to the embodiment. Figure 12 Shows the arrangement of the first dam DM1 and the second dam DM2 arranged on the right side of the display area DAA in the first direction DR1. Figure 13 Shows the arrangement of the first dam DM1 and the second dam DM2 arranged at the diagonal edge of the display area DAA.

[0234] Referring to Figure 12 and Figure 13 , in the display device 10 according to the embodiment (for example, seeFigure 1 ) In this case, multiple dams DM1 and DM2 may include dam patterns DMP1 and DMP2 spaced apart from each other. The first dam pattern DMP1 of the first dam DM1 may be arranged to be spaced apart from each other along the edge of the display area DAA. The length of each of the first dam patterns DMP1 measured in the direction in which they are spaced apart from each other may be greater than its width measured in a direction perpendicular or substantially perpendicular to the direction in which the first dam patterns DMP1 are spaced apart from each other. For example, on the left and right sides of the display area DAA, the first dam patterns DMP1 may be spaced apart from each other in the second direction DR2, and the length of each of the first dam patterns DMP1 measured in the second direction DR2 may be greater than its width measured in the first direction DR1. On the upper and lower sides of the display area DAA, the first dam patterns DMP1 may be spaced apart from each other in the first direction DR1, and the length of each of the first dam patterns DMP1 measured in the first direction DR1 may be greater than its width measured in the second direction DR2.

[0235] The second dam pattern DMP2 of the second dam DM2 may be arranged outside the first dam DM1 to be spaced apart from each other along the first dam pattern DMP1. The second dam pattern DMP2 may have the same or substantially the same shape as the first dam pattern DMP1, and may be arranged side by side spaced apart from the first dam pattern DMP1. For example, one first dam pattern DMP1 and one second dam pattern DMP2 may be arranged side by side in pairs, and may be arranged along the edge of the display area DAA.

[0236] The figure shows that the display device 10 includes a first dam DM1 and a second dam DM2, and the two dams DM1 and DM2 form a dam structure DAM. However, the present disclosure is not limited to this, and the display device 10 may include a greater number of dams. In this case, among the multiple dams DM1 and DM2, the first dam DM1 arranged on the inner side closest to the display area DAA may be the innermost dam, and the second dam DM2 arranged on the outer side adjacent to the edge of the display device 10 may be the outermost dam.

[0237] The display device 10 may include a packaging layer TFE arranged in a partial area of the display area DAA and the non-display area NDA (for example, see Figure 7 ) The first inorganic packaging layer TFE1 and the second inorganic packaging layer TFE3 of the packaging layer TFE (for example, see Figure 7) Each of them can be arranged to reach the outside of the dam structure DAM to form an inorganic bonding region. The organic encapsulation layer TFE2 can cover at least one of the plurality of dams DM1 and DM2 of the dam structure DAM (for example, taking the first dam DM1 as the innermost dam), but may not cover at least one dam (for example, taking the second dam DM2 as the outermost dam). The dam structure DAM can include a plurality of dams DM1 and DM2 to prevent or substantially prevent the organic encapsulation layer TFE2 including organic materials from overflowing outside the dam structure DAM until the outside of the display device 10.

[0238] In an embodiment, the organic encapsulation layer TFE2 can be formed by an inkjet printing process in which one or more organic insulating materials are discharged onto the display area DAA. When the ink droplets containing the organic insulating materials are discharged into the area surrounded by the dam structure DAM (for example, the dam structure DAM is around its periphery) while being spaced apart from each other (for example, being distant), the organic insulating materials can diffuse from the area where the ink droplets are discharged to the surrounding area, so that the organic insulating materials can be coated on the entire area surrounded by the dam structure DAM (for example, the dam structure DAM is around its periphery).

[0239] In the display device 10, the dam structure DAM for preventing or substantially preventing the overflow of organic materials includes dam patterns DMP1 and DMP2 spaced apart from each other, so that when the ink droplets diffuse, they can be guided to diffuse uniformly at their edges. Compared with the case when the dams DM1 and DM2 of the dam structure DAM have a linear shape, when the dams DM1 and DM2 have a shape in which the dam patterns DMP1 and DMP2 are spaced apart from each other, the organic materials of the ink droplets can flow sequentially to the dam patterns DMP1 and DMP2 or the area between them, and the straightness at the edge of the organic encapsulation layer TFE2 can be improved. The thickness of the organic encapsulation layer TFE2 can be reduced by reducing the spacing of the ink droplets. Even if the spacing of the ink droplets is reduced, since the dam structure DAM has a shape in which the dam patterns DMP1 and DMP2 are spaced apart from each other, the straightness of the outermost edge of the organic encapsulation layer TFE2 can be ensured. Accordingly, in the display device 10, the brightness and light emission efficiency can be improved by reducing the thickness of the organic encapsulation layer TFE2, and the product reliability can be ensured by controlling the edge shape of the organic encapsulation layer TFE2.

[0240] In an embodiment, the interval between adjacent first dam patterns DMP1 or the interval between adjacent second dam patterns DMP2 may be smaller than the pitch between ink droplets. For example, the pitch between ink droplets may have a size of about 100 μm, and the interval DW between adjacent first dam patterns DMP1 or the interval between adjacent second dam patterns DMP2 may be 100 μm or less. Since the interval DW between the dam patterns DMP1 (DMP2) is formed to be smaller than the pitch between ink droplets, at least one dam pattern DMP1 (DMP2) can be positioned between adjacent ink droplets, and thus it is possible to prevent or substantially prevent the formation of a curve at the edge as the ink droplets spread.

[0241] In an embodiment, the diagonal edge of the display area DAA may have a curved shape instead of a right-angled shape. As Figure 13 shown, in the display area DAA, the edge positioned in the diagonal direction between the first direction DR1 and the second direction DR2 may have a curved shape instead of a right angle, and accordingly, since the dam patterns DMP1 and DMP2 are arranged along the curved edge of the display area DAA, the first dam DM1 and the second dam DM2 may also have curved outer edges. The first dam DM1 may include a plurality of third dam patterns DMP3 arranged to correspond to the curved edge of the display area DAA, and the second dam DM2 may include a plurality of fourth dam patterns DMP4 arranged to correspond to the curved edge of the display area DAA.

[0242] The first dam pattern DMP1 and the second dam pattern DMP2 may have a shape in which each of their sides extends in one direction and the intersecting portion of the two sides may have a right angle. On the other hand, the third dam pattern DMP3 and the fourth dam pattern DMP4 may have a shape in which the side edges in the length direction are curved. The curvature (R value) of the side edges of the third dam pattern DMP3 and the fourth dam pattern DMP4 may be equal to or substantially equal to the curvature (R value) of the diagonal edge of the organic encapsulation layer TFE2. Since the first dam DM1 and the second dam DM2 include the dam patterns DMP3 and DMP4 having curved side edges to correspond to the diagonal edge of the display area DAA, the distance from the edge of the display area DAA to the first dam DM1 may be constant or substantially constant regardless of the position. Accordingly, the ink droplets forming the organic encapsulation layer TFE2 may spread uniformly or substantially uniformly in the area surrounded by the first dam DM1 (for example, the first dam DM1 surrounds it on its periphery).

[0243] Figure 14 is a plan view schematically showing the arrangement of the encapsulation layer and the dam structure of a display device according to another embodiment.

[0244] Referring to Figure 14 In the display device 10 according to an embodiment (for example, see Figure 1In [the figure], the first dam pattern DMP1 of the first dam DM1 may not be arranged side by side with the second dam pattern DMP2 of the second dam DM2. A plurality of first dam patterns DMP1 and a plurality of second dam patterns DMP2 may be arranged to be spaced apart from each other in one direction, and the interval DW between adjacent first dam patterns DMP1 may be equal to or substantially equal to the interval between adjacent second dam patterns DMP2. However, pairs of the first dam pattern DMP1 and the second dam pattern DMP2 may be alternately arranged without being side by side with each other, and one second dam pattern DMP2 may be arranged side by side with the space between adjacent first dam patterns DMP1 that are spaced apart from each other.

[0245] Figure 15 and Figure 16 are schematic cross-sectional views showing a part of a dam structure arranged in a display device according to one or more embodiments. Figure 15 and Figure 16 In the dam structure DAM shown in [the figure], the dams DM1 and DM2 may be substantially a pair of dam patterns DMP1 and DMP2 (for example, see Figure 10 ), and Figure 15 and Figure 16 may show a cross-section across a pair of dam patterns DMP1 and DMP2 in the first direction DR1.

[0246] Referring to Figure 15 , in the display device 10 (for example, see Figure 1 ), the eleventh interlayer insulating film INS11 may be omitted, and each of the first dam DM1 and the second dam DM2 may penetrate the pixel defining film PDL. The depths of the first dam DM1 and the second dam DM2 may be the same as or substantially the same as each other, and their bottom surfaces may be the top surface of the tenth interlayer insulating film INS10. The first inorganic encapsulation layer TFE1 may be arranged on the bottom surfaces of the first dam DM1 and the second dam DM2. The organic encapsulation layer TFE2 may be arranged in the first dam DM1, but may not be arranged in the second dam DM2. The second inorganic encapsulation layer TFE3 may be directly arranged on the first inorganic encapsulation layer TFE1 in the second dam DM2. An inorganic bonding region where the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 are arranged to be in direct contact with each other may be formed outside the second dam DM2.

[0247] Referring to Figure 16 , the display device 10 may further include a twelfth interlayer insulating film INS12 arranged on the eleventh interlayer insulating film INS11. The twelfth interlayer insulating film INS12 may include the same material as the material of the eleventh interlayer insulating film INS11. The twelfth interlayer insulating film INS12 may be arranged to be aligned with the first electrode AND (for example, see Figure 4 ) in the display area DAA (for example, see Figure 7) Overlap. In the display device 10, since two interlayer insulating films INS11 and INS12 are arranged, therefore, between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (for example, see Figure 7 ) the distance between the first electrode AND and the reflective electrode layer RL (for example, see Figure 7 ) can be different.

[0248] The first dam DM1 and the second dam DM2 of the dam structure DAM can penetrate the pixel defining film PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11. The depths of the first dam DM1 and the second dam DM2 can be the same or substantially the same as each other, and their bottom surfaces can be the top surface of the tenth interlayer insulating film INS10. In the first dam DM1 and the second dam DM2, the first inorganic encapsulation layer TFE1 can be in direct contact with the tenth interlayer insulating film INS10, the eleventh interlayer insulating film INS11, the twelfth interlayer insulating film INS12, and the pixel defining film PDL.

[0249] Figure 17 is a schematic cross-sectional view showing a part of a display device in which a dam structure is arranged according to another embodiment. Figure 18 is a more detailed view showing Figure 17 the dam of the display device.

[0250] Referring to Figure 17 and Figure 18 , in the display device 10 according to the embodiment (for example, see Figure 1 ), the first dam DM1 and the second dam DM2 can have different depths H1 and H2 from each other. For example, the display device 10 can include an eleventh interlayer insulating film INS11 and a twelfth interlayer insulating film INS12. The first dam DM1 can penetrate the pixel defining film PDL, but cannot penetrate the twelfth interlayer insulating film INS12 and the layers below it. The second dam DM2 can penetrate the pixel defining film PDL, the eleventh interlayer insulating film INS11, and the twelfth interlayer insulating film INS12. The depth H2 of the second dam DM2 can be greater than the depth H1 of the first dam DM1. In the display device 10, the depths of the plurality of dams DM1 and DM2 can increase as they are arranged outward from the innermost dam. As the depth of the dam structure DAM increases as it extends toward the dam at the outer position (for example, the second dam DM2), the difference in volume deviation according to the position of the organic encapsulation layer TFE2 can be offset, and the organic encapsulation layer TFE2 can have a uniform or substantially uniform shape regardless of its position.

[0251] The bottom surface of the first dam DM1 may be the top surface of the twelfth interlayer insulating film INS12, and the bottom surface of the second dam DM2 may be the top surface of the tenth interlayer insulating film INS10. The first inorganic encapsulation layer TFE1 may be in contact with the top surface of the twelfth interlayer insulating film INS12 in the first dam DM1 and may be in contact with the top surface of the tenth interlayer insulating film INS10 in the second dam DM2. The organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1 while filling the first dam DM1. The second inorganic encapsulation layer TFE3 may be directly disposed on the first inorganic encapsulation layer TFE1 in the second dam DM2 and may form an inorganic bonding region together with the first inorganic encapsulation layer TFE1 outside the second dam DM2.

[0252] Figure 19 is a schematic cross-sectional view showing the structure of a dam in a display device according to another embodiment.

[0253] Referring to Figure 19 , in the display device 10 (for example, see Figure 1 ), the second dam DM2 may partially penetrate the tenth interlayer insulating film INS10. The depth H2 of the second dam DM2 may be greater than Figure 18 the depth H2 shown in the embodiment of

[0254] Figures 20 to 22 is a schematic cross-sectional view of a dam of a display device according to one or more embodiments. For the sake of illustration, Figures 20 to 22 the schematic shapes of the first dam DM1 and the second dam DM2 of the dam structure DAM are shown, while the illustration of the arrangement of the encapsulation layer TFE (for example, see Figure 7 ) is omitted.

[0255] Referring to Figure 20 , in the display device 10 according to an embodiment (for example, see Figure 1 ), each of the first dam DM1 and the second dam DM2 may penetrate the pixel defining film PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11. The bottom surfaces of the first dam DM1 and the second dam DM2 may be the top surface of the tenth interlayer insulating film INS10.

[0256] In an embodiment, the widths W1 and W2 of the first dam DM1 and the second dam DM2 may be partially different. For example, the first width W1 of the portion of the first dam DM1 and the second dam DM2 that penetrates the pixel defining layer PDL may be smaller than the second width W2 of the portion that penetrates the twelfth interlayer insulating film INS12 and the eleventh interlayer insulating film INS11. In the first dam DM1 and the second dam DM2, the inner sidewalls of the pixel defining layer PDL may protrude more than the inner sidewalls of the twelfth interlayer insulating film INS12 and the eleventh interlayer insulating film INS11. The first dam DM1 and the second dam DM2 may include a tip or a protruding structure formed by the pixel defining layer PDL, and may prevent or substantially prevent the organic encapsulation layer TFE2 from overflowing outside the dam structure DAM until the outside of the display device 10 (such as up to the pad PD (for example, see Figure 4 ).

[0257] Referring to Figure 21 , in the display device 10 according to an embodiment, the first dam DM1 and the second dam DM2 may be formed such that they penetrate the pixel defining layer PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11, and such that a portion of the tenth interlayer insulating film INS10 is recessed.

[0258] The widths W1 and W2 of the first dam DM1 and the second dam DM2 may be partially different. For example, the first width W1 of the portion of the first dam DM1 and the second dam DM2 that penetrates the pixel defining layer PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11 may be smaller than the second width W2 of the portion formed such that a top surface portion of the tenth interlayer insulating film INS10 is recessed. In the first dam DM1 and the second dam DM2, the inner sidewalls of the pixel defining layer PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11 may protrude more than the inner sidewalls of the portion where the top surface of the tenth interlayer insulating film INS10 is recessed. The first dam DM1 and the second dam DM2 may include a tip or a protruding structure formed by the pixel defining layer PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11.

[0259] Referring to Figure 22, the first dam DM1 and the second dam DM2, the first width W1 of the portions penetrating the pixel defining layer PDL may be smaller than the second width W2 of the portions penetrating the twelfth interlayer insulating film INS12 and the eleventh interlayer insulating film INS11, and the third width W3 of the portions formed such that a part of the top surface of the tenth interlayer insulating film INS10 is recessed. The second width W2 of the portions of the first dam DM1 and the second dam DM2 penetrating the twelfth interlayer insulating film INS12 and the eleventh interlayer insulating film INS11 may be smaller than the third width W3 of the portions formed such that a part of the top surface of the tenth interlayer insulating film INS10 is recessed. In the first dam DM1 and the second dam DM2, the inner sidewalls of the pixel defining layer PDL may protrude inward more than the inner sidewalls of the twelfth interlayer insulating film INS12 and the eleventh interlayer insulating film INS11, and the inner sidewalls of the twelfth interlayer insulating film INS12 and the eleventh interlayer insulating film INS11 may protrude more than the inner sidewalls of the portions where the top surface of the tenth interlayer insulating film INS10 is recessed. The first dam DM1 and the second dam DM2 may include a tip or a protruding structure formed by the pixel defining layer PDL, the twelfth interlayer insulating film INS12, and the eleventh interlayer insulating film INS11.

[0260] Figure 23 is a perspective view showing a head-mounted display device according to an embodiment. Figure 24 is showing Figure 23 an exploded perspective view of an example of the head-mounted display device.

[0261] Referring to Figure 23 and Figure 24 , the head-mounted display device 1000 according to an embodiment includes a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0262] The first display device 11 provides an image to the user's left eye, and the second display device 12 provides an image to the user's right eye. Since each of the first display device 11 and the second display device 12 is the same as or substantially the same as the display device 10 described above with reference to Figure 1 , its redundant description will not be repeated.

[0263] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0264] The intermediate frame 1400 can be disposed between the first display device 11 and the control circuit board 1600, and between the second display device 12 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0265] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 11 and the second display device 12 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA (for example, see Figure 2 ), and can send the digital video data DATA to the first display device 11 and the second display device 12 through connectors.

[0266] The control circuit board 1600 can send the digital video data DATA corresponding to the left-eye image optimized for the user's left eye to the first display device 11, and can send the digital video data DATA corresponding to the right-eye image optimized for the user's right eye to the second display device 12. As another example, the control circuit board 1600 can send the same digital video data DATA to the first display device 11 and the second display device 12.

[0267] The display device housing 1100 is used to accommodate the first display device 11, the second display device 12, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connectors. The housing cover 1200 is arranged to cover an opening surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 where the user's left eye is disposed and a second eyepiece 1220 where the user's right eye is disposed. Figure 23 and Figure 24 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are arranged separately from each other, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined together into one.

[0268] The first eyepiece 1210 can be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 12 and the second optical member 1520. Accordingly, the user can view the image of the first display device 11 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 12 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0269] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively arranged in front of the user's left eye and right eye. When the display device housing 1200 is implemented to be lightweight and compact, the head-mounted display device 1000 can provide a spectacle frame as shown in Figure 25 instead of the headband 1300.

[0270] In addition, the head-mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a Universal Serial Bus (USB) terminal, a DisplayPort, or a High-Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0271] Figure 25 is a perspective view showing a head-mounted display device according to an embodiment.

[0272] Referring to Figure 25 , the head-mounted display device 1000_1 according to an embodiment may be a spectacle-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to an embodiment may include a display device 13, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple arms 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0273] The display device housing 1200_1 may accommodate the display device 13, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 13 may be magnified by the optical member 1060, and the optical path may be changed by the optical path changing member 1070 to provide the image to the user's right eye through the right-eye lens 1020. As a result, the user can view an augmented reality image in which the virtual image displayed on the display device 13 and the real image seen through the right-eye lens 1020 are combined through the right eye.

[0274] Figure 25 The display device housing 1200_1 is shown arranged at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be arranged on the left end of the support frame 1030, and in this case, the image of the display device 13 may be provided to the user's left eye. As another example, the display device housing 1200_1 may be arranged on both the left end and the right end of the support frame 1030, and in this case, the user can view the image displayed on the display device 13 through both the left eye and the right eye.

[0275] The foregoing is an illustration of some embodiments of the present disclosure and is not to be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made to the embodiments without departing from the scope of the present disclosure. It should be understood that, unless otherwise described, the description of the features or aspects within each embodiment is generally to be considered as available for other similar features or aspects in other embodiments. Thus, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, it should be understood that the foregoing is an illustration of various exemplary embodiments and is not to be construed as limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate including a display area, a non-display area surrounding the display area, and a plurality of transistors; a dam structure located in the non-display area; a light-emitting element layer including a plurality of light-emitting elements in the display area; a packaging layer located on the light-emitting element layer; and a cover layer located on the packaging layer, wherein the dam structure includes: a first dam including a plurality of first dam patterns spaced apart from each other; and a second dam including a plurality of second dam patterns spaced apart from each other, and wherein a distance between the second dam and the display area is greater than a distance between the first dam and the display area.

2. The display device according to claim 1, wherein, The packaging layer includes: a first inorganic packaging layer extending beyond the second dam in the display area and the non-display area; an organic packaging layer located on the first inorganic packaging layer and covering the first dam but not covering the second dam; and a second inorganic packaging layer located on the organic packaging layer and the first inorganic packaging layer.

3. The display device according to claim 2, wherein, The first inorganic packaging layer and the second inorganic packaging layer are in direct contact with each other outside the second dam.

4. The display device according to claim 1, wherein, A spacing between the first dam patterns spaced apart from each other is 100 μm or less.

5. The display device according to claim 1, wherein, A first dam pattern among the plurality of first dam patterns and a second dam pattern among the plurality of second dam patterns are positioned side by side.

6. The display device according to claim 5, wherein, The display area has a curved diagonal edge, the first dam includes a plurality of third dam patterns having side edges curved to correspond to the curved diagonal edge of the display area, and the second dam includes a plurality of fourth dam patterns having side edges curved to correspond to the curved diagonal edge of the display area.

7. The display device according to claim 1, wherein, The plurality of first dam patterns and the plurality of second dam patterns are alternately positioned, and an area between a second dam pattern among the plurality of second dam patterns and an adjacent first dam pattern among the plurality of first dam patterns is positioned side by side.

8. The display device according to claim 1, further comprising: a plurality of pads located in the non-display area, wherein the pads are positioned outside the dam structure and do not overlap with the packaging layer.

9. A display device, comprising: a substrate including a display area, a non-display area surrounding the display area, and a plurality of transistors; a first insulating film located on the substrate; a pixel defining film located on the first insulating film in the display area; a plurality of light-emitting elements respectively corresponding to a plurality of openings in the pixel defining film; a dam structure located in the non-display area and including a plurality of dams having a trench shape penetrating the pixel defining film; a packaging layer located on the light-emitting elements in the display area and covering at least a part of the plurality of dams; and a cover layer located on the packaging layer, Among them, the dam structure includes the innermost dam adjacent to the display area and the outermost dam outside the innermost dam, and Among them, the encapsulation layer includes an organic encapsulation layer, and the organic encapsulation layer covers at least the innermost dam among the plurality of dams without overlapping with the outermost dam, and covers the light-emitting element.

10. The display device according to claim 9, wherein, The plurality of dams have the same depth as each other.

11. The display device according to claim 10, further comprising: A second insulating film, the second insulating film being located between the pixel defining film and the first insulating film, Among them, each of the plurality of dams penetrates the pixel defining film and the second insulating film.

12. The display device according to claim 11, further comprising: A third insulating film, the third insulating film being located between the pixel defining film and the second insulating film, Among them, each of the plurality of dams penetrates the pixel defining film, the third insulating film, and the second insulating film.

13. The display device according to claim 9, wherein, The depth of the outermost dam among the plurality of dams is greater than the depth of the innermost dam among the plurality of dams.

14. The display device according to claim 13, further comprising: A second insulating film and a third insulating film, the second insulating film and the third insulating film being located between the pixel defining film and the first insulating film, Among them, the innermost dam penetrates the pixel defining film, and Among them, the outermost dam penetrates the pixel defining film, the second insulating film, and the third insulating film.

15. The display device according to claim 14, wherein, The outermost dam includes a recessed portion on the top surface of the first insulating film.

16. The display device according to claim 9, further comprising: A second insulating film and a third insulating film, the second insulating film and the third insulating film being located between the pixel defining film and the first insulating film, Among them, the plurality of dams penetrate the pixel defining film, the second insulating film, and the third insulating film, and have a width that increases in the downward direction.

17. The display device according to claim 16, wherein, The width of the portion of the plurality of dams that penetrates the pixel defining film is smaller than the width of the portion of the plurality of dams that penetrates the second insulating film and the third insulating film.

18. The display device according to claim 16, wherein, The plurality of dams include a recessed portion on the top surface of the first insulating film, and The width of the portion of the plurality of dams that penetrates the pixel defining film, the second insulating film, and the third insulating film is smaller than the width of the portion of the plurality of dams that includes the recessed portion on the top surface of the first insulating film.

19. The display device according to claim 18, wherein, The width of the portion of the plurality of dams that penetrates the second insulating film and the third insulating film is smaller than the width of the portion of the plurality of dams that includes the recessed portion on the top surface of the first insulating film.

20. The display device according to claim 9, wherein, The encapsulation layer includes a first inorganic encapsulation layer and a second inorganic encapsulation layer stacked on top of each other with the organic encapsulation layer therebetween, and The first inorganic encapsulation layer and the second inorganic encapsulation layer are in direct contact with each other outside the outermost dam of the dam structure.

21. A head-mounted display device, comprising: A frame configured to be mounted on a user's body corresponding to the user's left eye and right eye; A plurality of display devices located in the frame; and an eyepiece located on each of the plurality of display devices, wherein each of the plurality of display devices includes: a substrate including a display area, a non-display area surrounding the display area, and a plurality of transistors; a dam structure located in the non-display area; a light-emitting element layer including a plurality of light-emitting elements in the display area; a packaging layer located on the light-emitting element layer; and a cover layer located on the packaging layer, wherein the dam structure includes: a first dam including a plurality of first dam patterns spaced apart from each other; and a second dam including a plurality of second dam patterns spaced apart from each other, the second dam having a trench shape and being positioned at a greater distance from the display area than the first dam, and wherein the packaging layer includes an organic packaging layer that covers the first dam without overlapping with the second dam and covers the light-emitting elements.

22. The head-mounted display device according to claim 21, wherein, The first dam and the second dam have the same depth as each other.

23. The head-mounted display device according to claim 21, wherein, The depth of the second dam is greater than the depth of the first dam.

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