Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes a substrate having a display area and a non-display area surrounding the display area; the pixel circuit layer is arranged on the substrate, and the pixel circuit layer comprises a pixel circuit and a planarization layer covering the pixel circuit; a first main pixel electrode on the planarization layer; a peripheral pixel electrode on the planarization layer, the peripheral pixel electrode being spaced apart from the first main pixel electrode and surrounding the first main pixel electrode in a plan view; a bank layer including a first opening exposing a central portion of the first main pixel electrode; a first intermediate layer corresponding to the first main pixel electrode and disposed within the first opening; and an opposing electrode covering the bank layer and the first intermediate layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0001731, filed with the Korean Intellectual Property Office on January 4, 2024, the entire contents of which are incorporated herein by reference. Technical field

[0003] Embodiments of the present disclosure described herein relate to the structure of a display device and a method of manufacturing a display device. Background art

[0004] Generally, a display device includes a light - emitting device and thin - film transistors on a substrate, and can be operated to cause (and / or control) the light - emitting device to emit light (e.g., display an image). The light - emitting device converts electrical energy into light energy. Examples of the light - emitting device include an organic light - emitting device including an organic material (a plurality of organic materials) as a light - emitting material, a quantum - dot light - emitting device including quantum dots (a plurality of quantum dots) as a light - emitting material, etc.

[0005] For example, each pixel of a display device has a light - emitting device disposed between a pixel electrode and a counter electrode and including an intermediate layer. The display device generally controls the light emission or the degree of light emission of each pixel through thin - film transistors (a plurality of thin - film transistors) electrically connected to the pixel electrode. Some layers included in the intermediate layer of the light - emitting device are provided (e.g., commonly provided, e.g., provided without patterning) in a plurality of light - emitting devices.

[0006] The above information disclosed in this background - art section is only for enhancing the understanding of the background of the present disclosure, and thus this background - art section may contain information that does not constitute prior art. Summary of the invention

[0007] Aspects according to one or more embodiments of the present disclosure are directed to a display device including a light - emitting device having high luminous efficiency and long lifespan. However, this is only an example, and the scope of the present disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the following description, and in part will be obvious from the description, or may be learned by practice of the embodiments presented in the present disclosure.

[0009] According to one or more embodiments, a display device includes: a substrate having a display area and a non-display area surrounding (e.g., enclosing) the display area; a pixel circuit layer on the substrate, the pixel circuit layer including pixel circuits and a planarization layer covering the pixel circuits; a first main pixel electrode on the planarization layer; a peripheral pixel electrode on the planarization layer, the peripheral pixel electrode being spaced apart and / or separated from (e.g., spaced or separated from) the first main pixel electrode and surrounding (e.g., enclosing) the first main pixel electrode in a plan view; a bank layer including a first opening exposing a central portion of the first main pixel electrode; a first intermediate layer corresponding to the first main pixel electrode and disposed within the first opening; and a counter electrode covering the bank layer and the first intermediate layer.

[0010] In one or more embodiments, the first main pixel electrode and the peripheral pixel electrode may be disposed on the same layer.

[0011] In one or more embodiments, the bank layer may cover a top surface and ends of the peripheral pixel electrode.

[0012] In one or more embodiments, the display device may further include: a second main pixel electrode on the planarization layer and disposed adjacent to the first main pixel electrode; and a second intermediate layer disposed within a second opening of the bank layer exposing a central portion of the second main pixel electrode.

[0013] In one or more embodiments, the peripheral pixel electrode may be between the first main pixel electrode and the second main pixel electrode.

[0014] In one or more embodiments, each of the first intermediate layer and the second intermediate layer may include an emission layer including quantum dots.

[0015] In one or more embodiments, the display device may further include: a first connection wiring electrically connected to the first main pixel electrode and configured to transmit an electrical signal from an external device, and a second connection wiring electrically connected to the peripheral pixel electrode and configured to transmit an electrical signal from an external device.

[0016] In one or more embodiments, the display device may include a plurality of main pixel electrodes including the first main pixel electrode arranged (e.g., arranged in rows in a first direction) along a first direction, and the first connection wiring may be electrically connected to the plurality of main pixel electrodes.

[0017] In one or more embodiments, the first connection wiring and the second connection wiring may be disconnected within the non-display area.

[0018] In one or more embodiments, the first connection wiring may be on a different layer from the first main pixel electrode.

[0019] According to one or more embodiments, a method of manufacturing a display device includes: forming a pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; forming a main pixel electrode on the planarization layer; forming a peripheral pixel electrode on the planarization layer, the peripheral pixel electrode being spaced apart from and / or separated from (e.g., spaced or separated) the main pixel electrode and surrounding (e.g., enclosing) the main pixel electrode in a plan view; forming a bank layer including an opening exposing a central portion of the main pixel electrode; forming an intermediate layer corresponding to the main pixel electrode within the opening; and forming a counter electrode covering the bank layer and the intermediate layer.

[0020] In one or more embodiments, the main pixel electrode and the peripheral pixel electrode may be deposited by the same process.

[0021] In one or more embodiments, the bank layer may be formed to cover a top surface and an end portion of the peripheral pixel electrode.

[0022] In one or more embodiments, forming the intermediate layer may include: forming a material layer for forming the intermediate layer on the main pixel electrode; and drying the material layer.

[0023] In one or more embodiments, forming the intermediate layer may further include baking the dried material layer.

[0024] In one or more embodiments, forming the material layer may include discharging an intermediate layer forming material into the opening by an inkjet process.

[0025] In one or more embodiments, the method may further include: forming a first connection wiring electrically connected to the main pixel electrode and further extending (e.g., extending) to connect to an external device; and forming a second connection wiring electrically connected to the peripheral pixel electrode and further extending (e.g., extending) to connect to an external device.

[0026] In one or more embodiments, drying the material layer may include: applying an alternating current signal from an external device to the main pixel electrode through the first connection wiring; and applying an alternating current signal from an external device to the peripheral pixel electrode through the second connection wiring.

[0027] In one or more embodiments, drying the material layer may further include generating an alternating current electroosmosis (ACEO) phenomenon within the material layer.

[0028] In one or more embodiments, the method may further include disconnecting the first connection wiring and the second connection wiring within a non-display area of the substrate.

[0029] In one or more embodiments, the method may further include bringing a mobile device close to the back surface of the substrate, the mobile device including an auxiliary substrate, a first auxiliary electrode on the auxiliary substrate, and a second auxiliary electrode on the auxiliary substrate, wherein the first auxiliary electrode has an area the same as that of the main pixel electrode, and the second auxiliary electrode has an area the same as that of the peripheral pixel electrode.

[0030] In one or more embodiments, the dry material layer may include applying an alternating current signal from an external device to the first auxiliary electrode and the second auxiliary electrode.

[0031] According to one or more embodiments, a display device includes: a substrate having a display area and a non-display area surrounding (e.g., enclosing) the display area; a pixel circuit layer on the substrate, the pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; a first sub-pixel electrode on the planarization layer; a second sub-pixel electrode on the planarization layer and spaced apart and / or separated (e.g., spaced or separated) from the first sub-pixel electrode; a bank layer having a first opening exposing a portion of the first sub-pixel electrode and a portion of the second sub-pixel electrode; a first intermediate layer on the first sub-pixel electrode and the second sub-pixel electrode and disposed within the first opening; and a counter electrode covering the bank layer and the first intermediate layer.

[0032] In one or more embodiments, the first sub-pixel electrode and the second sub-pixel electrode may be disposed on the same layer.

[0033] In one or more embodiments, the first sub-pixel electrode and the second sub-pixel electrode may have the same area and may have shapes that are symmetric to each other, respectively.

[0034] In one or more embodiments, each of the first sub-pixel electrode and the second sub-pixel electrode may be electrically connected to the pixel circuit.

[0035] In one or more embodiments, the display device may further include: a first connection wiring electrically connected to the first sub-pixel electrode and configured to transmit an electrical signal from an external device; and a second connection wiring electrically connected to the second sub-pixel electrode and configured to transmit an electrical signal from an external device.

[0036] In one or more embodiments, the display device may further include: a third sub-pixel electrode on the planarization layer and disposed adjacent to the second sub-pixel electrode; a fourth sub-pixel electrode on the planarization layer and spaced apart and / or separated (e.g., spaced or separated) from the third sub-pixel electrode; and a second intermediate layer disposed within a second opening of the bank layer exposing a portion of the third sub-pixel electrode and a portion of the fourth sub-pixel electrode.

[0037] In one or more embodiments, each of the first connection wiring and the second connection wiring may be between the second sub-pixel electrode and the third sub-pixel electrode.

[0038] In one or more embodiments, only one selected from the first connection wiring and the second connection wiring may be between the second sub-pixel electrode and the third sub-pixel electrode.

[0039] In one or more embodiments, the display device may include a plurality of sub-pixel electrodes including a first sub-pixel electrode and a second sub-pixel electrode arranged along a first direction (e.g., arranged in a row in the first direction), and each of the first connection wiring and the second connection wiring may be electrically connected to the plurality of sub-pixel electrodes.

[0040] In one or more embodiments, the first connection wiring and the second connection wiring may be disconnected in a non-display area.

[0041] According to one or more embodiments, a method of manufacturing a display device includes: forming a pixel circuit layer on a substrate, the pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; forming a first sub-pixel electrode on the planarization layer; forming a second sub-pixel electrode on the planarization layer, the second sub-pixel electrode being spaced apart from and / or separated from (e.g., spaced or separated from) the first sub-pixel electrode; forming a bank layer having an opening exposing a portion of the first sub-pixel electrode and a portion of the second sub-pixel electrode; forming an intermediate layer on the first sub-pixel electrode and the second sub-pixel electrode within the opening; and forming a counter electrode covering the bank layer and the intermediate layer.

[0042] In one or more embodiments, the first sub-pixel electrode and the second sub-pixel electrode may be deposited by the same process.

[0043] In one or more embodiments, the first sub-pixel electrode and the second sub-pixel electrode may be formed in the same shape and formed to have the same area.

[0044] In one or more embodiments, forming the intermediate layer may include: forming a material layer for forming the intermediate layer on the first sub-pixel electrode and the second sub-pixel electrode; and drying the material layer.

[0045] In one or more embodiments, forming the material layer may include discharging an intermediate layer forming material into the opening by an inkjet process.

[0046] In one or more embodiments, the method may further include forming a first connection wiring electrically connected to the first sub-pixel electrode and further extending (e.g., extending) to connect to an external device; and forming a second connection wiring electrically connected to the second sub-pixel electrode and further extending (e.g., extending) to connect to an external device.

[0047] In one or more embodiments, the dry material layer may further include: applying an alternating current (AC) signal from an external device to the first sub-pixel electrode through a first connection wiring; and applying an AC signal from the external device to the second sub-pixel electrode through a second connection wiring.

[0048] In one or more embodiments, the dry material layer may further include generating an alternating current electro-osmosis (ACEO) phenomenon within the material layer.

[0049] In one or more embodiments, the method may further include disconnecting the first connection wiring and the second connection wiring within a non-display area of the substrate.

[0050] In one or more embodiments, the method may further include bringing a mobile device close to the rear surface of the substrate, the mobile device including an auxiliary substrate, a first auxiliary electrode on the auxiliary substrate, and a second auxiliary electrode on the auxiliary substrate, wherein the first auxiliary electrode may have an area equal to the area of the first sub-pixel electrode, and the second auxiliary electrode may have an area equal to the area of the second sub-pixel electrode.

[0051] In one or more embodiments, the dry material layer may include applying an AC signal from an external device to the first auxiliary electrode and the second auxiliary electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0053] Figure 1 is a schematic perspective view of a display device according to one or more embodiments;

[0054] Figure 2 is in Figure 1 an equivalent circuit diagram of a pixel circuit electrically connected to a light-emitting device included in a pixel in the display device of

[0055] Figure 3A and Figure 3B are schematic cross-sectional views of a display device according to one or more embodiments;

[0056] Figure 4 is a schematic plan view of a display device according to one or more embodiments;

[0057] Figure 5 is along Figure 4 the line I-I' of Figure 4 a schematic cross-sectional view of the display device of

[0058] Figures 6A to 6Eis a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments;

[0059] Figure 7 is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments;

[0060] Figure 8 is a schematic plan view of a display device according to one or more embodiments;

[0061] Figure 9 is along Figure 8 taken along line II-II' of Figure 8 a schematic cross-sectional view of the display device;

[0062] Figures 10A to 10E is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments;

[0063] Figure 11 is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments; and

[0064] Figure 12 is a schematic plan view of a display device according to one or more embodiments. Detailed Description

[0065] One or more embodiments, examples of which are now shown in the drawings, will be described in more detail below, where the same reference numerals always refer to the same elements and repeated descriptions of the same elements may not be provided. At this point, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, one or more embodiments are described in more detail herein only by reference to the drawings to illustrate aspects of the present specification.

[0066] In this specification, "including A or B", "A and / or B", etc. mean A or B or both A and B.

[0067] As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. As used herein, expressions such as "at least one of...", "one of...", and "selected from..." modify all the elements of the list when after / before the list of elements and do not modify individual elements in the list. For example, "at least one of a, b, and c", "at least one selected from a, b, and c", etc. may mean only a, only b, only c, both a and b (representing a and b simultaneously), both a and c (representing a and c simultaneously), both b and c (representing b and c simultaneously), all of a, b, and c, or variants thereof.

[0068] As used herein, the terms "substantially", "about" and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by a person of ordinary skill in the art. Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "substantially" as used herein includes the stated value and means within an acceptable variation of the particular value as determined by a person of ordinary skill in the art. For example, "substantially" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0069] In addition, any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges (and including the recited minimum value of 1.0 and the recited maximum value of 10.0) between the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit recited herein is intended to include all lower numerical limits subsumed therein, and any minimum numerical limit recited in this specification is intended to include all higher numerical limits subsumed therein. Accordingly, the applicant reserves the right to modify this specification (including the claims) to expressly recite any sub-range subsumed within the ranges expressly recited herein.

[0070] Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms.

[0071] The description of a feature or aspect within each embodiment should generally be considered available for other similar features or aspects in other embodiments.

[0072] In the context of this application, and unless otherwise limited, the terms "use", "using" and "used" may be respectively considered synonymous with the terms "utilize", "utilizing" and "utilized". In addition, when describing embodiments of the invention, the use of "may" means "one or more embodiments of the invention".

[0073] For ease of explanation, spatial relative terms such as "upper", "lower", "below", "beneath", "above", "on" etc. may be used in this document to describe the relationship of one element or feature to another (or others) as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to also encompass different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the example terms "below" and "beneath" can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0074] Since this specification allows for one or more suitable changes and numerous embodiments, certain embodiments will be shown in the drawings and described in more detail in the written description. The effects and features of the present disclosure, as well as the methods for achieving the effects and features, will be elucidated with reference to one or more embodiments described in more detail herein with reference to the drawings. However, the present disclosure is not limited to the following embodiments, and the present disclosure may be implemented in one or more suitable forms.

[0075] Hereinafter, the embodiments will be described in more detail with reference to the drawings. When describing the embodiments with reference to the drawings, the same or corresponding elements are denoted by the same reference numerals.

[0076] It will be understood that although the terms "first", "second", etc. may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0077] Unless the context clearly indicates otherwise, the singular forms as used herein are also intended to include the plural forms.

[0078] It will also be understood that the terms "comprises", "comprising", "includes", "including", "have", "having", "contain" and "containing" when used in this specification specify the presence of the recited features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0079] In this specification, it will be understood that when an element (such as a region, layer, film, area, or portion) is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or there can be one or more intervening elements. Further, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there can also be one or more intervening elements.

[0080] In addition, for ease of explanation, the dimensions of elements in the drawings may be enlarged or reduced. For example, since the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of explanation, the present disclosure is not limited thereto.

[0081] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the recited order. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to the recited order.

[0082] It will also be understood that if layers, regions, or components are referred to as being connected to each other (e.g., when layers, regions, or components are referred to as being connected to each other), they can be directly connected to each other, or they can be indirectly connected to each other and have intervening layers, regions, or components therebetween. For example, if layers, regions, or elements are referred to as being electrically connected to each other (e.g., when layers, regions, or elements are referred to as being electrically connected to each other), they can be directly electrically connected to each other, or they can be indirectly electrically connected to each other and have intervening layers, regions, or elements therebetween.

[0083] Figure 1 is a schematic perspective view of a display device 1 according to one or more embodiments.

[0084] Reference Figure 1 , the display device 1 may include a display area DA and a non-display area NDA in a substrate 100.

[0085] The display area DA can implement an image. In a plan view, a plurality of pixels PX can be two-dimensionally arranged in the display area DA. In this specification, the pixel PX refers to sub-pixels configured to emit light of different colors. The pixel PX can each be, for example, a red sub-pixel, a green sub-pixel, and / or a blue sub-pixel. The display device 1 can provide an image by using the light emitted from the pixel PX.

[0086] The non-display area NDA is an area that does not provide an image. No pixels PX are arranged in the non-display area NDA. The non-display area NDA can completely surround (e.g., enclose) the display area DA. A driver or voltage line configured to supply an electrical signal or power to the pixels PX can be arranged in the non-display area NDA. A pad portion that is an area to which an electronic device or a printed circuit board can be electrically connected can be arranged in the non-display area NDA.

[0087] The display area DA can have a polygonal shape. For example, as Figure 1 shown, the display area DA can have a rectangular shape in which its horizontal length is greater than its vertical length. In one or more embodiments, the display area DA can have a square shape. In one or more embodiments, the display area DA can have other shapes such as an oval shape or a circular shape.

[0088] Figure 2 is an equivalent circuit diagram of the pixel PX in a display device according to one or more embodiments.

[0089] Refer to Figure 2 , the pixel PX can include a pixel circuit PC and a display element (e.g., a light-emitting diode ED) connected to the pixel circuit PC. The pixel circuit PC can include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. The pixel PX can be configured to emit red light, green light, or blue light through the light-emitting diode ED, or can be configured to emit red light, green light, blue light, or white light through the light-emitting diode ED.

[0090] The second thin-film transistor T2 serving as a switching thin-film transistor can be connected to the scan line SL and the data line DL, and can be configured to transmit a data voltage or data signal Dm input from the data line DL to the first thin-film transistor T1 in response to a switching voltage or switching signal Sn input from the scan line SL. The storage capacitor Cst can be connected to the second thin-film transistor T2 and the driving voltage line PL, and can be configured to store a voltage corresponding to the difference between the voltage received from the second thin-film transistor T2 and the first power supply voltage ELVDD provided to the driving voltage line PL.

[0091] The first thin-film transistor T1 serving as a driving thin-film transistor can be connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL to the light-emitting diode ED according to the voltage value stored in the storage capacitor Cst. The light-emitting diode ED can be configured to emit light with a specific brightness according to the driving current. The opposite electrode (e.g., the cathode) of the light-emitting diode ED can be configured to receive the second power supply voltage ELVSS.

[0092] Figure 2It is shown that the pixel circuit PC includes two thin film transistors and a storage capacitor, but in one or more embodiments, the number of thin film transistors or the number of storage capacitors can be variously changed according to the design of the pixel circuit PC.

[0093] Figure 3A is a schematic cross-sectional view of the display device 1 according to one or more embodiments. Figure 3B is a schematic cross-sectional view of the display device 1 according to one or more embodiments.

[0094] Reference Figure 3A , the display device 1 may include a display layer DPL and a thin film encapsulation layer TFE on a substrate 100. The display layer DPL may include a pixel circuit layer PCL including a pixel circuit and an insulating layer, and a display element layer DEL on the pixel circuit layer PCL and including a plurality of display elements.

[0095] The substrate 100 may include glass, metal, or a polymer resin. Examples of the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or any mixture thereof. In one or more embodiments, other modifications are possible. For example, the substrate 100 may have a multilayer structure including two layers and a barrier layer between the two layers, where the two layers may include a polymer resin, and the barrier layer may include an inorganic material (e.g., silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), etc.).

[0096] The display element layer DEL may include display elements such as light emitting diodes. The pixel circuit layer PCL may include an insulating layer and a pixel circuit connected to the light emitting diodes. For example, the pixel circuit layer PCL may include a plurality of transistors, a plurality of storage capacitors, and an insulating layer between the plurality of transistors and the plurality of storage capacitors.

[0097] The display elements may be covered with an encapsulation member such as the thin film encapsulation layer TFE. The thin film encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer covering the display element layer DEL. The inorganic encapsulation layer may include, such as, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), silicon oxide (SiO x ), silicon nitride (SiN x) or an inorganic insulating material such as silicon oxynitride (SiON). The organic encapsulation layer may include a polymer-based material. The polymer-based material may include acrylic resins, epoxy-based resins, polyimides, polyethylene, etc. In one or more embodiments, the organic encapsulation layer may include acrylates.

[0098] Reference Figure 3B , the display device 1 may include a display layer DPL on a substrate 100 and a sealing substrate 400. A sealing member 300 may be between the substrate 100 and the sealing substrate 400. The sealing substrate 400 may be a transparent member. The substrate 100 and the sealing substrate 400 may be joined to each other by the sealing member 300 such that the internal space between the substrate 100 and the sealing substrate 400 is sealed. In this case, a moisture absorbent or a filler may be located in the internal space. The sealing member 300 may be a sealant. In one or more embodiments, the sealing member 300 may include a material curable by laser. For example, the sealing member 300 may be a frit. For example, the sealing member 300 may include an organic sealant such as a urethane-based resin, an epoxy-based resin, and / or an acrylic resin and / or an inorganic sealant such as a silicone resin. Examples of the urethane-based resin may include urethane acrylate. Examples of the acrylic resin may include butyl acrylate and 2-ethylhexyl acrylate. In one or more embodiments, the sealing member 300 may include a material curable by heating.

[0099] In one or more embodiments, the display element layer DEL may be covered with Figure 3B the sealing substrate 400 and the sealing member 300 and Figure 3A the thin film encapsulation layer TFE.

[0100] The touch electrode layer may be on the thin film encapsulation layer TFE and / or the sealing substrate 400, and the optical function layer may be on the touch electrode layer. The touch electrode layer may be configured to obtain coordinate information according to an external input (e.g., a touch event). The optical function layer may reduce the reflectance of light incident on the display device 1 from the outside (e.g., external light). In one or more embodiments, the optical function layer may improve the color purity of the light emitted from the display device 1. In one or more embodiments, the optical function layer may include a retarder and / or a polarizer. The retarder may be a film-type or film-like retarder or a liquid crystal coating-type or liquid crystal coating-like retarder, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be a film-type or film-like polarizer or a liquid crystal coating-type or liquid crystal coating-like polarizer. The film-type or film-like retarder or polarizer may include a stretched synthetic resin film, and the liquid crystal coating-type or liquid crystal coating-like retarder or polarizer may include liquid crystals arranged in a specific array. Each of the retarder and the polarizer may also include a protective film.

[0101] In one or more embodiments, the optical functional layer may include a black matrix and color filters. The color filters may be arranged based on the color of light emitted from each pixel PX of the display device 1. Each of the color filters may include pigments and / or dyes of red, green, and / or blue. In one or more embodiments, in addition to the pigments and / or dyes, each of the color filters may further include quantum dots (a plurality of quantum dots). In one or more embodiments, some of the color filters may not include the pigments or dyes described above (e.g., any one of the pigments or dyes described above may be excluded), and may include scattering particles such as titanium oxide.

[0102] The adhesive member may be between the touch electrode layer and the optical functional layer. Any suitable (e.g., general-purpose) adhesive member in the art may be employed as the adhesive member without limitation. In one or more embodiments, the adhesive member may be a pressure-sensitive adhesive (PSA).

[0103] Figure 4 is a schematic plan view of a display device according to one or more embodiments. Figure 4 is Figure 1 a schematic enlarged view of a part of the display area DA in the display device 1 shown in Figure 4 shows the bank layer 120 and a plurality of main pixel electrodes 210 arranged two-dimensionally in a plan view, and the bank layer 120 has an opening 120OP exposing the central portion of the main pixel electrode 210.

[0104] Refer to Figure 4 , the display device 1 may include a plurality of pixels (e.g., see Figure 1 the PX of Figure 1 . The pixels (see Figure 5 the PX of Figure 5 ) may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 may include a first light-emitting diode (e.g., see Figure 5 the ED1 of Figure 5 ), the second pixel PX2 may include a second light-emitting diode (e.g., see Figure 5 the ED2 of

[0105] ), and the third pixel PX3 may include a third light-emitting diode. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be configured to emit light of different colors. For example, the first pixel PX1 may be configured to emit red light, the second pixel PX2 may be configured to emit green light, and the third pixel PX3 may be configured to emit blue light. The red light may be light in a wavelength band of about 580 nm to about 780 nm, the blue light may be light in a wavelength band of about 380 nm to about 495 nm, and the green light may be light in a wavelength band of about 495 nm to about 580 nm.Each of the light-emitting diodes may include a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode. Here, in the present disclosure, the pixel electrode may be referred to as the main pixel electrode 210. For example, as Figure 4 shown in, the first pixel PX1 may include a first main pixel electrode 211 of a first light-emitting diode (e.g., see Figure 5 ED1 of), the second pixel PX2 may include a second main pixel electrode 212 of a second light-emitting diode (e.g., see Figure 5 ED2 of), and the third pixel PX3 may include a third main pixel electrode 213 of a third light-emitting diode. The first main pixel electrode 211, the second main pixel electrode 212, and the third main pixel electrode 213 may be spaced apart and / or separated (e.g., spaced or separated) from each other on a substrate (e.g., see Figure 5 100 of). In the present specification, the expression "in a plan view" means a plane viewed from a direction normal to (e.g., perpendicular to) the substrate 100. For example, the expression "A and B are spaced apart and / or separated (e.g., spaced or separated) from each other in a plan view" means that if viewed from a direction normal to (e.g., perpendicular to) the substrate 100 (e.g., when viewed from a direction normal to (e.g., perpendicular to) the substrate 100), then "A and B are spaced apart and / or separated (e.g., spaced or separated) from each other".

[0106] The bank layer 120 may be on the first main pixel electrode 211, the second main pixel electrode 212, and the third main pixel electrode 213, and may cover the edges of each of the first main pixel electrode 211, the second main pixel electrode 212, and the third main pixel electrode 213. For example, the bank layer 120 may have a first opening 120OP1 exposing the central portion of the first main pixel electrode 211, a second opening 120OP2 exposing the central portion of the second main pixel electrode 212, and a third opening 120OP3 exposing the central portion of the third main pixel electrode 213.

[0107] In one or more embodiments, an emission layer configured to emit light may be respectively located in the first opening 120OP1, the second opening 120OP2, and the third opening 120OP3 of the bank layer 120. The counter electrode may be on the emission layer. As described above, the stacked structure of the main pixel electrode 210, the emission layer, and the counter electrode may constitute a light-emitting diode. One opening of the bank layer 120 may correspond to one light-emitting diode and may define an emission region.

[0108] For example, an emission layer configured to emit red light may be disposed in the first opening 120OP1, and thus, the first opening 120OP1 may define a first emission region EA1. Similarly, an emission layer configured to emit green light may be disposed in the second opening 120OP2, and thus, the second opening 120OP2 may define a second emission region EA2. An emission layer configured to emit blue light may be disposed in the third opening 120OP3, and thus, the third opening 120OP3 may define a third emission region EA3. Therefore, the area of the first opening 120OP1 may be equal to the area of the first emission region EA1. Of course, the area of the second opening 120OP2 may be equal to the area of the second emission region EA2, and the area of the third opening 120OP3 may be equal to the area of the third emission region EA3.

[0109] If observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (e.g., see Figure 5 100), (e.g., when observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (e.g., see Figure 5 100)), (e.g., when observed in the plan view of the display device 1), then each of the first opening 120OP1, the second opening 120OP2, and the third opening 120OP3 may have a circular shape or an elliptical shape. For example, if observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (e.g., see Figure 5 100), (e.g., when observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (e.g., see Figure 5 100)), (e.g., when observed in the plan view of the display device 1), then each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a circular shape or an elliptical shape. Figure 4 It is shown that if observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (see Figure 5 100), (e.g., when observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (see Figure 5 100)), (e.g., when observed in the plan view of the display device 1), then each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 has an elliptical shape. However, the present disclosure is not limited thereto. For example, if observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (see Figure 5 100), (e.g., when observed from a direction (z-axis direction) normal to (e.g., perpendicular to) the substrate (see Figure 5When viewed in the direction (z-axis direction) of <100> (e.g., when viewed in the plan view of the display device 1), each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape.

[0110] In one or more embodiments, in addition to the main pixel electrode 210, the display device according to one or more embodiments may further include a peripheral pixel electrode 250. The peripheral pixel electrode 250 may be disposed on the same layer as the main pixel electrode 210 and may include the same material as that of the main pixel electrode 210. At this time, the peripheral pixel electrode 250 may be spaced apart from and / or separated from (e.g., spaced or separated) the main pixel electrode 210.

[0111] In one or more embodiments, if viewed in a direction normal to (e.g., perpendicular to) the substrate (e.g., see Figure 5 in the direction of <100> (e.g., z-axis direction) (e.g., when viewed in a direction normal to (e.g., perpendicular to) the substrate (e.g., see Figure 5 in the direction of <100> (e.g., z-axis direction)) (e.g., when viewed in the plan view of the display device 1), the peripheral pixel electrode 250 may be around the main pixel electrode 210 (e.g., surrounding the main pixel electrode 210). Since the bank layer 120 covers the end portion of the main pixel electrode 210, the peripheral pixel electrode 250 may overlap with the bank layer 120. However, since the peripheral pixel electrode 250 and the main pixel electrode 210 are disposed on the same layer, the bank layer 120 may be on the peripheral pixel electrode 250. For example, the bank layer 120 may cover the top surface and both end portions of the peripheral pixel electrode 250 (e.g., covering both end portions of the peripheral pixel electrode 250 at the same time), and the main pixel electrode 210 and the peripheral pixel electrode 250 may be insulated from each other by the bank layer 120.

[0112] In addition, the peripheral pixel electrode 250 may be between pixels arranged adjacent to each other (e.g., see Figure 1 of PX). For example, the peripheral pixel electrode 250 may be between the main pixel electrodes 210 arranged adjacent to each other. For example, the peripheral pixel electrode 250 may be between the first main pixel electrode 211 and the second main pixel electrode 212, and may be between the second main pixel electrode 212 and the third main pixel electrode 213.

[0113] In one or more embodiments, the peripheral pixel electrode 250 may be formed as a single body so as to be shared by pixels arranged adjacent to each other (e.g., see Figure 1 of PX). For example, the peripheral pixel electrode 250 may be integrally formed between the main pixel electrodes 210. Thus, as Figure 4As shown, the peripheral pixel electrode 250 may have a shape overlapping with the bank layer 120 in the plan view of the display device 1. However, the present disclosure is not limited thereto. In one or more embodiments, the peripheral pixel electrode 250 may be separately formed for each pixel (e.g., referring to Figure 1 the PX) while surrounding (e.g., enclosing) the main pixel electrode 210. For example, the peripheral pixel electrode 250 surrounding (e.g., enclosing) the first main pixel electrode 211 and the peripheral pixel electrode 250 surrounding (e.g., enclosing) the second main pixel electrode 212 may be separated from and / or apart from each other (e.g., spaced apart or separated).

[0114] The display device 1 according to one or more embodiments may apply an electrical signal from an external device to the main pixel electrode 210 and the peripheral pixel electrode 250 respectively having the structures described above. Although described in more detail later, the emission layer (e.g., referring to Figure 5 220) may be formed by discharging an emission layer forming material into the opening 120OP of the bank layer 120 through an inkjet process and then drying the emission layer forming material through a drying process. At this time, in the drying process, a convection phenomenon is caused in the intermediate layer forming material due to the application of the electrical signal to the main pixel electrode 210 and the peripheral pixel electrode 250, and thus, the emission layer (e.g., referring to Figure 5 220) may be formed to have a substantially uniform thickness.

[0115] Therefore, the display device 1 according to one or more embodiments may further include connection wirings that electrically connect each of the main pixel electrode 210 and the peripheral pixel electrode 250 to an external device to which an electrical signal is applied. The connection wirings may include a first connection wiring CW1 that connects the main pixel electrode 210 to the external device and a second connection wiring that connects the peripheral pixel electrode 250 to the external device. In one or more embodiments, the peripheral pixel electrode 250 is integrally formed on a substrate (e.g., referring to Figure 5 100), and thus, the peripheral pixel electrode 250 may be formed on the outside of the display device 1. For example, the second connection wiring may be formed in a non-display area (e.g., referring to Figure 1 NDA).

[0116] In the plan view, since the main pixel electrode 210 is surrounded by the peripheral pixel electrode 250, the first connection wiring CW1 that must be connected to and extend from the main pixel electrode 210 may be on a layer different from the layer on which the main pixel electrode 210 is located. For example, the first connection wiring CW1 may be below the main pixel electrode 210 and the peripheral pixel electrode 250.

[0117] The first connection wiring CW1 may extend in a first direction (e.g., the y direction) to connect the main pixel electrode 210 to an external device. At this time, the first connection wiring CW1 may be connected to only one main pixel electrode 210, and may also be electrically connected to a plurality of main pixel electrodes 210 arranged along the first direction (e.g., the y direction) (e.g., arranged in a row in the first direction). For example, as Figure 4 shown, the first connection wiring CW1 may include a 1-1 connection wiring CW11, a 1-2 connection wiring CW12, and a 1-3 connection wiring CW13. The 1-1 connection wiring CW11 may be electrically connected to the main pixel electrodes 210 corresponding to a plurality of first pixels PX1 and PX1' arranged in the first direction (e.g., the y direction), respectively. Similarly, the 1-2 connection wiring CW12 may be electrically connected to the main pixel electrodes 210 corresponding to a plurality of second pixels PX2 and PX2' arranged in the first direction (e.g., the y direction), respectively, and the 1-3 connection wiring CW13 may be electrically connected to the main pixel electrodes 210 corresponding to a plurality of third pixels PX3 and PX3' arranged in the first direction (e.g., the y direction), respectively.

[0118] At this time, an electrical signal of the same potential may be applied to the main pixel electrodes 210 connected to the first connection wiring CW1. Since the peripheral pixel electrodes 250 are integrally formed with each other, the peripheral pixel electrodes 250 may receive an electrical signal of the same potential on the entire surface of the substrate (e.g., see Figure 5 100).

[0119] However, the first connection wiring CW1 may be disconnected within the display device (e.g., see Figure 5 1). This is because, after connecting the external device to the main pixel electrode 210 and transmitting an electrical signal to the main pixel electrode 210 during the drying process, if the drying process is completed (e.g., when the drying process is completed), the external device and the main pixel electrode 210 are disconnected. In one or more embodiments, the first connection wiring CW1 may be disconnected within a non-display area of the display device (e.g., see Figure 1 NDA in Figure 1 1). However, the present disclosure is not limited thereto. The first connection wiring CW1 may be disconnected even within the display area (e.g., see Figure 1 DA in Figure 1 PX). In addition, similar to the first connection wiring CW1, the second connection wiring connecting the peripheral pixel electrodes 250 to the external device may be disconnected within the display device (e.g., see Figure 5 1).

[0120] Figure 5 is taken along the Figure 4 line I-I' of Figure 4 the display device shown in

[0121] Referring to Figure 5 , the pixel circuit layer PCL may be on the substrate 100. The pixel circuit layer PCL may include a first transistor TR1 and a second transistor TR2, and may include a buffer layer 111, a first gate insulating layer 113, a second gate insulating layer 115, an interlayer insulating layer 117, and a planarization layer 119 below and / or above the components of the first transistor TR1 and the second transistor TR2. Each of the first transistor TR1 and the second transistor TR2 may correspond to Figure 2 the first thin film transistor T1 shown in

[0122] The buffer layer 111 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiON), or silicon oxide (SiO x ), and may have a single-layer structure or a multi-layer structure including the inorganic insulating materials described above. The buffer layer 111 may increase the smoothness of the top surface of the substrate 100, or may prevent, minimize, or reduce impurities infiltrating from the substrate 100 and the like into the semiconductor layer Act.

[0123] The first transistor TR1 may include a semiconductor layer Act, and the semiconductor layer Act may include polysilicon. In one or more embodiments, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor material, or an organic semiconductor material.

[0124] The gate electrode GE may overlap a portion of the semiconductor layer Act. The gate electrode GE may include a conductive material. For example, the gate electrode GE may include a conductive material such as molybdenum (Mo), aluminum (Al), or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the conductive materials described above.

[0125] The first gate insulating layer 113 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide (SiO x(例如，2) ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc peroxide (ZnO2).

[0126] The second gate insulating layer 115 may cover the gate electrode GE. Similar to the first gate insulating layer 113, the second gate insulating layer 115 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc peroxide (ZnO2).

[0127] The upper electrode CE2 of the storage capacitor Cst may be on the second gate insulating layer 115. The upper electrode CE2 may overlap with the gate electrode GE located thereunder. In this case, the gate electrode GE and the upper electrode CE2 that overlap with each other and have the second gate insulating layer 115 therebetween may constitute the storage capacitor Cst. For example, the gate electrode GE may serve as the lower electrode CE1 of the storage capacitor Cst.

[0128] As described above, the storage capacitor Cst may overlap with the first transistor TR1. In one or more embodiments, the storage capacitor Cst may not overlap with the first transistor TR1.

[0129] The upper electrode CE2 may include a conductive material such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), and may have a single-layer structure or a multi-layer structure including the conductive materials described above.

[0130] The interlayer insulating layer 117 may cover the upper electrode CE2. The interlayer insulating layer 117 may include an inorganic insulating material such as silicon oxide (SiO x(例如，2) ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc peroxide (ZnO2). The interlayer insulating layer 117 may include a single-layer structure or a multi-layer structure including the inorganic insulating materials described above.

[0131] The drain electrode SD1 and the source electrode SD2 may be on the interlayer insulating layer 117. The drain electrode SD1 and the source electrode SD2 may be electrically connected to the semiconductor layer Act through contact holes provided in the first gate insulating layer 113, the second gate insulating layer 115, and the interlayer insulating layer 117, respectively. Each of the drain electrode SD1 and the source electrode SD2 may include a material having good or suitable conductivity. Each of the drain electrode SD1 and the source electrode SD2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer structure or a multi-layer structure including the above-described conductive material. In one or more embodiments, each of the drain electrode SD1 and the source electrode SD2 may have a multi-layer structure of Ti / Al / Ti. In one or more embodiments, one of the drain electrode SD1 and the source electrode SD2 may not be provided, and a part of the semiconductor layer Act may be made conductive to replace the one not provided in the drain electrode SD1 and the source electrode SD2.

[0132] In one or more embodiments, the first connection wiring CW1 may be on the interlayer insulating layer 117. As described above, the first connection wiring CW1 may electrically connect the main pixel electrode 210 to an external device to which an electrical signal is applied. In one or more embodiments, the first connection wiring CW1 may be connected to the main pixel electrode 210 through a contact hole of the planarization layer 119. For example, the 1-1 connection wiring CW11 may be electrically connected to the first main pixel electrode 211, and the 1-2 connection wiring CW12 may be electrically connected to the second main pixel electrode 212.

[0133] In one or more embodiments, the first connection wiring CW1 may be disposed on the same layer as the drain electrode SD1 and the source electrode SD2, and may include the same material as the materials of the drain electrode SD1 and the source electrode SD2. For example, the first connection wiring CW1 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer structure or a multi-layer structure including the above-described conductive material. However, the present disclosure is not limited thereto. When the planarization layer 119 to be described in more detail later includes multiple layers, the first connection wiring CW1 may be between the planarization layers 119.

[0134] The planarization layer 119 may cover the first transistor TR1 and may include contact holes exposing portions of the first transistor TR1. The planarization layer 119 may include an organic insulating material. The planarization layer 119 may include an organic insulating material such as a general polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene-based polymer, a polyvinyl alcohol-based polymer, and / or any blend or combination thereof.

[0135] The display element layer DEL may be on the pixel circuit layer PCL. The display element layer DEL may include a first light-emitting diode ED1 and a second light-emitting diode ED2 and a bank layer 120 under and / or above components of the first light-emitting diode ED1 and the second light-emitting diode ED2. In one or more embodiments, each of the first light-emitting diode ED1 and the second light-emitting diode ED2 may be a quantum dot light-emitting device. For example, each of the first light-emitting diode ED1 and the second light-emitting diode ED2 may have an emission layer including quantum dots. However, the present disclosure is not limited thereto. In one or more embodiments, each of the first light-emitting diode ED1 and the second light-emitting diode ED2 may be an organic light-emitting device. For example, each of the first light-emitting diode ED1 and the second light-emitting diode ED2 may have an emission layer that does not include quantum dots but only includes organic materials.

[0136] Each of the first light-emitting diode ED1 and the second light-emitting diode ED2 may include a main pixel electrode 210. The main pixel electrode 210 may include a first main pixel electrode 211 constituting the first light-emitting diode ED1 and a second main pixel electrode 212 constituting the second light-emitting diode ED2. The first main pixel electrode 211 and the second main pixel electrode 212 may be on the planarization layer 119 of the pixel circuit layer PCL. The first main pixel electrode 211 may be electrically connected to the drain electrode SD1 or the source electrode SD2 of the first transistor TR1 through a contact hole passing through the planarization layer 119. Similarly, the second main pixel electrode 212 may be electrically connected to the second transistor TR2 through a contact hole passing through the planarization layer 119.

[0137] The main pixel electrode 210 may be a reflective electrode, a semi-transmissive semi-reflective electrode, or a transmissive electrode. To form the main pixel electrode 210 into a transmissive electrode, indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO2), zinc oxide (ZnO), or any combination thereof may be used as the material of the pixel electrode. To form the main pixel electrode 210 into a semi-transmissive semi-reflective electrode or a reflective electrode, magnesium (Mg), silver (Ag), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), or any combination thereof may be used as the material of the pixel electrode. The main pixel electrode 210 may have a single-layer structure composed of a single layer or a multi-layer structure including multiple layers. For example, the main pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0138] As described above Figure 4 The display device 1 according to one or more embodiments may include an outer peripheral pixel electrode 250. In the plan view of the display device 1, the outer peripheral pixel electrode 250 may be spaced apart and / or separated (e.g., spaced or separated) from the main pixel electrode 210 by a certain distance in a second direction (e.g., the x direction). For example, in the plan view of the display device 1, the outer peripheral pixel electrode 250 may be spaced apart and / or separated from the main pixel electrode 210 by a distance of about 5 μm to about 10 μm. If observed from a direction normal to (e.g., perpendicular to) the substrate 100 (e.g., when observed from a direction normal to (e.g., perpendicular to) the substrate 100) (e.g., when observing the plan view of the display device 1), the outer peripheral pixel electrode 250 may surround (e.g., may enclose) the main pixel electrode 210. The outer peripheral pixel electrode 250 may be between adjacent main pixel electrodes 210. For example, the outer peripheral pixel electrode 250 may be between a first main pixel electrode 211 and a second main pixel electrode 212 and may be shared by a first pixel PX1 and a second pixel PX2.

[0139] In one or more embodiments, the peripheral pixel electrode 250 may be disposed on the same layer as the main pixel electrode 210. For example, the peripheral pixel electrode 250 and the main pixel electrode 210 are on the same layer. For example, the peripheral pixel electrode 250 may be on the planarization layer 119. The peripheral pixel electrode 250 may include the same material as the main pixel electrode 210. For example, the peripheral pixel electrode 250 and the main pixel electrode 210 may include the same material. Thus, the peripheral pixel electrode 250 may be a reflective electrode, a semi-transmissive semi-reflective electrode, or a transmissive electrode. When the peripheral pixel electrode 250 is formed as a transmissive electrode, the peripheral pixel electrode 250 may include indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO2), zinc oxide (ZnO), or any combination thereof. When the peripheral pixel electrode 250 is formed as a reflective electrode or a semi-transmissive semi-reflective electrode, the peripheral pixel electrode 250 may include magnesium (Mg), silver (Ag), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), or any combination thereof. However, the present disclosure is not limited thereto. The peripheral pixel electrode 250 may include a material different from that of the main pixel electrode 210. For example, the peripheral pixel electrode 250 and the main pixel electrode 210 include different materials from each other.

[0140] The bank layer 120 may be on the planarization layer 119 of the pixel circuit layer PCL. The bank layer 120 may cover the edges of the first main pixel electrode 211 and the second main pixel electrode 212. For example, the bank layer 120 may contact the top surface and the side surfaces of the ends of the main pixel electrode 210. In addition, since the peripheral pixel electrode 250 is between adjacent main pixel electrodes 210, the bank layer 120 may be on the peripheral pixel electrode 250. The bank layer 120 may cover the top surface of the peripheral pixel electrode 250 and both ends of the peripheral pixel electrode 250 (e.g., covering both ends of the peripheral pixel electrode 250 simultaneously). As Figure 5 shown, the bank layer 120 may insulate the main pixel electrode 210 and the peripheral pixel electrode 250 from each other.

[0141] The bank layer 120 may include one or more suitable materials. In one or more embodiments, the bank layer 120 may include an organic material such as acrylic, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). In one or more embodiments, the bank layer 120 may include a photoresist, i.e., a photosensitive resin. For example, the bank layer 120 may include a negative photoresist or a negative-type photoresist that undergoes a reaction such as crosslinking upon exposure.

[0142] The bank layer 120 may define a first opening 120OP1 that exposes a central portion of the first main pixel electrode 211 and a second opening 120OP2 that exposes a central portion of the second main pixel electrode 212. For example, the bank layer 120 may define an emission region of the first light-emitting diode ED1 and an emission region of the second light-emitting diode ED2. By increasing the distance between the edge of the main pixel electrode 210 and the counter electrode 230, the bank layer 120 may prevent or reduce the occurrence of an arc or the like on the edge of the main pixel electrode 210.

[0143] The intermediate layer may be located within the opening 120OP of the bank layer 120. The intermediate layer included in the light-emitting diode ED may include an emission layer 220. The emission layer 220 may include a first emission layer 221 that constitutes the first light-emitting diode ED1 and a second emission layer 222 that constitutes the second light-emitting diode ED2. For example, the first emission layer 221 may be on the first main pixel electrode 211 and within the first opening 120OP1. Similarly, the second emission layer 222 may be on the second main pixel electrode 212 and within the second opening 120OP2.

[0144] In one or more embodiments, the emission layer 220 may include quantum dots (a plurality of quantum dots). For example, the quantum dots (a plurality of quantum dots) included in the emission layer 220 may be used as a dopant, and the emission layer 220 may further include a host and / or a delayed fluorescence material. Quantum dots refer to crystals of semiconductor compounds. Quantum dots may be configured to emit light of one or more suitable emission wavelengths according to the size of the crystal. Quantum dots may be configured to emit light of one or more suitable emission wavelengths by controlling the ratio of the elements constituting the quantum dots. For example, the diameter of the quantum dots may be about 1 nm to about 10 nm. In the present disclosure, when the quantum dots, a plurality of quantum dots, or quantum dot particles are spherical, "diameter" represents the particle diameter or the average particle diameter, and when the particles are non-spherical, "diameter" represents the major axis length or the average major axis length. The diameter of the particles may be measured using a scanning electron microscope or a particle size analyzer. For example, the HORIBA, LA-950 laser particle size analyzer may be used as the particle size analyzer. When measuring the size of the particles using a particle size analyzer, the average particle diameter is referred to as D50. D50 refers to the average diameter of the particles whose cumulative volume corresponds to 50 vol% in the particle size distribution (e.g., cumulative distribution), and refers to the particle size value corresponding to 50% from the smallest particle in the distribution curve accumulated in the order of the smallest particle size to the largest particle size when the total number of particles is 100%.

[0145] Quantum dots can be synthesized by wet chemical processes, metalorganic chemical vapor deposition processes, molecular beam epitaxy processes, or other similar processes. The wet chemical process is a method of growing quantum dot particle crystals after mixing an organic solvent with a precursor material. When the crystals grow, the organic solvent naturally serves as a dispersant that coordinates with the surface of the quantum dot crystals and regulates the crystal growth. Therefore, the wet chemical process is easier to perform than vapor deposition methods such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), and the growth of quantum dot particles can be controlled or selected by a low-cost process.

[0146] Quantum dots can include II-VI group semiconductor compounds, III-V group semiconductor compounds, III-VI group semiconductor compounds, I-III-VI group semiconductor compounds, IV-VI group semiconductor compounds, group IV elements or compounds, or any combination thereof.

[0147] Examples of II-VI group semiconductor compounds can include binary compounds such as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, or MgS, ternary compounds such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, or MgZnS, quaternary compounds such as CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe, or any combination thereof.

[0148] Examples of III-V semiconductor compounds can include binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, or InSb, ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, or InPSb, quaternary compounds such as GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, or InAlPSb, and any combination thereof. In one or more embodiments, the III-V semiconductor compounds can further include Group II elements. Examples of III-V semiconductor compounds that also include Group II elements can include InZnP, InGaZnP, or InAlZnP.

[0149] Examples of III-VI semiconductor compounds can include binary compounds such as GaS, Ga2S3, GaSe, Ga2Se3, GaTe, InS, InSe, In2S3, In2Se3, or InTe, ternary compounds such as InGaS3 or InGaSe3, or any combination thereof.

[0150] Examples of I-III-VI semiconductor compounds can include ternary compounds such as AgInS, AgInS2, AgInSe2, AgGaS, AgGaS2, AgGaSe2, CuInS, CuInS2, CuInSe2, CuGaS2, CuGaSe2, CuGaO2, AgGaO2, or AgAlO2, quaternary compounds such as AgInGaS2, AgInGaSe2, or CuInGaS, or any combination thereof.

[0151] Examples of IV-VI semiconductor compounds can include binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, or PbTe, ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, or SnPbTe, quaternary compounds such as SnPbSSe, SnPbSeTe, or SnPbSTe, or any combination thereof.

[0152] Examples of group IV elements or compounds may include monoatomic compounds such as Si or Ge, binary compounds such as SiC or SiGe, or any combination thereof.

[0153] Each of the elements included in polyatomic compounds such as binary compounds, ternary compounds, and quaternary compounds may be present in the particles at a substantially uniform concentration or a substantially non-uniform concentration. For example, the above chemical formula refers to the type or species of elements included in the compound, and the ratio of elements within the compound may be different. For example, AgInGaS2 may refer to AgIn x Ga 1-x S2 (x is a real number between 0 and 1).

[0154] In one or more embodiments, the quantum dots may have a single structure or a core-shell double structure, in which the concentration of each of the elements included in the quantum dots is substantially uniform. For example, the material included in the core may be different from the material included in the shell. The shell may cover at least a portion of the core.

[0155] The core may include Cd, Zn, Hg, Mg, Ga, Al, In, Sn, Pb, Se, Te, P, or Sb.

[0156] The shell of the quantum dot may serve as a protective layer for maintaining semiconductor properties by preventing or reducing chemical modification of the core and / or the charge layer that imparts electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. The interface between the core and the shell may have a concentration gradient in which the concentration of the elements present in the shell decreases toward the center of the interface.

[0157] Examples of the shell of the quantum dots may include metal oxides or non-metal oxides, semiconductor compounds, or any combination thereof. Examples of the metal oxides or non-metal oxides may include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO, ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4, or any combination thereof. As described above, examples of the semiconductor compounds may include group III-VI semiconductor compounds, group II-VI semiconductor compounds, group III-V semiconductor compounds, group III-VI semiconductor compounds, group I-III-VI semiconductor compounds, group IV-VI semiconductor compounds, or any combination thereof. Examples of the semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaS, GaSe, AgGaS, AgGaS2, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, or any combination thereof.

[0158] Each of the elements included in the polyatomic compounds such as binary compounds, ternary compounds, and quaternary compounds may be present in the particles at a substantially uniform concentration or a substantially non-uniform concentration. For example, the above chemical formulas refer to the type or kind of elements included in the compounds, and the ratios of the elements within the compounds may be different.

[0159] The quantum dots may have a full width at half maximum (FWHM) of the emission wavelength spectrum in the range of about 45 nm or less (specifically about 40 nm or less, and more specifically about 30 nm or less). Within this range, color purity or color reproducibility can be improved. Since the light emitted from the quantum dots is emitted in all directions, the viewing angle can be improved.

[0160] In addition, as the quantum dots, spherical nanoparticles, pyramidal nanoparticles, multi-arm nanoparticles, or cubic nanoparticles, nanotubes, nanowires, nanofibers, or nanosheet particles can be used.

[0161] Since the bandgap can be controlled or selected by adjusting the size of the quantum dots or the ratio of the elements within the quantum dot compound, one or more lights having appropriate wavelengths can be obtained from the quantum dot emitting layer. Accordingly, a light emitting device configured to emit one or more lights having appropriate wavelengths can be implemented by using quantum dots as described above (using quantum dots having different sizes or quantum dots having different element ratios within the quantum dot compound). For example, the size of the quantum dots or the ratio of the elements within the quantum dot compound can be selected to emit red light, green light, and / or blue light. In addition, the quantum dots can be configured to emit white light by combining lights of one or more appropriate colors.

[0162] In one or more embodiments, the emitting layer 220 may be an emitting layer including only organic materials (e.g., not including quantum dots). In this case, the emitting layer 220 may include an organic material including a fluorescent material or a phosphorescent material configured to emit red light, green light, blue light, or white light. The emitting layer 220 may be an organic emitting layer including a low molecular weight organic material or a high molecular weight organic material. For example, if the emitting layer 220 is an organic emitting layer (e.g., when the emitting layer 220 is an organic emitting layer), the emitting layer 220 may include copper phthalocyanine, tris(8-hydroxyquinoline)aluminum, a poly(p-phenylene vinylene) (PPV)-based material, or a polyfluorene-based material.

[0163] However, the present disclosure is not limited thereto. The emitting layer 220 may partially include quantum dots and partially include only organic materials. For example, a first emitting layer 221 configured to emit red light and a second emitting layer 222 configured to emit green light may each include quantum dots, and the emitting layer 220 of a third pixel configured to emit blue light (e.g., see Figure 4 PX3) may include only organic materials (e.g., the emitting layer 220 of the third pixel PX3 configured to emit blue light does not include quantum dots (e.g., does not include any quantum dots)).

[0164] In one or more embodiments, the intermediate layer may further include a common layer between the pixel electrode 210 and the emitting layer 220 and / or between the emitting layer 220 and the counter electrode 230. Hereinafter, the common layer between the pixel electrode 210 and the emitting layer 220 may be referred to as a first common layer, and the common layer between the emitting layer 220 and the counter electrode 230 may be referred to as a second common layer. Each of the first common layer and the second common layer may include an organic material.

[0165] The first common layer is a hole transport region and may include a hole injection layer, a hole transport layer, an emission assist layer, an electron blocking layer, or any combination thereof. For example, the first common layer may have a multi-layer structure of a hole injection layer / hole transport layer, a hole injection layer / hole transport layer / emission assist layer, a hole injection layer / emission assist layer, a hole transport layer / emission assist layer, or a hole injection layer / hole transport layer / electron blocking layer, and the layers in the multi-layer structure are sequentially stacked in the described order from the pixel electrode 210.

[0166] The second common layer is an electron transport region and may include a buffer layer, a hole blocking layer, an electron control layer, an electron transport layer, an electron injection layer, or any combination thereof. For example, the electron transport region may have a structure of an electron transport layer / electron injection layer, a hole blocking layer / electron transport layer / electron injection layer, an electron control layer / electron transport layer / electron injection layer, or a buffer layer / electron transport layer / electron injection layer, and the layers in the structure are sequentially stacked in the described order from the emission layer 220.

[0167] The counter electrode 230 may cover the emission layer 220 and the bank layer 120. For example, the counter electrode 230 may be integrally formed across the entire surface of the substrate 100 to cover the first emission layer 221 and the second emission layer 222. For example, the counter electrode 230 may overlap the emission layer 220 and the bank layer 120 in the plan view of the display device 1. Metals, alloys, conductive compounds, or any combination thereof each having a low work function may be used as the material of the counter electrode 230. The counter electrode 230 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 230 may be a transmissive electrode, a semi-transmissive semi-reflective electrode, or a reflective electrode. The counter electrode 230 may have a single-layer structure composed of a single layer or a multi-layer structure including multiple layers.

[0168] In one or more embodiments, in the first light-emitting diode ED1 and the second light-emitting diode ED2 respectively having the structures described above, the intermediate layer, particularly the emission layer 220, may be formed to have a substantially uniform thickness. In addition, the thickness uniformity of the emission layer 220 affects the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED. Therefore, the display device 1 according to one or more embodiments can improve the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED.

[0169] The emission layer 220 can be formed by discharging an emission layer forming material into the opening 120OP of the bank layer 120 through an inkjet process and then drying the emission layer forming material through a drying process. At this time, due to differences in evaporation rate and / or surface tension during the drying process, capillary flow and Marangoni flow may occur within the emission layer forming material. Generally, since the liquid dries starting from the edges, the liquid located inside the emission layer forming material flows towards the edges due to capillary flow. For example, the liquid tends to maintain a spherical shape due to surface tension, and thus, if the edge portion of the liquid evaporates first (e.g., when the edge portion of the liquid evaporates first), the liquid inside the emission layer forming material can flow towards the edges and move to maintain the original shape as much as possible. However, if the emission layer forming material flows towards the edges (e.g., when the emission layer forming material flows towards the edges), the surface tension of the central portion of the emission layer forming material decreases. Therefore, the solute can retreat towards the center of the emission layer forming material on the surface of the emission layer forming material due to Marangoni flow. For example, capillary flow and Marangoni phenomena can occur in a complex manner within the emission layer forming material.

[0170] In one or more embodiments, depending on the characteristics of the emission layer forming material itself or the drying environment, the capillary flow can be stronger than the Marangoni flow. When the capillary flow is stronger than the Marangoni flow, the solute that has moved from the inside of the emission layer forming material accumulates at the edges, and the solute can continue to accumulate as the liquid continues to evaporate. As described above, the phenomenon in which the solute is pushed out by the solvent due to differences in evaporation rate and accumulates in an annular shape from the outside can be referred to as the coffee ring effect. The emission layer 220 can be dried into a U-shaped shape due to the coffee ring effect, and the central portion of the emission layer 220 is deeply recessed. For example, if the capillary flow is stronger than the Marangoni flow (e.g., when the capillary flow is stronger than the Marangoni flow), the thickness of the emission layer 220 may become substantially non-uniform, which may deteriorate the characteristics of the light emitting diode ED.

[0171] At this time, in the display device 1 according to one or more embodiments, the emission layer 220 can be formed to have a substantially uniform thickness by applying an electrical signal to the main pixel electrode 210 and the peripheral pixel electrode 250 during the drying process. For example, the main pixel electrode 210 can be connected to an external device through the first connection wiring CW1, and the peripheral pixel electrode 250 can be connected to an external device through the second connection wiring so that the main pixel electrode 210 and the peripheral pixel electrode 250 can receive an alternating current signal.

[0172] When an alternating current signal is applied to the main pixel electrode 210 and the peripheral pixel electrode 250 during the drying process, the flow of the emission layer forming material may be caused by the alternating current electro-osmosis (ACEO) phenomenon. In the ACEO phenomenon, the solvent moves on the two electrodes, forming an electric field in a direction opposite to the direction in which the electrodes face each other, and thus causing the flow. Therefore, if an electric field is formed by applying an alternating current signal to the main pixel electrode 210 and the peripheral pixel electrode 250 respectively having the structures described above (for example, when an electric field is formed by applying an alternating current signal to the main pixel electrode 210 and the peripheral pixel electrode 250 respectively having the structures described above), then the flow of the solvent moving from the edge to the central region within the emission layer 220 may occur.

[0173] Therefore, in the case where the capillary flow of the solvent moving towards the edge is stronger than the Marangoni flow, if an electrical signal is applied to the main pixel electrode 210 and the peripheral pixel electrode 250 respectively having the Figure 5 structures shown in (for example, when an electrical signal is applied to the main pixel electrode 210 and the peripheral pixel electrode 250 respectively having the Figure 5 structures shown in), then the capillary flow can be mitigated by ACEO. Therefore, in the display device 1 according to one or more embodiments, since the emission layer forming material balances the capillary flow and the Marangoni flow during the drying process, the emission layer 220 can be formed to have a substantially uniform thickness.

[0174] Figures 6A to 6E is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments. Figures 6A to 6E is a cross-sectional view of the Figure 4 display device taken along line I-I' according to the manufacturing process.

[0175] Referring to Figure 6A , a pixel circuit layer PCL can be formed on the substrate 100, and the main pixel electrode 210 and the peripheral pixel electrode 250 can be formed on the pixel circuit layer PCL.

[0176] For example, a first main pixel electrode 211 corresponding to the first pixel (for example, referring to Figure 5 PX1) and a second main pixel electrode 212 corresponding to the second pixel (for example, referring to Figure 5 PX2) can be formed on the planarization layer 119. The peripheral pixel electrode 250 can be separated from and / or apart from (for example, spaced apart or separated from) the main pixel electrode 210, and can be formed to surround (for example, enclose) the main pixel electrode 210.

[0177] The peripheral pixel electrode 250 may be formed on the same layer as the main pixel electrode 210 and may include the same material as that of the main pixel electrode 210. For example, the peripheral pixel electrode 250 and the main pixel electrode 210 may be formed on the same layer and may include the same material. Therefore, the main pixel electrode 210 and the peripheral pixel electrode 250 may be deposited in parallel (e.g., simultaneously) by the same deposition process.

[0178] A bank layer 120 may be formed on the main pixel electrode 210 and the peripheral pixel electrode 250. The bank layer 120 may be formed to cover the end portion of the main pixel electrode 210 and the top surface of the peripheral pixel electrode 250. The bank layer 120 may be formed by forming an inorganic insulating material layer or an organic insulating material layer and then patterning an opening 120OP to expose the central portion of the main pixel electrode 210.

[0179] Reference Figure 6B , by discharging an ink including a light-emitting layer forming material, a first material layer 221' may be formed in the first opening 120OP1, and a second material layer 222' may be formed in the second opening 120OP2. The first material layer 221' and the second material layer 222' constitute the material layer 220'. For example, the first material layer 221' may be formed on the first main pixel electrode 211, and the second material layer 222' may be formed on the second main pixel electrode 212. In one or more embodiments, the material layer 220' may include a light-emitting material including quantum dots.

[0180] In one or more embodiments, the material layer 220' may be formed by an inkjet printing process. Considering the surface tension and volume shrinkage after drying, the material layer 220' may have a convex shape with a thick central portion with respect to the substrate 100. However, the present disclosure is not limited thereto. In one or more embodiments, depending on the injection amount of the ink including the light-emitting material, the material layer 220' may have a flat shape or a concave shape with respect to the substrate 100.

[0181] Reference Figure 6C , the light-emitting layer (e.g., see Figure 6D 220) may be formed by drying the material layer 220'. However, as described above, the solvent of the ink including the light-emitting material evaporates. When the capillary flow phenomenon is strong, the light-emitting layer (e.g., see Figure 6D 220) may have a substantially non-uniform thickness in a U shape.

[0182] Accordingly, in a method of manufacturing a display device according to one or more embodiments, an electrical signal may be applied from an external device to the main pixel electrode 210 and the peripheral pixel electrode 250. The electrical signal may be transmitted to the first main pixel electrode 211 through the first connection wiring CW11, and the electrical signal may be transmitted to the second main pixel electrode 212 through the second connection wiring CW12. In one or more embodiments, the peripheral pixel electrode 250 may also receive an electrical signal from the external device through the second connection wiring.

[0183] The peripheral pixel electrode 250 has a shape surrounding (e.g., enclosing) the main pixel electrode 210. Accordingly, if an alternating current signal is applied to the main pixel electrode 210 and the peripheral pixel electrode 250 (e.g., when an alternating current signal is applied to the main pixel electrode 210 and the peripheral pixel electrode 250), an electric field may be formed between the main pixel electrode 210 and the peripheral pixel electrode 250, and thus, the solvent in the material layer 220' may move from the edge to the central portion due to the ACEO phenomenon. For example, as Figure 6C shown, the solvent in the material layer 220' may move from the region adjacent to the bank layer 120 to the central portion of the main pixel electrode 210.

[0184] When the flow occurs in the above-described direction, the effect due to capillary flow is weakened, and thus, the material layer 220' may be dried to have a substantially uniform thickness. Accordingly, according to one or more embodiments, the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED may be improved by the method of manufacturing a display device. At this time, after the drying process is completed, the first connection wiring CW1 and the second connection wiring may be disconnected within a non-display region (e.g., see Figure 1 the NDA).

[0185] Refer to Figure 6D , after the drying of the emission layer 220 is completed, a baking process may be additionally performed. When the emission layer 220 is heat-treated under conditions of about 140°C to about 230°C, the density inside the emission layer 220 may be increased, and the light-emitting efficiency may be improved.

[0186] Specific conditions such as the temperature and time of the baking process may be appropriately or suitably selected according to the type or kind and capacity of the material. However, the present disclosure is not limited thereto. In some cases, the baking process may not be provided.

[0187] Refer to Figure 6E, a counter electrode 230 may be formed on the emission layer 220 and the bank layer 120. The counter electrode 230 may be integrally formed across the entire surface of the substrate 100. Accordingly, the first main pixel electrode 211, the first emission layer 221, and the counter electrode 230 may constitute the first light-emitting diode ED1, and the second main pixel electrode 212, the second emission layer 222, and the counter electrode 230 may constitute the second light-emitting diode ED2.

[0188] Figure 7 is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments. Refer to Figure 7 , other features except for the mobile device 2 may be the same as those described with reference to Figures 6A to 6E respectively. In Figure 7 , the same reference numerals denote the same elements as those described with reference to Figures 6A to 6E , and the differences will be mainly described in more detail later.

[0189] Refer to Figure 7 , an electric field may be formed by bringing the mobile device 2 close to the display device 1. For example, the mobile device 2 may include an auxiliary substrate 500, a first auxiliary electrode 510, and a second auxiliary electrode 520.

[0190] Similar to the substrate 100, the auxiliary substrate 500 may include glass, metal, or a polymer resin. Examples of the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or any mixture thereof. In one or more embodiments, other modifications are possible. For example, the auxiliary substrate 500 may have a multilayer structure including two layers and a barrier layer between the two layers, where the two layers may include a polymer resin, and the barrier layer may include an inorganic material (e.g., silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), etc.).

[0191] However, in the case of the mobile device 2, the pixel circuit layer PCL, etc. may not be on the auxiliary substrate 500, and the first auxiliary electrode 510 and the second auxiliary electrode 520 may be deposited on the auxiliary substrate 500. The first auxiliary electrode 510 and the second auxiliary electrode 520 may include the same materials as those of the main pixel electrode 210 and the peripheral pixel electrode 250 of the display device 1. For example, the first auxiliary electrode 510, the second auxiliary electrode 520, the main pixel electrode 210, and the peripheral pixel electrode 250 include the same materials. For example, each of the first auxiliary electrode 510 and the second auxiliary electrode 520 may include a conductive material capable of electric field induction.

[0192] In this case, the first auxiliary electrode 510 may be formed in a shape substantially the same as the shape of the main pixel electrode 210, and may be formed to have the same area as the area of the main pixel electrode 210. Further, if the substrate 100 and the auxiliary substrate 500 are aligned with each other (e.g., when the substrate 100 and the auxiliary substrate 500 are aligned with each other), the first auxiliary electrode 510 may be formed at a position where it can overlap with the main pixel electrode 210 in the plan view of the display device 1. For example, the 1-1 auxiliary electrode 511 may be formed at the same position as the position of the first main pixel electrode 211, and may be formed to have the same area as the area of the first main pixel electrode 211, and the 1-2 auxiliary electrode 512 may be formed at the same position as the position of the second main pixel electrode 212, and may be formed to have the same area as the area of the second main pixel electrode 212.

[0193] Similarly, the second auxiliary electrode 520 may be formed in a shape substantially the same as the shape of the peripheral pixel electrode 250, and may be formed to have the same area as the area of the peripheral pixel electrode 250. Further, if the substrate 100 and the auxiliary substrate 500 are aligned with each other (e.g., when the substrate 100 and the auxiliary substrate 500 are aligned with each other), the second auxiliary electrode 520 may be formed at a position where it can overlap with the peripheral pixel electrode 250 in the plan view of the display device 1. Thus, the second auxiliary electrode 520 may be formed to surround (e.g., enclose) the first auxiliary electrode 510 in the plan view, and may be between the 1-1 auxiliary electrode 511 and the 1-2 auxiliary electrode 512.

[0194] At this time, in the method of manufacturing a display device according to one or more embodiments, in the process of drying the material layer 220' to form an emission layer (e.g., see Figure 5 220), the mobile device 2 having the above-described structure may be brought close to the display device 1, and then, an external device for applying an electrical signal to the mobile device 2 may be connected to the mobile device 2. For example, by connecting the external device to the first auxiliary electrode 510 and the second auxiliary electrode 520 of the mobile device 2, an alternating current signal may be applied to the first auxiliary electrode 510 and the second auxiliary electrode 520.

[0195] When an AC signal is applied to the first auxiliary electrode 510 and the second auxiliary electrode 520, an electric field can be formed between the first auxiliary electrode 510 and the second auxiliary electrode 520. When the mobile device 2 in which the electric field is formed approaches the display device 1, the electric field formed between the first auxiliary electrode 510 and the second auxiliary electrode 520 can affect the material layer 220'. In particular, since the second auxiliary electrode 520 has a shape surrounding (e.g., enclosing) the first auxiliary electrode 510, the solvent in the material layer 220' can move from the edge to the central portion due to the ACEO phenomenon. For example, as Figure 7 shown, the solvent in the material layer 220' can move from the region adjacent to the bank layer 120 to the central portion of the main pixel electrode 210.

[0196] As Figure 7 shown, if the mobile device 2 is brought close to the display device 1 and flow occurs in the above-described direction (e.g., when the mobile device 2 is brought close to the display device 1 and flow occurs in the above-described direction), the influence caused by capillary flow can be weakened, and thus, the material layer 220' can be dried to have a substantially uniform thickness. Therefore, according to one or more embodiments, the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED can be improved by a method of manufacturing a display device.

[0197] Figure 8 is a schematic plan view of a display device according to one or more embodiments. Figure 9 is a schematic cross-sectional view of the display device taken along the line II-II' of Figure 8 . Referring to Figure 8 and Figure 8 , other features except for the pixel electrode 210', the first connection wiring CW1', and the second connection wiring CW2' can be the same as those described with reference to Figure 9 independently. In Figure 4 and Figure 5 , the same reference numerals denote the same elements as those described with reference to Figure 8 and Figure 9 , and the differences are mainly described in more detail. Figure 4 and Figure 5 .

[0198] Referring to Figure 8 , the pixel electrode 210' can include a first pixel electrode 211' corresponding to the first pixel PX1, a second pixel electrode 212' corresponding to the second pixel PX2, and a third pixel electrode 213' corresponding to the third pixel PX3.

[0199] In one or more embodiments, the pixel electrode 210' may include two sub-pixel electrodes that are spaced apart and / or separated from each other (e.g., spaced or separated). For example, the first pixel electrode 211' may include a first sub-pixel electrode 211a and a second sub-pixel electrode 211b that is spaced apart and / or separated from the first sub-pixel electrode 211a (e.g., spaced or separated). The second pixel electrode 212' may include a third sub-pixel electrode 212a and a fourth sub-pixel electrode 212b that is spaced apart and / or separated from the third sub-pixel electrode 212a (e.g., spaced or separated). Similarly, the third pixel electrode 213' may include a fifth sub-pixel electrode 213a and a sixth sub-pixel electrode 213b that is spaced apart and / or separated from the fifth sub-pixel electrode 213a (e.g., spaced or separated).

[0200] In one or more embodiments, the two sub-pixel electrodes that are spaced apart and / or separated from each other (e.g., spaced or separated) may have the same area and may have shapes that are symmetric with each other, respectively. For example, the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may have the same area and may have shapes that are symmetric with each other, respectively. The third sub-pixel electrode 212a and the fourth sub-pixel electrode 212b may have the same area and may have shapes that are symmetric with each other, respectively, and the fifth sub-pixel electrode 213a and the sixth sub-pixel electrode 213b may have the same area and may have shapes that are symmetric with each other, respectively.

[0201] In addition, each of the two sub-pixel electrodes that are spaced apart and / or separated from each other (e.g., spaced or separated) may be connected to a pixel circuit PC corresponding to the associated pixel PX. For example, the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may be individually connected to the first transistor TR1.

[0202] The bank layer 120 may be on the pixel electrode 210' and may cover the edges of each of the sub-pixel electrodes. For example, the bank layer 120 may have a first opening 120OP1 that exposes the first sub-pixel electrode 211a and the second sub-pixel electrode 211b, a second opening 120OP2 that exposes the third sub-pixel electrode 212a and the fourth sub-pixel electrode 212b, and a third opening 120OP3 that exposes the fifth sub-pixel electrode 213a and the sixth sub-pixel electrode 213b. The opening 120OP of the bank layer 120 may expose the top surface of the sub-pixel electrode. In addition, when the two sub-pixel electrodes are spaced apart and / or separated from each other (e.g., spaced or separated), the opening 120OP of the bank layer 120 may expose a partial region of the planarization layer (e.g., see Figure 9 119).

[0203] In one or more embodiments, the display device 1 according to one or more embodiments may further include connection wirings that electrically connect each of the sub-pixel electrodes to an external device to which an electrical signal is applied. The connection wirings may include a first connection wiring CW1' and a second connection wiring CW2' respectively configured to transmit an electrical signal to two sub-pixel electrodes corresponding to one pixel (e.g., see Figure 1 's PX). For example, the first connection wiring CW1' may be configured to transmit an electrical signal to the sub-pixel electrode arranged on the left with respect to the second direction (e.g., the x direction) among the two sub-pixel electrodes. The second connection wiring CW2' may be configured to transmit an electrical signal to the sub-pixel electrode arranged on the right with respect to the second direction (e.g., the x direction) among the two sub-pixel electrodes. For example, the 1-1 connection wiring CW11' may be electrically connected to the first sub-pixel electrode 211a, the 1-2 connection wiring CW12' may be electrically connected to the third sub-pixel electrode 212a, and the 1-3 connection wiring CW13' may be electrically connected to the fifth sub-pixel electrode 213a. The 2-1 connection wiring CW21' may be electrically connected to the second sub-pixel electrode 211b, the 2-2 connection wiring CW22' may be electrically connected to the fourth sub-pixel electrode 212b, and the 2-3 connection wiring CW23' may be electrically connected to the sixth sub-pixel electrode 213b.

[0204] Each of the first connection wiring CW1' and the second connection wiring CW2' may extend in a first direction (e.g., the y direction) to connect the sub-pixel electrodes to the external device. At this time, each of the first connection wiring CW1' and the second connection wiring CW2' may be connected to only one sub-pixel electrode, and may also be electrically connected to a plurality of sub-pixel electrodes arranged adjacent to each other in the first direction (e.g., arranged in a row adjacent to each other in the first direction (e.g., the y direction)).

[0205] In this case, electrical signals of the same potential may be applied to the sub-pixel electrodes connected to the first connection wiring CW1', and electrical signals of the same potential may be applied to the sub-pixel electrodes connected to the second connection wiring CW2'. For example, the first sub-pixel electrode 211a, the third sub-pixel electrode 212a, and the fifth sub-pixel electrode 213a may respectively receive electrical signals of the same potential, and the second sub-pixel electrode 211b, the fourth sub-pixel electrode 212b, and the sixth sub-pixel electrode 213b may respectively receive electrical signals of the same potential.

[0206] For example, the first connection wiring CW1' and the second connection wiring CW2' may be between adjacent pixels (e.g., see Figure 1 's PX). For example, the two connection wirings may be between adjacent pixels (e.g., see Figure 1 's PX).

[0207] However, the first connection wiring CW1' and the second connection wiring CW2' may be disconnected within the display device 1. In one or more embodiments, the first connection wiring CW1' and the second connection wiring CW2' may be disconnected within a non-display area (e.g., see Figure 1 the NDA).

[0208] Reference Figure 9 , the first pixel electrode 211' and the second pixel electrode 212' may be on the planarization layer 119. As described above, the first pixel electrode 211' may include a first sub-pixel electrode 211a and a second sub-pixel electrode 211b. The first sub-pixel electrode 211a and the second sub-pixel electrode 211b may be spaced apart from and / or separated (e.g., spaced or separated) by a certain distance. For example, the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may be spaced apart from and / or separated (e.g., spaced or separated) by a distance of about 5 μm to about 10 μm.

[0209] The first sub-pixel electrode 211a and the second sub-pixel electrode 211b may be disposed on the same layer. The first sub-pixel electrode 211a and the second sub-pixel electrode 211b may have the same area and may include the same material. For example, each of the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may be a reflective electrode, a semi-transmissive semi-reflective electrode, or a transmissive electrode. To form the first sub-pixel electrode 211a and the second sub-pixel electrode 211b into transmissive electrodes, indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO2), zinc oxide (ZnO), or any combination thereof may be used as the material of the pixel electrode. To form the first sub-pixel electrode 211a and the second sub-pixel electrode 211b into semi-transmissive semi-reflective electrodes or reflective electrodes, magnesium (Mg), silver (Ag), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), or any combination thereof may be used as the material of the pixel electrode. Each of the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may have a single-layer structure composed of a single layer or a multi-layer structure including multiple layers. For example, each of the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may have a three-layer structure of ITO / Ag / ITO. The characteristics of the first sub-pixel electrode 211a and the second sub-pixel electrode 211b may be equally applied to the third sub-pixel electrode 212a and the fourth sub-pixel electrode 212b.

[0210] In one or more embodiments, the first connection wiring CW1' and the second connection wiring CW2' may be on the planarization layer 119. For example, the first connection wiring CW1' and the second connection wiring CW2' may include the same material as that of the first sub-pixel electrode 211a and the second sub-pixel electrode 211b. For example, the first connection wiring CW1', the second connection wiring CW2', the first sub-pixel electrode 211a, and the second sub-pixel electrode 211b may include the same material. For example, each of the first connection wiring CW1' and the second connection wiring CW2' may include indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO2), zinc oxide (ZnO), or any combination thereof, or may include magnesium (Mg), silver (Ag), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), or any combination thereof. However, the present disclosure is not limited thereto. In one or more embodiments, the first connection wiring CW1' and the second connection wiring CW2' may be under the first pixel electrode 211'. For example, the first connection wiring CW1' and the second connection wiring CW2' may be arranged on the same layer as the drain electrode SD1 and may include the same material as that of the drain electrode SD1. For example, the first connection wiring CW1', the second connection wiring CW2', and the drain electrode SD1 may be arranged on the same layer and may include the same material.

[0211] The bank layer 120 may be on the planarization layer 119. The bank layer 120 may cover the edges of the first pixel electrode 211' and the second pixel electrode 212'. For example, the bank layer 120 may cover the end portion of the first sub-pixel electrode 211a that does not face the second sub-pixel electrode 211b and may cover the end portion of the second sub-pixel electrode 211b that does not face the first sub-pixel electrode 211a. In addition, since the first connection wiring CW1' and the second connection wiring CW2' are between adjacent pixel electrodes, the bank layer 120 may cover the top surfaces of the first connection wiring CW1' and the second connection wiring CW2'.

[0212] In the first light-emitting diode ED1 and the second light-emitting diode ED2 each having the above-described structure, the intermediate layer, particularly the emission layer 220, may be formed to have a substantially uniform thickness. In addition, the thickness uniformity of the emission layer 220 affects the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED. Therefore, the display device 1 according to one or more embodiments may improve the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED.

[0213] As described above, the emission layer 220 can be formed by discharging an emission layer forming material into the opening 120OP of the bank layer 120 through an inkjet process and then drying the emission layer forming material through a drying process. At this time, capillary flow and Marangoni flow may occur within the emission layer forming material.

[0214] In one or more embodiments, depending on the characteristics of the emission layer forming material itself or the drying environment, the Marangoni flow can be stronger than the capillary flow. When the Marangoni flow is stronger than the capillary flow, solutes moving from the inside of the emission layer forming material accumulate at the central portion, and the solutes can continue to accumulate as the liquid continues to evaporate. For example, if the Marangoni flow is strong in the emission layer forming material (e.g., when the Marangoni flow is strong in the emission layer forming material), the emission layer 220 may be dried into a W shape having a raised central region. For example, if the Marangoni flow is stronger than the capillary flow (e.g., when the Marangoni flow is stronger than the capillary flow), the thickness of the emission layer 220 may become substantially non-uniform, which may deteriorate the characteristics of the light emitting diode ED.

[0215] At this time, in the display device 1 according to one or more embodiments, the emission layer 220 can be formed to have a substantially uniform thickness by applying an electrical signal to the first sub-pixel electrode 211a and the second sub-pixel electrode 211b during the drying process. For example, the first sub-pixel electrode 211a can be connected to an external device through the first connection wiring CW1', and the second sub-pixel electrode 211b can be connected to an external device through the second connection wiring CW2', such that the first sub-pixel electrode 211a and the second sub-pixel electrode 211b can receive an alternating current signal.

[0216] When an alternating current signal is applied to the first sub-pixel electrode 211a and the second sub-pixel electrode 211b during the drying process, the flow of the emission layer forming material can be caused by the ACEO phenomenon. In the ACEO phenomenon, the solvent moves on the two electrodes, forming an electric field in a direction opposite to the direction in which the electrodes face each other, and thus causing flow. Therefore, if an electric field is formed by applying an alternating current signal to the first sub-pixel electrode 211a and the second sub-pixel electrode 211b respectively having the above-described structure (e.g., when an electric field is formed by applying an alternating current signal to the first sub-pixel electrode 211a and the second sub-pixel electrode 211b respectively having the above-described structure), a flow of the solvent moving from the central portion to the edge within the emission layer 220 can be caused.

[0217] Therefore, in the case where the Marangoni flow is stronger than the capillary flow of the solvent moving to the edge, if an electrical signal is applied to each having Figure 9The first sub-pixel electrode 211a and the second sub-pixel electrode 211b of the structure shown (e.g., when an electrical signal is applied to each having Figure 9 the first sub-pixel electrode 211a and the second sub-pixel electrode 211b of the structure shown), the phenomenon of capillary flow can be enhanced by ACEO, thereby relatively reducing the Marangoni flow. Therefore, in the display device according to one or more embodiments, since the emissive layer forming material balances the capillary flow and the Marangoni flow during the drying process, the emissive layer 220 can be formed to have a substantially uniform thickness.

[0218] Figures 10A to 10E is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments. Figures 10A to 10E is along the manufacturing process Figure 8 taken along line II-II' of Figure 8 the display device.

[0219] Referring to Figure 10A , a pixel circuit layer PCL can be formed on the substrate 100, and a pixel electrode 210' can be formed on the pixel circuit layer PCL.

[0220] For example, a first pixel electrode 211' corresponding to a first pixel (e.g., referring to Figure 9 PX1) and a second pixel electrode 212' corresponding to a second pixel (e.g., referring to Figure 9 PX2) can be formed on the planarization layer 119. In this case, the first pixel electrode 211' may include a first sub-pixel electrode 211a and a second sub-pixel electrode 211b that are separated or spaced apart (e.g., spaced apart or separated) from each other by a certain distance, and the second pixel electrode 212' may include a third sub-pixel electrode 212a and a fourth sub-pixel electrode 212b that are separated or spaced apart (e.g., spaced apart or separated) from each other by a certain distance.

[0221] In addition, a first connection wiring CW1' (e.g., referring to Figure 9 ) and a second connection wiring CW2' (e.g., referring to Figure 9 ) can be deposited on the planarization layer 119. The first connection wiring CW1' and the second connection wiring CW2' can be electrically connected to the sub-pixel electrodes arranged adjacent to them, respectively.

[0222] The first sub-pixel electrode 211a, the second sub-pixel electrode 211b, the third sub-pixel electrode 212a, the fourth sub-pixel electrode 212b, the first connection wiring CW1', and the second connection wiring CW2' may be formed to include the same material on the same layer. In this regard, the first sub-pixel electrode 211a, the second sub-pixel electrode 211b, the third sub-pixel electrode 212a, the fourth sub-pixel electrode 212b, the first connection wiring CW1', and the second connection wiring CW2' may be deposited in parallel (e.g., simultaneously) by the same deposition process.

[0223] The bank layer 120 may be formed on the pixel electrode 210', the first connection wiring CW1', and the second connection wiring CW2'. The bank layer 120 may be formed to cover the end portion of the pixel electrode 210' opposite (e.g., facing) the edge of the opening 120OP, the top surface of the first connection wiring CW1', and the top surface of the second connection wiring CW2'. The bank layer 120 may be formed by forming an inorganic insulating material layer or an organic insulating material layer and then patterning the opening 120OP to expose the central portion of the pixel electrode 210'.

[0224] Reference Figure 10B , by discharging the ink including the emission layer forming material, the first material layer 221' may be formed in the first opening 120OP1, and the second material layer 222' may be formed in the second opening 120OP2. The first material layer 221' and the second material layer 222' may each constitute the material layer 220'. For example, the first material layer 221' may be formed on the first sub-pixel electrode 211a and the second sub-pixel electrode 211b, and the second material layer 222' may be formed on the third sub-pixel electrode 212a and the fourth sub-pixel electrode 212b. In one or more embodiments, the material layer 220' may include a light-emitting material containing quantum dots.

[0225] In one or more embodiments, the material layer 220' may be formed by an inkjet printing process. Considering the surface tension and volume shrinkage after drying, the material layer 220' may have a convex shape having a thick central portion. However, the present disclosure is not limited thereto. In one or more embodiments, depending on the injection amount of the ink including the light-emitting material, the material layer 220' may have a flat shape or a concave shape.

[0226] Reference Figure 10C , the emission layer (e.g., see Figure 10D 220) may be formed by drying the material layer 220'. However, as described above, the solvent of the ink including the light-emitting material evaporates. When the Marangoni flow phenomenon is strong, the emission layer (e.g., see Figure 10D 220) may have a substantially non-uniform thickness in a W shape.

[0227] Therefore, in a method of manufacturing a display device according to one or more embodiments, an electrical signal can be applied from an external device to a first sub-pixel electrode 211a and a second sub-pixel electrode 211b. The electrical signal can be transmitted to the first sub-pixel electrode 211a through a first connection wiring CW11', and the electrical signal can be transmitted to the second sub-pixel electrode 211b through a second connection wiring CW12'.

[0228] The first sub-pixel electrode 211a and the second sub-pixel electrode 211b have shapes that face each other (e.g., having side ends that face each other). Therefore, if an alternating current signal is applied to the first sub-pixel electrode 211a and the second sub-pixel electrode 211b (e.g., when an alternating current signal is applied to the first sub-pixel electrode 211a and the second sub-pixel electrode 211b), an electric field can be formed between the first sub-pixel electrode 211a and the second sub-pixel electrode 211b, and thus, the solvent in the material layer 220' can move from the central portion to the edge due to the ACEO phenomenon. For example, as Figure 10C shown, the solvent in the material layer 220' can move from the central portion of the opening 120OP to the region adjacent to the bank layer 120.

[0229] When the flow occurs in the above-described direction, the capillary flow can be enhanced, which weakens the influence caused by the Marangoni flow, and thus, the material layer 220' can be dried to have a substantially uniform thickness. Therefore, according to one or more embodiments, the light-emitting efficiency and lifetime efficiency of the light-emitting diode ED can be improved by the method of manufacturing a display device. At this time, after the drying process is completed, the first connection wiring CW1' and the second connection wiring CW2' can be disconnected within a non-display area (e.g., see Figure 1 the NDA).

[0230] Referring to Figure 10D , after the drying of the emission layer 220 is completed, a baking process can be additionally performed. When the emission layer 220 is heat-treated under conditions of about 140°C to about 230°C, the density inside the emission layer 220 can be increased, and the light-emitting efficiency can be improved.

[0231] Specific conditions such as the temperature and time of the baking process can be appropriately or suitably selected according to the type or kind and capacity of the material. However, the present disclosure is not limited thereto. In some cases, the baking process may not be provided.

[0232] Referring to Figure 10E, a counter electrode 230 may be formed on the emission layer 220 and the bank layer 120. The counter electrode 230 may be integrally formed across the entire surface of the substrate 100. Accordingly, the first sub-pixel electrode 211a, the second sub-pixel electrode 211b, the first emission layer 221, and the counter electrode 230 may constitute a first light-emitting diode ED1, and the third sub-pixel electrode 212a, the fourth sub-pixel electrode 212b, the second emission layer 222, and the counter electrode 230 may constitute a second light-emitting diode ED2.

[0233] Figure 11 is a cross-sectional view schematically showing a method of manufacturing a display device according to one or more embodiments. Refer to Figure 11 , other features except for the mobile device 2 may be the same as those described with reference to Figures 10A to 10E independently. In Figure 11 , the same reference numerals denote the same elements as those described with reference to Figures 10A to 10E , and the differences will be mainly described in more detail later.

[0234] Refer to Figure 11 , an electric field may be formed by bringing the mobile device 2 close to the display device 1. For example, the mobile device 2 may include an auxiliary substrate 500, a first auxiliary electrode 511a, a second auxiliary electrode 511b, a third auxiliary electrode 512a, and a fourth auxiliary electrode 512b.

[0235] Similar to the substrate 100, the auxiliary substrate 500 may include glass, metal, or a polymer resin. Examples of the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or any mixture thereof. In one or more embodiments, other modifications are possible. For example, the auxiliary substrate 500 may have a multi-layer structure including two layers and a barrier layer between the two layers, where the two layers may include a polymer resin, and the barrier layer may include an inorganic material (e.g., silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), etc.).

[0236] However, in the mobile device 2, the pixel circuit layer PCL, etc. may not be on the auxiliary substrate 500, and the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b may be deposited on the auxiliary substrate 500. Each of the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b may include a conductive material capable of electric field induction. For example, each of the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b may include indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO2), zinc oxide (ZnO), or any combination thereof, or may include magnesium (Mg), silver (Ag), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), or any combination thereof.

[0237] In this case, each of the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b may be formed to have a shape substantially the same as that of the corresponding one of the first sub-pixel electrode 211a, the second sub-pixel electrode 211b, the third sub-pixel electrode 212a, and the fourth sub-pixel electrode 212b, and may be formed to have an area the same as that of the corresponding one of the first sub-pixel electrode 211a, the second sub-pixel electrode 211b, the third sub-pixel electrode 212a, and the fourth sub-pixel electrode 212b. Further, if the substrate 100 and the auxiliary substrate 500 are aligned with each other (e.g., when the substrate 100 and the auxiliary substrate 500 are aligned with each other), the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b may be respectively formed at positions that may overlap with the first sub-pixel electrode 211a, the second sub-pixel electrode 211b, the third sub-pixel electrode 212a, and the fourth sub-pixel electrode 212b in the plan view of the display device 1. For example, the first auxiliary electrode 511a may be formed at the same position as the first sub-pixel electrode 211a and may be formed to have an area the same as that of the first sub-pixel electrode 211a, and the second auxiliary electrode 511b may be formed at the same position as the second sub-pixel electrode 211b and may be formed to have an area the same as that of the second sub-pixel electrode 211b.

[0238] At this time, in the method of manufacturing a display device according to one or more embodiments, when drying the material layer 220' to form an emission layer (e.g., see Figure 9In the process of 220), the mobile device 2 having the structure described above can be brought close to the display device 1 and then connected to an external device that applies an electrical signal thereto. For example, the external device can be connected to the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b of the mobile device 2, and an alternating current signal can be applied to the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b.

[0239] The external device 2 can apply electrical signals of the same potential to the first auxiliary electrode 511a and the third auxiliary electrode 512a, and can apply electrical signals of the same potential to the second auxiliary electrode 511b and the fourth auxiliary electrode 512b. Therefore, if an alternating current signal is applied to the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b (for example, when an alternating current signal is applied to the first auxiliary electrode 511a, the second auxiliary electrode 511b, the third auxiliary electrode 512a, and the fourth auxiliary electrode 512b), an electric field can be formed between the first auxiliary electrode 511a and the second auxiliary electrode 511b, and an electric field can be formed between the third auxiliary electrode 512a and the fourth auxiliary electrode 512b.

[0240] When the mobile device 2 in which an electric field is formed approaches the display device 1, the electric field formed between the first auxiliary electrode 511a and the second auxiliary electrode 511b can affect the material layer 220'. In particular, since the first auxiliary electrode 511a and the second auxiliary electrode 511b have shapes that are opposite to each other with respect to the center of the opening 120OP (for example, having side ends facing each other), the solvent in the material layer 220' can move from the central portion to the edge due to the ACEO phenomenon.

[0241] As Figure 11 shown, if the mobile device 2 is brought close to the display device 1 and flow occurs in the direction described above (for example, when the mobile device 2 is brought close to the display device 1 and flow occurs in the direction described above), the influence caused by capillary flow can be enhanced, and thus, the material layer 220' can be dried to have a substantially uniform thickness. Therefore, according to one or more embodiments, the luminous efficiency and lifetime efficiency of the light-emitting diode ED can be improved by a method of manufacturing a display device.

[0242] Figure 12 is a schematic plan view of a display device according to one or more embodiments. Referring to Figure 12 , other features except for the first connection wiring CW1” and the second connection wiring CW2” can be independently associated with reference Figure 8 and Figure 9Those described features are the same. In Figure 12 the same reference numerals denote elements that are the same as those described in the reference Figure 8 and Figure 9 described, and the differences will be mainly described in more detail later.

[0243] Reference Figure 12 , according to one or more embodiments, the display device may further include connection wirings that electrically connect each of the sub-pixel electrodes to an external device to which an electrical signal is applied. The connection wirings may include a first connection wiring CW1” and a second connection wiring CW2” respectively configured to transmit an electrical signal to two sub-pixel electrodes corresponding to one pixel (e.g., see Figure 1 PX).

[0244] The first connection wiring CW1” and the second connection wiring CW2” may be configured to transmit an electrical signal to sub-pixel electrodes disposed on both sides (e.g., opposite sides) of the connection wiring, respectively. For example, the 1-1 connection wiring CW11” may be electrically connected to the first sub-pixel electrode 211a, and the 2-1 connection wiring CW21” may be electrically connected to the second sub-pixel electrode 211b and the third sub-pixel electrode 212a. Similarly, the 1-2 connection wiring CW12” may be electrically connected to the fourth sub-pixel electrode 212b and the fifth sub-pixel electrode 213a, and the 2-2 connection wiring CW22” may be electrically connected to the sixth sub-pixel electrode 213b.

[0245] Each of the first connection wiring CW1” and the second connection wiring CW2” may extend in a first direction (e.g., the y direction) to connect the sub-pixel electrodes to the external device. At this time, each of the first connection wiring CW1” and the second connection wiring CW2” may be connected to only one sub-pixel electrode and may also be electrically connected to a plurality of sub-pixel electrodes arranged along the first direction (e.g., arranged in a row in the first direction) with respect to each other.

[0246] In this case, electrical signals of the same potential may be applied to the sub-pixel electrodes connected to the first connection wiring CW1”, and electrical signals of the same potential may be applied to the sub-pixel electrodes connected to the second connection wiring CW2”. For example, the first sub-pixel electrode 211a, the fourth sub-pixel electrode 212b, and the fifth sub-pixel electrode 213a may receive electrical signals of the same potential, and the second sub-pixel electrode 211b, the third sub-pixel electrode 212a, and the sixth sub-pixel electrode 213b may receive electrical signals of the same potential.

[0247] For example, only one selected from the first connection wiring CW1” and the second connection wiring CW2” may be in adjacent pixels (e.g., see Figure 1between PXs). For example, a connection wiring can be between pixels adjacent to each other (e.g., see Figure 1 between PXs). The display device 1 according to one or more embodiments, the area between pixels (e.g., see Figure 1 between PXs) can be reduced. Therefore, the resolution can be improved, and also the effect of forming an emission layer having a substantially uniform thickness (e.g., see Figure 9 of 220) can be achieved.

[0248] The display device according to one or more embodiments can improve the luminous efficiency and lifetime of the light-emitting device by forming an intermediate layer having a substantially uniform thickness. These effects are only examples, and the scope of the present disclosure is not limited by these effects.

[0249] The display device, electronic device, electronic facility, or any other related device or component according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on one integrated circuit (IC) chip or formed on separate IC chips. In addition, various components of the device can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate. In addition, various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components for performing various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device such as, for example, random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as, for example, CD-ROM, flash drive, etc. In addition, those skilled in the art should recognize that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0250] Unless otherwise stated or implied, considering the entire content of the present disclosure, those of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, and can be interlocked and operated in various suitable ways technically, and each embodiment can be implemented independently of each other or implemented in combination with each other in any suitable way.

[0251] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment is generally to be considered applicable to other similar features or aspects in one or more other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that one or more suitable changes in form and detail may be made in the embodiments without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate having a display area and a non-display area surrounding the display area; a pixel circuit layer on the substrate, the pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; a first main pixel electrode on the planarization layer; a peripheral pixel electrode on the planarization layer, the peripheral pixel electrode being spaced apart from the first main pixel electrode and surrounding the first main pixel electrode in a plan view; a bank layer including a first opening exposing a central portion of the first main pixel electrode; a first intermediate layer corresponding to the first main pixel electrode and disposed within the first opening; and a counter electrode covering the bank layer and the first intermediate layer.

2. The display device according to claim 1, wherein, The first main pixel electrode and the peripheral pixel electrode are disposed on the same layer.

3. The display device according to claim 1, wherein, The bank layer covers a top surface and an end portion of the peripheral pixel electrode.

4. The display device according to claim 1, further comprising: a second main pixel electrode on the planarization layer and disposed adjacent to the first main pixel electrode; and a second intermediate layer disposed within a second opening of the bank layer exposing a central portion of the second main pixel electrode, wherein the peripheral pixel electrode is between the first main pixel electrode and the second main pixel electrode.

5. The display device according to claim 4, wherein, Each of the first intermediate layer and the second intermediate layer includes an emission layer containing quantum dots.

6. The display device according to claim 1, further comprising: a first connection wiring electrically connected to the first main pixel electrode and configured to transmit an electrical signal from an external device; and a second connection wiring electrically connected to the peripheral pixel electrode and configured to transmit an electrical signal from the external device.

7. The display device according to claim 6, wherein, The display device includes a plurality of main pixel electrodes including the first main pixel electrode arranged along a first direction, and the first connection wiring is electrically connected to the plurality of main pixel electrodes.

8. The display device according to claim 6, wherein, The first connection wiring and the second connection wiring are disconnected within the non-display area.

9. The display device according to claim 6, wherein, The first connection wiring and the first main pixel electrode are on different layers.

10. A method of manufacturing a display device, the method comprising: forming a pixel circuit layer on a substrate, the pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; forming a main pixel electrode on the planarization layer; forming a peripheral pixel electrode on the planarization layer, the peripheral pixel electrode being spaced apart from the main pixel electrode and surrounding the main pixel electrode in a plan view; forming a bank layer including an opening exposing a central portion of the main pixel electrode; forming an intermediate layer corresponding to the main pixel electrode within the opening; and forming a counter electrode covering the bank layer and the intermediate layer.

11. The method according to claim 10, wherein The main pixel electrode and the peripheral pixel electrode are deposited by the same process.

12. The method according to claim 10, wherein, The bank layer covers a top surface and an end portion of the peripheral pixel electrode.

13. The method according to claim 10, wherein, Forming the intermediate layer includes: forming a material layer for forming the intermediate layer on the main pixel electrode; and drying the material layer.

14. The method according to claim 13, wherein, Forming the intermediate layer further includes baking the dried material layer.

15. The method according to claim 13, wherein, Forming the material layer includes discharging an intermediate layer forming material into the opening by an inkjet process.

16. The method according to claim 13, further comprising: forming a first connection wiring electrically connected to the main pixel electrode and further extending to connect to an external device; and forming a second connection wiring electrically connected to the peripheral pixel electrode and further extending to connect to the external device.

17. The method according to claim 16, wherein Drying the material layer includes: applying an alternating current signal from the external device to the main pixel electrode through the first connection wiring; and applying an alternating current signal from the external device to the peripheral pixel electrode through the second connection wiring.

18. The method according to claim 17, wherein, Drying the material layer further includes generating an AC electroosmosis phenomenon within the material layer.

19. The method according to claim 16, further comprising disconnecting the first connection wiring and the second connection wiring within a non-display area of the substrate.

20. The method according to claim 13, further comprising bringing a mobile device close to a rear surface of the substrate, the mobile device including an auxiliary substrate, a first auxiliary electrode on the auxiliary substrate, and a second auxiliary electrode on the auxiliary substrate, Among them, wherein the first auxiliary electrode has an area equal to an area of the main pixel electrode, and the second auxiliary electrode has an area equal to an area of the peripheral pixel electrode.

21. The method according to claim 20, wherein, Drying the material layer includes applying an alternating current signal from an external device to the first auxiliary electrode and the second auxiliary electrode.

22. A display device, comprising: a substrate having a display area and a non-display area surrounding the display area; a pixel circuit layer on the substrate, the pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; a first sub-pixel electrode on the planarization layer; a second sub-pixel electrode on the planarization layer and spaced apart from the first sub-pixel electrode; a bank layer having a first opening exposing a portion of the first sub-pixel electrode and a portion of the second sub-pixel electrode; a first intermediate layer on the first sub-pixel electrode and the second sub-pixel electrode and disposed within the first opening; and a counter electrode covering the bank layer and covering the first intermediate layer.

23. The display device according to claim 22, wherein, The first sub-pixel electrode and the second sub-pixel electrode are disposed on the same layer.

24. The display device according to claim 22, wherein, The first sub-pixel electrode and the second sub-pixel electrode have the same area and respectively have symmetric shapes with respect to each other.

25. The display device according to claim 22, wherein, Each of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to the pixel circuit.

26. The display device according to claim 22, further comprising: a first connection wiring electrically connected to the first sub-pixel electrode and configured to transmit an electrical signal from an external device; and a second connection wiring electrically connected to the second sub-pixel electrode and configured to transmit an electrical signal from the external device.

27. The display device according to claim 26, further comprising: a third sub-pixel electrode on the planarization layer and disposed adjacent to the second sub-pixel electrode; a fourth sub-pixel electrode on the planarization layer and spaced apart from the third sub-pixel electrode; and A second intermediate layer is disposed within a second opening exposing a portion of the third sub-pixel electrode and a portion of the fourth sub-pixel electrode of the bank layer.

28. The display device according to claim 27, wherein, Each of the first connection wiring and the second connection wiring is between the second sub-pixel electrode and the third sub-pixel electrode.

29. The display device according to claim 27, wherein, Only one selected from the first connection wiring and the second connection wiring is between the second sub-pixel electrode and the third sub-pixel electrode.

30. The display device according to claim 26, wherein, The display device includes a plurality of sub-pixel electrodes disposed along a first direction and including the first sub-pixel electrode and the second sub-pixel electrode, and each of the first connection wiring and the second connection wiring is electrically connected to the plurality of sub-pixel electrodes.

31. The display device according to claim 26, wherein, The first connection wiring and the second connection wiring are disconnected within the non-display area.

32. A method of manufacturing a display device, the method comprising: Forming a pixel circuit layer on a substrate, the pixel circuit layer including a pixel circuit and a planarization layer covering the pixel circuit; Forming a first sub-pixel electrode on the planarization layer; Forming a second sub-pixel electrode on the planarization layer, the second sub-pixel electrode being spaced apart from the first sub-pixel electrode; Forming a bank layer having an opening exposing a portion of the first sub-pixel electrode and a portion of the second sub-pixel electrode; Forming an intermediate layer on the first sub-pixel electrode and the second sub-pixel electrode within the opening; And Forming a counter electrode covering the bank layer and the intermediate layer.

33. The method according to claim 32, wherein, The first sub-pixel electrode and the second sub-pixel electrode are deposited by the same process.

34. The method according to claim 32, wherein, The first sub-pixel electrode and the second sub-pixel electrode have the same shape and the same area.

35. The method according to claim 32, wherein, Forming the intermediate layer includes: Forming a material layer for forming the intermediate layer on the first sub-pixel electrode and the second sub-pixel electrode; and Drying the material layer.

36. The method according to claim 35, wherein Forming the material layer includes discharging an intermediate layer forming material into the opening by an inkjet process.

37. The method according to claim 35, further comprising: Forming a first connection wiring electrically connected to the first sub-pixel electrode and further extending to connect to an external device; And Forming a second connection wiring electrically connected to the second sub-pixel electrode and further extending to connect to the external device.

38. The method according to claim 37, wherein, Drying the material layer includes: Applying an alternating current signal from the external device to the first sub-pixel electrode through the first connection wiring; and Applying an alternating current signal from the external device to the second sub-pixel electrode through the second connection wiring.

39. The method according to claim 38, wherein, Drying the material layer further includes generating an alternating current osmosis phenomenon within the material layer.

40. The method according to claim 37, further comprising disconnecting the first connection wiring and the second connection wiring within a non-display area of the substrate.

41. The method according to claim 35, further comprising bringing a mobile device close to a rear surface of the substrate, the mobile device including an auxiliary substrate, a first auxiliary electrode on the auxiliary substrate, and a second auxiliary electrode on the auxiliary substrate. Among them, The area of the first auxiliary electrode is the same as the area of the first sub-pixel electrode, and the area of the second auxiliary electrode is the same as the area of the second sub-pixel electrode.

42. The method according to claim 41, wherein, Drying the material layer includes applying an alternating current signal from an external device to the first auxiliary electrode and the second auxiliary electrode.

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