Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first data signal line, a second data signal line and a plurality of repeating units, a first sub-pixel unit is electrically connected with the first data signal line through a first electric connecting component, and a second sub-pixel unit is electrically connected with the second data signal line through a second electric connecting component. The first electric connection component, the second electric connection component, the first data signal line and the second data signal line are arranged on the same side of the repeating unit; the first data signal line and the first electric connection component which are connected with the first sub-pixel unit in the repeating unit, and the second data signal line and the second electric connection component which are connected with the second sub-pixel unit in the repeating unit are arranged on the same side of the repeating unit; the first electric connecting component or the second electric connecting component is prevented from crossing the corresponding pixel driving circuit, the parasitic capacitance on the data signal line is reduced, and the display picture of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology. Due to its unique advantages such as low power consumption, high saturation, fast response time, and wide viewing angle, it has gradually attracted people's attention and occupies a certain position in the field of panel display technologies.

[0003] In related technologies, the film layer structures of the sub-pixel units of an OLED display panel are the same. Usually, data lines are arranged on both sides of the sub-pixel units. Some sub-pixel units in the same column need an electrical connection line that spans across the sub-pixel units to be electrically connected to the corresponding data lines. This electrical connection line overlaps with each film layer in the sub-pixel unit, resulting in a relatively large parasitic capacitance of the data signal line, which in turn affects the transmission of data signals and causes abnormal display of the display panel. Summary of the Invention

[0004] This application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above solution, the technical solutions provided in this application are as follows:

[0006] This application provides a display panel, including a plurality of repeating units, a first data signal line, and a second data signal line disposed on one side of the repeating units. The repeating unit includes at least one first sub-pixel unit and at least one second sub-pixel unit. Both the first sub-pixel unit and the second sub-pixel unit include a pixel driving circuit and a light-emitting device connected to the pixel driving circuit;

[0007] Wherein, the display panel further includes a first electrical connection member and a second electrical connection member. The pixel driving circuit of the first sub-pixel unit is electrically connected to the first data signal line through the first electrical connection member, and the pixel driving circuit of the second sub-pixel unit is electrically connected to the second data signal line through the second electrical connection member. The first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are all disposed on the same side of the repeating unit.

[0008] This application also proposes a display device, which includes the above display panel.

[0009] Beneficial effects: The present application discloses a display panel and a display device; the display panel includes a first data signal line, a second data signal line, and a plurality of repeating units. The first sub-pixel unit is electrically connected to the first data signal line through a first electrical connection member, and the second sub-pixel unit is electrically connected to the second data signal line through a second electrical connection member. The first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are all disposed on the same side of the repeating unit. By disposing the first data signal line and the first electrical connection member connected to the first sub-pixel unit in the repeating unit and the second data signal line and the second electrical connection member connected to the second sub-pixel unit on the same side of the repeating unit, the present application avoids the first electrical connection member or the second electrical connection member from straddling the corresponding pixel driving circuit, reduces the parasitic capacitance on the data signal line, and improves the display picture of the display panel. Description of the Drawings

[0010] The following will, by way of a detailed description of the specific embodiments of the present application in conjunction with the drawings, make the technical solutions and other beneficial effects of the present application obvious.

[0011] Figure 1 It is a connection diagram of different sub-pixel units and different data lines in a display panel in the prior art;

[0012] Figure 2 It is a connection diagram of different sub-pixel units and different data lines in the display panel of the present application;

[0013] Figure 3 It is a schematic structural diagram of the display panel of the present application;

[0014] Figure 4 It is an equivalent circuit diagram of a pixel driving circuit in the display panel of the present application;

[0015] Figure 5 It is a schematic diagram of a film layer in the display panel of the present application;

[0016] Figure 6 It is a film layer diagram of the first gate layer in the display panel of the present application;

[0017] Figure 7 It is a film layer diagram of the first active layer in the display panel of the present application;

[0018] Figure 8 It is a film layer stack diagram of the first gate layer and the first active layer in the display panel of the present application;

[0019] Figure 9 It is a film layer diagram of the second gate layer in the display panel of the present application;

[0020] Figure 10 It is a film layer stack diagram of the first gate layer and the second gate layer in the display panel of the present application;

[0021] Figure 11 This is the layer diagram of the second active layer in the display panel of this application;

[0022] Figure 12 This is the layer diagram of the third gate layer in the display panel of this application;

[0023] Figure 13 This is the layer diagram of the first active layer, second active layer, second gate layer, and third gate layer in the display panel of this application;

[0024] Figure 14 This is the layer diagram of the first source-drain layer of the first sub-pixel unit in the display panel of this application;

[0025] Figure 15 This is the layer diagram of the first gate layer, third gate layer, first active layer, second active layer, and first source-drain layer of the first sub-pixel unit in the display panel of this application;

[0026] Figure 16 This is the layer diagram of the second active layer, second gate layer, and first source-drain layer of the first sub-pixel unit in the display panel of this application;

[0027] Figure 17 This is the layer diagram of the first gate layer, second gate layer, third gate layer, first active layer, second active layer, and first source-drain layer of the first sub-pixel unit in the display panel of this application;

[0028] Figure 18 This is the first layer diagram of the second source-drain layer in the display panel of this application;

[0029] Figure 19 This is the superposition diagram of the first active layer, second active layer, third gate layer, first source-drain layer, and second source-drain layer of the first sub-pixel unit in the display panel of this application;

[0030] Figure 20 This is the superposition diagram of the film layers of the pixel driving circuit of this application;

[0031] Figure 21 This is the layer diagram of the first source-drain layer of the second sub-pixel unit in the display panel of this application;

[0032] Figure 22 This is the superposition diagram of the first active layer, second active layer, third gate layer, first source-drain layer, and second source-drain layer of the second sub-pixel unit in the display panel of this application;

[0033] Figure 23 This is the second layer diagram of the second source-drain layer in the display panel of this application;

[0034] Figure 24It is a film layer diagram of the third source-drain layer in the display panel of the present application;

[0035] Figure 25 It is a film layer diagram of the superposition of the second source-drain layer and the third source-drain layer in the display panel of the present application;

[0036] Figure 26 It is the fourth film layer superposition diagram of the pixel driving circuit of the present application;

[0037] Figure 27 It is a film layer diagram of the third source-drain layer in multiple sub-pixel units in the display panel of the present application;

[0038] Figure 28 It is a connection relationship diagram of the first reset signal line, the second reset signal line, the third reset signal line and the fourth reset signal line in the display panel of the present application;

[0039] Figure 29 It is a film layer superposition diagram of the third source-drain layer, the data signal line and the anode of the light-emitting device in the display panel of the present application. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" refer to the outline of the device.

[0041] In the prior art, the structures of the pixel driving circuits in different sub-pixel units are the same, that is, the input ends of the data signals equivalent to the pixel driving circuits are all located on the same side, while the data signal lines in the current display panel are all located on both sides of the sub-pixel units, for example Figure 1In the structure, the first data signal line Data1 is disposed on the left side of the sub-pixel unit P, and the second data signal line Data2 is disposed on the right side of the sub-pixel unit P. Then, the data signal input end of the sub-pixel unit P in the first row is disposed adjacent to the first data signal line Data1, while the distance between the data signal input end of the sub-pixel unit P in the second row and the second data signal line Data2 is the width of one sub-pixel unit P. That is, a connecting line spanning the sub-pixel unit P is required to electrically connect the second data signal line Data2 and the data signal input end of the sub-pixel unit P in the second row. This connecting line overlaps with multiple film layer structures in the sub-pixel unit P, increasing the coupling capacitance between the second data signal line Data2 and the corresponding film layer, thereby affecting the transmission of the data signal on the second data signal line Data2 and resulting in abnormal display of the display panel. Based on the above technical problems, the present application proposes a display panel to solve the above technical problems.

[0042] Please refer to Figures 2 to 28 , the present application provides a display panel 100. The display panel 100 may include a display portion 200 and a gate driving circuit 300 located on one side of the display portion 200. The gate driving circuit 300 is configured to input a control signal to the display portion 200.

[0043] In this embodiment, please refer to Figure 3 , the display portion 200 includes a plurality of sub-pixel rows 210. Each sub-pixel row 210 includes a plurality of sub-pixel units 211. Each sub-pixel unit 211 is provided with a light-emitting device 211b and a pixel driving circuit 211a connected to the light-emitting device 211b. The gate driving circuit 300 is configured to input a gate control signal to a transistor in the pixel driving circuit 211a.

[0044] Please refer to Figure 2 , the plurality of sub-pixel units 211 may include a plurality of repeating units 500. The repeating unit 500 includes at least one first sub-pixel unit 211c and at least one second sub-pixel unit 211d. Both the first sub-pixel unit 211c and the second sub-pixel unit 211d include a pixel driving circuit 211a. In the following embodiments, an example in which only the first sub-pixel unit 211c and the second sub-pixel unit 211d are provided in one repeating unit 500 will be described.

[0045] In this embodiment, the display panel 100 further includes a first data signal line Data1 and a second data signal line Data2 disposed on one side of the repeating unit 500, as well as a first electrical connection member 610 and a second electrical connection member 620. The pixel driving circuit 211a of the first sub-pixel unit 211c is electrically connected to the first data signal line Data1 through the first electrical connection member 610, and the pixel driving circuit 211a of the second sub-pixel unit 211d is electrically connected to the second data signal line Data2 through the second electrical connection member 620.

[0046] In this embodiment, the first electrical connection member 610, the second electrical connection member 620, the first data signal line Data1, and the second data signal line Data2 are all disposed on the same side of the repeating unit 500.

[0047] In this application, by disposing the first data signal line Data1 and the first electrical connection member 610 connected to the first sub-pixel unit 211c in the repeating unit 500, and the second data signal line Data2 and the second electrical connection member 620 connected to the second sub-pixel unit 211d on the same side of the repeating unit 500, the connection distance between the data signal line and the input end of the data signal in the sub-pixel unit 211 is reduced, avoiding the first electrical connection member 610 or the second electrical connection member 620 from straddling the corresponding pixel driving circuit 211a, reducing the parasitic capacitance on the data signal line, improving the stability of the pixel driving circuit 211a, and improving the display picture of the display panel 100.

[0048] It should be noted that the structures of the pixel driving circuits 211a in different sub-pixel units 211 of this application may be the same, and the difference is only that different electrical connection members are provided for different sub-pixel units 211. For example, the first electrical connection member 610 in the first sub-pixel unit 211c and the second electrical connection member 620 in the second sub-pixel unit 211d are disposed at different positions within the corresponding sub-pixel unit 211.

[0049] It should be noted that the light-emitting device 211b of this application may be an organic light-emitting diode, a Mini LED, a MicroLED, a conventional-sized LED, or other light sources.

[0050] Now, the technical solution of this application will be described in combination with specific embodiments.

[0051] Please refer to Figure 3, the display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA. A display portion 200 is provided in the display area AA. Optionally, the non-display area NA surrounds the display area AA, such that the display area AA is surrounded by the non-display area NA. The display area AA is an area within the display panel 100 for performing a display function, and a plurality of sub-pixel units 211 for implementing its display function are provided therein. The non-display area NA may be a border area of the display panel 100, and functional components for assisting the sub-pixel units 211 in the display area AA to perform display may be provided therein.

[0052] Please refer to Figure 3 , a bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit, and the bonding terminal 400 transmits the signal input by the external circuit to the data trace, thereby driving the display panel 100 to display an image. For example, the bonding terminal 400 can be bonded and connected to a chip or a chip-on-film, etc., for providing a power supply and a driving signal, etc. to the display panel 100.

[0053] In this embodiment, the gate driving circuit 300 is provided in the non-display area NA, and the gate driving circuit 300 can be provided on both sides of the display area AA; the gate driving circuit 300 can include a plurality of cascaded gate driving units, and the plurality of gate driving units can be arranged along the first direction X. The structure of the gate driving unit is not specifically limited in this application.

[0054] In this embodiment, a plurality of light-emitting devices 211b and pixel driving circuits 211a for driving the light-emitting devices 211b can be arranged in an array in the display area AA. The pixel driving circuits 211a can be 7T1C, 7T2C, 8T2C, 8T3C, 8T4C and other pixel driving circuits 211a. In the following embodiments, the 8T3C pixel driving circuit 211a is taken as an example for description. Since the structures of the pixel driving circuits 211a in different sub-pixel units 211 are the same, the structure of the pixel driving circuit 211a of the first sub-pixel unit 211c is first described below.

[0055] Please refer to Figure 4 , the pixel driving circuit 211a can include a switching transistor T2, a driving transistor T1, a compensating transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a boosting capacitor Cboost, and a storage capacitor Cst. The storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2, and the boosting capacitor Cboost includes a third electrode plate and a fourth electrode plate.

[0056] Please refer to Figure 4, the first electrode of the switching transistor T2 is connected to the first data signal line Data1, the second electrode of the switching transistor T2 is connected to the first node A, and the switching gate T2G of the switching transistor T2 is connected to the second control signal line Pscan1; the first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the driving gate T1G of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control signal line Nscan1; the first electrode of the first reset transistor T4 is connected to the first reset signal line Vi1, the second electrode of the first reset transistor T4 is connected to the third node Q, and the first reset gate T4G of the first reset transistor T4 is connected to the third control signal line Nscan2; the first electrode of the second reset transistor T7 is connected to the second reset signal line Vi2, the second electrode of the second reset transistor T7 is connected to the anode of the light-emitting device 211b, and the second reset gate T7G of the second reset transistor T7 is connected to the fourth control signal line Pscan2; the first electrode of the third reset transistor T8 is connected to the third reset signal line Vi3, the second electrode of the third reset transistor T8 is connected to the first node A, and the third reset gate T8G of the third reset transistor T8 is connected to the fourth control signal line Pscan2; the first electrode of the first light-emitting transistor T5 is connected to the first high potential line VDD1, the second electrode of the first light-emitting transistor T5 is connected to the first node A, and the first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting signal line EM; the first electrode of the second light-emitting transistor T6 is connected to the second node B, the second electrode of the second light-emitting transistor T6 is connected to the anode of the light-emitting device 211b, and the second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting signal line EM; the third electrode plate of the boost capacitor Cboost is connected to the third node Q, and the fourth electrode plate of the boost capacitor Cboost is connected to the second control signal line Pscan1; the first electrode plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second electrode plate Cst2 of the storage capacitor Cst is connected to the first high potential line VDD1.

[0057] It should be noted that for the switching transistors T2 in different sub-pixel units 211, the data signal lines they are connected to are different. In this application, only one of them is taken as an example for illustration.

[0058] In this embodiment, the first high potential line VDD1 is used to provide a constant voltage high level to the pixel driving circuit 211a, and the first low potential line VSS is used to provide a constant voltage low level to the pixel driving circuit 211a.

[0059] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 can be one of a P-type transistor or an N-type transistor, and the compensation transistor T3 and the first reset transistor T4 can be the other of a P-type transistor or an N-type transistor; in this application, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 are taken as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 are taken as N-type transistors as an example for illustration.

[0060] In this embodiment, the capacitance value of the boost capacitor Cboost is smaller than the capacitance value of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used to maintain the stability of the potential of the third node Q. Therefore, the storage capacitor Cst has a relatively large capacitance. For example, the capacitance value range of the storage capacitor Cst can be from 45 fF to 55 fF, and the capacitance value range of the boost capacitor Cboost can be from 5 fF to 15 fF.

[0061] In this embodiment, the first electrode can be one of the source electrode or the drain electrode, and the second electrode can be the other of the source electrode or the drain electrode.

[0062] In the following embodiments, the included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction.

[0063] The following is directed to Figure 4 the structure of, and describes the film layer structure of the pixel driving circuit 211a of this application.

[0064] Please refer to Figure 5 , the display area AA and the non-display area NA of the display panel 100 can be provided with a substrate 110 and an array driving layer 120 provided on the substrate 110; within the display area AA, the display panel 100 can also be provided with a pixel definition layer (not shown) provided on the array driving layer 120, a light-emitting device layer (not shown) provided on the same layer as the pixel definition layer, and a packaging layer (not shown) provided on the pixel definition layer. The following mainly describes the film layer structure within the display area AA.

[0065] In this embodiment, the substrate 110 supports each layer provided on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided emitting light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate and a transparent substrate can be used.

[0066] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110, and the substrate 110 can be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 can be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0067] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 can be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0068] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a support substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the same material as that of the first flexible substrate 111 and curing the material, and the second flexible substrate 113 is formed by the same method as that for forming the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, so that the above defects can be removed.

[0069] Please refer to Figure 5 , the array driving layer 120 may include a plurality of thin film transistors. The thin film transistors can be of an etch stop type, a back channel etch type, or can be divided into structures such as bottom gate thin film transistors and top gate thin film transistors according to the positions of the gate and the active layer, or can be divided into N-type thin film transistors and P-type thin film transistors according to the performance of the thin film transistors; wherein, Figure 5 the thin film transistors in Figure 4 do not represent the structural diagrams of any of the transistors in

[0070] Please refer to Figure 5, the array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the third gate insulating layer 128, a fourth gate insulating layer 130 disposed on the second active layer 129, a third gate layer 131 disposed on the fourth gate insulating layer 130, a first inter-insulating layer 132 disposed on the third gate layer 131, a first source-drain layer 133 disposed on the first inter-insulating layer 132, a second inter-insulating layer 134 disposed on the first source-drain layer 133, a second source-drain layer 135 disposed on the second inter-insulating layer 134, a third inter-insulating layer 136 disposed on the second source-drain layer 135, a third source-drain layer 137 disposed on the third inter-insulating layer 136, and a planarization layer 138 disposed on the third source-drain layer 137.

[0071] Please refer to Figure 5 , the light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 may be composed of a black light-shielding material, such as a black light-shielding metal or a black organic material, etc.

[0072] Please refer to Figure 5 , the buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 and the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon, and oxygen elements, such as a single-layer silicon oxide film layer, or a stacked structure of silicon oxide - silicon nitride.

[0073] Please refer to Figure 5 , the first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 may be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 may be indium gallium zinc oxide semiconductor, amorphous silicon, or low-temperature polycrystalline silicon. For example, in this application, the material of the first active layer 123 may be low-temperature polycrystalline silicon, and the material of the second active layer 129 may be indium gallium zinc oxide semiconductor.

[0074] Please refer to Figure 5, a first gate insulating layer 124, a second gate insulating layer 126, a third gate insulating layer 128, a fourth gate insulating layer 130, a first inter-insulating layer 132, a second inter-insulating layer 134, and a third inter-insulating layer 136 are respectively disposed on corresponding metal layers or semiconductor layers, and are separated and disposed by metal layers or semiconductor layers of different layers; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first inter-insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, the second inter-insulating layer 134, and the third inter-insulating layer 136 may be inorganic substances combined with silicon and oxygen or organic materials with flatness.

[0075] Please refer to Figure 5 , a first gate layer 125, a second gate layer 127, and a third gate layer 131 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125, the second gate layer 127, and the third gate layer 131 may be copper, molybdenum, or molybdenum-titanium alloy, etc. The materials of the three gate layers in this application may be molybdenum.

[0076] Please refer to Figure 5 , a first source-drain layer 133 is disposed on the first inter-insulating layer 132, a second source-drain layer 135 is disposed on the second inter-insulating layer 134, and a third source-drain layer 137 is disposed on the third inter-insulating layer 136. The materials of the first source-drain layer 133, the second source-drain layer 135, and the third source-drain layer 137 may be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium triple metal, etc. The materials of the three source-drain layers in this application may be titanium-aluminum-titanium.

[0077] Please refer to Figure 5 , a planarization layer 138 is laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The material of the planarization layer 138 may be an inorganic substance combined with silicon and oxygen or an organic material with flatness.

[0078] Please refer to Figure 6 , the first gate layer 125 includes a light-emitting signal line EM, a first reset signal line Vi1, a third reset signal line Vi3, and a fourth control signal line Pscan2. The light-emitting signal line EM, the first reset signal line Vi1, the third reset signal line Vi3, and the fourth control signal line Pscan2 all extend along the first direction X, and the third reset signal line Vi3, the fourth control signal line Pscan2, the light-emitting signal line EM, and the first reset signal line Vi1 are arranged at intervals along the second direction Y.

[0079] Please refer to Figure 6, the first gate layer 125 further includes a switching gate T2G and a first plate Cst1 of a storage capacitor Cst disposed between the light-emitting signal line EM and the first reset signal line Vi1. The switching gate T2G and the first plate Cst1 are arranged at intervals in the second direction Y, and the first plate Cst1 is disposed close to the light-emitting signal line EM, while the switching gate T2G is disposed away from the light-emitting signal line EM.

[0080] In this embodiment, the light-emitting signal line EM can directly serve as the first light-emitting gate T5G and the second light-emitting gate T6G, and the fourth control signal line Pscan2 can directly serve as the second reset gate T7G and the third reset gate T8G.

[0081] Please refer to Figure 6 , the shapes of the switching gate T2G and the first plate Cst1 can be rectangular, and chamfers can be provided at the four top corners of the first plate Cst1.

[0082] Please refer to Figure 7 , the first active layer 123 includes a switching active part T2A of a switching transistor T2, a driving active part T1A of a driving transistor T1, a second reset active part T7A of a second reset transistor T7, a third reset active part T8A of a third reset transistor T8, a first light-emitting active part T5A of a first light-emitting transistor T5, and a second light-emitting active part T6A of a second light-emitting transistor T6.

[0083] Please refer to Figure 7 , the switching active part T2A, the driving active part T1A, the second reset active part T7A, the first light-emitting active part T5A, and the second light-emitting active part T6A are connected to each other, the third reset active part T8A is separated from other active parts, the switching active part T2A, the second reset active part T7A, the third reset active part T8A, the first light-emitting active part T5A, and the second light-emitting active part T6A are all strip-shaped and extend along the second direction Y, the driving active part T1A is in a several-character shape and is disposed between the first light-emitting active part T5A and the second light-emitting active part T6A, the first end of the switching active part T2A, the first end of the driving active part T1A, and the first end of the first light-emitting active part T5A are connected to a first connection point P1, the second end of the driving active part T1A and the first end of the second light-emitting active part T6A are connected to a second connection point P2, and the first end of the second reset active part T7A and the second end of the second light-emitting active part T6A are connected to a third connection point P3.

[0084] In this embodiment, the first connection point P1 is the first node A, the second connection point P2 is the second node B, and the third connection point P3 is the position where the anode of the light-emitting device 211b is located.

[0085] It should be noted that the patterns of the switching active parts of the first sub-pixel unit 211c and the second sub-pixel unit 211d are the same.

[0086] Please refer to Figure 8 , the light-emitting signal line EM partially overlaps with the first light-emitting active part T5A, and the overlapping part is the channel of the first light-emitting active part T5A; the light-emitting signal line EM partially overlaps with the second light-emitting active part T6A, and the overlapping part is the channel of the second light-emitting active part T6A; the switching gate T2G partially overlaps with the switching active part T2A, and the overlapping part is the channel of the switching active part T2A; the fourth control signal line Pscan2 partially overlaps with the second reset active part T7A, and the overlapping part is the channel of the second reset active part T7A; the fourth control signal line Pscan2 partially overlaps with the third reset active part T8A, and the overlapping part is the channel of the third reset active part T8A; the driving active part T1A partially overlaps with the first electrode plate Cst1, and the overlapping part is the channel of the driving active part T1A. The first electrode plate Cst1 of the present application is multiplexed as the driving gate T1G of the driving transistor T1.

[0087] Please refer to Figure 9 and Figure 10 , the second gate layer 127 includes the second electrode plate Cst2 of the storage capacitor Cst arranged along the second direction Y, the first light-shielding unit T3S of the compensation transistor T3, and the second light-shielding unit T4S of the first reset transistor T4. The second electrode plate Cst2, the first light-shielding unit T3S, and the second light-shielding unit T4S are located between the light-emitting signal line EM and the first reset signal line Vi1. The first electrode plate Cst1 is arranged close to the light-emitting signal line EM, the second light-shielding unit T4S is arranged close to the first reset signal line Vi1, and the first light-shielding unit T3S is located between the second light-shielding unit T4S and the second electrode plate Cst2.

[0088] Please refer to Figure 9 and Figure 10 , the area of the second electrode plate Cst2 is larger than the area of the first electrode plate Cst1, and the positive projection of the first electrode plate Cst1 on the second electrode plate Cst2 is located within the second electrode plate Cst2. A first through hole HL0 is formed on the second electrode plate Cst2 to expose a part of the first electrode plate Cst1.

[0089] Please refer to Figure 10 , the shapes of the first light-shielding unit T3S, the second light-shielding unit T4S, and the second electrode plate Cst2 can be rectangular, and at least some of the top corners of the three can be chamfered.

[0090] Please refer to Figure 10, the second gate layer 127 further includes first electrical connection segments 311 disposed on both sides of the second electrode plate Cst2. Both of the two first electrical connection segments 311 extend along the first direction X, and in two adjacent sub-pixel units 211 arranged along the first direction X, the second electrode plates Cst2 in the two sub-pixel units 211 are electrically connected through the first electrical connection segments 311; the second electrode plate Cst2 in this embodiment is connected to the first high potential line VDD1. In order to reduce the impedance on the second electrode plate Cst2, in this application, the second electrode plates Cst2 in the sub-pixel units 211 arranged along the first direction X can be connected to each other and are arranged in parallel with the upper-layer first high potential line VDD1 to reduce the impedance of the first high potential line VDD1 and the second electrode plate Cst2.

[0091] Please refer to Figure 11 and Figure 13 , the second active layer 129 includes a compensation active part T3A of the compensation transistor T3 and a first reset active part T4A of the first reset transistor T4. Both the compensation active part T3A and the first reset active part T4A extend along the second direction Y. The first ends of the compensation active part T3A and the first reset active part T4A are connected to the fourth connection point P4. The second end of the compensation active part T3A extends towards the second connection point P2 and is separated from the second connection point P2. The second end of the first reset active part T4A extends towards the first reset signal line Vi1 and overlaps with the first reset signal line Vi1.

[0092] In this embodiment, the fourth connection point P4 can be the third node Q.

[0093] Please refer to Figure 11 and Figure 13 , the second active layer 129 further includes a first extension segment 321 connected to the fourth connection point P4 and a second extension segment 322 connected to the second end of the first reset active part T4A; the first extension segment 321 extends along the second direction Y and extends towards the position where the storage capacitor Cst is located, and the first extension segment 321 is separated from the storage capacitor Cst; the second extension segment 322 extends along the first direction X, and the second extension segment 322 and the first reset signal line Vi1 at least partially overlap.

[0094] Please refer to Figure 12 and Figure 13 , the third gate layer 131 includes a compensation gate T3G and a first reset gate T4G of the first reset transistor T4. The area of the compensation gate T3G is smaller than the area of the first light-shielding unit T3S, and the positive projection of the compensation gate T3G on the first light-shielding unit T3S is located within the first light-shielding unit T3S. The area of the first reset gate T4G is smaller than the area of the second light-shielding unit T4S, and the positive projection of the first reset gate T4G on the second light-shielding unit T4S is located within the second light-shielding unit T4S.

[0095] Please refer to Figure 12 and Figure 13 , the first reset gate T4G and the first reset active part T4A partially overlap, and the overlapping part is the channel of the first reset active part T4A; the compensation gate T3G and the compensation active part T3A partially overlap, and the overlapping part is the channel of the compensation active part T3A.

[0096] Please refer to Figure 12 and Figure 13 , the shapes of the first reset gate T4G and the compensation gate T3G can both be rectangular, and chamfers can be provided at some top corners of the first reset gate T4G and the compensation gate T3G.

[0097] Please refer to Figure 12 and Figure 13 , the third gate layer 131 further includes a first conductive segment 331 connected to the compensation gate T3G and a second conductive segment 332 connected to the first reset gate T4G. The first conductive segment 331 extends along the second direction Y and toward the side away from the compensation gate T3G, and the second conductive segment 332 extends along the second direction Y and toward the side away from the first reset gate T4G.

[0098] Please refer to Figure 9 and Figure 13 , the second gate layer 127 further includes a third conductive segment 333 connected to the first light-shielding unit T3S and a fourth conductive segment 334 connected to the second light-shielding unit T4S. The third conductive segment 333 extends along the second direction Y and toward the side away from the compensation gate T3G. The line width of the first conductive segment 331 can be less than or equal to the line width of the third conductive segment 333, and the orthographic projection of the first conductive segment 331 on the third conductive segment 333 can be located within the third conductive segment 333; the fourth conductive segment 334 can first extend along the second direction Y and toward the side away from the first reset gate T4G, and then can extend along the first direction X and away from the side of the compensation transistor T3. The ends of the second conductive segment 332 and the fourth conductive segment 334 away from the first reset gate T4G can be on the same horizontal line.

[0099] Please refer to Figure 14 , the first source-drain layer 133 includes second reset signal lines Vi2, second control signal lines Nscan3, second high-potential lines VDD2, second control signal lines Pscan1, first control signal lines Nscan1, and third control signal lines Nscan2 arranged along the second direction Y. The second reset signal lines Vi2, second control signal lines Nscan3, second high-potential lines VDD2, second control signal lines Pscan1, first control signal lines Nscan1, and third control signal lines Nscan2 can all extend along the first direction X.

[0100] Please refer to Figures 14 to 17, the second reset signal line Vi2 is disposed between the third reset signal line Vi3 and the first control signal line Nscan1. The second control signal line Nscan3 and the fourth control signal line Pscan2 partially overlap. The second high potential line VDD2 is disposed between the light emitting signal line EM and the first electrical connection segment 311. The second control signal line Pscan1, the first control signal line Nscan1, and the third control signal line Nscan2 are disposed between the first electrical connection segment 311 and the first reset signal line Vi1. And the second control signal line Pscan1 is disposed close to the first electrical connection segment 311, the third control signal line Nscan2 is disposed close to the first reset signal line Vi1, and the first control signal line Nscan1 is disposed between the second control signal line Pscan1 and the third control signal line Nscan2.

[0101] Please refer to Figures 14 to 17 , the first source-drain layer 133 further includes a second electrical connection segment 312 disposed between the second reset signal line Vi2 and the third reset signal line Vi3. The first end of the second electrical connection segment 312 passes through the first via hole HL1 and is electrically connected to the third reset signal line Vi3. The second end of the second electrical connection segment 312 passes through the second via hole HL2 and is electrically connected to the first end of the third reset active portion T8A. The third reset signal line Vi3 transmits the reference voltage to the third reset transistor T8 through the second electrical connection segment 312.

[0102] In this embodiment, the first via hole HL1 penetrates through the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132. The second via hole HL2 penetrates through the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

[0103] In this embodiment, in order to avoid the interference between the second electrical connection segment 312 and the second reset signal line Vi2, the second reset signal line Vi2 is designed to sink at the position corresponding to the second electrical connection segment 312, that is, the signal line in this area is offset away from the third reset signal line Vi3. At the same time, in order to ensure the line distance between the second control signal line Nscan3 and the second reset signal line Vi2, the second control signal line Nscan3 is also designed to sink.

[0104] Please refer to Figures 14 to 17 , the first source-drain layer 133 further includes a third extension segment 323, a third electrical connection segment 313, and a fourth electrical connection segment 314 disposed between the second high potential line VDD2 and the second control signal line Nscan3. Both the third extension segment 323 and the third electrical connection segment 313 extend along the second direction Y, and the fourth electrical connection segment 314 extends along the first direction X.

[0105] In this embodiment, the first end of the third extension segment 323 is electrically connected to the second high potential line VDD2, the second end of the third extension segment 323 extends away from the second high potential line VDD2, and the third extension segment 323 overlaps with a part of the first light-emitting active part T5A, and the second end of the third extension segment 323 passes through the third via hole HL3 and is electrically connected to the second end of the first light-emitting active part T5A; the first end of the third electrical connection segment 313 passes through the fourth via hole HL4 and is electrically connected to the second end of the third reset active part T8A. The first active layer 123 further includes a fourth extension segment 324 connected to the first light-emitting active part T5A. The fourth extension segment 324 extends along the first direction X. The second end of the third electrical connection segment 313 passes through the fifth via hole HL5 and is electrically connected to the fourth extension segment 324. The third reset signal line Vi3 transmits the reference voltage to the first connection point P1 through the second electrical connection segment 312, the third electrical connection segment 313 and the fourth extension segment 324 to reset the potential of the first node A; one end of the fourth electrical connection segment 314 passes through a via hole and is electrically connected to the third connection point P3 in the first active layer 123, and the other end of the fourth electrical connection segment 314 passes through another via hole and is electrically connected to the conductive layer in the second source-drain layer 135.

[0106] In this embodiment, the third via hole HL3 penetrates through the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132. Both the fourth via hole HL4 and the fifth via hole HL5 penetrate through the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

[0107] Please refer to Figures 14 to 17 , the first source-drain layer 133 further includes a fifth electrical connection segment 315 and a sixth electrical connection segment 316 disposed between the second high potential line VDD2 and the second control signal line Pscan1. Both the fifth electrical connection segment 315 and the sixth electrical connection segment 316 extend along the second direction Y.

[0108] In this embodiment, the first end of the fifth electrical connection segment 315 passes through the sixth via hole HL6 and is electrically connected to the end of the first extension segment 321 away from the second control signal line Pscan1. The second end of the fifth electrical connection segment 315 extends into the storage capacitor Cst and passes through the seventh via hole HL7 to be electrically connected to the first electrode plate Cst1 of the storage capacitor Cst. Figure 16In the structure, the seventh via hole HL7 passes through the first via hole HL0 on the second electrode plate Cst2. The centers of the first via hole HL0 and the seventh via hole HL7 can be located on the same straight line perpendicular to the light-emitting surface of the display panel 100. The fifth electrical connection segment 315 of the present application serves as an electrical connection member. One end thereof passes through the sixth via hole HL6 and is electrically connected to the first extension segment 321, and the other end passes through the seventh via hole HL7 and is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst, that is, the wire of the third node Q between the first gate layer 125 and the second active layer 129 is electrically connected through the metal of the first source-drain layer 133.

[0109] In this embodiment, the first end of the sixth electrical connection segment 316 passes through the eighth via hole HL8 and is electrically connected to the second connection point P2 in the first active layer 123, and the second end of the sixth electrical connection segment 316 passes through the ninth via hole HL9 and is electrically connected to the second end in the compensation active part T3A.

[0110] In this embodiment, the sixth via hole HL6 and the ninth via hole HL9 penetrate the fourth gate insulating layer 130 and the first inter-insulating layer 132, and the seventh via hole HL7 and the eighth via hole HL8 penetrate the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

[0111] Please refer to Figures 14 to 17 , the first source-drain layer 133 further includes a fifth extension segment 325. One end of the fifth extension segment 325 is electrically connected to the first control signal line Nscan1, and the fifth extension segment 325 extends along the second direction Y and toward the side away from the first control signal line Nscan1. The end of the fifth extension segment 325 away from the first control signal line Nscan1 passes through the tenth via hole HL10 and is electrically connected to the first conductive segment 331. The first control signal line Nscan1 transmits the control signal to the compensation gate T3G of the compensation transistor T3 through the fifth extension segment 325 and the first conductive segment 331. At the same time, the end of the second conductive segment 332 away from the first reset gate T4G overlaps with the third control signal line Nscan2 and is electrically connected to the third control signal line Nscan2 through the eleventh via hole HL11. The third control signal line Nscan2 transmits the control signal to the first reset gate T4G of the first reset transistor T4 through the second conductive segment 332.

[0112] In this embodiment, both the tenth via hole HL10 and the eleventh via hole HL11 penetrate the first inter-insulating layer 132.

[0113] Please refer to Figures 14 to 17, the third conductive segment 333 overlaps with both the first conductive segment 331 and the third conductive segment 333, and the third conductive segment 333 is electrically connected to the first control signal line Nscan1 through the twelfth via hole HL12. The first control signal line Nscan1 transmits the control signal to the first light-shielding unit T3S through the third conductive segment 333. That is, the first light-shielding unit T3S can be multiplexed as the bottom gate of the compensation transistor T3, and the compensation gate T3G is the top gate of the compensation transistor T3. The settings of the first light-shielding unit T3S and the compensation gate T3G can increase the conduction rate of the compensation transistor T3 and improve the device effect of the compensation transistor T3. The fourth conductive segment 334 overlaps with a part of the third control signal line Nscan2 and is electrically connected to the third control signal line Nscan2 through the thirteenth via hole HL13. The third control signal line Nscan2 transmits the control signal to the second light-shielding unit T4S through the fourth conductive segment 334. That is, the second light-shielding unit T4S can be multiplexed as the bottom gate of the first reset transistor T4, and the first reset gate T4G is the top gate of the first reset transistor T4. The settings of the second light-shielding unit T4S and the first reset gate T4G can increase the conduction rate of the first reset transistor T4 and improve the device effect of the first reset transistor T4.

[0114] In this embodiment, both the twelfth via hole HL12 and the thirteenth via hole HL13 penetrate through the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

[0115] It should be noted that the third conductive segment 333 can be insulated from the first control signal line Nscan1, and the fourth conductive segment 334 can be insulated from the third control signal line Nscan2.

[0116] Please refer to Figures 14 to 17 , the second control signal line Nscan3 can pass through the fourteenth via hole HL14 and be connected in parallel with the fourth control signal line Pscan2. That is, the fifth control signal is connected in parallel with the fourth control signal line Pscan2, reducing the impedance of the second control signal line Nscan3 and the fourth control signal line Pscan2.

[0117] In this embodiment, the fourteenth via hole HL14 penetrates through the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first inter-insulating layer 132.

[0118] Please refer to Figures 14 to 17, the first control signal line Nscan1 and the first reset active part T4A partially overlap, the second control signal line Pscan1 and the first extension section 321 partially overlap, and the second control signal line Pscan1 and the compensation active part T3A partially overlap. The third control signal line Nscan2 and the first reset active part T4A partially overlap. These four overlapping areas are all overlaps between the material of the second active layer 129 and the material of the first source-drain layer 133. There is a fourth gate insulating layer 130 and a first inter-insulating layer 132 between the first source-drain layer 133 and the second active layer 129, and no material of the third gate layer 131 is provided in the middle, avoiding the technical problem that the third gate layer 131 is prone to short-circuit with the first source-drain layer 133.

[0119] Please refer to Figures 14 to 17 , the overlapping part of the second control signal line Pscan1 and the first extension section 321 is the boost capacitor Cboost of the present application. The third electrode plate of the boost capacitor Cboost can be the part of the first extension section 321 that overlaps with the second control signal line Pscan1, and the fourth electrode plate of the boost capacitor Cboost can be the part of the second control signal line Pscan1 that overlaps with the first extension section 321.

[0120] Please refer to Figures 14 to 17 , the first source-drain layer 133 further includes a seventh electrical connection section 317 disposed between the second reset signal line Vi2 and the third control signal line Nscan2. The seventh electrical connection section 317 extends along the second direction Y and toward the side away from the second reset signal line Vi2; the seventh electrical connection section 317 and the second extension section 322 are overlapped, which is equivalent to forming a capacitor between the first reset signal line Vi1 and the second reset signal line Vi2, ensuring the voltage stability on the first reset signal line Vi1 and the second reset signal line Vi2.

[0121] In this embodiment, both the fifth electrical connection section 315 and the first extension section 321 are conductors in the area where the third node of the present application is located, that is, the potentials on the fifth electrical connection section 315 and the first extension section 321 are the potential of the third node Q; at the same time, the second control signal line Pscan1 and the first extension section 321 are overlapped in the first area M1, that is, the first extension section 321 of the present application is in the second active layer 129, and the second control signal line Pscan1 is in the first source-drain layer 133. Part of the conductors in the area where the third node Q is located are replaced from the original third gate layer 131 to the second active layer 129 of the present application, avoiding the technical problem of cracks in the upper insulating layer and at the same time avoiding the technical problem of short-circuit between the horizontally arranged second control signal line Pscan1 and the lower conductors in the first area M1.

[0122] Meanwhile, the first control signal line Nscan1 and the compensation active part T3A overlap and are arranged within the second region M2, the second control signal line Pscan1 and the first reset active part T4A overlap and are arranged within the third region M3, and the third control signal line Nscan2 and the first reset active part T4A overlap and are arranged within the fourth region M4; that is, the compensation active part T3A and the first reset active part T4A of the present application are both within the second active layer 129, and the first control signal line Nscan1 and the third control signal line Nscan2 are both within the first source-drain layer 133, so that the first control signal line Nscan1, the second control signal line Pscan1, and the third control signal line Nscan2 are changed from the gate layer with a larger impedance to the first source-drain layer 133 with a smaller impedance. For example, the original molybdenum metal is replaced with titanium-aluminum-titanium of the present application, reducing the impedance of these three control signal lines; secondly, due to the risk of short circuit caused by the overlap between the first source-drain layer 133 and the third gate layer 131, the wires within the region where the third node Q is located are replaced from the third gate layer 131 with the second active layer 129 in the present application, avoiding short circuit between the wires within the region where the third node Q is located and the first source-drain layer 133.

[0123] Please refer to Figure 18 , the second source-drain layer 135 includes a first data signal line Data1, a second data signal line Data2, and a first high-potential line VDD1. The second data signal line Data2, the first data signal line Data1, and the first high-potential line VDD1 are arranged along the first direction X and extend along the second direction Y. The first data signal line Data1 is arranged between the second data signal line Data2 and the first high-potential line VDD1.

[0124] Please refer to Figures 18 to 20 , the first high-potential line VDD1 includes a first sub-board 341, a second sub-board 342, a third sub-board 343, a fourth sub-board 344, and a fifth sub-board 345. The third sub-board 343, the first sub-board 341, the fourth sub-board 344, the second sub-board 342, and the fifth sub-board 345 are arranged along the second direction Y. The first sub-board 341 is arranged between the third sub-board 343 and the fourth sub-board 344, and the second sub-board 342 is arranged between the fourth sub-board 344 and the fifth sub-board 345; in the first direction X, the width of the first sub-board 341 is smaller than the width of the second sub-board 342, the width of the first sub-board 341 may be greater than the width of the fourth sub-board 344, and the width of the fourth sub-board 344 may be greater than or equal to the widths of the third sub-board 343 and the fifth sub-board 345.

[0125] In this embodiment, since the potential of the driving gate T1G is the potential of the third node Q, and the change in the potential of the third node Q directly affects the working current of the light-emitting device 211b, the present application needs to ensure the stability of the potential of the third node Q; the present application can make the positive projection of the driving gate T1G on the first high-potential line VDD1 located within the first sub-board 341, that is, it is equivalent to using the first sub-board 341 as a shielding layer to maintain the stability of the potential of the third node Q. Therefore, the present application needs to increase the lateral width of the first sub-board 341 so that the first sub-board 341 completely covers the driving gate T1G, and the first electrode plate Cst1 of the storage capacitor Cst is reused as the driving gate T1G, that is, the positive projection of the first electrode plate Cst1 on the first high-potential line VDD1 can be located within the first sub-board 341. Therefore, the width of the first sub-board 341 of the present application can be greater than the widths of the third sub-board 343, the fourth sub-board 344, and the fifth sub-board 345.

[0126] In this embodiment, both the fifth electrical connection segment 315 and the first extension segment 321 are electrically connected to the driving gate T1G. Therefore, the change in the potential on the fifth electrical connection segment 315 and the first extension segment 321 will also affect the potential of the driving gate T1G. Therefore, the present application can increase the width of the fourth sub-board 344 to completely cover the fifth electrical connection segment 315 and the first extension segment 321. Therefore, the lateral width of the fourth sub-board 344 of the present application can be greater than the lateral widths of the third sub-board 343 and the fifth sub-board 345.

[0127] Please refer to Figure 18 and Figure 19 , the positive projection of the compensation gate T3G on the first high-potential line VDD1 is located within the second sub-board 342. Part of the first high-potential line VDD1 overlaps with the compensation gate T3G and part of the first control signal line Nscan1. The two can form a capacitor, improving the anti-coupling ability of the first control signal line Nscan1, thereby improving the stability of the control signal transmitted by the first control signal line Nscan1, avoiding the abnormal turn-on of the compensation transistor T3, and ensuring the stability of the potential of the gate of the driving transistor T1.

[0128] Please refer to Figures 18 to 20 , the first source-drain layer 133 of the first sub-pixel unit 211c may include an eighth electrical connection segment 318a disposed between the first control signal line Nscan1 and the second control signal line Pscan1. One end of the eighth electrical connection segment 318a is electrically connected to the second end of the switching active part T2A, and the other end of the eighth electrical connection segment 318a is electrically connected to the first data signal line Data1. The first data signal line Data1 transmits the data signal to the switching transistor T2 through the eighth electrical connection segment 318a.

[0129] In this embodiment, Figures 18 to 20The eighth electrical connection segment 318a in [reference] can be the first electrical connection member 610 of the first sub-pixel unit 211c of the present application. That is, the switching active part T2A of the first sub-pixel unit 211c is electrically connected to the first data signal line Data1 through the first electrical connection member 610.

[0130] Please refer to Figure 21 and Figure 22 , the first source-drain layer 133 of the second sub-pixel unit 211d can include an eighth electrical connection segment 318b disposed between the first control signal line Nscan1 and the second control signal line Pscan1. One end of the eighth electrical connection segment 318b is electrically connected to the second end of the switching active part T2A, and the other end of the eighth electrical connection segment 318b is electrically connected to the second data signal line Data2. The second data signal line Data2 transmits the data signal to the switching transistor T2 through the eighth electrical connection segment 318b.

[0131] In this embodiment, Figure 21 and Figure 22 the eighth electrical connection segment 318b in [reference] can be the second electrical connection member 620 of the second sub-pixel unit 211d of the present application. That is, the switching active part T2A of the second sub-pixel unit 211d is electrically connected to the second data signal line Data2 through the second electrical connection member 620.

[0132] In Figure 2 's structure, the present application lists 6 sub-pixel units 211. The sub-pixel units 211 located in the first row are all connected to the first data signal line Data1, and the sub-pixel units 211 located in the second row are all connected to the second data signal line Data2. The sub-pixel units 211 listed in the present application Figure 19 and Figure 20 are the first sub-pixel unit 211c in the first row in [[reference]], and the sub-pixel units 211 listed in the present application Figure 2 are the second sub-pixel unit 211d in the second row in [[reference]]. Figure 21 and Figure 22 are the second sub-pixel unit 211d in the second row in [[reference]]. Figure 2 In [[reference]] and [[reference]], the switching active part T2A of the first sub-pixel unit 211c and the switching active part T2A of the second sub-pixel unit 211d both extend between the first data signal line Data1 and the second data signal line Data2, and partially overlap with one of the first data signal line Data1 or the second data signal line Data2.

[0133] In Figure 19 and Figure 22 and [[reference]], the switching active part T2A of the first sub-pixel unit 211c and the switching active part T2A of the second sub-pixel unit 211d both overlap with the first data signal line Data1. Figure 19 and Figure 22 In [[reference]] and [[reference]], the switching active part T2A of the first sub-pixel unit 211c and the switching active part T2A of the second sub-pixel unit 211d both overlap with the first data signal line Data1.

[0134] In Figure 19 and Figure 22 Since the patterns of the switching active parts T2A of the first sub-pixel unit 211c and the second sub-pixel unit 211d are the same, the switching active part T2A of the first sub-pixel unit 211c has a first connection end electrically connected to the first electrical connection member 610, and the switching active part T2A of the second sub-pixel unit 211d has a second connection end electrically connected to the second electrical connection member 620. The center connection line of the first connection end and the second connection end is parallel to the second direction Y. At the same time, both the first connection end and the second connection end are arranged between the first data signal line Data1 and the second data signal line Data2.

[0135] In Figure 19 and Figure 22 The first electrical connection member 610 extends toward the side close to the repeating unit 500, and the second electrical connection member 620 extends toward the side away from the repeating unit 500. The first electrical connection member 610 and the first data signal line Data1 partially overlap so that the first electrical connection member 610 and the first data signal line Data1 are electrically connected. The first electrical connection member 610 and the second data signal line Data2 do not overlap. The second electrical connection member 620 and the second data signal line Data2 partially overlap, and the second electrical connection member 620 and the first data signal line Data1 do not overlap, so that the second electrical connection member 620 and the second data signal line Data2 are electrically connected.

[0136] Please refer to Figure 19 , the first data signal line Data1 includes a plurality of first longitudinal segments Data1a and a first avoidance segment Data1b provided between two adjacent first longitudinal segments Data1a. The distance between the first avoidance segment Data1b and the repeating unit 500 is smaller than the distance between the first longitudinal segment Data1a and the repeating unit 500. The switching active part T2A of the first sub-pixel unit 211c is electrically connected to the first avoidance segment Data1b through the first electrical connection member 610.

[0137] Please refer to Figure 22 , the second data signal line Data2 includes a plurality of second longitudinal segments Data2a and a second avoidance segment Data2b provided between two adjacent second longitudinal segments Data2a. The first avoidance segment Data1b and the second avoidance segment Data2b are opposite and parallel to each other. The distance between the second avoidance segment Data2b and the repeating unit 500 is greater than the distance between the second longitudinal segment Data2a and the repeating unit 500. The switching active part T2A of the second sub-pixel unit 211d is electrically connected to the second avoidance segment Data2b through the second electrical connection member 620.

[0138] The settings of the first avoidance segment Data1b and the second avoidance segment Data2b in this application are mainly that the first avoidance segment Data1b needs to pass through a via hole and be electrically connected to the first electrical connection member 610, and the second avoidance segment Data2b needs to pass through the corresponding via hole and be electrically connected to the second electrical connection member 620. In order to avoid interference between the via hole and adjacent data signal lines, avoidance segments are respectively arranged at the positions of the via holes.

[0139] Please refer to Figure 18 , there is a central axis O1 between the first data signal line Data1 and the second data signal line Data2, and the first avoidance segment Data1b and the second avoidance segment Data2b are symmetrically arranged with the central axis O1 as the axis.

[0140] Please refer to Figure 23 , there is a central axis O1 between the first data signal line Data1 and the second data signal line Data2, and the distance between the first avoidance segment Data1b and the central axis O1 is less than the distance between the second avoidance segment Data2b and the central axis O1; since the distance between the first avoidance segment Data1b and the adjacent first high potential line VDD1 is smaller than the distance between the second avoidance segment Data2b and the adjacent first high potential line VDD1, this application can reduce the distance between the first avoidance segment Data1b and the central axis O1, so that the distance between the first avoidance segment Data1b and the adjacent first high potential line VDD1 is equal to the distance between the second avoidance segment Data2b and the adjacent first high potential line VDD1, avoiding capacitance differences between the data signal line and the first high potential line VDD1, which may cause differences in the data signals transmitted by the first data signal line Data1 and the second data signal line Data2.

[0141] Please refer to Figure 24 and Figure 26 , the third source-drain layer 137 may include a third high potential line VDD3 extending along the second direction Y, the third high potential line VDD3 is electrically connected to the second high potential line VDD2, and the setting of the third high potential line VDD3 is mainly used to reduce the impedance of the wire transmitting the constant voltage high level.

[0142] It should be noted that in Figures 18 to 24In this case, the first high potential line VDD1 of the present application can be electrically connected to the second high potential line VDD2. Secondly, the second high potential line VDD2 is electrically connected to the second electrode plate Cst2 of the storage capacitor Cst, and the second electrode plates Cst2 in the same row are electrically connected through the first electrical connection segment 311. Therefore, the wire for transmitting the constant voltage high level in the present application has four metal layers, namely, the second electrode plate Cst2 and the first electrical connection segment 311 located in the second gate layer 127, the second high potential line VDD2 located in the first source-drain layer 133, the first high potential line VDD1 located in the second source-drain layer 135, and the third high potential line VDD3 located in the third source-drain layer 137. The second electrode plate Cst2, the first electrical connection segment 311, and the second high potential line VDD2 all extend along the first direction X, and the first high potential line VDD1 and the third high potential line VDD3 both extend along the second direction Y. Therefore, the present application uses four metal layers to transmit the constant voltage high level to form a metal mesh with horizontal and vertical intersections in a mesh shape to reduce the impedance of the wire, thereby reducing the loss of the constant voltage high level on the transmitted wire.

[0143] Please refer to Figure 27 , the third source-drain layer 137 of the present application includes a plurality of potential line units 137a, and each potential line unit 137a corresponds to three adjacent sub-pixel units 211 arranged along the first direction X, such as the red sub-pixel unit 212, the green sub-pixel unit 213, and the blue sub-pixel unit 214. Taking the three sub-pixel units 211 as the red sub-pixel unit 212, the green sub-pixel unit 213, and the blue sub-pixel unit 214 as an example, each potential line unit 137a may include the first third high potential line VDD3 corresponding to the red sub-pixel unit 212, the third third high potential line VDD3 corresponding to the blue sub-pixel unit 214, the second high potential line corresponding to the green sub-pixel unit 213, and the fourth reset signal line Vi4. The patterns of the first third high potential line VDD3 and the third third high potential line VDD3 may be the same, the patterns of the second third high potential line VDD3 and the third third high potential line VDD3 are different, and the lateral width of the second third high potential line VDD3 is smaller than the lateral width of the third third high potential line VDD3.

[0144] It should be noted that the sub-pixel colors corresponding to the above three high potential lines can be randomly arranged, not limited to the above embodiments.

[0145] Please refer to Figure 27, each potential line unit 137a is provided with a longitudinal reset signal line and three transverse reset signal lines. That is, each potential line unit 137a may further include a fourth reset signal line Vi4 located in the green sub-pixel unit 213. The fourth reset signal line Vi4 in each potential line unit 137a is electrically connected to one of the first reset signal line Vi1, the second reset signal line Vi2, and the third reset signal line Vi3, and the reset signal lines connected by the fourth reset signal lines Vi4 in three adjacent potential line units 137a are different.

[0146] In order to reduce the impedance of the reset signal line in this application, the longitudinally arranged reset signal line can be electrically connected to one of the three transverse reset signal lines; for example Figure 28 is provided with 3 rows of potential line units 137a. Each row of potential line units 137a includes 3 potential line units 137a. Each potential line unit 137a is provided with 1 fourth reset signal line Vi4. The fourth reset signal line Vi4 in the first potential line unit 137a can be electrically connected to the first reset signal line Vi1 in each row. The fourth reset signal line Vi4 in the second potential line unit 137a can be electrically connected to the second reset signal line Vi2 in each row. The fourth reset signal line Vi4 in the third potential line unit 137a can be electrically connected to the third reset signal line Vi3 in each row. Thus, each horizontally arranged reset signal line and the fourth reset signal line Vi4 are electrically connected to form a criss-cross metal mesh, reducing the impedance of the reset signal line.

[0147] It should be noted that Figure 27 the first sub-pixel unit 212, the second sub-pixel unit 213, and the third sub-pixel unit 214 in only represent the positions of the pixel driving circuits 211a of the corresponding sub-pixel units 211, while the position of the anode in the sub-pixel unit 211 may not be in the corresponding area; for example, please refer to Figure 29 , the pixel driving circuit 211a in the first sub-pixel unit 212 of this application is electrically connected to the first anode 211b1, and the pixel driving circuit 211a in the second sub-pixel unit 213 is electrically connected to the second anode 211b2. The first anode 211b1 and the second anode 211b2 are arranged along the second direction Y, and both the first anode 211b1 and the second anode 211b2 straddle the first sub-pixel unit 212 and the second sub-pixel unit 213.

[0148] It should be noted that in Figure 29In the above, the third source-drain layer 137 may further include a ninth electrical connection segment 319 and a tenth electrical connection segment 320. The ninth electrical connection segment 319 is disposed between the fourth reset signal line Vi4 and the second third high-potential line VDD3. The tenth electrical connection segment 320 is disposed on one side of the first third high-potential line VDD3 and the third third high-potential line VDD3. The tenth electrical connection segment 320 corresponds to the fourth electrical connection segment 314. The second source-drain layer 135 may further include an eleventh electrical connection segment 321. The second anode 211b2 may be electrically connected through the ninth electrical connection segment 319, the eleventh electrical connection segment 321, the fourth electrical connection segment 314 of the second sub-pixel unit 213, and the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the second sub-pixel unit 213. Similarly, the first anode 211b1 may be electrically connected through the tenth electrical connection segment 320, the eleventh electrical connection segment 321, the fourth electrical connection segment 314 of the first sub-pixel unit 212, and the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the first sub-pixel unit 212. Similarly, the connection manner of the anode in the third sub-pixel unit 314 is the same as that of the first anode 211b1.

[0149] The present application further provides a display device, and the display device includes the above-mentioned display panel. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component having a display function.

[0150] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0151] The above has introduced in detail a display panel and a display device provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, Comprising: Multiple repeating units, including at least one first sub-pixel unit and at least one second sub-pixel unit. Both the first sub-pixel unit and the second sub-pixel unit include a pixel driving circuit, and the pixel driving circuit includes a switching transistor having a switching active portion. A first data signal line and a second data signal line, both disposed on the same side of the repeating unit. The switching active portion of the first sub-pixel unit is electrically connected to the first data signal line, and the switching active portion of the second sub-pixel unit is electrically connected to the second data signal line. Wherein, the switching active portion of the first sub-pixel unit has a first connection end electrically connected to the first data signal line, and the switching active portion of the second sub-pixel unit has a second connection end electrically connected to the second data signal line. Both the first connection end and the second connection end are disposed between the first data signal line and the second data signal line.

2. The display panel according to claim 1, wherein, The display panel further includes a first electrical connection member and a second electrical connection member disposed on the same side of the repeating unit. Wherein, the switching active portion of the first sub-pixel unit is electrically connected to the first data signal line through the first electrical connection member, and the switching active portion of the second sub-pixel unit is electrically connected to the second data signal line through the second electrical connection member.

3. The display panel according to claim 2, wherein The patterns of the switching active portions of the first sub-pixel unit and the second sub-pixel unit are the same. Wherein, the switching active portions of the first sub-pixel unit and the second sub-pixel unit both partially overlap with one of the first data signal line or the second data signal line.

4. The display panel according to claim 3, characterized in that, The first data signal line is disposed between the repeating unit and the second data signal line. Wherein, the first electrical connection member extends towards the side close to the repeating unit, the second electrical connection member extends towards the side away from the repeating unit, the first electrical connection member and the first data signal line partially overlap, and the first electrical connection member and the second data signal line do not overlap.

5. The display panel according to claim 4, wherein The second electrical connection member and the second data signal line partially overlap, and the second electrical connection member and the first data signal line do not overlap.

6. The display panel according to claim 5, wherein The first data signal line includes a plurality of first longitudinal segments and a first avoidance segment disposed between two adjacent first longitudinal segments. The second data signal line includes a plurality of second longitudinal segments and a second avoidance segment disposed between two adjacent second longitudinal segments. The first avoidance segment and the second avoidance segment are opposite and parallel to each other. Wherein, the distance between the first avoidance segment and the repeating unit is less than the distance between the first longitudinal segment and the repeating unit, the distance between the second avoidance segment and the repeating unit is greater than the distance between the second longitudinal segment and the repeating unit. The switching active portion of the first sub-pixel unit is electrically connected to the first avoidance segment through the first electrical connection member, and the switching active portion of the second sub-pixel unit is electrically connected to the second avoidance segment through the second electrical connection member.

7. The display panel according to claim 6, characterized in that A central axis is provided between the first data signal line and the second data signal line, and the first avoidance section and the second avoidance section are symmetrically arranged with the central axis as the axis.

8. The display panel according to claim 2, wherein, The pixel driving circuit further includes a driving transistor and a compensating transistor; A first electrode of the switching transistor is connected to one of the first data signal line and the second data signal line, and a second electrode of the switching transistor is connected to a first node; A first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to a second node, and a driving gate of the driving transistor is connected to a third node; A first electrode of the compensating transistor is connected to the third node, and a second electrode of the compensating transistor is connected to the second node; Wherein, a compensating gate of the compensating transistor is connected to a first control signal line, a switching gate of the switching transistor is connected to a second control signal line, and both the first electrical connection member and the second electrical connection member are disposed between the first control signal line and the second control signal line in the corresponding pixel driving circuit.

9. The display panel according to any one of claims 1 to 8, characterized in that, A central connection line between the first connection end and the second connection end is parallel to an extending direction of the first data signal line or the second data signal line.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 9.

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