Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to reduce the production cycle of the display panel. The display panel comprises a substrate and a driving circuit layer. The driving circuit layer comprises a plurality of pixel driving circuits, a plurality of data write-in signal lines and a plurality of data leads. The data lead comprises a first lead section located on the first wiring metal layer and a second lead section located on the second wiring metal layer. And the first lead section is electrically connected with one data write-in signal line located in the edge area and one end of the second lead section. The second lead segment extends from the middle area to the binding area. The semiconductor layer includes a first conductive portion including a second pole of the first reset transistor. The second gate metal layer includes a first shielding portion. The orthographic projection of the first shielding part on the substrate, the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first lead section on the substrate are overlapped. The display panel is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display devices have become one of the most competitive and promising display devices at present because of a series of advantages such as self-luminescence, fast response speed, high brightness, full viewing angle, and flexible display. Summary of the Invention

[0003] An object of an embodiment of the present disclosure is to provide a display panel and a display device, which are used to reduce the production cycle and cost of the display panel and improve the production efficiency of the display panel.

[0004] To achieve the above object, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a display panel is provided. The display panel includes a display area and a bonding area, and the bonding area is located on one side of the display area. The display area includes a middle area and two edge areas, and along a first direction, the middle area is located between the two edge areas. The display panel includes a substrate and a driving circuit layer, and the driving circuit layer is located on one side of the substrate. The driving circuit layer includes: a plurality of pixel driving circuits, a plurality of data writing signal lines, and a plurality of data leads. The plurality of pixel driving circuits are arranged in multiple rows and columns in the display area. The pixel driving circuit includes a driving transistor and a first reset transistor. The control electrode of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node. A first reset transistor, the control electrode of the first reset transistor is electrically connected to a first reset signal line, the first electrode of the first reset transistor is electrically connected to a first initialization signal line, and the second electrode of the first reset transistor is electrically connected to the first node. The plurality of data writing signal lines are located in the display area, and the plurality of data writing signal lines are arranged along the first direction and extend along a second direction, and the second direction intersects with the first direction. One data writing signal line is connected to one column of the pixel driving circuits. A plurality of data leads, the data leads include a first lead segment and a second lead segment, one end of the first lead segment is electrically connected to a data writing signal line located in the edge area, and the other end of the first lead segment is electrically connected to one end of the second lead segment. The first lead segment extends along the first direction, the second lead segment extends along the second direction, and the second lead segment extends from the middle area to the bonding area. Along the direction away from the substrate, the driving circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer, and a second routing metal layer. The semiconductor layer includes a first conductive portion, and the first conductive portion includes the second electrode of the first reset transistor. The second gate metal layer includes a first shielding portion, and the first shielding portion is configured to have a constant voltage signal. The first routing metal layer includes the first lead segment. The second routing metal layer includes the data writing signal lines and the second lead segment. Wherein, the orthographic projection of the first shielding portion on the substrate, the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the first lead segment on the substrate have an overlap.

[0006] In the above display panel, the data writing signal lines and data leads are distributed within the spaces of the first wiring metal layer and the second wiring metal layer. Compared with a display panel provided with a third wiring metal layer, two lithography processes can be reduced. Therefore, the cost of the display panel can be reduced, the production cycle of the display panel can be shortened, and the production efficiency of the display panel can be improved. In addition, the first shielding portion with a constant voltage signal can be used to isolate the first conductive portion and the first lead segment, improving the voltage jump at the position of the first conductive portion caused by the data writing signal jump in the first lead segment, indirectly improving the stability of the control electrode of the driving transistor, which is beneficial to optimizing the brightness uniformity of the display panel.

[0007] In some embodiments, the second gate metal layer further includes the first initialization signal line, and the first reset signal line is connected to the first shielding portion.

[0008] In some embodiments, the first initialization signal line includes a first auxiliary portion protruding toward the first reset transistor. The orthographic projection of the first auxiliary portion on the substrate, the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the first lead segment on the substrate overlap. The first auxiliary portion is multiplexed as the first shielding portion.

[0009] In some embodiments, the pixel driving circuit further includes a compensation transistor. The control electrode of the compensation transistor is electrically connected to the second scanning signal line, the first pole of the compensation transistor is electrically connected to the third node, and the second pole of the compensation transistor is electrically connected to the first node. The compensation transistor is a double-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode. The semiconductor layer further includes: a first channel portion of the compensation transistor, a second channel portion of the compensation transistor, and a second conductive portion. One end of the second conductive portion is connected to the first channel portion, and the other end of the second conductive portion is connected to the second channel portion. The first initialization signal line further includes a second auxiliary portion protruding toward the driving transistor. The orthographic projection of the second auxiliary portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate.

[0010] In some embodiments, the orthographic projection of the second conductive portion on the substrate is located within the boundary of the orthographic projection of the second auxiliary portion on the substrate.

[0011] In some embodiments, the second conductive portion includes a first sub-portion, a second sub-portion, and a third sub-portion, and the first sub-portion, the second sub-portion, and the third sub-portion intersect at the same point. Among them, the first sub-portion is electrically connected to the first channel portion, the second sub-portion is electrically connected to the second channel portion, and the third sub-portion is located on a side of the second sub-portion away from the second channel portion.

[0012] In some embodiments, the pixel driving circuit further includes a data writing transistor and a second reset transistor. A control electrode of the data writing transistor is connected to a first scanning signal line, a first electrode of the data writing transistor is electrically connected to the data writing signal line, and a second electrode of the data writing transistor is electrically connected to the second node. A control electrode of the second reset transistor is electrically connected to the first scanning signal line, a first electrode of the second reset transistor is electrically connected to a second initialization signal line, and a second electrode of the second reset transistor is electrically connected to a fourth node. Along the first direction, the control electrode of the data writing transistor and the control electrode of the second reset transistor overlap.

[0013] In some embodiments, the pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. A control electrode of the first light-emitting control transistor is electrically connected to a first enable signal line, a first electrode of the first light-emitting control transistor is electrically connected to a first power supply signal line, and a second electrode of the first light-emitting control transistor is electrically connected to the second node. A control electrode of the second light-emitting control transistor is electrically connected to a second enable signal line, a first electrode of the second light-emitting control transistor is electrically connected to the third node, and a second electrode of the second light-emitting control transistor is electrically connected to the fourth node.

[0014] In some embodiments, the pixel driving circuit further includes a storage capacitor and a first capacitor. A first electrode plate of the storage capacitor is electrically connected to the first node, and a second electrode plate of the storage capacitor is electrically connected to the first power supply signal line. A first electrode plate of the first capacitor is electrically connected to the second node, and a first electrode plate of the first capacitor is electrically connected to the first power supply signal line.

[0015] In some embodiments, the pixel driving circuit includes a data writing transistor and a first light-emitting control transistor. The semiconductor layer includes a third conductive portion, and the third conductive portion includes a first pole of the driving transistor, a second pole of the first light-emitting control transistor, and a second pole of the data writing transistor. The second gate metal layer further includes a fourth conductive portion. One end of the fourth conductive portion is electrically connected to the second electrode plate of the storage capacitor, and the other end of the fourth conductive portion is electrically connected to the first pole of the first light-emitting control transistor. A positive projection of the fourth conductive portion on the substrate substantially overlaps with a positive projection of the third conductive portion on the substrate. Wherein, the third conductive portion is reused as the first electrode plate of the first capacitor, and the fourth conductive portion is reused as the second electrode plate of the first capacitor.

[0016] In some embodiments, along the second direction, a side of the third conductive portion facing away from the channel portion of the first light-emitting control transistor protrudes from the channel portion of the driving transistor.

[0017] In some embodiments, along the first direction, two adjacent pixel driving circuits are symmetric.

[0018] In some embodiments, along the first direction, the first pole of the driving transistor of the nth pixel driving circuit is adjacent to the first pole of the driving transistor of the (n + 1)th pixel driving circuit. Wherein, n is a positive integer.

[0019] In some embodiments, the second electrode plate of the storage capacitor of the nth pixel driving circuit is electrically connected to the second electrode plate of the storage capacitor of the (n + 1)th sub-pixel pixel driving circuit. Wherein, n is a positive integer.

[0020] In some embodiments, along the first direction, the second reset transistor in the (n + 1)th pixel driving circuit is adjacent to the second reset transistor in the (n + 2)th pixel driving circuit, and the first pole of the second reset transistor in the (n + 1)th pixel driving circuit is reused as the first pole of the second reset transistor in the (n + 2)th pixel driving circuit.

[0021] In some embodiments, the first routing metal layer further includes a plurality of first virtual lead segments, the first virtual lead segments correspond to the first lead segments one by one, and along the first direction, the first lead segments and the first virtual lead segments are arranged at intervals.

[0022] In some embodiments, the second routing metal layer further includes a plurality of second virtual lead segments, the second virtual lead segments correspond to the second lead segments one by one, and along the first direction, the second lead segments and the second virtual lead segments are arranged at intervals.

[0023] In some embodiments, the display panel further includes a bottom shielding layer located between the substrate and the pixel driving circuit, and a positive projection of the bottom shielding layer on the substrate covers a positive projection of the driving transistor on the substrate.

[0024] In some embodiments, the display panel further includes a light-emitting device layer located on a side of the driving circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the pixel driving circuit.

[0025] On the other hand, a display device is provided. The display device includes: the display panel according to any one of the above embodiments.

[0026] The above display device has the same structure and beneficial technical effects as the display panel provided in the above some embodiments, and will not be described in detail herein. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required to be used in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0028] Figure 1 Structural diagram of a display device according to some embodiments;

[0029] Figure 2 Structural diagram of a display panel according to some embodiments;

[0030] Figure 3 Cross-sectional view of a display panel according to some embodiments;

[0031] Figure 4 Circuit diagram of a pixel driving circuit according to some embodiments;

[0032] Figure 5 Circuit diagram of a pixel driving circuit according to some other embodiments;

[0033] Figure 6 Timing diagram of a pixel driving circuit according to some embodiments;

[0034] Figure 7 Circuit diagram of a pixel driving circuit according to some other embodiments;

[0035] Figure 8 Membrane layer structure diagram of multiple pixel driving circuits according to some embodiments;

[0036] Figure 9 Membrane layer structure diagram of multiple pixel driving circuits according to some other embodiments;

[0037] Figure 10 For Figure 9 Structure diagram of the semiconductor layer in;

[0038] Figure 11 Structure diagram of the semiconductor layer according to some embodiments;

[0039] Figure 12 For Figure 9 Structure diagram of the first gate metal layer in;

[0040] Figure 13 For Figure 9 Structure diagram of the second gate metal layer in;

[0041] Figure 14 For Figure 9 Structure diagram of the semiconductor layer, the first gate metal layer and the second gate metal layer in;

[0042] Figure 15 For Figure 9 Structure diagram of the first routing metal layer in;

[0043] Figure 16 For Figure 9 Structure diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first routing metal layer in;

[0044] Figure 17 For Figure 9 Structure diagram of the second routing metal layer in;

[0045] Figure 18 Membrane layer structure diagram of multiple pixel driving circuits according to some other embodiments;

[0046] Figure 19 For Figure 18 Structure diagram of the bottom shielding layer in. Detailed implementation manners

[0047] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, terms such as "some embodiments", "example", or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described above may be included in any one or more embodiments or examples in any suitable manner.

[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0050] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content herein.

[0051] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0052] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0053] As used herein, depending on the context, the term "if" is optionally interpreted to mean "when" or "at the time of". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" is optionally interpreted to mean "when it is determined that..." or "in response to determining...".

[0054] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude a device that is suitable for or configured to perform additional tasks or steps.

[0055] In addition, the use of "based on" implies openness and inclusivity because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can, in practice, be based on additional conditions or values beyond those stated.

[0056] As used herein, "about", "substantially", or "approximate" includes the stated value and an average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel", "perpendicular", "equal" include the stated situation and situations similar to the stated situation, where the range of the similar situations is within an acceptable deviation range, and the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal values is less than or equal to 5% of either one.

[0058] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] In the circuit provided by the embodiments of the present disclosure, the first node, the second node, the third node, and the fourth node do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0061] Figure 1 FIG. is a structural diagram of a display device according to some embodiments. Please refer to Figure 1 As shown, some embodiments of the present disclosure provide a display device 200, and the display device 200 includes a display panel 100.

[0062] Exemplarily, the display device 200 further includes a frame, and other electronic accessories, etc.

[0063] Exemplarily, the display device 200 can be an electroluminescent display device or a photoluminescent display device. In the case where the display device is an electroluminescent display device, the electroluminescent display device can be an Organic Light Emitting Diode (OLED for short) or a Quantum Dot Light Emitting Diodes (QLED for short). In the case where the display device is a photoluminescent display device, the photoluminescent display device can be a quantum dot photoluminescent display device.

[0064] Exemplarily, the above-mentioned display device 200 can be any display device that displays whether it is moving (e.g., video) or stationary (e.g., still image), and whether it is text or an image. More specifically, it is expected that the display device of the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0065] Figure 2 FIG. is a structural diagram of a display panel according to some embodiments.

[0066] As Figure 2As shown, some embodiments of the present disclosure provide a display panel 100, and the display panel 100 includes a display area (full English name: Active Area, abbreviated as AA area; also referred to as the effective display area) AA.

[0067] The display panel 100 may include a plurality of sub-pixels P, and the plurality of sub-pixels P are arranged in the display area AA, wherein the plurality of sub-pixels may be arranged in an array.

[0068] The sub-pixel P is the smallest unit for the display panel 100 to display an image. The plurality of sub-pixels P may include red sub-pixels, blue sub-pixels, and green sub-pixels. By adjusting the brightness (gray scale) of different color sub-pixels, various colors can be displayed through color combination and superposition, thereby realizing the full-color display of the display panel 100.

[0069] In some other examples, the display panel 100 may further include white sub-pixels.

[0070] In some examples, the display area AA includes a middle area AA1 and two edge areas AA2. Along the first direction X, the middle area AA1 is located between the two edge areas AA2.

[0071] Exemplarily, along the first direction X, the widths of the two edge areas AA2 of the display area AA are the same or approximately the same.

[0072] Figure 3 It is a cross-sectional view of a display panel according to some embodiments.

[0073] As Figure 3 shown, each sub-pixel P may include a light-emitting device O and a pixel driving circuit Q for driving the light-emitting device O.

[0074] In addition, the display panel 100 may further include a variety of signal lines. The above-mentioned plurality of signal lines may be electrically connected to the pixel driving circuit Q to provide the signals required by the pixel driving circuit Q. Among them, the functions and layouts of the plurality of signal lines electrically connected to the pixel driving circuit Q will be described in detail below.

[0075] Combined with Figure 2 and Figure 3 shown, the display panel 100 includes a substrate 10, a driving circuit layer 20, and a light-emitting device layer 30. Among them, the driving circuit layer 20 is located between the substrate 10 and the light-emitting device layer 30.

[0076] In some examples, the substrate 10 may be a flexible substrate. Exemplarily, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI for short), polycarbonate (PC for short), or polyvinyl chloride (PVC for short).

[0077] In other examples, the substrate 10 may be a rigid substrate. Exemplarily, the rigid substrate may be a glass substrate or a PMMA (polymethyl methacrylate) substrate, etc.

[0078] In some examples, the light-emitting device layer 30 includes a plurality of light-emitting devices O, and the plurality of light-emitting devices O are electrically connected to a plurality of pixel driving circuits Q.

[0079] In some examples, the above-mentioned plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be electrically connected in one-to-one correspondence. In other examples, one pixel driving circuit Q may be electrically connected to a plurality of light-emitting devices O, or a plurality of pixel driving circuits Q may be electrically connected to one light-emitting device O.

[0080] Below, taking one pixel driving circuit Q being electrically connected to one light-emitting device O as an example, the structure of the display panel 100 will be schematically described.

[0081] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer that are sequentially stacked. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer. Exemplarily, the above-mentioned light-emitting device O may be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the types of light-emitting devices, that is, the light-emitting device O may be any other light-emitting device (such as a light-emitting device that emits light through discharge), as long as they can emit light so that the display panel 100 can display an image.

[0082] The driving circuit layer 20 further includes a plurality of pixel driving circuits Q, and the plurality of pixel driving circuits Q are arranged in multiple rows and multiple columns in the display area AA. Among them, the pixel driving circuits Q arranged in a row along the first direction X are called a pixel driving circuit row, and the pixel driving circuits Q arranged in a row along the second direction Y are called a pixel driving circuit column.

[0083] Among them, the first direction X and the second direction Y intersect.

[0084] In some examples, the first direction X and the second direction Y may be approximately perpendicular to each other. At this time, the angle between the first direction X and the second direction Y is approximately equal to 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0085] The pixel driving circuit Q is distributed in the film layer of the driving circuit layer 20 described above. The specific distribution of the pixel driving circuit Q in the driving circuit layer 20 will be described in detail below.

[0086] For the convenience of description, in the present disclosure, the above-mentioned multiple pixel driving circuits Q are described by taking the example of being arranged in a matrix form.

[0087] In some examples, the structure of the pixel driving circuit Q includes various types and can be selected and set according to actual needs. For example, the structure of the sub-pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C", or "8T1C", etc. Here, "T" represents a thin-film transistor, and the number in front of "T" represents the number of thin-film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following takes the sub-pixel driving circuit of "7T1C" as an example for introduction.

[0088] Figure 4 It is a circuit diagram of a pixel driving circuit according to some embodiments.

[0089] In some examples, as Figure 4 shown, the pixel driving circuit Q includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a storage capacitor Cst.

[0090] The gate g1 of the first reset transistor T1 is electrically connected to the first reset signal line R1, the first pole s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second pole d1 of the first reset transistor T1 is electrically connected to the first node N1. The first reset transistor T1 is configured to transmit the first initialization signal received at the first initialization signal line Vinit1 to the first node N1 under the control of the first reset signal received from the first reset signal line R1, and reset the first node N1.

[0091] The gate g2 of the compensation transistor T2 is electrically connected to the second scan signal line G2, the first pole s2 of the compensation transistor T2 is electrically connected to the first node N1, and the second pole d2 of the compensation transistor T2 is electrically connected to the third node N3.

[0092] The gate g3 of the driving transistor T3 is electrically connected to the first node N1, the first pole s3 of the driving transistor T3 is electrically connected to the second node N2, and the second pole d3 of the driving transistor T3 is electrically connected to the third node N3.

[0093] The gate g4 of the data writing transistor T4 is electrically connected to the first scan signal line G1, the first pole s4 of the data writing transistor T4 is electrically connected to the data writing signal line Data, and the second pole d4 of the data writing transistor T4 is electrically connected to the second node N2.

[0094] The gate g5 of the first light-emitting control transistor T5 is electrically connected to the first enable signal line EM1, the first pole s5 of the first light-emitting control transistor T5 is electrically connected to the first power supply signal line VDD, and the second pole d5 of the first light-emitting control transistor T5 is electrically connected to the second node N2.

[0095] The gate g6 of the second light-emitting control transistor T6 is electrically connected to the first enable signal line EM1, the first pole s6 of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second pole d6 of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. Among them, the fourth node in the pixel driving circuit Q can be the output terminal of the pixel driving circuit. That is, the fourth node N4 of the pixel driving circuit Q can be electrically connected to the light-emitting device O. Exemplarily, the fourth node N4 of the pixel driving circuit Q can be electrically connected to the anode of the light-emitting device O. In addition, the cathode of the light-emitting device O can be electrically connected to the second power supply signal line VSS. Among them, the voltage of the first power supply signal provided by the first power supply signal line VDD is higher than the voltage of the second power supply signal provided by the second power supply signal line VSS.

[0096] Among them, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are configured to: under the control of the first enable signal from the first enable signal line EM1, cooperate with the driving transistor T3 to transmit a driving signal to the light-emitting device O.

[0097] The gate g7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, the first pole s7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second pole d7 of the second reset transistor T7 is electrically connected to the fourth node N4. The second reset transistor T7 is configured to: under the control of the second reset signal received from the second reset signal line R2, transmit the second initialization signal received on the second initialization signal line V2 to the fourth node N4 to reset the fourth node N4. Among them, the fourth node N4 is electrically connected to the light-emitting device O, and resetting the fourth node N4 is equivalent to resetting the anode of the light-emitting device O with this signal, improving the stability of the light-emitting device O.

[0098] The first electrode Cst-1 of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode Cst-2 of the storage capacitor Cst is electrically connected to the first power supply signal line VDD.

[0099] In some examples, the compensation transistor T2 can be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 can be P-type transistors.

[0100] In some examples, the compensation transistor T2 can be an oxide transistor, and the oxide transistor can be an N-type transistor, while the other transistors can be LTPS (Low Temperature Poly Silicon) transistors, and the LTPS transistors can be P-type transistors.

[0101] Among them, the N-type transistor is turned on when a high-voltage signal is received at the gate, while the P-type transistor is turned on when a low-voltage signal is received at the gate. It should be noted that the above-mentioned "high-voltage signal" and "low-voltage signal" are common terms. Generally speaking, the turn-on condition of the N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. Since the threshold voltage of the N-type transistor is positive, the gate voltage signal that makes the N-type transistor turn on is called a high-voltage signal. The turn-on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, and the threshold voltage of the P-type transistor is negative, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. Then, the gate voltage signal that makes the P-type transistor turn on is called a low-voltage signal. Among them, the voltage of the "high-voltage signal" is greater than the voltage of the "low-voltage signal".

[0102] In some other examples, the above-mentioned multiple transistors can all be P-type transistors, and in some other examples, the above-mentioned multiple transistors can all be N-type transistors.

[0103] Among them, Figure 4 The pixel driving circuit Q shown takes the first reset transistor T1 and the compensation transistor T2 as N-type transistors, and the other transistors as P-type transistors as an example for illustration. Such a setting can help reduce the risk of leakage of the compensation transistor T2 and the first reset transistor T1, and is more conducive to ensuring the stability of the voltage of the first node N1, that is, ensuring the stability of the control electrode g1 of the driving transistor T3.

[0104] Figure 5 It is a circuit diagram of a pixel driving circuit according to some other embodiments.

[0105] In some embodiments, such as Figure 5As shown, the second scan signal line G2 for driving the pixel driving circuit Q of the nth row responds to the same signal terminal as the first reset signal line R1(n+m) of the pixel driving circuit Q of the (n+m)th row. In other words, the second scan signal line G2 for driving the pixel driving circuit Q of the nth row can be multiplexed as the first reset signal line R1(n+m) of the subsequent m rows of pixel driving circuits Q. Wherein, both n and m are natural numbers, and n > m. And Figure 5 illustrates with m = 7 as an example.

[0106] It can also be understood that the first reset signal line R1 for driving the pixel driving circuit Q of the nth row responds to the same signal terminal as the second scan signal line G2(n-m) of the pixel driving circuit Q of the (n-m)th row. That is to say, the first reset transistor T1 of the pixel driving circuit Q of the nth row can be driven by using the second scan signal line G2(n-m) that drives the pixel driving circuit Q of the (n-m)th row. Based on this, hereinafter, the first reset signal line R1 for driving the pixel driving circuit Q of the nth row will be represented by using the second scan signal line G2(n-m), while the second scan signal line G2 will still be represented as the second scan signal line for driving the pixel driving circuit Q of the nth row.

[0107] Thus, when the second scan signal line G2 drives the compensation transistor T2 of the pixel driving circuit Q of the nth row to turn on, the first reset transistors T1 of the subsequent m rows of pixel driving circuits Q can also be turned on to reset the first node N1.

[0108] With the above setting, the second scan signal line G2 and the first reset signal line R1 (the second scan signal line G2(n-m)) for driving the pixel driving circuit Q of the nth row respond to the same signal terminal, which can reduce the number of signal terminals in the display panel 100 and facilitate saving space in the display panel 100.

[0109] In some examples, m = 7. The first reset signal line R1 for driving the pixel driving circuit Q of the nth row responds to the same signal terminal as the second scan signal line G2(n-7) of the pixel driving circuit Q of the (n-7)th row. In other words, the first reset transistor T1 of the pixel driving circuit Q of the nth row can be driven by using the second scan signal line G2(n-7) that drives the pixel driving circuit Q of the (n-7)th row. Wherein, Figure 5 in this case, G2(n-7) is represented as the second scan signal line G2 electrically connected to the pixel driving circuits Q of the first 7 rows of the pixel driving circuit Q. Hereinafter, the first reset signal line R1 will be represented by the second scan signal line G2(n-7) of the pixel driving circuit Q of the (n-7)th row.

[0110] Based on this, when the second scan signal line G2(n - 7) drives the compensation transistor T2 of the pixel driving circuit Q of the (n - 7)-th row to turn on, it can also drive the first reset transistor T1 of the pixel driving circuit Q of the n-th row to turn on, and reset the first node N1. Furthermore, it can ensure that before the compensation stage (data writing stage), the control electrode g3 (the first node N1) of the driving transistor T3 is initialized, improving the stability of the driving transistor T3.

[0111] It can be understood that in some other examples, m can be other natural numbers. For example, the pixel driving circuit Q of the n-th row can be driven by the second scan signal line G2 that drives the pixel driving circuit Q of the (n - 3)-th row.

[0112] Based on this, it can be realized that the first reset transistor T1 of the pixel driving circuit Q of the n-th row can be driven by the second scan signal line G2(n - 7) that drives the pixel driving circuit Q of the (n - 7)-th row.

[0113] In some embodiments, as Figure 5 shown, the first scan signal line G1 can be multiplexed as the second reset signal line R2. When the first scan signal line G1 controls the data writing transistor T4 to turn on, it can simultaneously control the second reset transistor T7 to turn on, and transmit the second initialization signal received on the second initialization signal line V2 to the fourth node N4 to reset the fourth node N4. That is, the anode of the light-emitting device O is reset, improving the stability of the light-emitting device O.

[0114] In some embodiments, as Figure 5 shown, the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a storage capacitor Cst.

[0115] Figure 5 In the pixel driving circuit Q shown, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 may not be controlled by the same first enable signal line EM1. That is, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are respectively controlled by two enable signal lines.

[0116] Specifically, the control electrode g5 of the first light-emitting control transistor T5 is electrically connected to the first enable signal line EM1, and the control electrode g6 of the second light-emitting control transistor T6 is electrically connected to the second enable signal line EM2.

[0117] Based on this, two enable signal lines (the first enable signal line EM1 and the second enable signal line EM2) can be used to control two light-emitting control transistors (the first light-emitting control transistor T5 and the second light-emitting control transistor T6) respectively. Furthermore, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be controlled to turn on in sequence.

[0118] Thus, before the light-emitting device O receives the driving signal and emits light, the second node N2 is reset by the first power supply signal line first, so that the voltage at the first pole s3 position of the driving transistor T3 of the pixel driving circuit Q in a row of the pixel driving circuit remains the same for a period of time. Thus, the problem of afterimage caused by the drift of TFT characteristics can be improved, and the display quality of the display panel 100 can be improved.

[0119] Figure 6 It is a timing diagram of a pixel driving circuit according to some embodiments.

[0120] Combined Figure 5 and Figure 6 As shown, the driving process of the pixel driving circuit Q is as follows: One frame period includes an initialization stage t1, a data writing stage t2, and a light-emitting stage t3.

[0121] Initialization stage t1: The first enable signal line transmitted by the first enable signal line is a high-voltage signal, the second enable signal line transmitted by the second enable signal line is a high-voltage signal, the first scan signal transmitted by the first scan signal line G1 is a high-voltage signal, the second scan signal transmitted by the second scan signal line G2 is a high-voltage signal line, and the first reset signal (the second scan signal) transmitted by the second scan signal line G2 to which the first 7 rows of pixel driving circuits Q are electrically connected is a low-voltage signal.

[0122] At this time, the compensation transistor T2, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are in the off state. And the first reset transistor T1 is in the on state, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the first node N1 to reset the first node N1. At this time, the voltage at the first node N1 position is the voltage V1 of the first initial signal.

[0123] Data writing stage t2: The first enable signal line transmitted by the first enable signal line is a high-voltage signal, the second enable signal line transmitted by the second enable signal line is a high-voltage signal, and the first reset signal (the second scan signal) transmitted by the second scan signal line G2 to which the first 7 rows of pixel driving circuits Q are electrically connected is a high-voltage signal. Also, the first scan signal transmitted by the first scan signal line G1 is a low-voltage signal and the second scan signal transmitted by the second scan signal line G2 is a low-voltage signal line.

[0124] At this time, the first reset transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are in the off state. The data writing transistor T4 and the compensation transistor T2 are in the on state. At this time, the data writing signal transmitted on the data writing signal line Data can be transmitted to the second node N2 through the data writing transistor T4. That is, the voltage at the position of the second node N2 is the voltage Vdata of the data writing signal. Thus, Vgs of the driving transistor T3 = V1 - Vdata, Vgs < Vth, and the driving transistor T3 is in the on state.

[0125] Since the data writing transistor T4, the driving transistor T3, and the compensation transistor T2 are all in the on state during this stage, the data writing signal transmitted on the data writing signal line Data can be sequentially transmitted to the first node N1 through the data writing transistor T4, the driving transistor T3, and the compensation transistor T2 to compensate the first node N1, and the potential of the first node N1 gradually rises to Vdata + Vth, and the driving transistor T3 turns off, and the storage capacitor Cst completes the charging process.

[0126] Wherein, Vdata is the voltage value of the data writing signal provided by the data writing signal line Data, and Vth is the threshold voltage of the driving transistor T3 in the pixel driving circuit Q.

[0127] Moreover, since the first scanning signal line G1 can be multiplexed as the second reset signal line R2. Therefore, during this stage, the second reset transistor T7 can receive the low-voltage signal from the first scanning signal line G1 and turn on, and transmit the second initialization signal received on the second initialization signal line V2 to the fourth node N4 to reset the fourth node N4. Among them, the fourth node N4 is electrically connected to the light-emitting device O, and resetting the fourth node N4 is equivalent to resetting the anode of the light-emitting device O using this signal, improving the stability of the light-emitting device O.

[0128] In the light-emitting stage t3: the first scanning signal transmitted on the first scanning signal line G1 is a high-voltage signal, the second scanning signal transmitted on the second scanning signal line G2 is a high-voltage signal line, and the first reset signal transmitted on the first reset signal line R1 (the second scanning signal line G2(n - 7)) is a high-voltage signal. Also, the first enable signal transmitted on the first enable signal line is a low-voltage signal, and the second enable signal transmitted on the second enable signal line is a low-voltage signal.

[0129] At this time, the first reset transistor T1, the compensation transistor T2, the data writing transistor T4, and the second reset transistor T7 are in the off state. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are on. In addition, the driving transistor T3 remains conducting during this stage.

[0130] Based on this, the constant voltage power signal provided by the first power supply signal line VDD can sequentially flow through the first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6 to reach the anode of the light-emitting device O, and the cathode of the light-emitting device O can be electrically connected to the second power supply signal line VSS, thereby driving the light-emitting device O to emit light.

[0131] In addition, since the two light-emitting control transistors (the first light-emitting control transistor T5 and the second light-emitting control transistor T6) are respectively controlled by two enable signal lines (the first enable signal line EM1 and the second enable signal line EM2). Among them, the falling edge of the first enable signal transmitted by the first enable signal line EM1 is earlier than the falling edge of the second enable signal transmitted by the second enable signal line EM2. Furthermore, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be controlled to turn on sequentially.

[0132] In the light-emitting stage t3: under the control of the first enable signal from the first enable signal line EM1, the first light-emitting control transistor T5 can be controlled to turn on first, and the first power supply signal from the first power supply signal line VDD can be transmitted to the second node N2 (the first pole s3 of the driving transistor T3) via the first light-emitting control transistor T5. Furthermore, the second node N2 can be reset using the first power supply signal line, so that the voltage at the position of the first pole s3 of the driving transistor T3 of the pixel driving circuit Q in a row of pixel driving circuits remains consistent for a period of time. After that, the first light-emitting control transistor T5 remains in the on state. Under the control of the second enable signal from the second enable signal line EM2, the second light-emitting control transistor T6 is controlled to turn on, and in cooperation with the driving transistor T3, a driving signal is transmitted to the light-emitting device O.

[0133] Based on this, before the light-emitting device O receives the driving signal and emits light, the second node N2 is reset using the first power supply signal line first, so that the voltage at the position of the first pole s3 of the driving transistor T3 of the pixel driving circuit Q in a row of pixel driving circuits remains consistent for a period of time. Thus, the problem of afterimage caused by the drift of TFT characteristics can be improved, and the display quality of the display panel 100 can be improved.

[0134] Figure 7 It is a circuit diagram of a pixel driving circuit according to some other embodiments.

[0135] In some embodiments, as Figure 7 shown, the pixel driving circuit Q further includes a first capacitor C1. The first electrode plate C1-1 of the first capacitor C1 is electrically connected to the first power supply signal line VDD, and the second electrode plate C1-2 of the first capacitor C1 is electrically connected to the second node N2.

[0136] Figure 7 The pixel driving circuit Q shown and Figure 5 the difference between the pixel driving circuit Q shown lies in that: Figure 7 In the pixel driving circuit Q shown, a first capacitor is connected in series between the second node N2 and the first power supply signal line VDD, and other devices are the same.

[0137] The following will introduce Figure 7 the driving process of the pixel driving circuit Q. Among them, the case where all 7 transistors in the pixel driving circuit Q are P-type transistors is taken as an example for introduction.

[0138] Combined with Figure 6 and Figure 7 shown, Figure 7 the driving process of the pixel driving circuit Q shown is as follows: A frame period includes an initialization stage t1, a data writing stage t2, and a light emitting stage t3. Among them, Figure 7 the initialization stage t1 and the light emitting stage t3 in the driving process of the pixel driving circuit Q shown are substantially the same as those in the driving process of the pixel driving circuit Q shown above, Figure 5 which will not be elaborated here.

[0139] However Figure 7 the difference between the driving process of the pixel driving circuit Q shown and Figure 5 the driving process of the pixel driving circuit Q shown lies in that: Figure 7 In the data writing stage t2 in the driving process of the pixel driving circuit Q shown, it not only includes the data writing stage t2 in the driving process of the pixel driving circuit Q shown above, Figure 5 but also includes the following stages.

[0140] When the data writing signal is transmitted to the second node N2, it is equivalent to transmitting the data writing signal to the first capacitor C1. Based on this, the first capacitor C1 also stores the voltage of the data writing signal synchronously in this stage.

[0141] After the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off in the sub-stage t21, the first capacitor C1 can discharge to the first node N1 until the compensation transistor T2 is turned off. Thus, the time for writing the data writing signal can be indirectly extended, which is beneficial to improving the display uniformity of the display panel.

[0142] Figure 8 It is a layer structure diagram of multiple pixel driving circuits according to some embodiments. Among them, Figure 8 the case of the pixel driving circuit Q of two rows and four columns in the display panel 100 is taken as an example for introduction, but it does not mean that the display panel 100 only includes the illustrated number of pixel driving circuits Q.

[0143] In some embodiments, combined with Figure 2 ,Figure 6 and Figure 8 As shown in Figure 8 , the driving circuit layer 20 includes a semiconductor layer POLY, a first gate metal layer Gate1, a first routing metal layer SD1, and a second routing metal layer SD2, which are stacked on the substrate 10. Among them, the semiconductor layer POLY is located between the substrate 10 and the first gate metal layer Gate1.

[0144] The driving circuit layer 20 further includes a plurality of signal lines electrically connected to the driving circuit Q. Exemplarily, the driving circuit layer 20 includes a plurality of first scan signal lines G1, a plurality of second scan signal lines G2, a plurality of first initialization signal lines Vinit1, a plurality of second initialization signal lines Vinit2, a plurality of first power signal lines VDD, a plurality of second power signal lines VSS, and a plurality of data write signal lines Data.

[0145] Among them, the plurality of data write signal lines Data are arranged along the first direction X and extend along the second direction Y. The data write signal line Data is configured to provide a data write signal to the pixel driving circuit Q.

[0146] In some examples, the plurality of data write signal lines Data may be located in the second routing metal layer SD2. The plurality of data write signal lines Data are located in the display area AA, and one data write signal line Data is connected to a column of sub-pixel driving circuits Q.

[0147] Among them, a part of the plurality of data write signal lines Data is located in one edge area AA2, another part of the plurality of data write signal lines Data is located in another edge area AA2, and still another part of the plurality of data write signal lines Data is located in the middle area AA1.

[0148] In some examples, the number of data write signal lines Data in the two edge areas AA2 may be the same. In other examples, the number of data write signal lines Data in the two edge areas AA2 may be different.

[0149] In some examples, the number of data write signal lines Data in one edge area AA2 may be the same as the number of data write signal lines Data in the middle area AA1. In other examples, the number of data write signal lines Data in one edge area AA2 may be different from the number of data write signal lines Data in the middle area AA1.

[0150] In some examples, the display panel further includes a bonding region BB. The bonding region BB is located on one side of the display region AA. The driving circuit layer 20 in the display panel 100 further includes a plurality of data leads L. The data lead L includes a first lead segment L1 and a second lead segment L2. The second lead segment L2 is located in the middle region AA1, the second lead segment L2 extends along the second direction Y, and extends to the bonding region BB. And, the first lead segment L1 extends along the first direction X, one end of the first lead segment L1 is located in the edge region AA2, and the other end of the first lead segment L1 is located in the middle region AA2. One end of the first lead segment L1 can be electrically connected to a data writing signal line Data located in the edge region AA2, and the other end of the first lead segment L1 can be electrically connected to one end of the second lead segment L2 located in the middle region AA1.

[0151] Based on this, the data writing signal line Data in the edge region AA2 can be rewired to the middle region AA1 by using the first lead segment L1 of the data lead L, and then extended to the bonding region BB by using the second lead segment L2 of the data lead L. That is, the signal lines that need to be electrically connected to the bonding region BB (the second lead segment L2 electrically connected to the data writing signal line Data in the edge region AA2 and the data writing signal line Data in the middle region AA1) can be concentrated in the display region AA at the corresponding position of the driving chip IC, which is beneficial to realizing a narrow bezel.

[0152] Thus, the display panel 100 can implement the technology of FIAA, and layout the data lead L in the display region AA, which is beneficial to realizing a narrow bezel of the display panel 100.

[0153] In some examples, the bonding region BB includes a driving chip (full English name: Integrated Circuit, English abbreviation: IC).

[0154] However, since the data lead L is disposed in the display region AA, it is easy to have an overlap between the positive projection of the data lead L on the substrate 10 and the positive projection of some transistors in the pixel driving circuit Q on the substrate 10, which affects the stability of the transistors.

[0155] Specifically, when the positive projection of the data lead L on the substrate 10 overlaps with the positive projection of the second pole d1 of the first reset transistor T1 in the pixel driving circuit Q on the substrate 10. Since the data writing signal can be a pulse signal. That is, the data writing signal is a continuously changing and non-constant signal. Based on the effect of capacitive coupling, when the data writing signal transmitted by the data lead L jumps, it will cause the potential of the second pole d1 of the first reset transistor T1 to jump. Furthermore, it will also indirectly cause the potential of the control pole g3 of the driving transistor T3 to change, affecting the stability of the driving transistor T3.

[0156] Based on this, a third wiring metal layer can be added in the driving circuit layer 20 to form a first lead segment L1 of the data lead L in the second wiring metal layer SD2 and a second lead segment of the data lead L in the third wiring metal layer. Thus, the distance between each transistor in the pixel driving circuit Q and the data lead L in the direction perpendicular to the substrate 10 is increased. This can improve the problem that when the data write signal transmitted by the data lead L jumps, the potential of the second pole d1 of the first reset transistor T1 will jump.

[0157] However, the inventors of the present disclosure have found through research that adding a third wiring metal layer in the driving circuit layer 20 will require one more lithography process when manufacturing the display panel 100 to form the data write signal line Data and the second lead segment L2 of the data lead L in the third wiring metal layer. And since the third wiring metal layer is located on the side of the second wiring metal layer SD2 away from the first wiring metal layer SD1, to prevent a short circuit problem between the third wiring metal layer and the second wiring metal layer, an insulating layer needs to be provided between the third wiring metal layer and the second wiring metal layer to insulate the third wiring metal layer and the second wiring metal layer from each other. The first lead segment L1 of the data lead L is formed in the second wiring metal layer SD2, and the first lead segment L1 and the second lead segment L2 of the data lead L need to be connected to each other. Therefore, vias need to be formed in the insulating layer between the third wiring metal layer and the second wiring metal layer to facilitate the connection between the first lead segment L1 of the data lead L located in the second wiring metal layer SD2 and the second lead segment L2 of the data lead L located in the third wiring metal layer. That is, when manufacturing the display panel 100, another lithography process is also required to form the vias in the insulating layer between the third wiring metal layer and the second wiring metal layer.

[0158] In summary, due to adding a third wiring metal layer in the driving circuit layer 20, two more lithography processes are required when manufacturing the display panel 100. This will increase the cost of the display panel 100 and also increase the production cycle of the display panel 100, reducing the production efficiency of the display panel 100.

[0159] Figure 9 It is a film layer structure diagram of multiple pixel driving circuits according to some other embodiments. Figure 10 For Figure 9 the structure diagram of the semiconductor layer in Figure 11 It is a structure diagram of the semiconductor layer according to some embodiments. Figure 12 For Figure 9 the structure diagram of the first gate metal layer in Figure 13 For Figure 9 the structure diagram of the second gate metal layer in Figure 14 For Figure 9Structural diagrams of the middle semiconductor layer, the first gate metal layer, and the second gate metal layer Figure 15 is Figure 9 the structural diagram of the first routing metal layer in Figure 16 is Figure 9 structural diagrams of the middle semiconductor layer, the first gate metal layer, the second gate metal layer, and the first routing metal layer Figure 17 is Figure 9 the structural diagram of the second routing metal layer in

[0160] Among them, Figure 9 is Figure 8 taking the four pixel driving circuits Q below in as an example for illustration, the structure of each pixel driving circuit Q can be observed more clearly.

[0161] Based on the above problems, combined with Figures 8 to 17 as shown in , in the display panel 100 provided by the embodiments of the present disclosure, the driving circuit layer 20 includes a semiconductor layer POLY, a first gate metal layer Gate1, a second gate metal layer Gate2, a first routing metal layer SD1, and a second routing metal layer SD2 that are stacked on the substrate 10 (such as Figure 3 as shown in ). Among them, the semiconductor layer POLY is located between the first gate metal layer Gate1 and the substrate 10.

[0162] It can be set that the first routing metal layer SD1 includes a first segment L1 of the data lead L, and the second routing metal layer SD2 includes a data write signal line Data and a second segment L2 of the data lead L.

[0163] Based on this, the data write signal line Data and the data lead L are distributed in the spaces of the first routing metal layer SD1 and the second routing metal layer SD2. Thus, there is no need to add a third routing metal layer in the driving circuit layer 20 in the display panel 100. Compared with the display panel 100 provided with a third routing metal layer, the display panel 100 provided by the embodiments of the present disclosure can reduce two lithography processes. Therefore, the cost of the display panel 100 can be reduced, the production cycle of the display panel 100 can be shortened, and the production efficiency of the display panel 100 can be improved.

[0164] The above mainly introduced the downward-shifted data lead L and the data write signal line Data, so as to realize that there is no need to provide a third metal trace layer in the driving circuit layer, thereby reducing the cost of the display panel 100, shortening the production cycle of the display panel 100, and improving the production efficiency of the display panel 100. After shifting the data lead L and the data write signal line Data downward to the side of the substrate 10, the distance between the data lead L and the data write signal line Data and the transistors in the pixel driving circuit Q is reduced, which is likely to cause problems affecting the stability of the transistors. The following will introduce how to reduce the mutual crosstalk problem between the data lead L and the transistors in combination with the structures in multiple film layers in the driving circuit layer.

[0165] In some examples, such as Figure 10 shown, the semiconductor layer POLY further includes the channel portions of the respective transistors in the pixel driving circuit Q. Moreover, the semiconductor layer POLY further includes a first conductive portion U1, and the first conductive portion U1 includes the second pole d1 of the first reset transistor T1, and the first conductive portion U1 is connected to the channel portion a1 of the first reset transistor T1. Additionally, the first conductive portion U1 may further include the second pole d2 of the compensation transistor T2, so as to realize the connection between the second pole d1 of the first reset transistor T1 and the second pole d2 of the compensation transistor T2.

[0166] Exemplarily, when the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7: the semiconductor layer POLY includes: the first pole s1, the second pole d1, and the channel portion a1 of the first reset transistor T1, the first pole s2, the second pole d2, and the channel portion a2 of the compensation transistor T2, the first pole s3, the second pole d3, and the channel portion a3 of the driving transistor T3, the first pole s4, the second pole d4, and the channel portion a4 of the data write transistor T4, the first pole s5, the second pole d5, and the channel portion a5 of the first light-emitting control transistor T5, the first pole s6, the second pole d6, and the channel portion a6 of the second light-emitting control transistor T6, the first pole s7, the second pole d7, and the channel portion a7 of the second reset transistor T7.

[0167] It should be noted that, as shown in combination with Figure 9 and Figure 10 shown, the orthographic projection of the semiconductor layer POLY on the substrate 10 (as shown in Figure 3 shown) overlaps with the orthographic projection of the first gate metal layer Gate1 on the substrate 10. Among them, the portion of the semiconductor layer POLY covered by the first gate metal layer Gate1 constitutes the channel portions of the respective transistors, and the portion of the semiconductor layer POLY not covered by the first gate metal layer G1 is the conductive portion, which constitutes a part of the first pole or the second pole of each transistor.

[0168] In some examples, such as Figure 10 shown, the shape of the orthographic projection of the channel portion a3 of the driving transistor T3 on the substrate 10 is an inverted "one" shape. At this time, the channel portion a3 of the driving transistor T3 extends along the first direction X. The structure of the channel portion a3 of the driving transistor T3 is regular, which can facilitate the flexible arrangement of other transistors on the semiconductor layer POLY.

[0169] In other examples, such as Figure 11 shown, the shape of the orthographic projection of the channel portion a3 of the driving transistor T3 on the substrate 10 is a "Ji" shape. Among them, the "Ji" shape can be understood as an Ω shape, or similar to an Ω shape or a "Ji" shape, that is, the channel portion a3 of the driving transistor T3 includes a protruding structure. Such a setting can facilitate improving the stability of the driving transistor T3 so that it can satisfy a larger driving current flowing through it and improve the display quality of the display panel 100.

[0170] In some examples, the material of the semiconductor layer POLY may include amorphous silicon, single crystal silicon or polycrystalline silicon semiconductor materials.

[0171] In some examples, in combination with Figure 9 and Figure 12 shown, the first gate metal layer Gate1 is located on the side of the semiconductor layer POLY away from the substrate 10 (as Figure 3 shown). That is, the first gate metal layer Gate1 is located between the semiconductor layer POLY and the second gate metal layer Gate2.

[0172] The first gate metal layer Gate1 may include the control electrodes of the respective transistors in the pixel driving circuit Q. Exemplarily, in the case where the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6 and a second reset transistor T7: the first gate metal layer Gate1 may include the control electrode g1 of the first reset transistor T1, the control electrode g2 of the compensation transistor T2, the control electrode g3 of the driving transistor T3, the control electrode g4 of the data writing transistor T4, the control electrode g5 of the first light emitting control transistor T5, the control electrode g6 of the second light emitting control transistor T6 and the control electrode g7 of the second reset transistor T7.

[0173] In addition, the first gate metal layer Gate1 can also be used to form partial signal lines. The partial signal lines include a plurality of first scan signal lines G1 and a plurality of second scan signal lines G2. Among them, the plurality of first scan signal lines G1 extend along the first direction X and are arranged along the second direction Y. And, the plurality of second scan signal lines G1 extend along the first direction X and are arranged along the second direction Y.

[0174] In some examples, the first scan signal line G1 located on the first gate metal layer Gate1 may include a first portion G11, and the first portion G11 of the first scan signal line G1 may be multiplexed as the control electrode g4 of the data writing transistor T4.

[0175] Based on this, directly using the first portion G11 of the first scan signal line G1 as the control electrode g4 of the data writing transistor T4 not only eliminates the need to separately provide the control electrode g4 of the data writing transistor T4, but also eliminates the need to provide a conductive portion for connecting the control electrode g4 of the data writing transistor T4 and the first description signal line G1. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also help save resources.

[0176] In some examples, when the first scan signal line G1 is multiplexed as the second reset signal line, the first scan signal line G1 located on the first gate metal layer Gate1 may further include a second portion G12, and the second portion G12 of the first scan signal line G1 may be multiplexed as the control electrode g7 of the second reset transistor T7.

[0177] Based on this, directly using the second portion G12 of the first scan signal line G1 as the control electrode g7 of the second reset transistor T7 not only eliminates the need to separately provide the control electrode g7 of the second reset transistor T7, but also eliminates the need to provide a conductive portion for connecting the control electrode g7 of the second reset transistor T7 and the first description signal line G1. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplify the manufacturing process of the pixel driving circuit Q and help save resources.

[0178] In some examples, the second scan signal line Gate2 located on the first gate metal layer Gate1 may include a first portion G21, and the first portion G21 of the second scan signal line Gate2 may be multiplexed as the control electrode g2 of the compensation transistor T2.

[0179] Based on this, directly using the first portion G21 of the second scan signal line Gate2 as the control electrode g2 of the compensation transistor T2 not only eliminates the need to separately provide the control electrode g2 of the compensation transistor T2, but also eliminates the need to provide a conductive portion for connecting the control electrode g2 of the compensation transistor T2 and the second scan signal line Gate2. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplify the manufacturing process of the pixel driving circuit Q and help save resources.

[0180] In some examples, the second scan signal line G2(n - 7) / the first reset signal line R1 located on the first gate metal layer Gate1 may include a first portion R11, and the first portion R11 of the second scan signal line G2(n - 7) / the first reset signal line R1 may be multiplexed as the control gate g1 of the first reset transistor T1.

[0181] Based on this, directly using the first portion R11 of the second scan signal line G2(n - 7) / the first reset signal line R1 as the control gate g1 of the first reset transistor T1 not only eliminates the need to separately provide the control gate g1 of the first reset transistor T1 but also eliminates the need to provide a conductive portion for connecting the control gate g1 of the first reset transistor T1 and the second scan signal line G2(n - 7) / the first reset signal line R1. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplify the manufacturing process of the pixel driving circuit Q, which is beneficial to resource conservation.

[0182] In some examples, the material of the first gate metal layer Gate1 includes a conductive metal. The conductive metal may include at least one of aluminum, copper, and molybdenum, and the present disclosure is not limited thereto.

[0183] In some examples, a first gate insulating layer is provided between the first semiconductor layer POLY1 and the first gate metal layer Gate1, and the first gate insulating layer electrically insulates the first semiconductor layer POLY1 and the first gate metal layer Gate1.

[0184] Exemplarily, the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer may also include silicon dioxide, and the present disclosure is not limited thereto.

[0185] In some examples, in combination Figure 9 、 Figure 13 and Figure 14 as shown, the second gate metal layer Gate2 is located on the side of the first gate metal layer Gate1 away from the semiconductor layer POLY. That is, the second gate metal layer Gate2 is located between the first gate metal layer Gate1 and the first routing metal layer SD1.

[0186] In some examples, the pixel driving circuit Q further includes a storage capacitor Cst. The first electrode plate Cst - 1 of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate Cst - 2 of the storage capacitor Cst is electrically connected to the first power supply signal line VDD.

[0187] The first gate metal layer Gate1 further includes the first electrode plate Cst - 1 of the storage capacitor Cst. It can be set that the first electrode plate Cst - 1 of the storage capacitor Cst is on the substrate 10 (such asFigure 3 The positive projection on the substrate substrate 10 shown overlaps with the positive projection of the channel portion a3 of the driving transistor T3 on the substrate substrate 10, so as to reuse the first electrode plate of the storage capacitor Cst as the control electrode g3 of the driving transistor T3.

[0188] The second gate metal layer Gate2 includes the second electrode plate Cst-2 of the storage capacitor Cst. The positive projection of the second electrode plate Cst-2 of the storage capacitor Cst on the substrate substrate 10 (as Figure 3 shown) overlaps with the positive projection of the first electrode plate Cst-1 of the storage capacitor Cst on the substrate substrate 10, so as to form the storage capacitor Cst.

[0189] Among them, the first electrode plate Cst-1 of the storage capacitor Cst located on the first gate metal layer Gate1 can be reused as the control electrode g3 of the driving transistor T3. Based on this, there is no need to separately provide the control electrode g3 of the driving transistor T3, which is beneficial to simplifying the manufacturing process of the pixel driving circuit Q. And, by using the first electrode plate Cst-1 of the storage capacitor Cst as the control electrode g3 of the driving transistor T3, the first electrode plate Cst-1 of the storage capacitor Cst can be directly electrically connected to the control electrode g3 of the driving transistor T3 without separately providing a connecting portion, which is also beneficial to the layout of the pixel driving circuit Q.

[0190] In addition, the second gate metal layer Gate2 can also be used to form part of the signal lines. The part of the signal lines includes a plurality of first initialization signal lines Vinit1 and a plurality of second initialization signal lines Vinit2. Among them, the plurality of first initialization signal lines Vinit1 extend along the first direction X and are arranged along the second direction Y. And, the plurality of second initialization signal lines Vinit2 extend along the first direction X and are arranged along the second direction Y.

[0191] In addition, since the second gate metal layer Gate2 is located between the semiconductor POLY and the first trace metal layer SD1, a first shielding portion J1 can be provided on the second gate metal layer Gate2. Among them, the first shielding portion J is configured to have a constant voltage signal.

[0192] Based on this, the positive projection of the first shielding portion J on the substrate substrate 10 can be set to overlap partially with the positive projection of the first conductive portion U1 on the substrate substrate 10.

[0193] In some examples, the material of the second gate metal layer Gate2 can be the same as that of the first gate metal layer Gate1. It can be understood that, in other examples, the material of the second gate metal layer Gate2 can be different from that of the first gate metal layer Gate1. The embodiments of the present disclosure do not limit this.

[0194] In some examples, a second gate insulating layer may be provided between the second gate metal layer Gate2 and the first gate metal layer Gate1. The second gate insulating layer electrically insulates the second gate metal layer Gate2 and the first gate metal layer Gate1.

[0195] Exemplarily, the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon dioxide. The material of the second gate insulating layer may also include silicon dioxide, and the present disclosure is not limited thereto.

[0196] In some examples, in combination Figure 9 、 Figure 15 and Figure 16 as shown, the first routing metal layer SD1 is located on the side of the second gate metal layer Gate2 away from the first gate metal layer Gate1. That is, the first routing metal layer SD1 is located between the second gate metal layer Gate2 and the second routing metal layer SD2.

[0197] Exemplarily, the material of the first routing metal layer SD1 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0198] Exemplarily, a first planarization layer (full English name: Planarization Layer, English abbreviation: PLN) is provided between the first routing metal layer SD1 and the second gate metal layer Gate2. The first planarization layer can electrically insulate the first routing metal layer SD1 and the second gate metal layer Gate2.

[0199] Exemplarily, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (full English name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0200] In addition, the first routing metal layer SD1 can also be used to form part of the signal lines. The part of the signal lines includes the first segment L1 of multiple data leads L, multiple first enable signal lines EM1, and multiple second enable signal lines EM2. Among them, the multiple first enable signal lines EM1 extend along the first direction X and are arranged along the second direction Y. And, the multiple second enable signal lines EM2 extend along the first direction X and are arranged along the second direction Y.

[0201] In some embodiments, in combination Figure 8 、 Figure 9 and Figure 16 as shown, the first routing metal layer SD1 further includes multiple first virtual segment 31, extending along the first direction X and arranged along the second direction Y. The first virtual segment 31 corresponds to the first segment L1 one by one, and along the first direction X, the first virtual segment 31 and the first segment L1 are arranged at intervals.

[0202] Based on this, multiple first virtual lead segments 31 and multiple first lead segments L1 can be used in cooperation to achieve uniform routing arrangement on the first routing metal layer SD1, improve the uniformity of the external ambient light reflection of the first routing metal layer SD1, and thus improve the display effect of the display panel 100.

[0203] In some examples, the first virtual lead segment 31 can be configured to transmit a constant voltage signal. Exemplarily, the first virtual lead segment 31 can be electrically connected to the second power signal line VSS.

[0204] In some embodiments, the first routing metal layer SD1 further includes multiple connection parts.

[0205] The connection part includes a first connection part PAD1, and the first connection part PAD1 is used to connect the control electrode g3 of the driving transistor T3 located in the first gate metal layer Gate1 and the first conductive part U1 located in the semiconductor layer POLY, so as to realize the electrical connection of the control electrode g3 of the driving transistor T3, the second electrode d1 of the first reset transistor T1, and the second electrode d2 of the compensation transistor T2.

[0206] Wherein, the first connection part PAD1 can be connected to the first conductive part U1 through a via, and the first connection part PAD1 can be connected to the control electrode g3 of the driving transistor T3 through another via.

[0207] The connection part further includes a second connection part PAD2, and the second connection part PAD2 is used to connect the first initialization signal line Vinit1 located in the second gate metal layer Gate2 and the first electrode s1 of the first reset transistor T1 located in the semiconductor layer POLY, so as to realize the electrical connection of the first initialization signal line Vinit1 and the first electrode s1 of the first reset transistor T1.

[0208] Wherein, the second connection part PAD2 can be connected to the first initialization signal line Vinit1 through a via, and the second connection part PAD2 can also be connected to the first electrode s1 of the first reset transistor T1 through another via.

[0209] The connection part may further include a third connection part PAD3, and the third connection part PAD3 can be used to connect the second electrode plate Cst-2 of the storage capacitor Cst and the first power signal line VDD.

[0210] Wherein, the third connection part PAD3 can be connected to the second electrode plate Cst-2 of the storage capacitor Cst through a via, and the third connection part PAD3 can also be connected to the first power signal line VDD through another via.

[0211] The connecting portion may further include a fourth connecting portion PAD4, and the fourth connecting portion PAD4 is used to connect the second pole d6 of the second light-emitting control transistor T6, the second pole d7 of the second reset transistor T7, and the anode of the light-emitting device, so as to electrically connect the second pole d6 of the second light-emitting control transistor T6, the second pole d7 of the second reset transistor T7, and the anode of the light-emitting device.

[0212] Wherein, the fourth connecting portion PAD4 can be connected to the second pole d6 of the second light-emitting control transistor T6 and the second pole d7 of the second reset transistor T7 through vias, and the fourth connecting portion PAD4 can also be connected to the anode of the light-emitting device through additional vias.

[0213] The connecting portion may further include a fifth connecting portion PAD5, and the fifth connecting portion PAD5 is used to connect the first pole s7 of the second reset transistor T7 located in the semiconductor layer POLY and the second initialization signal line Vinit2 located in the second gate metal layer Gate2, so as to electrically connect the first pole s7 of the second reset transistor T7 and the second initialization signal line Vinit2.

[0214] Wherein, the fifth connecting portion PAD5 can be connected to the first pole s7 of the second reset transistor T7 through a via, and the fifth connecting portion PAD5 can also be connected to the second initialization signal line Vinit2 through an additional via.

[0215] The connecting portion may further include a sixth connecting portion PAD6, and the sixth connecting portion PAD6 is used to connect the first pole s4 of the data writing transistor T4 located in the semiconductor layer POLY and the first scanning signal line G1 located in the first gate metal layer Gate1, so as to electrically connect the first pole s4 of the data writing transistor T4 and the first scanning signal line G1.

[0216] In some examples, in combination with Figure 8 、 Figure 9 and Figure 17 as shown, the second routing metal layer SD2 is located on a side of the first routing metal layer SD1 away from the second gate metal layer Gate2.

[0217] In some examples, the material of the second routing metal layer SD2 may be the same as that of the first routing metal layer SD1. Alternatively, in other examples, the material of the second routing metal layer SD2 may be different from that of the first routing metal layer SD1. Embodiments of the present disclosure do not limit this.

[0218] In some examples, a second planarization layer is provided between the second routing metal layer SD2 and the first routing metal layer SD1. The second planarization layer electrically insulates the second routing metal layer SD2 and the first routing metal layer SD1.

[0219] Exemplarily, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (full English name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0220] In some embodiments, as shown in Figure 8 and Figure 9 , the second routing metal layer SD2 further includes a plurality of second virtual lead segments 32, and the plurality of second virtual lead segments 32 extend along the second direction Y and are arranged in the first direction X. Among them, the second virtual lead segments 32 correspond one-to-one with the second lead segments L2, and along the second direction Y, the second virtual lead segments 32 are spaced apart from the second lead segments L2.

[0221] Based on this, the cooperation of the plurality of second virtual lead segments 32 and the plurality of second lead segments L2 can be utilized to achieve uniform routing arrangement on the second routing metal layer SD2, and improve the uniformity of the external ambient light reflection of the second routing metal layer SD2. Thus, the display effect of the display panel 100 is improved.

[0222] In some examples, the second virtual lead segment 32 can be configured to transmit a constant voltage signal. Exemplarily, the second virtual lead segment 32 can be electrically connected to the second power signal line VSS.

[0223] In some examples, within the same data lead L: the orthographic projection of the first lead segment L1 on the substrate 10 overlaps with the orthographic projection of the second lead segment L2 on the substrate 10. Based on this, it is convenient to connect the first lead segment L1 and the second lead segment L2 through a punching process.

[0224] Furthermore, the width of the first part of the second lead segment L2 can be set to be greater than the width of the second part. Among them, the orthographic projection of the first part of the second lead segment L2 on the substrate 10 overlaps with the orthographic projection of the first lead segment L1 on the substrate 10, and the orthographic projection of the second part of the second lead segment L2 on the substrate 10 does not overlap with the orthographic projection of the first lead segment L1 on the substrate 10. Based on this, the area of the overlapping region between the orthographic projection of the first lead segment L1 on the substrate 10 and the orthographic projection of the second lead segment L2 on the substrate 10 can be increased, thereby reducing the difficulty of the punching process and facilitating the connection of the first lead segment L1 and the second lead segment L2 through the punching process.

[0225] In some examples, the orthographic projection of the first lead segment L1 on the substrate 10 overlaps with the orthographic projection of the data write signal line Data on the substrate 10. Based on this, it is convenient to connect the first lead segment L1 and the data write signal line Data through a punching process.

[0226] In some embodiments, in combination with Figure 2 , Figure 6 and Figure 8 as shown, the second lead segment L2 of the data lead L is located between two adjacent pixel driving circuits Q in the first direction X. That is, the second lead segment L2 of the data lead L is arranged in the region where the driving transistor T3 is close to the edge of the pixel driving circuit Q in the first direction X, so that the positive projection of the second lead segment L2 of the data lead L on the substrate 10 (return Figure 3 as shown) does not overlap with the positive projection of the driving transistor T3 on the substrate 10.

[0227] Thereby, when the data write signal transmitted by the second lead segment L2 of the data lead L jumps, the influence on the potentials of each pole of the driving transistor T3 can be prevented, which is beneficial to improving the stability of the driving transistor T3 in the pixel driving circuit Q, and thus beneficial to improving the brightness uniformity of the display panel 100.

[0228] In combination with Figures 9 to 16 as shown, based on the above introduction to the structures of the respective film layers in the driving circuit layer 20, the first conductive part U1 in the semiconductor layer POLY includes the second pole d1 of the first reset transistor T1, and the first shielding part J with a constant voltage signal is provided in the second gate metal layer Gate2. The first lead metal layer SD1 is provided with the first lead segment L1 of the data lead L. That is, along the direction perpendicular to the substrate 10 (such as Figure 3 as shown), the first shielding part J is located between the first conductive part U1 and the first lead segment.

[0229] Furthermore, it can be set that there is an overlap between the positive projection of the first conductive part U1 on the substrate 10, the positive projection of the first shielding part J on the substrate 10, and the positive projection of the first lead segment L1 on the substrate 10.

[0230] Based on this, the first shielding part J with a constant voltage signal can be used to isolate the first conductive part U1 and the first lead segment L1, so as to improve the voltage jump at the position of the first conductive part U1 when the data write signal transmitted by the first lead segment L1 jumps. Since the second pole d1 of the first reset transistor T1 and the control pole g3 of the driving transistor T3 are both electrically connected to the first node. That is, the first conductive part U1 will be electrically connected to the control pole g3 of the driving transistor T3, and thus the stability of the control pole g3 of the driving transistor T3 can be indirectly improved, which is beneficial to optimizing the brightness uniformity of the display panel 100.

[0231] In some embodiments, in combination with Figures 9 to 16As shown, the first reset transistor T1 and the compensation transistor T2 are located on the same side of the driving transistor T3 in the second direction Y. Among them, along the second direction Y, the control electrode g1 of the first reset transistor T1 is located on the side of the compensation transistor T2 away from the driving transistor T3, and both the first electrode s1 and the second electrode d1 of the first reset transistor T1 are located between the control electrode g1 of the first reset transistor T1 and the driving transistor, and the second electrode d1 of the first reset transistor T1 is adjacent to the second electrode d2 of the compensation transistor T2.

[0232] Based on this, it is convenient to connect the second electrode d1 of the first reset transistor T1 to the second electrode d2 of the compensation transistor T2, so as to facilitate subsequent electrical connection to the control electrode g3 of the driving transistor T3.

[0233] In some examples, the second electrode d1 of the first reset transistor T1 is multiplexed as the second electrode d2 of the compensation transistor T2.

[0234] Based on this, it is convenient to realize the connection between the second electrode d1 of the first reset transistor T1 and the second electrode d2 of the compensation transistor T2, and it is also beneficial to save the space of the semiconductor layer POLY.

[0235] In some embodiments, in combination with Figures 9 to 16 As shown, the second gate metal layer Gate2 further includes a plurality of first initialization signal lines Vinit1. Since the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, the first initialization signal line Vinit1 can be arranged between the control electrode g1 of the first reset transistor T1, the first electrode s1 and the second electrode d1 of the first reset transistor T1.

[0236] Based on this, it is convenient to reduce the distance between the first initialization signal line Vinit1 and the first electrode s1 of the first reset transistor T1, and it is convenient for the two to achieve electrical connection.

[0237] In some embodiments, in combination with Figures 9 to 16 As shown, since the first initialization signal transmitted by the first initialization signal line Vinit1 is a constant voltage signal. The first initialization signal line Vinit1 can be electrically connected to the first shielding part J to transmit the constant voltage signal to the first shielding part J by using the first initialization signal line.

[0238] Based on this, it can be realized that the first shielding part J has a constant voltage signal, so as to use the first shielding part J to isolate the first lead segment L1 and the first conductive part U1, and improve the problem that the voltage of the first conductive part U1 jumps due to the data write signal transmitted by the first lead segment L1. And, there is no need to set an independent constant voltage signal line in the driving circuit layer, which can facilitate saving the space of the driving circuit layer and saving resources.

[0239] In some examples, the first initialization signal line Vinit1 is on the same layer as the first shielding portion J. The first initialization signal line Vinit1 and the first shielding portion J can be formed by a single lithography process, which is convenient for simplifying the manufacturing process of the pixel driving circuit Q.

[0240] It should be noted that "on the same layer" means forming a film layer for forming a specific pattern by the same film forming process, and then forming a layer structure by a single lithography process using the same mask. Depending on the different specific patterns, the single lithography process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0241] In some embodiments, in combination with Figures 9 to 16 as shown, it can be set that the first initialization signal line Vinit1 includes a main body portion B1 and a first auxiliary portion F1, and the first auxiliary portion F1 is located on the side of the main body portion B1 close to the first reset transistor T1. That is, the first auxiliary portion F1 is the protruding portion of the first initialization signal line Vinit1 towards the first reset transistor T1.

[0242] At this time, the positive projection of the first auxiliary portion F1 of the first initialization signal line Vinit1 on the substrate 10 (as Figure 3 shown), the positive projection of the first conductive portion U1 on the substrate 10, and the positive projection of the first lead segment L1 on the substrate 10 overlap.

[0243] Thus, the first auxiliary portion F1 of the first initialization signal line Vinit1 can be reused as the first shielding portion J, which serves to isolate the first lead segment L1 from the first conductive portion U1 and improve the problem that the voltage of the first conductive portion U1 jumps due to the data write signal transmitted by the first lead segment L1.

[0244] Moreover, since the first auxiliary portion F1 of the first initialization signal line Vinit1 is reused as the first shielding portion J, there is no need to separately provide the first shielding portion J, which can simplify the manufacturing process of the display panel.

[0245] In addition, since the positive projection of the main body portion B1 of the first initialization signal line Vinit1 on the substrate 10 and the positive projection of the first conductive portion U1 on the substrate 10 overlap at least partially. Furthermore, the relative area between the first initialization signal line Vinit1 and the first conductive portion U1 can be increased, further improving the stability of the first conductive portion U1 to improve the stability of the driving transistor T3.

[0246] In some embodiments, in combination with Figures 9 to 14As shown, the control electrode g2 of the compensation transistor T2 includes a first control electrode g1 and a second control electrode g2.

[0247] The channel portion a2 of the compensation transistor T2 includes: a first channel portion a21 and a second channel portion a22. The semiconductor layer POLY further includes a second conductive portion U2, and the second conductive portion U2 is located between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2. One end of the second conductive portion U2 is connected to the first channel portion a21 of the compensation transistor T2, and the other end of the second conductive portion U2 is connected to the second channel portion a22 of the compensation transistor T2, so as to realize connecting the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 by using the second conductive portion U2.

[0248] It should be noted that, among them, the first channel portion a21 of the compensation transistor T2 is opposite to the first control electrode g21 of the compensation transistor T2. That is, the orthographic projection of the first channel portion a21 of the compensation transistor T2 on the substrate 10 overlaps with the orthographic projection of the first control electrode g21 of the compensation transistor T2 on the substrate 10. And, the second channel portion a22 of the compensation transistor T2 is opposite to the second control electrode g22 of the compensation transistor T2. That is, the orthographic projection of the second channel portion a22 of the compensation transistor T2 on the substrate 10 overlaps with the orthographic projection of the second control electrode g22 of the compensation transistor T2 on the substrate 10.

[0249] With the above arrangement, the compensation transistor T2 can be a double-gate transistor, which can improve the problem of leakage current from the compensation transistor T2 to the first node N1. Furthermore, it is beneficial to improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0250] In some embodiments, in combination with Figures 9 to 14 As shown, in some examples, in combination with Figure 13 and Figure 14 As shown, the first initialization signal line Vinit1 further includes a second auxiliary portion F2, and the second auxiliary portion F2 is located on the side of the body portion B1 of the first initialization signal line Vinit1 close to the driving transistor. That is, the portion of the first initialization signal line Vinit protruding toward the driving transistor T3 is the second auxiliary portion F2. The orthographic projection of the second auxiliary portion F2 on the substrate 10 overlaps at least partially with the orthographic projection of the second conductive portion U2 on the substrate 10.

[0251] It is equivalent to setting the positive projection of the second auxiliary portion F2 on the substrate 10 to at least partially overlap with the positive projection of the conductive portion (second conductive portion U2) between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 on the substrate 10. Therefore, the second auxiliary portion F2 of the first initialization signal line Vinit1 can form a capacitor with the second conductive portion U2 between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2.

[0252] Since the first initialization signal transmitted by the first initialization signal line Vinit1 is a constant voltage signal. Based on this, it is convenient to improve the stability of the compensation transistor T2 and improve the problem of leakage current to the first node N1 via the compensation transistor T2. Furthermore, it is beneficial to improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0253] Among them, the positive projection of the second auxiliary portion F2 on the substrate 10 and the positive projection of the second conductive portion U2 on the substrate 10 at least partially overlap, which can include the following two cases.

[0254] The first case: The positive projection of the second auxiliary portion F2 on the substrate 10 overlaps with the positive projection of a part of the second conductive portion U2 on the substrate 10. That is, the positive projection of a part of the second conductive portion U2 on the substrate 10 is located within the boundary of the positive projection of the second auxiliary portion F2 on the substrate 10.

[0255] The second case: The positive projection of the second conductive portion U2 on the substrate 10 is entirely located within the boundary of the positive projection of the second auxiliary portion F2 on the substrate 10.

[0256] Regardless of any of the above overlapping situations between the second auxiliary portion F2 and the second conductive portion U2, a capacitor can be formed between the two, which is convenient to improve the stability of the compensation transistor T2 and improve the problem of leakage current to the first node N1 via the compensation transistor T2.

[0257] Among them, compared with the first method, the second method can further increase the overlapping area of the positive projections between the second conductive portion U2 and the second auxiliary portion F2. Thus, it is beneficial to increase the capacitance formed between the second conductive portion U2 and the second auxiliary portion F2, so as to better improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0258] In some embodiments, in combination with Figures 9 to 14As shown, the second conductive part U2 includes a first sub-part U21 and a second sub-part U22. The first sub-part U21 protruding toward the first channel part a21 of the compensation transistor T2 in the second conductive part U2 can be electrically connected to the first channel part a21, and the second sub-part U22 protruding toward the second channel part a22 of the compensation transistor T2 in the second conductive part U2 can be electrically connected to the second channel part a22.

[0259] Based on this, the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 are electrically connected by utilizing the second conductive portion U2.

[0260] In some examples, the second conductive portion U2 may include a third sub-portion U23 on the basis of the first sub-portion U21 and the second sub-portion U22. The first sub-portion U21, the second sub-portion U22 and the third sub-portion U23 intersect at the same point, and the third sub-portion U23 is located on the side of the second sub-portion U22 away from the second channel portion a22. The second conductive portion U2 consisting of the first sub-portion U21, the second sub-portion U22 and the third sub-portion U23 is formed on the substrate 10 (such as Figure 3 The shape of the orthographic projection on the surface is “├”.

[0261] Since the third sub-portion U23 is located on the side of the second sub-portion U22 away from the second channel portion a22, that is, the main body B1 of the first initialization signal line Vinit1 of the third sub-portion U23, the orthographic projection of the third sub-portion U23 on the base substrate 10 is located within the boundary of the orthographic projection of the second auxiliary portion F2 on the base substrate 10. This is equivalent to increasing the size of the second conductive portion U2 by using the third sub-portion U23, thereby increasing the facing area between the second conductive portion U2 and the second auxiliary portion F2, thereby increasing the capacitance of the capacitor formed between the second conductive portion U2 and the second auxiliary portion F2, so as to better improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0262] In some embodiments, in combination Figures 9 to 16 As shown, the pixel driving circuit Q further includes a first light emitting control transistor T5 and a second light emitting control transistor T6, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are located on the same side of the driving transistor T3.

[0263] Furthermore, along the first direction X, the first light emission control transistor T5 and the second light emission control transistor T6 overlap. In other words, the first light emission control transistor T5 and the second light emission control transistor T6 are arranged side by side along the first direction X. The first light emission control transistor T5 is closer to the first electrode s3 of the driving transistor T3 than the second light emission control transistor T6, and the second light emission control transistor T6 is closer to the second electrode d3 of the driving transistor T3 than the first light emission control transistor T5.

[0264] Based on this, the distance between the first light-emitting control transistor T5 and the first pole s3 of the driving transistor T3 can be reduced, and the distance between the second light-emitting control transistor T6 and the second pole d3 of the driving transistor T3 can be reduced. It is convenient to connect the second pole d5 of the first light-emitting control transistor T5 to the first pole s3 of the driving transistor T3, and connect the first pole s6 of the second light-emitting control transistor T6 to the second pole d3 of the driving transistor T3.

[0265] In some embodiments, in combination with Figures 9 to 16 As shown, the first routing metal layer SD1 further includes a first enable signal line EM1 and a second enable signal line EM2.

[0266] When the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are on the same side of the driving transistor T3, along the second direction Y, the first enable signal line EM1 electrically connected to the first light-emitting control transistor T5 is located between the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6, and the control electrode g3 of the driving transistor T3. That is, the first enable signal line EM1 is located on the side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6 that is close to the control electrode g3 of the driving transistor T3. And, the second enable signal line EM2 electrically connected to the second light-emitting control transistor T6 is arranged on the side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6 that is far from the control electrode g3 of the driving transistor T3.

[0267] In other words, one of the first enable signal line EM1 and the second enable signal line EM2 can be arranged on one side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6, and the other of the first enable signal line EM1 and the second enable signal line EM2 can be arranged on the other side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6.

[0268] Thus, it is possible to drive two light-emitting control transistors respectively by using two enable signal lines, and the space of the first routing metal layer SD1 of the display panel can be fully utilized, and the distance between the first enable signal line EM1 and the second enable signal line EM2 can be increased to avoid conductive components located between the first enable signal line EM1 and the second enable signal line EM2 in the first routing metal layer SD1.

[0269] In some embodiments, in combination with Figures 9 to 16As shown, the first enable signal line EM1 includes a first portion and a second portion. Among them, along the second direction Y, the first portion is located between the control electrode g3 of the driving transistor T3 and the control electrode g6 of the second light-emitting control transistor T6, and the second portion is located between the control electrode g3 of the driving transistor T3 and the control electrode g5 of the first light-emitting control transistor T5.

[0270] The first portion of the first enable signal line EM1 can be set to be closer to the control electrode g3 of the driving transistor T3 than the second portion of the first enable signal line EM1, while increasing the first enable signal line EM1 of this portion and the second light-emitting control transistor T6, so as to prevent the positive projection of the first enable signal line EM1 on the substrate from overlapping with the positive projection of the second light-emitting control transistor T6 on the substrate, so as to prevent affecting the subsequent electrical connection between the second light-emitting control transistor T6 and the second reset transistor T7.

[0271] In some embodiments, in combination with Figures 9 to 16 As shown, the second enable signal line EM2 further includes a second auxiliary portion F2 protruding toward the control electrode g6 of the second light-emitting control transistor T6, and the second auxiliary portion F2 extends along the second direction Y.

[0272] Based on this, the second enable signal line EM can be moved away from the driving transistor T3 by using the second auxiliary portion F2. Furthermore, the distance between the second enable signal line EM2 and the first light-emitting control transistor T5 can be increased. Thus, the conductive component located between the first enable signal line EM1 and the second enable signal line EM2 in the first wiring metal layer SD1 layer can be avoided.

[0273] In some embodiments, in combination with Figures 9 to 14 As shown, on the basis that the first scan signal line G1 is multiplexed as the second reset signal line R2: the control electrode of the second reset transistor T7 is electrically connected to the first scan signal line G1, and the control electrode g4 of the data writing transistor T4 is also electrically connected to the first scan signal line G1.

[0274] Thus, it is set that along the first direction X, the control electrode g4 of the data writing transistor T4 and the control electrode g7 of the second reset transistor T7 overlap.

[0275] It can facilitate the electrical connection between the first scan signal line G1 and the control electrode g4 of the data writing transistor T4 and the control electrode g7 of the second reset transistor T7. There is no need to provide a bending portion / avoiding portion, etc. on the first scan signal line G1, which can simplify the layout of the film layer structure of the pixel driving circuit Q.

[0276] In some embodiments, in combination with Figures 9 to 14As shown, the semiconductor layer POLY includes the first pole s1 of the driving transistor T3, the second pole d5 of the first light-emitting control transistor T5, and the second pole d4 of the data writing transistor T4. The semiconductor layer POLY further includes a third conductive portion U3, and the third conductive portion U3 electrically connects the first pole s1 of the driving transistor T3, the second pole d5 of the first light-emitting control transistor T5, and the second pole d4 of the data writing transistor T4. That is, the third connection portion L3 is used to electrically connect the first pole s1, the second pole d5 of the first light-emitting control transistor T5, and the second pole d4 of the data writing transistor T4 to the second node N2 (as Figure 6 shown).

[0277] The second gate metal layer Gate2 further includes a fourth conductive portion U4. One end of the fourth conductive portion U4 is electrically connected to the second electrode plate Cst-2 of the storage capacitor Cst, and the other end of the fourth conductive portion U4 is electrically connected to the first pole s5 of the first light-emitting control transistor T5. Subsequently, the fourth conductive portion U4 is electrically connected to the first power supply signal line VDD to realize that both the second electrode plate Cst-2 of the storage capacitor Cst and the first pole s5 of the first light-emitting control transistor T5 are electrically connected to the first power supply signal line VDD.

[0278] Since the first electrode plate C1-1 of the first capacitor C1 is electrically connected to the second node N2, and the second electrode plate C1-2 of the first capacitor C1 is electrically connected to the first pole s5 of the first light-emitting control transistor T5.

[0279] Thus, the orthographic projection of the fourth conductive portion U4 on the substrate 10 overlaps with the orthographic projection of the third conductive portion U3 on the substrate 10. So that the third conductive portion U3 is reused as the first electrode plate C1-1 of the first capacitor C1, and the fourth conductive portion U4 is reused as the second electrode plate C1-2 of the first capacitor C1.

[0280] Based on this, there is no need to separately fabricate the first electrode plate C1-1 and the second electrode plate C1-2 of the first capacitor C1, which can simplify the manufacturing process of the pixel driving circuit Q in the display panel 100.

[0281] In addition, since the fourth conductive portion U4 (the second electrode plate C1-2 of the first capacitor C1) is electrically connected to the second electrode plate Cst-2 of the storage capacitor Cst. It can be understood that the second electrode plate C1-2 of the first capacitor C1 and the second electrode plate Cst-2 of the storage capacitor Cst are an integral body. Furthermore, the size of the second electrode plate Cst-2 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Thus, the discharge duration of the first capacitor C1 to the first node N1 can be prolonged during the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can also be further extended, which is beneficial to improving the display uniformity of the display panel.

[0282] In some examples, the fourth conductive portion U4 and the second electrode plate Cst-2 of the storage capacitor Cst are disposed on the same layer.

[0283] Based on this, the fourth conductive portion U4 and the second electrode plate Cst-2 of the storage capacitor Cst can be formed by a single lithography process, which is convenient for simplifying the manufacturing process of the pixel driving circuit Q.

[0284] It should be noted that "on the same layer" means a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask through a single lithography process. According to the different specific patterns, a single lithography process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0285] In some embodiments, as Figure 10 and Figure 14 shown, one side of the third conductive portion U3 close to the channel portion a5 of the first light-emitting control transistor T5 is connected to the channel portion a5 of the first light-emitting control transistor T5. That is, it is equivalent to that the third conductive portion U3 extends along the second direction Y to the position of the channel portion a5 of the first light-emitting control transistor T5 and is connected to the channel portion a5 of the first light-emitting control transistor T5.

[0286] Thus, the length of the third conductive portion U3 along the second direction Y can be increased. Furthermore, the size of the first electrode plate C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased.

[0287] Based on this, the discharge duration of the first capacitor C1 to the first node N1 can be increased during the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the time for writing the data writing signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0288] In some embodiments, as Figure 10 and Figure 14 shown, one side of the third conductive portion U3 close to the channel portion a3 of the driving transistor T3 is connected to the channel portion a3 of the driving transistor T3. That is, it is equivalent to extending the third conductive portion U3 to the position of the channel portion a3 of the driving transistor T3 and connecting it to the channel portion a3 of the driving transistor T3 to increase the size of the third conductive portion U3.

[0289] Thus, the size of the first electrode C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge duration of the first capacitor C1 to the first node N1 can be increased during the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the time for writing the data writing signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0290] In some embodiments, as Figure 10 and Figure 14 shown, one side of the third conductive portion U3 close to the channel portion a4 of the data writing transistor T4 is connected to the channel portion a4 of the data writing transistor T4. That is, it is equivalent to extending the third conductive portion U3 to the position of the channel portion a4 of the data writing transistor T4 and connecting it to the channel portion a4 of the data writing transistor T4 to increase the size of the third conductive portion U3.

[0291] Thus, the size of the first electrode C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge duration of the first capacitor C1 to the first node N1 can be increased during the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the time for writing the data writing signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0292] In some embodiments, as Figure 10 and Figure 14 shown, along the second direction Y, the side of the third conductive portion U3 facing away from the channel portion a5 of the first light-emitting control transistor T5 protrudes from the channel portion a5 of the driving transistor T3.

[0293] It is equivalent to extending the third conductive portion U3 along the second direction Y out of the channel portion a5 of the driving transistor T3 to maximize the length of the third conductive portion U3 in the space of the semiconductor layer POLY in the second direction Y.

[0294] Thus, the size of the first electrode C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge duration of the first capacitor C1 to the first node N1 can be increased during the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the time for writing the data writing signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0295] In some embodiments, as Figure 13 and Figure 14 shown, the fourth conductive portion U4 includes a fourth auxiliary portion F4 protruding toward the control electrode g5 of the first light-emitting control transistor T5. Among them, the fourth auxiliary portion F4 is on the substrate (such as Figure 3The positive projection on the (as shown) overlaps at least partially with the second pole d5 of the first light-emitting control transistor T5.

[0296] Thus, the size of the second electrode plate C1-2 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, during the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off, the discharge duration of the first capacitor C1 to the first node N1 can be prolonged. Therefore, the time for writing the data writing signal can also be further extended, which is beneficial to improving the display uniformity of the display panel.

[0297] In some embodiments, as Figure 9 shown, along the first direction X, two adjacent pixel driving circuits Q are symmetrical. Exemplarily, along the first direction X, two adjacent pixel driving circuits Q are mirror-symmetrical.

[0298] Based on this, the regularity of the pixel driving circuits Q in the display panel 100 can be improved, which is convenient for simplifying the layout of the pixel driving circuits Q in the display panel 100.

[0299] In some embodiments, as Figures 9 to 17 shown, in the case where two adjacent pixel driving circuits Q are symmetrical along the first direction X: the first pole s3 of the driving transistor T3 of the nth pixel driving circuit Q along the first direction X can be set to be adjacent to the first pole s3 of the driving transistor T3 in the (n + 1)th pixel driving circuit Q. Wherein, n is a positive integer.

[0300] When the first poles s3 of the driving transistors T3 of two adjacent pixel driving circuits Q are adjacent along the first direction X, the second electrode plate Cst-2 of the storage capacitor Cst located on the second gate metal layer Gate2 does not need to avoid the second pole d3 of the driving transistor T3. It can be ensured that the positive projection of the second electrode plate Cst-2 of the storage capacitor Cst on the substrate 10 (as Figure 3 shown) covers the positive projection of the first pole s3 of the driving transistor T3 on the substrate 10.

[0301] Thus, the problem that the second electrode plates Cst-2 of the storage capacitors Cst in two adjacent pixel driving circuits Q do not need to consider avoidance can be realized, and the space between the second electrode plates Cst-2 of the storage capacitors Cst of the two pixel driving circuits Q can be directly filled. That is to say, the space utilization rate in the horizontal direction of the driving circuit layer can be fully utilized, and the size of the second electrode plate Cst-2 of the storage capacitor Cst can be increased, which is beneficial to increasing the capacitances of the storage capacitor Cst and the first capacitor C1.

[0302] In some examples, n = 1 is taken as an example for introduction. In the first direction X, the first pole s3 of the driving transistor T3 of the first pixel driving circuit Q is adjacent to the first pole s3 of the driving transistor T3 in the second pixel driving circuit Q. Here, n is a positive integer.

[0303] Thus, the second pole d3 of the driving transistor T3 of the first pixel driving circuit Q is located on the side of the first pixel driving circuit Q away from the second pixel driving circuit Q. Also, the second pole d3 of the driving transistor T3 in the second pixel driving circuit Q is located on the side of the second pixel driving circuit Q away from the first pixel driving circuit Q.

[0304] Based on this, it can be made such that the positive projection of the second plate Cst-2 of the storage capacitor Cst on the substrate 10 (as Figure 3 shown) covers the positive projection of the first pole s3 of the driving transistor T3 on the substrate 10, and the second plate Cst-2 of the storage capacitor Cst does not need to avoid the second pole d3 of the driving transistor T3. That is, the second plate Cst-2 of the storage capacitor Cst can directly cover the space between the second poles d3 of the driving transistors T3 of two pixel driving circuits Q, making full use of the horizontal space utilization rate of the driving circuit layer.

[0305] In some embodiments, as Figures 9 to 17 shown, in the case where two adjacent pixel driving circuits Q are symmetrically arranged along the first direction X: it can be made such that the second plate Cst-2 of the storage capacitor Cst of the nth pixel driving circuit Q is electrically connected to the second plate Cst-2 of the storage capacitor Cst in the (n + 1)th pixel driving circuit Q. Here, n is a positive integer.

[0306] Based on this, the size of the second plate Cst-2 of the storage capacitor Cst in the pixel driving circuit Q can be increased. Thus, the size of the second plate C1-2 of the first capacitor C1 can also be increased synchronously, increasing the capacitance of the first capacitor C1. Furthermore, the discharge duration of the first capacitor C1 to the first node N1 within the period after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off can be increased. Therefore, the time for writing the data writing signal can also be further extended, which is beneficial to improving the display uniformity of the display panel.

[0307] In some examples, n = 1 is taken as an example for introduction. In the first direction X, the first pole s3 of the driving transistor T3 of the first pixel driving circuit Q is adjacent to the first pole s3 of the driving transistor T3 in the second pixel driving circuit Q. Here, n is a positive integer.

[0308] Thus, the second electrode plate Cst-2 of the storage capacitor Cst of the first pixel driving circuit Q is electrically connected to the second electrode plate Cst-2 of the storage capacitor Cst of the second pixel driving circuit Q. Furthermore, it is equivalent to setting that the third conductive part U3 corresponding to the first pixel driving circuit Q is connected to the third conductive part U3 corresponding to the second pixel driving circuit Q.

[0309] Based on this, the size of the second electrode plate Cst-2 of the storage capacitor Cst in the pixel driving circuit Q can be increased, and the size of the second electrode plate C1-2 of the first capacitor C1 can be increased. Therefore, the time for writing the data write signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0310] In some embodiments, as Figures 9 to 17 shown, since along the first direction X, the second poles d2 of the second reset transistor T7 and the driving transistor T3 are respectively located in the two side regions of the pixel driving circuit Q. On the basis that the first pole s3 of the driving transistor T3 in the nth pixel driving circuit Q is adjacent to the first pole s3 of the driving transistor T3 in the (n + 1)th pixel driving circuit Q, the second reset transistor T7 in the (n + 1)th pixel driving circuit Q can be arranged adjacent to the second reset transistor T7 in the (n + 2)th pixel driving circuit Q. Wherein, n is a positive integer.

[0311] Furthermore, the first pole s7 of the second reset transistor T7 in the (n + 1)th pixel driving circuit Q can be arranged adjacent to the first pole s7 of the second reset transistor T7 in the (n + 2)th pixel driving circuit Q.

[0312] Based on this, it is convenient to electrically connect the first initialization signal line Vinit1 to the first pole s7 of the second reset transistor T7 in the (n + 1)th pixel driving circuit Q and the first pole s7 of the second reset transistor T7 in the (n + 2)th pixel driving circuit Q. There is no need to provide a bending part / avoiding part, etc. on the first initialization signal line Vinit1, which can simplify the layout of the film layer structure of the pixel driving circuit Q.

[0313] In some examples, the first pole s7 of the second reset transistor T7 in the (n + 1)th pixel driving circuit Q is multiplexed as the first pole s7 of the second reset transistor T7 in the (n + 2)th pixel driving circuit Q.

[0314] Based on this, there is no need to separately set the first pole s7 of the second reset transistor T7 in the (n + 2)-th pixel driving circuit Q, which can simplify the manufacturing process of the pixel driving circuit Q in the display panel 100. In addition, since the first pole s7 of the second reset transistor T7 in the (n + 1)-th pixel driving circuit Q is directly multiplexed as the first pole s7 of the second reset transistor T7 in the (n + 2)-th pixel driving circuit Q, and the first initialization signal line Vinit1 is directly electrically connected to the first pole s7 of the second reset transistor T7 in the (n + 1)-th pixel driving circuit Q, it can be realized that it is also electrically connected to the first pole s7 of the second reset transistor T7 in the (n + 2)-th pixel driving circuit Q.

[0315] Thus, the film layer structure of the pixel driving circuit Q can be simplified, which is convenient for simplifying the process of the pixel driving circuit Q.

[0316] Figure 18 FIG. is a film layer structure diagram of a plurality of pixel driving circuits according to still other embodiments. Figure 19 is Figure 18 a structure diagram of the bottom shielding layer in. Among them, Figure 18 the pixel driving circuit Q shown Figure 9 is different from the pixel driving circuit Q shown in that the display panel 100 further includes a bottom shielding layer 40.

[0317] In some embodiments, as shown in combination with Figure 18 and Figure 19 , the display panel 100 further includes a bottom shielding layer (Bottom Shield Metal, abbreviated as BSM) 40. The bottom shielding layer 40 is located between the substrate 10 (as shown in Figure 3 ) and the pixel driving circuit Q. The orthographic projection of the bottom shielding layer 40 on the substrate 10 covers the orthographic projection of the driving transistor T3 on the substrate 10.

[0318] Based on this, the bottom shielding layer 40 can be used to shield the influence of static electricity on the driving transistor T3. In addition, the bottom shielding layer 40 can also be used as a light shielding layer to reduce the influence of external light incident from one side of the substrate 10 on the semiconductor layer POLY, and improve the performance of the semiconductor layer POLY.

[0319] In some examples, the orthographic projection of the driving transistor T3 on the substrate 10 is located within the boundary of the orthographic projection of the bottom shielding layer 40 on the substrate 10, which can enable the bottom shielding 40 to completely cover the driving transistor T3 to shield the influence of static electricity on the driving transistor T3.

[0320] In some examples, the bottom shielding layer 40 is configured to receive a first power signal. Based on this, the static electricity accumulation generated by the bottom shielding layer 40 can be reduced.

[0321] In addition, two bottom shielding layers 40 corresponding to two adjacent pixel driving circuits Q can be electrically connected through a connecting portion, which can reduce the impedance of the bottom shielding layer 40.

[0322] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claimed rights.

Claims

1. A display panel, characterized in that, It includes a display area and a bonding area, and the bonding area is located on one side of the display area; the display area includes a middle area and two edge areas, and along a first direction, the middle area is located between the two edge areas; The display panel includes: a substrate; and, a driving circuit layer located on one side of the substrate; the driving circuit layer includes: a plurality of pixel driving circuits arranged in multiple rows and columns in the display area; the pixel driving circuit includes a driving transistor and a first reset transistor; The control electrode of the driving transistor is electrically connected to a first node, the first pole of the driving transistor is electrically connected to a second node, and the second pole of the driving transistor is electrically connected to a third node; The control electrode of the first reset transistor is electrically connected to a first reset signal line, the first pole of the first reset transistor is electrically connected to a first initialization signal line, and the second pole of the first reset transistor is electrically connected to the first node; a plurality of data writing signal lines located in the display area, and the plurality of data writing signal lines are arranged along the first direction and extend along a second direction, and the second direction intersects with the first direction; one data writing signal line is connected to one column of the pixel driving circuits; a plurality of data leads, the data leads include a first lead segment and a second lead segment, one end of the first lead segment is electrically connected to a data writing signal line located in the edge area, and the other end of the first lead segment is electrically connected to one end of the second lead segment; the first lead segment extends along the first direction, the second lead segment extends along the second direction, and the second lead segment extends from the middle area to the bonding area; In the direction away from the substrate, the driving circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer and a second routing metal layer; The semiconductor layer includes a first conductive portion, and the first conductive portion includes the second pole of the first reset transistor; the second gate metal layer includes a first shielding portion, and the first shielding portion is configured to have a constant voltage signal; the first routing metal layer includes the first lead segment; the second routing metal layer includes the data writing signal line and the second lead segment; wherein, the orthographic projection of the first shielding portion on the substrate, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first lead segment on the substrate have an overlap.

2. The display panel according to claim 1, wherein The second gate metal layer further includes the first initialization signal line, and the first reset signal line is connected to the first shielding portion.

3. The display panel according to claim 2, wherein The first initialization signal line includes a first auxiliary portion protruding towards the first reset transistor, and the orthographic projection of the first auxiliary portion on the substrate, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first lead segment on the substrate have an overlap; the first auxiliary portion is multiplexed as the first shielding portion.

4. The display panel according to claim 1, characterized in that The pixel driving circuit further includes: A compensation transistor, wherein a control electrode of the compensation transistor is electrically connected to a second scan signal line, a first pole of the compensation transistor is electrically connected to the third node, and a second pole of the compensation transistor is electrically connected to the first node; The compensation transistor is a double-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode; The semiconductor layer further includes: a first channel portion of the compensation transistor, a second channel portion of the compensation transistor, and a second conductive portion, one end of the second conductive portion is connected to the first channel portion, and the other end of the second conductive portion is connected to the second channel portion; The first initialization signal line further includes a second auxiliary portion protruding toward the driving transistor, and a positive projection of the second auxiliary portion on the substrate at least partially overlaps a positive projection of the second conductive portion on the substrate.

5. The display panel according to claim 4, wherein A positive projection of the second conductive portion on the substrate is located within a boundary of a positive projection of the second auxiliary portion on the substrate.

6. The display panel according to claim 4 or 5, characterized in that, The second conductive portion includes a first sub-portion, a second sub-portion, and a third sub-portion, and the first sub-portion, the second sub-portion, and the third sub-portion intersect at the same point; wherein, the first sub-portion is electrically connected to the first channel portion, the second sub-portion is electrically connected to the second channel portion, and the third sub-portion is located on a side of the second sub-portion away from the second channel portion.

7. The display panel according to claim 1, wherein The pixel driving circuit further includes: A data writing transistor, wherein a control electrode of the data writing transistor is connected to a first scan signal line, a first pole of the data writing transistor is electrically connected to the data writing signal line, and a second pole of the data writing transistor is electrically connected to the second node; A second reset transistor, wherein a control electrode of the second reset transistor is electrically connected to the first scan signal line, a first pole of the second reset transistor is electrically connected to a second initialization signal line, and a second pole of the second reset transistor is electrically connected to a fourth node; Along the first direction, the control electrodes of the data writing transistor and the second reset transistor overlap.

8. The display panel according to claim 1, wherein The pixel driving circuit further includes: A first light-emitting control transistor, wherein a control electrode of the first light-emitting control transistor is electrically connected to a first enable signal line, a first pole of the first light-emitting control transistor is electrically connected to a first power supply signal line, and a second pole of the first light-emitting control transistor is electrically connected to the second node; A second light-emitting control transistor, wherein a control electrode of the second light-emitting control transistor is electrically connected to a second enable signal line, a first pole of the second light-emitting control transistor is electrically connected to the third node, and a second pole of the second light-emitting control transistor is electrically connected to the fourth node.

9. The display panel according to claim 1, wherein The pixel driving circuit further includes: A storage capacitor, wherein a first electrode plate of the storage capacitor is electrically connected to the first node, and a second electrode plate of the storage capacitor is electrically connected to the first power supply signal line; A first capacitor, wherein a first electrode plate of the first capacitor is electrically connected to the second node, and a first electrode plate of the first capacitor is electrically connected to the first power supply signal line.

10. The display panel according to claim 9, wherein The pixel driving circuit includes a data writing transistor and a first light-emitting control transistor; The semiconductor layer includes a third conductive portion, and the third conductive portion includes a first pole of the driving transistor, a second pole of the first light-emitting control transistor, and a second pole of the data writing transistor; The second gate metal layer further includes a fourth conductive portion, one end of the fourth conductive portion is electrically connected to a second electrode plate of the storage capacitor, and the other end of the fourth conductive portion is electrically connected to a first pole of the first light-emitting control transistor; A positive projection of the fourth conductive portion on the substrate overlaps at least partially with a positive projection of the third conductive portion on the substrate; Wherein, the third conductive portion is multiplexed as a first electrode plate of the first capacitor, and the fourth conductive portion is multiplexed as a second electrode plate of the first capacitor.

11. The display panel according to claim 10, wherein Along the second direction, a side of the third conductive portion facing away from the channel portion of the first light-emitting control transistor protrudes from the channel portion of the driving transistor.

12. The display panel according to claim 1, wherein, Along the first direction, two adjacent pixel driving circuits are symmetrical.

13. The display panel according to claim 12, wherein Along the first direction, a first pole of the driving transistor of the nth pixel driving circuit is adjacent to a first pole of the driving transistor of the (n + 1)th pixel driving circuit; wherein, n is a positive integer.

14. The display panel according to claim 12 or 13, wherein A second electrode plate of the storage capacitor of the nth pixel driving circuit is electrically connected to a second electrode plate of the storage capacitor in the (n + 1)th pixel driving circuit; wherein, n is a positive integer.

15. The display panel according to claim 14, wherein Along the first direction, a second reset transistor in the (n + 1)th pixel driving circuit is adjacent to a second reset transistor in the (n + 2)th pixel driving circuit, and a first pole of the second reset transistor in the (n + 1)th pixel driving circuit is multiplexed as a first pole of the second reset transistor in the (n + 2)th pixel driving circuit.

16. The display panel according to claim 1, wherein, The first wiring metal layer further includes a plurality of first virtual lead segments, the first virtual lead segments correspond to the first lead segments one by one, and along the first direction, the first lead segments and the first virtual lead segments are arranged at intervals.

17. The display panel according to claim 1, wherein The second wiring metal layer further includes a plurality of second virtual lead segments, the second virtual lead segments correspond to the second lead segments one by one, and along the first direction, the second lead segments and the second virtual lead segments are arranged at intervals.

18. The display panel according to claim 1, characterized in that, It further includes a bottom shielding layer, which is located between the substrate and the pixel driving circuit, and a positive projection of the bottom shielding layer on the substrate covers a positive projection of the driving transistor on the substrate.

19. The display panel according to claim 1, wherein It further includes: A light-emitting device layer, which is located on a side of the driving circuit layer away from the substrate; the light-emitting device layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the pixel driving circuits.

20. A display device, characterized in that, Including the display panel according to any one of claims 1 to 19.

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