Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises an array substrate, the array substrate comprises a substrate, a first conductive layer, an insulating layer and a second conductive layer, the first conductive layer comprises a first signal line and a second signal line which extend along a first direction, the second conductive layer comprises a third signal line and a fourth signal line which extend in the second direction, and the third signal line and the fourth signal line transmit the same signal; in the direction perpendicular to the substrate, the first signal line and the third signal line have a first overlapping area and are electrically connected in the first overlapping area, the second signal line and the fourth signal line have a fourth overlapping area and are electrically connected in the fourth overlapping area, and the first signal line and the fourth signal line have a second overlapping area and are insulated. The second signal line and the third signal line have a third overlapping area and are insulated. The orthographic projection of the second overlapping area and the orthographic projection of the third overlapping area on the substrate are at least partially located in the orthographic projection of the pixel opening on the substrate. The display panel provided by the invention can improve the color cast of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, televisions, laptop computers, and desktop computers due to their advantages of high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Embodiments of this application provide a display panel and a display device, which can improve the color shift of the display panel and enhance the performance of the display panel.

[0005] An embodiment of the first aspect of the embodiments of this application provides a display panel, including:

[0006] An array substrate, the array substrate includes a substrate and a first conductive layer, an insulating layer, and a second conductive layer sequentially stacked on one side of the substrate. The first conductive layer includes a first signal line and a second signal line extending along a first direction, the second conductive layer includes a third signal line and a fourth signal line extending along a second direction, the first direction intersects the second direction, the first signal line and the second signal line are arranged along the second direction, the third signal line and the fourth signal line are arranged along the first direction, and the third signal line and the fourth signal line transmit the same signal;

[0007] Along the direction perpendicular to the substrate, there is a first overlapping region between the first signal line and the third signal line, a second overlapping region between the first signal line and the fourth signal line, a third overlapping region between the second signal line and the third signal line, and a fourth overlapping region between the second signal line and the fourth signal line. The first signal line and the third signal line are electrically connected in the first overlapping region, the first signal line and the fourth signal line are insulated in the second overlapping region and / or the second signal line and the third signal line are insulated in the third overlapping region, and the second signal line and the fourth signal line are electrically connected in the fourth overlapping region. The orthographic projections of the first overlapping region and the fourth overlapping region on the substrate are both located outside the orthographic projection of the pixel opening on the substrate, and the orthographic projections of the second overlapping region and the third overlapping region on the substrate are both at least partially located within the orthographic projection of the pixel opening on the substrate, where the pixel opening is located on one side of the array substrate in the direction from the substrate to the insulating layer.

[0008] According to an embodiment of the first aspect of the present invention, the pixel opening includes a first pixel opening, and the orthographic projections of the second overlapping region and the third overlapping region on the substrate are both at least partially located within the orthographic projection of the first pixel opening on the substrate;

[0009] Preferably, the first pixel opening is used to accommodate a blue light-emitting unit.

[0010] According to any one of the foregoing embodiments of the first aspect of the present invention, the pixel opening further includes a second pixel opening. The first pixel opening and the second pixel opening are alternately arranged along the second direction, and the first pixel opening and the second pixel opening are also alternately arranged along the first direction. The first overlapping region and the fourth overlapping region are located between the adjacent first pixel opening and the second pixel opening along the second direction;

[0011] Preferably, the second pixel opening is used to accommodate a red light-emitting unit.

[0012] According to any one of the foregoing embodiments of the first aspect of the present invention, a plurality of the first pixel openings and the second pixel openings are alternately arranged along the second direction to form a first pixel column. In two adjacent first pixel columns, the first overlapping region and the third overlapping region are located in one of the first pixel columns, and the second overlapping region and the fourth overlapping region are located in the other first pixel column.

[0013] According to any one of the foregoing embodiments of the first aspect of the present invention, the pixel opening further includes a third pixel opening. A plurality of the third pixel openings are arranged along the second direction to form a second pixel column, and the first pixel column and the second pixel column are alternately arranged along the first direction.

[0014] According to any of the foregoing embodiments of the first aspect of the present invention, two of the first pixel openings and two of the second pixel openings are provided on the periphery of the third pixel opening, and the two first pixel openings and the two second pixel openings are alternately distributed on the periphery of the third pixel opening.

[0015] According to any of the foregoing embodiments of the first aspect of the present invention, the positive projection of the first signal line on the substrate does not overlap with the positive projections of the second pixel opening and the third pixel opening on the substrate, and the positive projection of the first signal line on the substrate passes through the positive projection of the first pixel opening on the substrate along the first direction;

[0016] Preferably, the positive projection of the second signal line on the substrate does not overlap with the positive projections of the second pixel opening and the third pixel opening on the substrate, and the positive projection of the second signal line on the substrate passes through the positive projection of the first pixel opening on the substrate along the first direction;

[0017] Preferably, the positive projection of the third signal line on the substrate does not overlap with the positive projection of the third pixel opening on the substrate, and the positive projection of the third signal line on the substrate passes through the positive projections of the first pixel opening and the second pixel opening on the substrate along the second direction;

[0018] Preferably, the positive projection of the fourth signal line on the substrate does not overlap with the positive projection of the third pixel opening on the substrate, and the positive projection of the fourth signal line on the substrate passes through the positive projections of the first pixel opening and the second pixel opening on the substrate along the second direction.

[0019] According to any of the foregoing embodiments of the first aspect of the present invention, the first signal line and the fourth signal line are insulated in the second overlapping region, and the second signal line and the third signal line are insulated in the third overlapping region;

[0020] Alternatively, the first signal line and the fourth signal line are insulated in the second overlapping region, and the second signal line and the third signal line are electrically connected in the third overlapping region;

[0021] Alternatively, the first signal line and the fourth signal line are electrically connected in the second overlapping region, and the second signal line and the third signal line are insulated in the third overlapping region;

[0022] Alternatively, the first signal line and the fourth signal line are insulated in part of the second overlapping region and electrically connected at a part of the preset second overlapping region, the second signal line and the third signal line are insulated in part of the third overlapping region and electrically connected at a part of the preset third overlapping region;

[0023] Preferably, the sum of the number of the part of the preset second overlapping region and the number of the part of the preset third overlapping region is half or one-fourth of the sum of the number of the second overlapping region and the number of the third overlapping region.

[0024] According to any of the foregoing embodiments of the first aspect of the present invention, the first conductive layer further includes a fifth signal line and a sixth signal line extending along the first direction, the second conductive layer further includes a seventh signal line and an eighth signal line extending along the second direction, the fifth signal line and the sixth signal line are arranged along the second direction, the seventh signal line and the eighth signal line are arranged along the first direction, and the seventh signal line and the eighth signal line transmit the same signal.

[0025] According to any of the foregoing embodiments of the first aspect of the present invention, the third signal line and the fourth signal line are arranged adjacent to each other along the first direction, and the seventh signal line and the eighth signal line are arranged adjacent to each other along the first direction; the fifth signal line is located between the adjacent first signal line and the second signal line, the sixth signal line is located between the adjacent first signal line and the second signal line, and the first signal line or the second signal line is arranged between the fifth signal line and the sixth signal line.

[0026] According to any of the foregoing embodiments of the first aspect of the present invention, the orthographic projection of the fifth signal line on the substrate does not overlap with the orthographic projections of the first pixel opening and the second pixel opening on the substrate, and the orthographic projection of the first signal line on the substrate passes through the orthographic projection of the third pixel opening on the substrate along the first direction;

[0027] Preferably, the orthographic projection of the sixth signal line on the substrate does not overlap with the orthographic projections of the first pixel opening and the second pixel opening on the substrate, and the orthographic projection of the sixth signal line on the substrate passes through the orthographic projection of the third pixel opening on the substrate along the first direction;

[0028] Preferably, the orthographic projection of the seventh signal line on the substrate does not overlap with the orthographic projection of the third pixel opening on the substrate, and the orthographic projection of the seventh signal line on the substrate passes through the orthographic projections of the first pixel opening and the second pixel opening on the substrate along the second direction;

[0029] Preferably, the positive projection of the eighth signal line on the substrate does not overlap with the positive projection of the third pixel opening on the substrate, and the positive projection of the eighth signal line on the substrate passes through the positive projection of the first pixel opening on the substrate and the positive projection of the second pixel opening on the substrate along the second direction.

[0030] According to any one of the foregoing embodiments of the first aspect of the present invention, the first signal line further includes a first extension portion, the first extension portion is connected to the second overlapping region, and is arranged with the second overlapping region along the second direction. At least a part of the positive projection of the first extension portion on the substrate is located outside the positive projection of the first pixel opening on the substrate. The first extension portion is electrically connected to the fourth signal line through a first through hole, and the positive projection of the first through hole on the substrate does not overlap with the positive projection of the first pixel opening on the substrate;

[0031] Preferably, the fifth signal line includes a first partition region for accommodating the first extension portion, and at least a part of the first extension portion is located in the first partition region.

[0032] According to any one of the foregoing embodiments of the first aspect of the present invention, the second signal line further includes a second extension portion, the second extension portion is connected to the third overlapping region, and is arranged with the third overlapping region along the second direction. At least a part of the positive projection of the second extension portion on the substrate is located outside the positive projection of the first pixel opening on the substrate. The second extension portion is electrically connected to the third signal line through a second through hole, and the positive projection of the second through hole on the substrate does not overlap with the positive projection of the first pixel opening on the substrate;

[0033] Preferably, the sixth signal line includes a second partition region for accommodating the second extension portion, and at least a part of the second extension portion is located in the second partition region.

[0034] According to any one of the foregoing embodiments of the first aspect of the present invention, there is a fifth overlapping region between the fifth signal line and the seventh signal line, a sixth overlapping region between the fifth signal line and the eighth signal line, a seventh overlapping region between the sixth signal line and the seventh signal line, and an eighth overlapping region between the sixth signal line and the eighth signal line. The fifth signal line and the seventh signal line are electrically connected in the fifth overlapping region, and the sixth signal line and the eighth signal line are electrically connected in the eighth overlapping region, and / or, the fifth signal line and the eighth signal line are electrically connected in the sixth overlapping region, and the sixth signal line and the seventh signal line are electrically connected in the seventh overlapping region.

[0035] According to any of the foregoing embodiments of the first aspect of the present invention, a first reset signal is provided in the third signal line, and a second reset signal is provided in the seventh signal line;

[0036] Preferably, it further includes a plurality of driving circuits, the driving circuits are electrically connected to at least one light-emitting unit, and the driving circuits include a first light-emitting control module, a first initialization module, and a second initialization module;

[0037] The control end of the second initialization module is electrically connected to the first scanning signal line, the first end of the second initialization module is electrically connected to the second reset signal line, and the second end of the second initialization module is electrically connected to the first end of the first light-emitting control module;

[0038] The control end of the first initialization module is electrically connected to the first scanning signal line, the first end of the first initialization module is electrically connected to the first reset signal line, and the second end of the first initialization module is electrically connected to the second end of the first light-emitting control module and the light-emitting unit.

[0039] According to any of the foregoing embodiments of the first aspect of the present invention, it further includes a first high-level signal line located in the second conductive layer. The first high-level signal line extends along the second direction, and in the orthographic projection of the first high-level signal line on the substrate, the portions within the orthographic projections of the second pixel opening and the first pixel opening on the substrate are symmetric about the axis of symmetry parallel to the second direction.

[0040] An embodiment of the second aspect of the present application further provides a display panel, the display panel includes an array substrate, the array substrate includes a substrate and a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer stacked in a direction away from the substrate, wherein:

[0041] The array substrate includes a first type of transistor, a second type of transistor, and a capacitor. The first semiconductor layer is used to form the source region, drain region, and channel region of the first type of transistor. The first metal layer is used to form the gate of the first type of transistor and the first electrode plate of the capacitor. The second metal layer is used to form the bottom gate of the second type of transistor. The second semiconductor layer is used to form the source region, drain region, and channel region of the second type of transistor. The third metal layer is used to form the top gate of the second type of transistor. The fourth metal layer is used to form the source electrodes and drain electrodes of the first type of transistor and the second type of transistor;

[0042] Among them, a first signal line and a second signal line extending in a first direction are formed in one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer. The first signal line and the second signal line are arranged along a second direction. The fourth metal layer is formed with a third signal line and a fourth signal line extending in the second direction. The third signal line and the fourth signal line are arranged along the first direction. The first direction intersects the second direction. The third signal line and the fourth signal line transmit the same signal;

[0043] Along a direction perpendicular to the substrate, there is a first overlapping region between the first signal line and the third signal line, a second overlapping region between the first signal line and the fourth signal line, a third overlapping region between the second signal line and the third signal line, and a fourth overlapping region between the second signal line and the fourth signal line. The first signal line and the third signal line are electrically connected in the first overlapping region. The first signal line and the fourth signal line are insulated in the second overlapping region and / or the second signal line and the third signal line are insulated in the third overlapping region. The second signal line and the fourth signal line are electrically connected in the fourth overlapping region. The orthographic projections of the first overlapping region and the fourth overlapping region on the substrate are both located outside the orthographic projection of the pixel opening on the substrate. The orthographic projections of the second overlapping region and the third overlapping region on the substrate are both at least partially located within the orthographic projection of the pixel opening on the substrate.

[0044] According to an embodiment of the second aspect of the present invention, a first insulating layer is formed between the first semiconductor layer and the first metal layer, a second insulating layer is formed between the first metal layer and the second metal layer, a third insulating layer is formed between the second metal layer and the second semiconductor layer, a fourth insulating layer is formed between the second semiconductor layer and the third metal layer, a fifth insulating layer is formed between the third metal layer and the fourth metal layer, a sixth insulating layer is formed between the fourth metal layer and the fifth metal layer. The third signal line and the fourth signal line are formed in the fourth metal layer;

[0045] The first signal line and the second signal line are formed in the first metal layer. The first signal line and the third signal line are electrically connected through a first via at the first overlapping region. The second signal line and the fourth signal line are electrically connected through a second via at the fourth overlapping region. The first via and the second via penetrate through the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer;

[0046] Alternatively, the first signal line and the second signal line are formed on the second metal layer. The first signal line and the third signal line are electrically connected through a first via hole at the first overlapping region, and the second signal line and the fourth signal line are electrically connected through a second via hole at the fourth overlapping region. The first via hole and the second via hole penetrate through the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer;

[0047] Alternatively, the first signal line and the second signal line are formed on the fourth metal layer. The first signal line and the third signal line are electrically connected through a first via hole at the first overlapping region, and the second signal line and the fourth signal line are electrically connected through a second via hole at the fourth overlapping region. The first via hole and the second via hole penetrate through the sixth insulating layer;

[0048] Alternatively, the first signal line and the second signal line are formed on the third metal layer. The first signal line and the third signal line are electrically connected through a first via hole at the first overlapping region, and the second signal line and the fourth signal line are electrically connected through a second via hole at the fourth overlapping region. The first via hole and the second via hole penetrate through the fifth insulating layer and the sixth insulating layer;

[0049] Preferably, the material of the first semiconductor layer includes polysilicon semiconductor, and the material of the second semiconductor layer includes metal oxide semiconductor.

[0050] According to any of the foregoing embodiments of the second aspect of the present invention, it further includes a light-emitting layer and an isolation structure located on one side of the array substrate. The light-emitting layer includes light-emitting units, and the isolation structure includes a body portion and an isolation opening formed in the body portion. The orthographic projection of the light-emitting unit on the array substrate is located within the orthographic projection of the isolation opening on the array substrate;

[0051] Preferably, the body portion includes a first isolation portion and a second isolation portion. The second isolation portion is located on the side of the first isolation portion away from the array substrate, and the orthographic projection of the second isolation portion on the array substrate covers the orthographic projection of the first isolation portion on the array substrate.

[0052] Preferably, the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate, and the second electrode is electrically connected to the first isolation portion.

[0053] An embodiment of the second aspect of the present application further provides a display device, including any one of the display panels provided by the first aspect of the present application.

[0054] In the above display panel provided by the present application, the signals in the first signal line and the third signal line are the same, and a first overlapping region is formed at the intersecting position and electrically connected, so that the first signal line and the third signal line form a mesh structure. The orthographic projection of the first overlapping region on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate. Therefore, the electrical connection between the first signal line and the third signal line can be realized through a via at the first overlapping region, and the via is not located within the pixel opening region, so that the display of the light-emitting unit corresponding to the pixel opening will not be affected by the uneven film layer above the via. The signals in the second signal line and the fourth signal line are the same, and a fourth overlapping region is formed at the intersecting position and electrically connected, so that the second signal line and the fourth signal line form a mesh structure. The orthographic projection of the fourth overlapping region on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate. That is, the electrical connection between the second signal line and the fourth signal line is realized through a via at the fourth overlapping region, and the via is not located within the pixel opening region, so that the display of the light-emitting unit corresponding to the pixel opening will not be affected by the uneven film layer above the via. There is a second overlapping region between the first signal line and the fourth signal line, and a third overlapping region between the second signal line and the third signal line. The first signal line and the fourth signal line are insulated at the second overlapping region, and the second signal line and the third signal line are insulated at the third overlapping region. The orthographic projections of the second overlapping region and the third overlapping region on the substrate are at least partially located within the orthographic projection of the pixel opening on the substrate. Therefore, vias do not need to be provided at the positions of the second overlapping region and the third overlapping region, so as not to affect the display yield of the light-emitting unit corresponding to the pixel opening. On the basis of realizing the electrical connection between the first signal line and the third signal line and the electrical connection between the second signal line and the fourth signal line, the orthographic projections of the vias required for electrical connection on the substrate in the display panel provided by the present application are all located outside the orthographic projection of the pixel opening on the substrate, which improves the problem of large color deviation caused by the influence of the via on the electrode flatness of the light-emitting unit within the pixel opening, thereby improving the display quality of the display panel. Description of the Drawings

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0056] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0057] Figure 2 is Figure 1 a cross-sectional view taken along P-P' in

[0058] Figure 3 is Figure 1Partial enlarged view of area Q;

[0059] Figure 4 is Figure 1 Partial enlarged view of area Q;

[0060] Figure 5 is Figure 1 Partial enlarged view of area Q;

[0061] Figure 6 is Figure 1 Partial enlarged view of area Q;

[0062] Figure 7 is Figure 1 Partial enlarged view of area Q;

[0063] Figure 8 is Figure 1 Partial enlarged view of area Q;

[0064] Figure 9 is Figure 1 Partial enlarged view of area Q;

[0065] Figure 10 is Figure 1 Partial enlarged view of area Q;

[0066] Figure 11 is Figure 1 Partial enlarged view of area Q;

[0067] Figure 12 is Figure 11 Partial enlarged view of;

[0068] Figure 13 is Figure 1 Partial enlarged view of area Q;

[0069] Figure 14 is Figure 13 Partial enlarged view of;

[0070] Figure 15 is a circuit diagram of an in - driving circuit in a display panel provided by an embodiment of the present application;

[0071] Figure 16 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0072] Figure 17 is a schematic structural diagram of a display device provided by an embodiment of the present application.

[0073] In the accompanying drawings:

[0074] 1 - Display panel; 11 - Array substrate; 110 - Substrate; 111 - First conductive layer; 1111 - First signal line; 1112 - Second signal line; 1113 - Fifth signal line; 1114 - Sixth signal line; 112 - Second conductive layer; 1121 - Third signal line; 1122 - Fourth signal line; 1123 - Seventh signal line; 1124 - Eighth signal line; 12 - First overlapping region; 13 - Second overlapping region; 14 - Third overlapping region; 15 - Fourth overlapping region; 16 - Pixel opening; 161 - First pixel opening; 162 - Second pixel opening; 163 - Third pixel opening; 17 - First extension; 18 - Second extension; 19 - Fifth overlapping region; 20 - Sixth overlapping region; 21 - Seventh overlapping region; 22 - Eighth overlapping region; 23 - First semiconductor layer; 24 - First metal layer; 25 - Second metal layer; 26 - Second semiconductor layer; 27 - Third metal layer; 28 - Fourth metal layer; 29 - Fifth metal layer; 30 - First insulating layer; 31 - Second insulating layer; 32 - Third insulating layer; 33 - Fourth insulating layer; 34 - Fifth insulating layer; 35 - Sixth insulating layer; 36 - Light-emitting unit; 361 - First electrode; 362 - Light-emitting functional layer; 363 - Second electrode; 37 - Isolation structure; 371 - First isolation part; 372 - Second isolation part; 370 - Isolation opening; 100 - Driving module; 200 - Data writing module; 300 - Compensation module; 400 - Storage module; 500 - First light-emitting control module; 600 - Second light-emitting control module; 700 - First initialization module; 800 - Second initialization module; 900 - Third initialization module; Vref1 - First reset signal line; Vref2 - Second reset signal line; ELVDD - First high-level signal line; ELVSS - First low-level signal line; S1 - First scan signal line; S2 - Second scan signal line; S3 - Third scan signal line; S4 Fourth scan signal line; EM - Light-emitting control signal line; Data - Data signal line; Vref3 - Third reset signal line; 2 - Display device. Detailed implementation manners

[0075] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0076] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0077] For a better understanding of the present application, the following will be described in detail with reference to Figures 1 to 17 the display panel and the display device 2 according to the embodiments of the present application.

[0078] Please refer to Figures 1 to 3 , the embodiments of the present application provide a display panel 1, including an array substrate 11. The array substrate 11 includes a substrate 110, and a first conductive layer 111, an insulating layer, and a second conductive layer 112 sequentially stacked on one side of the substrate 110. The first conductive layer 111 includes a first signal line 1111 and a second signal line 1112 extending along a first direction x, and the second conductive layer 112 includes a third signal line 1121 and a fourth signal line 1122 extending along a second direction y. The first direction x intersects the second direction y. The first signal line 1111 and the second signal line 1112 are arranged along the second direction y, the third signal line 1121 and the fourth signal line 1122 are arranged along the first direction x, and the third signal line 1121 and the fourth signal line 1122 transmit the same signal.

[0079] Along the direction perpendicular to the substrate 110, there is a first overlapping region 12 between the first signal line 1111 and the third signal line 1121, a second overlapping region 13 between the first signal line 1111 and the fourth signal line 1122, a third overlapping region 14 between the second signal line 1112 and the third signal line 1121, and a fourth overlapping region 15 between the second signal line 1112 and the fourth signal line 1122. The first signal line 1111 and the third signal line 1121 are electrically connected in the first overlapping region 12, the first signal line 1111 and the fourth signal line 1122 are insulated in the second overlapping region 13 and / or the second signal line 1112 and the third signal line 1121 are insulated in the third overlapping region 14, and the second signal line 1112 and the fourth signal line 1122 are electrically connected in the fourth overlapping region 15.

[0080] The positive projections of the first overlapping region 12 and the fourth overlapping region 15 on the substrate 110 are both located outside the positive projection of the pixel opening 16 on the substrate 110, and the positive projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are both at least partially located inside the positive projection of the pixel opening 16 on the substrate 110, where the pixel opening 16 is located on one side of the array substrate 11 in the direction from the substrate 110 to the insulating layer.

[0081] In the above embodiment, the second conductive layer 112 is located on one side of the first conductive layer 111. Specifically, it can be located on the upper side of the first conductive layer 111 or on the lower side of the first conductive layer 111. This application does not make a special limitation on this.

[0082] In the above embodiment, the first overlapping region 12 is the region where the positive projections of the first signal line 1111 and the third signal line 1121 on the substrate 110 overlap. The second overlapping region 13 is the region where the positive projections of the first signal line 1111 and the third signal line 1121 on the substrate 110 overlap. The third overlapping region 14 is the region where the positive projections of the second signal line 1112 and the third signal line 1121 on the substrate 110 overlap. The fourth overlapping region 15 is the region where the positive projections of the second signal line 1112 and the fourth signal line 1122 on the substrate 110 overlap.

[0083] The pixel opening 16 is located on one side of the array substrate 11 in the direction from the substrate 110 to the insulating layer, that is, on the side of the second conductive layer 112 away from the substrate 110. The pixel opening 16 is used to accommodate and define the light-emitting unit.

[0084] In the display panel 1 provided by this application, the signals in the first signal line 1111 and the third signal line 1121 are the same, and a first overlapping region 12 is formed and electrically connected at the intersecting position, so that the first signal line 1111 and the third signal line 1121 form a mesh structure. The positive projection of the first overlapping region 12 on the substrate 110 does not overlap with the positive projection of the pixel opening 16 on the substrate 110. Thus, the electrical connection between the first signal line 1111 and the third signal line 1121 can be realized through a via at the first overlapping region 12. This via is not located in the pixel opening 16 region, so that the display of the light-emitting unit corresponding to the pixel opening 16 will not be affected by the uneven film layer above the via.

[0085] The signals in the second signal line 1112 and the fourth signal line 1122 are the same, and a fourth overlapping region 15 is formed at the intersecting position and electrically connected, so that the second signal line 1112 and the fourth signal line 1122 form a mesh structure. The orthographic projection of the fourth overlapping region 15 on the substrate 110 does not overlap with the orthographic projection of the pixel opening 16 on the substrate 110. That is, at the fourth overlapping region 15, the second signal line 1112 and the fourth signal line 1122 are electrically connected through vias, and the vias are not located within the pixel opening 16 region, so that the display of the light-emitting unit corresponding to the pixel opening 16 will not be affected by the unevenness of the film layer above the vias.

[0086] There is a second overlapping region 13 between the first signal line 1111 and the fourth signal line 1122, and a third overlapping region 14 between the second signal line 1112 and the third signal line 1121. The first signal line 1111 and the fourth signal line 1122 are insulated in the second overlapping region 13, and / or the second signal line 1112 and the third signal line 1121 are insulated in the third overlapping region 14. The orthographic projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are at least partially located within the orthographic projection of the pixel opening 16 on the substrate 110. Therefore, vias do not need to be provided at the position of the second overlapping region 13 and / or the third overlapping region 14, so as to reduce the number of vias and reduce the impact on the display yield of the light-emitting unit corresponding to the pixel opening 16.

[0087] Based on the above display panel 1 provided by the present application, when the third signal line 1121 and the fourth signal line 1122 transmit the same signal, and the first signal line 1111 and the third signal line 1121 are electrically connected, and the second signal line 1112 and the fourth signal line 1122 are electrically connected, most or all of the orthographic projections of the vias required for electrical connection on the substrate 110 are located outside the orthographic projection of the pixel opening 16 on the substrate 110, which improves the problem of large color deviation caused by the influence of the vias on the electrode flatness of the light-emitting unit in the pixel opening 16, thereby improving the display quality of the display panel 1.

[0088] In a feasible implementation manner, as Figure 4 shown, the pixel opening 16 includes a first pixel opening 161, and the orthographic projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are at least partially located within the orthographic projection of the first pixel opening 161 on the substrate 110.

[0089] In the above implementation manner, the pixel opening 16 is used to define the light-emitting unit. The light-emitting unit may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. Among them, the area of the blue light-emitting unit is relatively large, and its color deviation has the most serious impact on the yield of the display panel 1. The first pixel opening 161 can be used to accommodate the blue light-emitting unit.

[0090] The orthographic projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are both set to be at least partially located within the orthographic projection of the first pixel opening 161 on the substrate 110. Since vias do not need to be provided at the positions of the second overlapping region 13 and / or the third overlapping region 14, on the one hand, the influence of the second overlapping region 13 and / or the third overlapping region 14 on the planarization of the upper film layer can be reduced to ensure the yield of the blue light-emitting units and improve the problem of poor display of the blue light-emitting units corresponding to the first pixel opening 161 caused by the unevenness of the upper film layer due to the vias.

[0091] On the other hand, since the first pixel opening 161 is relatively large, the orthographic projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are both set to be at least partially located within the orthographic projection of the first pixel opening 161 on the substrate 110, thereby facilitating the simplification of the wiring difficulty and ensuring the wiring pitch. In a feasible implementation manner, the display panel 1 may further include a pixel definition layer formed on the side of one of the first conductive layer 111 and the second conductive layer 112 away from the substrate 110 and away from the substrate 110, which can be used to define the pixel opening 16.

[0092] In a feasible implementation manner, as Figure 4 shown, the pixel opening 16 further includes a second pixel opening 162. The first pixel opening 161 and the second pixel opening 162 are alternately arranged along the second direction y, and the first pixel opening 161 and the second pixel opening 162 are also alternately arranged along the first direction x. The first overlapping region 12 and the fourth overlapping region 15 are located between the first pixel opening 161 and the second pixel opening 162 adjacent along the second direction y. That is, the vias for electrically connecting the first signal line 1111 and the third signal line 1121 and the vias for electrically connecting the second signal line 1112 and the fourth signal line 1122 are arranged between the first pixel opening 161 and the second pixel opening 162, which can reduce the adverse effects on different color light-emitting units caused by the unevenness of the upper film layer due to the vias, so as to improve the display effect.

[0093] Specifically, the second pixel opening 162 can be used to accommodate the red light-emitting units.

[0094] In a feasible implementation manner, as Figure 4As shown, a plurality of first pixel openings 161 and second pixel openings 162 are alternately arranged along the second direction y to form a first pixel column. In two adjacent first pixel columns, the first overlapping region 12 and the third overlapping region 14 are located in one of the first pixel columns, and the second overlapping region 13 and the fourth overlapping region 15 are located in the other first pixel column; thus, in each pixel column, there is one of the first overlapping region 12 and the fourth overlapping region 15 and one of the second overlapping region 13 or the third overlapping region 14. The first overlapping region 12 and the fourth overlapping region 15 are used for electrical connection, and the second overlapping region 13 and / or the third overlapping region 14 are insulated. Therefore, in the above embodiment, the first overlapping region 12 and the fourth overlapping region 15 for electrical connection, and the second overlapping region 13 and / or the third overlapping region 14 that can be used for insulation are alternately arranged along the first direction x and the second direction y, thereby improving the uniformity of the display panel 1.

[0095] In a feasible embodiment, as Figure 4 shown, the pixel opening 16 further includes a third pixel opening 163. A plurality of third pixel openings 163 are arranged along the second direction y to form a second pixel column, and the first pixel column and the second pixel column are alternately arranged along the first direction x.

[0096] In the above embodiment, the third pixel opening 163 can be used to form a green light-emitting unit.

[0097] In a feasible embodiment, as Figure 4 shown, two first pixel openings 161 and two second pixel openings 162 are arranged on the periphery of the third pixel opening 163, and the two first pixel openings 161 and the two second pixel openings 162 are alternately distributed on the periphery of the third pixel opening 163. The above pixel arrangement can achieve a better light mixing effect.

[0098] In the above pixel arrangement, the display panel 1 includes a plurality of virtual quadrilaterals C, and the plurality of virtual quadrilaterals C are arranged in rows and columns. In each virtual quadrilateral C, the centers of two opposite vertices respectively coincide with the centers of the first pixel openings 161, and the centers of the other two opposite vertices respectively coincide with the centers of the second pixel openings 162.

[0099] In the above pixel arrangement, the orthographic projection of the first signal line 1111 on the substrate 110 does not overlap with the orthographic projections of the second pixel opening 162 and the third pixel opening 163 on the substrate 110, and the orthographic projection of the first signal line 1111 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 along the first direction x.

[0100] The orthographic projection of the second signal line 1112 on the substrate 110 does not overlap with the orthographic projections of the second pixel opening 162 and the third pixel opening 163 on the substrate 110, and the orthographic projection of the second signal line 1112 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 along the first direction x.

[0101] The orthographic projection of the third signal line 1121 on the substrate 110 does not overlap with the orthographic projection of the third pixel opening 163 on the substrate 110, and the orthographic projection of the third signal line 1121 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 and the orthographic projection of the second pixel opening 162 on the substrate 110 along the second direction y.

[0102] The orthographic projection of the fourth signal line 1122 on the substrate 110 does not overlap with the orthographic projection of the third pixel opening 163 on the substrate 110, and the orthographic projection of the fourth signal line 1122 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 and the orthographic projection of the second pixel opening 162 on the substrate 110 along the second direction y.

[0103] In the above embodiments, the orthographic projection of the first signal line 1111 on the substrate 110 does not overlap with the orthographic projections of the second pixel opening 162 and the third pixel opening 163 on the substrate 110, and the orthographic projection of the first signal line 1111 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 along the first direction x. The orthographic projection of the third signal line 1121 on the substrate 110 does not overlap with the orthographic projection of the third pixel opening 163 on the substrate 110, and the orthographic projection of the third signal line 1121 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 and the orthographic projection of the second pixel opening 162 on the substrate 110 along the second direction y.

[0104] Within the orthographic projection of the same virtual quadrilateral C on the substrate 110, it is possible to pass through the orthographic projection of a first signal line 1111 or a second signal line 1112 on the substrate 110. The orthographic projection of the first signal line 1111 on the substrate 110 does not overlap with the orthographic projections of the second pixel opening 162 and the third pixel opening 163 on the substrate 110. The orthographic projection of the third signal line 1121 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 and the orthographic projection of the second pixel opening 162 on the substrate 110 along the second direction y. As a result, the first overlapping region 12 formed by the overlap between the first signal line 1111 and the third signal line 1121 can be located between the second pixel opening 162 and the first pixel opening 161 along the second direction y. Thus, the orthographic projection of the first overlapping region 12 on the substrate 110 does not overlap with the orthographic projection of the pixel opening 16 on the substrate 110. The first signal line 1111 and the third signal line 1121 are arranged to achieve electrical connection at the position of the first overlapping region 12, so as to prevent the flatness of the electrodes of the light-emitting unit 36 corresponding to the pixel opening 16 from being affected and to improve color deviation.

[0105] In the above embodiment, the orthographic projection of the second signal line 1112 on the substrate 110 does not overlap with the orthographic projections of the second pixel opening 162 and the third pixel opening 163 on the substrate 110, and the orthographic projection of the second signal line 1112 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 along the first direction x. The orthographic projection of the fourth signal line 1122 on the substrate 110 does not overlap with the orthographic projection of the third pixel opening 163 on the substrate 110, and the orthographic projection of the fourth signal line 1122 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 and the orthographic projection of the second pixel opening 162 on the substrate 110 along the second direction y.

[0106] Within the orthographic projection of the same virtual quadrilateral C on the substrate 110, it is possible to pass through the orthographic projection of a first signal line 1111 or a second signal line 1112 on the substrate 110. Moreover, the orthographic projection of the second signal line 1112 on the substrate 110 does not overlap with the orthographic projections of the second pixel opening 162 and the third pixel opening 163 on the substrate 110, and only overlaps with the orthographic projection of the first pixel opening 161 on the substrate 110. As a result, the orthographic projection of the fourth signal line 1122 on the substrate 110 can pass through the orthographic projections of the first pixel opening 161 and the second pixel opening 162 on the substrate 110 along the second direction y and then form a fourth overlapping region 15 with the second signal line 1112. And the orthographic projection of the fourth overlapping region 15 on the substrate 110 is located between the orthographic projections of the second pixel opening 162 and the first pixel opening 161 on the substrate 110, so that the orthographic projection of the fourth overlapping region 15 on the substrate 110 does not overlap with the orthographic projection of the pixel opening 16 on the substrate 110. The second signal line 1112 and the fourth signal line 1122 are arranged to achieve electrical connection at the position of the second overlapping region 13, so as to prevent the flatness of the electrodes of the light-emitting unit 36 corresponding to the pixel opening 16 from being affected and to improve color deviation.

[0107] In a feasible implementation manner, as Figure 4 shown, the first signal line 1111 and the fourth signal line 1122 are insulated in the second overlapping region 13, and the second signal line 1112 and the third signal line 1121 are insulated in the third overlapping region 14.

[0108] In the above implementation manner, the signal lines at the second overlapping region 13 and the third overlapping region 14 are insulated. Therefore, in the display panel 1, the orthographic projections of the first overlapping region 12 and the fourth overlapping region 15 for electrical connection on the substrate 110 are both located outside the pixel opening 16, and the signal lines at the second overlapping region 13 and the third overlapping region 14 whose orthographic projections on the substrate 110 overlap with the orthographic projection of the pixel opening 16 on the substrate 110 are insulated. As a result, the vias for electrical connection can completely avoid the pixel opening 16 region, thereby minimizing the influence of the vias for electrical connection on the color deviation of the light-emitting unit within the pixel opening 16, and thus improving the display quality.

[0109] In another feasible implementation manner, as Figure 5 shown, the first signal line 1111 and the fourth signal line 1122 are insulated in the second overlapping region 13, and the second signal line 1112 and the third signal line 1121 are electrically connected in the third overlapping region 14. Thereby, the position of the connection point between the second signal line 1112 and the third signal line 1121 can be increased, and thus the electrical connection effect between the second signal line 1112 and the third signal line 1121 can be further improved.

[0110] In another feasible implementation manner, as Figure 6As shown, the first signal line 1111 and the fourth signal line 1122 are electrically connected in the second overlapping region 13, and the second signal line 1112 and the third signal line 1121 are insulated in the third overlapping region 14. Thus, the position of the connection point between the first signal line 1111 and the fourth signal line 1122 can be increased, and the electrical connection effect between the first signal line 1111 and the fourth signal line 1122 can be further improved.

[0111] In another feasible embodiment, as Figure 7 and Figure 8 shown, the first signal line 1111 and the fourth signal line 1122 are insulated in a part of the second overlapping region 13 and are electrically connected at a part of the preset second overlapping region 13, and the second signal line 1112 and the third signal line 1121 are insulated in a part of the third overlapping region 14 and are electrically connected at a part of the preset third overlapping region 14. Thus, the position of the connection point between the first signal line 1111 and the fourth signal line 1122, and the position of the connection point between the second signal line 1112 and the third signal line 1121 can be increased, so that the electrical connection effect between the second signal line 1112 and the third signal line 1121 can be further improved, and the electrical connection effect between the first signal line 1111 and the fourth signal line 1122 can be further improved.

[0112] In the above embodiment, as Figure 7 shown, the sum of the number of the part of the preset second overlapping region 13 and the part of the preset third overlapping region 14 is half of the sum of the number of the second overlapping region 13 and the third overlapping region 14, or as Figure 8 shown, the sum of the number of the part of the preset second overlapping region 13 and the part of the preset third overlapping region 14 is one-fourth of the sum of the number of the second overlapping region 13 and the third overlapping region 14. Thus, half or three-fourths of the connection points can be reduced, and the problem of color deviation can be improved to a certain extent.

[0113] In a feasible embodiment, as Figure 9 shown, the first conductive layer 111 further includes a fifth signal line 1113 and a sixth signal line 1114 extending along the first direction x, the second conductive layer 112 further includes a seventh signal line 1123 and an eighth signal line 1124 extending along the second direction y, the fifth signal line 1113 and the sixth signal line 1114 are arranged along the second direction y, the seventh signal line 1123 and the eighth signal line 1124 are arranged along the first direction x, and the seventh signal line 1123 and the eighth signal line 1124 transmit the same signal.

[0114] In the above embodiments, the third signal line 1121 and the fourth signal line 1122 transmit the same signal, and cross the first signal line 1111 and the second signal line 1112 to form a network for transmitting one kind of signal; the seventh signal line 1123 and the eighth signal line 1124 transmit the same signal, and cross the fifth signal line 1113 and the sixth signal line 1114 to form a network for transmitting another kind of signal.

[0115] In a feasible embodiment, as Figure 9 shown, the third signal line 1121 and the fourth signal line 1122 are arranged adjacent to each other along the first direction x, and the seventh signal line 1123 and the eighth signal line 1124 are arranged adjacent to each other along the first direction x; the fifth signal line 1113 is located between the adjacent first signal line 1111 and the second signal line 1112, the sixth signal line 1114 is located between the adjacent first signal line 1111 and the second signal line 1112, and the first signal line 1111 or the second signal line 1112 is arranged between the fifth signal line 1113 and the sixth signal line 1114.

[0116] In the above embodiments, by arranging the third signal line 1121 and the fourth signal line 1122 adjacent to each other along the first direction x, and the seventh signal line 1123 and the eighth signal line 1124 adjacent to each other along the first direction x; it is possible to ensure that while being insulated at the positions of the second overlapping region 13 and the third overlapping region 14, the third signal line 1121 and the fourth signal line 1122 can respectively form a mesh.

[0117] In a feasible embodiment, as Figure 9 shown, the orthographic projection of the fifth signal line 1113 on the substrate 110 does not overlap with the orthographic projections of the first pixel opening 161 and the second pixel opening 162 on the substrate 110, and the orthographic projection of the first signal line 1111 on the substrate 110 passes through the orthographic projection of the third pixel opening 163 on the substrate 110 along the first direction x.

[0118] The orthographic projection of the sixth signal line 1114 on the substrate 110 does not overlap with the orthographic projections of the first pixel opening 161 and the second pixel opening 162 on the substrate 110, and the orthographic projection of the sixth signal line 1114 on the substrate 110 passes through the orthographic projection of the third pixel opening 163 on the substrate 110 along the first direction x.

[0119] The orthographic projection of the seventh signal line 1123 on the substrate 110 does not overlap with the orthographic projection of the third pixel opening 163 on the substrate 110, and the orthographic projection of the seventh signal line 1123 on the substrate 110 passes through the orthographic projection of the first pixel opening 161 on the substrate 110 and the orthographic projection of the second pixel opening 162 on the substrate 110 along the second direction y.

[0120] The positive projection of the eighth signal line 1124 on the substrate 110 does not overlap with the positive projection of the third pixel opening 163 on the substrate 110, and the positive projection of the eighth signal line 1124 on the substrate 110 passes through the positive projection of the first pixel opening 161 on the substrate 110 and the positive projection of the second pixel opening 162 on the substrate 110 along the second direction y.

[0121] In the above embodiment, since neither the fifth signal line 1113 nor the sixth signal line 1114 passes through the first pixel opening 161 and the second pixel opening 162, the electrical connection positions of the fifth signal line 1113, the sixth signal line 1114, the seventh signal line 1123 and the eighth signal line 1124 can be set between the first pixel opening 161 and the second pixel opening 162 arranged along the second direction y, so as not to affect the luminous yield of the light-emitting unit 36 in the pixel opening 16.

[0122] In a feasible embodiment, as Figure 9 shown, there is a fifth overlapping area 19 between the fifth signal line 1113 and the seventh signal line 1123, a sixth overlapping area 20 between the fifth signal line 1113 and the eighth signal line 1124, a seventh overlapping area 21 between the sixth signal line 1114 and the seventh signal line 1123, and an eighth overlapping area 22 between the sixth signal line and the eighth signal line 1124. The fifth signal line 1113 and the seventh signal line 1123 are electrically connected in the fifth overlapping area 19, and the sixth signal line 1114 and the eighth signal line 1124 are electrically connected in the eighth overlapping area 22, and / or the fifth signal line 1113 and the eighth signal line 1124 are electrically connected in the sixth overlapping area 20, and the sixth signal line 1114 and the seventh signal line 1123 are electrically connected in the seventh overlapping area 21.

[0123] In the above embodiment, as Figure 9 shown, the fifth overlapping area 19, the sixth overlapping area 20, the seventh overlapping area 21, and the eighth overlapping area 22 can all be overlapping areas for electrical connection. Or some are insulating overlapping areas and some are electrically connected overlapping areas, as long as the fifth signal line 1113, the eighth signal line 1124, the sixth signal line 1114, and the seventh signal line 1123 form a mesh. Specifically, it can form one mesh or two meshes. Specifically, as Figure 10 shown, the fifth signal line 1113 and the seventh signal line 1123 can be electrically connected in the fifth overlapping area 19, the fifth signal line 1113 and the eighth signal line 1124 can be insulated in the sixth overlapping area 20, the sixth signal line 1114 and the seventh signal line 1123 can be insulated in the seventh overlapping area 21, and the sixth signal line and the eighth signal line 1124 can be electrically connected in the eighth overlapping area 22.

[0124] In a feasible embodiment, as Figure 11 and Figure 12As shown, the first signal line 1111 further includes a first extension portion 17. The first extension portion 17 is connected to the second overlapping region 13 and is arranged with the second overlapping region 13 along the second direction y. At least a part of the orthographic projection of the first extension portion 17 on the substrate 110 is located outside the orthographic projection of the first pixel opening 161 on the substrate 110. The first extension portion 17 is electrically connected to the fourth signal line 1122 through a first through hole, and the orthographic projection of the first through hole on the substrate 110 does not overlap with the orthographic projection of the first pixel opening 161 on the substrate 110.

[0125] In the above embodiment, the electrical connection between the first signal line 1111 and the fourth signal line 1122 can be achieved by providing a first through hole in the first extension portion 17. Specifically, the first through hole is formed in the first extension portion 17, and the first extension portion 17 is connected to the second overlapping region 13, so that the overlapping area between the first signal line 1111 and the fourth signal line 1122 can be increased. Through the first extension portion 17, the position where the first signal line 1111 and the fourth signal line 1122 overlap and the first through hole is formed can be moved outside the orthographic projection of the pixel opening 16 on the substrate 110 to achieve the electrical connection between the first signal line 1111 and the fourth signal line 1122, so that the first through hole does not affect the color shift of the light-emitting unit 36 in the pixel opening 16.

[0126] In the above embodiment, the fifth signal line 1113 includes a first partition region for accommodating the first extension portion 17, and at least a part of the first extension portion 17 is located in the first partition region.

[0127] Since the fifth signal line 1113 is relatively close to the first signal line 1111, a first partition region is provided on the fifth signal line 1113 to accommodate the first extension portion 17, providing conditions for providing the first through hole on the first extension portion 17.

[0128] In a feasible embodiment, as Figure 13 and Figure 14 shown, the second signal line 1112 further includes a second extension portion 18. The second extension portion 18 is connected to the third overlapping region 14 and is arranged with the third overlapping region 14 along the second direction y. At least a part of the orthographic projection of the second extension portion 18 on the substrate 110 is located outside the orthographic projection of the first pixel opening 161 on the substrate 110. The second extension portion 18 is electrically connected to the third signal line 1121 through a second through hole, and the orthographic projection of the second through hole on the substrate 110 does not overlap with the orthographic projection of the first pixel opening 161 on the substrate 110.

[0129] In the above embodiment, the second through hole can be provided on the second extension portion 18 to realize the electrical connection between the second signal line 1112 and the third signal line 1121. Specifically, the second through hole is formed on the second extension portion 18, and the second extension portion 18 is connected to the third overlapping area 14, so that the overlapping area between the second signal line 1112 and the third signal line 1121 can be increased. The position where the second signal line 1112 and the third signal line 1121 overlap and form the second through hole can be moved to outside the positive projection of the pixel opening 16 on the substrate 110 through the second extension portion 18 to realize the electrical connection between the second signal line 1112 and the third signal line 1121, so that the second through hole will not affect the color deviation of the light-emitting unit 36 ​​in the pixel opening 16.

[0130] In the above embodiment, the sixth signal line 1114 includes a second isolation region for accommodating the second extension portion 18 , and the second extension portion 18 is at least partially located in the second isolation region.

[0131] Since the sixth signal line 1114 is close to the second signal line 1112 , a second partition area is provided on the sixth signal line 1114 to accommodate the second extension portion 18 , thereby providing conditions for setting a second through hole on the second extension portion 18 .

[0132] In a feasible embodiment, it also includes a first high-level signal line, which is located in the second conductive layer 112, and the first high-level signal line extends along the second direction y. The first high-level signal line is located in the second pixel opening 162 in the orthographic projection on the substrate 110, and the part of the first pixel opening 161 in the orthographic projection on the substrate 110 is symmetrical about the symmetry axis parallel to the second direction y.

[0133] Thereby, the symmetry of the first electrode 361 of the light emitting unit 36 ​​can be made stronger, so as to improve the color shift phenomenon and enhance the display quality of the display panel 1 .

[0134] In a feasible implementation, the second conductive layer 112 is located on a side of the first conductive layer 111 facing away from the substrate 110 .

[0135] In a feasible implementation manner, the signals in the first signal line 1111 and the signals in the fifth signal line 1113 are different.

[0136] Specifically, the first signal line 1111 has a first reset signal, that is, the first signal line 1111, the second signal line 1112, the third signal line 1121 and the fourth signal line 1122 are all first reset signal lines Vref1, and the fifth signal line 1113 has a second reset signal, that is, the fifth signal line 1113, the sixth signal line 1114, the seventh signal line 1123 and the eighth signal line 1124 are all second reset signal lines Vref2.

[0137] Specifically,Figure 15 As shown, the driving circuit is electrically connected to at least one light-emitting unit 36. The driving circuit includes a first light-emitting control module 500, a first initialization module 700, and a second initialization module 800. The control terminal of the second initialization module 800 is electrically connected to the first scanning signal line S1. The first terminal of the second initialization module 800 is electrically connected to the second reset signal line Vref2. The second terminal of the second initialization module 800 is electrically connected to the first terminal of the first light-emitting control module 500. The control terminal of the first initialization module 700 is electrically connected to the first scanning signal line S1. The first terminal of the first initialization module 700 is electrically connected to the first reset signal line Vref1. The second terminal of the first initialization module 700 is electrically connected to the second terminal of the first light-emitting control module 500 and the light-emitting unit 36. The control terminal of the first light-emitting control module 500 is electrically connected to the light-emitting control signal line EM. The first terminal of the first light-emitting control module 500 is electrically connected to the second initialization module 800. The second terminal of the first light-emitting control module 500 is electrically connected to the first initialization module 700 and the light-emitting unit 36.

[0138] The driving circuit further includes a driving module 100, a data writing module 200, a compensation module 300, a storage module 400, a second light-emitting control module 600, and a third initialization module 900. The display panel 1 further includes a first high-level signal line ELVDD, a first low-level signal line ELVSS, a second scanning signal line S2, a first scanning signal line S1, a third scanning signal line S3, a fourth scanning signal line S4S4, a light-emitting control signal line EM, a data signal line Data, and a third reset signal line Vref3. Among them,

[0139] The control terminal of the second light-emitting control module 600 is connected to the light-emitting control signal line EM. The first terminal of the second light-emitting control module 600 is connected to the first high-level signal line ELVDD and the first terminal of the storage module 400. The second terminal of the second light-emitting control module 600 is connected to the second terminal of the data writing module 200 and the first terminal of the driving module 100;

[0140] The first terminal of the storage module 400 is connected to the first high-level signal line ELVDD and the first terminal of the second light-emitting control module 600. The second terminal of the storage module 400 is connected to the first terminal of the compensation module 300 and the control terminal of the driving module 100;

[0141] The control terminal of the data writing module 200 is electrically connected to the second scanning signal line S2. The first terminal of the data writing module 200 is electrically connected to the data signal line Data. The second terminal of the data writing module 200 is connected to the first terminal of the driving module 100 and the second terminal of the second light-emitting control module 600;

[0142] The control terminal of the compensation module 300 is connected to the fourth scanning signal line S4. The first terminal of the compensation module 300 is connected to the second terminal of the storage module 400 and the control terminal of the driving module 100. The second terminal of the compensation module 300 is electrically connected to the first node N.

[0143] The control terminal of the driving module 100 is electrically connected to the second terminal of the storage module 400 and the first terminal of the compensation module 300. The first terminal of the driving module 100 is connected to the second terminal of the data writing module 200 and the second terminal of the second light-emitting control module 600. The second terminal of the driving module 100 is electrically connected to the first node N.

[0144] The control terminal of the first light-emitting control module 500 is connected to the light-emitting control signal line EM. The first terminal of the first light-emitting control module 500 is connected to the second initialization module 800 and the first node N. The second terminal of the first light-emitting control module 500 is connected to the first initialization module 700 and the light-emitting unit 36.

[0145] The control terminal of the second initialization module 800 is connected to the first scanning signal line S1. The first terminal of the second initialization module 800 is connected to the second reset signal line Vref2. The second terminal of the second initialization module 800 is connected to the first terminal of the first light-emitting control module 500 and the first node N.

[0146] The control terminal of the first initialization module 700 is connected to the first scanning signal line S1. The first terminal of the first initialization module 700 is connected to the first reset signal line Vref1. The second terminal of the first initialization module 700 is connected to the second terminal of the first light-emitting control module 500 and the light-emitting unit 36.

[0147] The control terminal of the third initialization module 900 is connected to the third scanning signal line S3. The first terminal of the third initialization module 900 is connected to the third reset signal line Vref3. The second terminal of the third initialization module 900 is connected to the second terminal of the second initialization module 800 and the first node N.

[0148] The light-emitting unit 36 includes a first electrode 361 and a second electrode 363. The first electrode 361 is electrically connected to the second terminal of the first initialization module 700 and the second terminal of the first light-emitting control module 500. The second electrode 363 is electrically connected to the first low-level signal line ELVSS.

[0149] In the above embodiments, the first initialization module 700 is used to reset the first electrode 361 of the light-emitting unit 36. The second initialization module 800 is used to reset the second terminal of the driving module 100. The third initialization module 900 is used to reset the control terminal of the driving module 100, thereby helping to improve the display quality.

[0150] The present application also provides a display panel 1, as Figure 16 shown. The display panel 1 includes an array substrate 11. The array substrate 11 includes a substrate 110 and a first semiconductor layer 23, a first metal layer 24, a second metal layer 25, a second semiconductor layer 26, a third metal layer 27, a fourth metal layer 28, and a fifth metal layer 29 that are stacked in a direction away from the substrate 110. Among them:

[0151] The array substrate 11 includes a first type of transistor, a second type of transistor, and a capacitor. The first semiconductor layer 23 is used to form the source region, drain region, and channel region of the first type of transistor. The first metal layer 24 is used to form the gate of the first type of transistor and the first electrode plate of the capacitor. The second metal layer 25 is used to form the bottom gate of the second type of transistor. The second semiconductor layer 26 is used to form the source region, drain region, and channel region of the second type of transistor. The third metal layer 27 is used to form the top gate of the second type of transistor. The fourth metal layer 28 is used to form the source and drain electrodes of the first type of transistor and the second type of transistor.

[0152] Among them, a first signal line 1111 and a second signal line 1112 extending along a first direction x are formed in one of the first metal layer 24, the second metal layer 25, the fourth metal layer 28, and the third metal layer 27. The first signal line 1111 and the second signal line 1112 are arranged along a second direction y. The fifth metal layer 29 forms a third signal line 1121 and a fourth signal line 1122 extending along the second direction y. The third signal line 1121 and the fourth signal line 1122 are arranged along the first direction x. The first direction x intersects the second direction y. The third signal line 1121 and the fourth signal line 1122 transmit the same signal.

[0153] Along the direction perpendicular to the substrate 110, there is a first overlapping region 12 between the first signal line 1111 and the third signal line 1121, a second overlapping region 13 between the first signal line 1111 and the fourth signal line 1122, a third overlapping region 14 between the second signal line 1112 and the third signal line 1121, and a fourth overlapping region 15 between the second signal line 1112 and the fourth signal line 1122. The first signal line 1111 and the third signal line 1121 are electrically connected in the first overlapping region 12. The first signal line 1111 and the fourth signal line 1122 are insulated in the second overlapping region 13 and / or the second signal line 1112 and the third signal line 1121 are insulated in the third overlapping region 14. The second signal line 1112 and the fourth signal line 1122 are electrically connected in the fourth overlapping region 15. The orthographic projections of the first overlapping region 12 and the fourth overlapping region 15 on the substrate 110 are both located outside the orthographic projection of the pixel opening 16 on the substrate 110. The orthographic projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are both at least partially located inside the orthographic projection of the pixel opening 16 on the substrate 110.

[0154] In the above-mentioned display panel 1 provided by the present application, the signals in the first signal line 1111 and the third signal line 1121 are the same, and a first overlapping region 12 is formed at the intersecting position and electrically connected, so that the first signal line 1111 and the third signal line 1121 form a mesh structure. The orthographic projection of the first overlapping region 12 on the substrate 110 does not overlap with the orthographic projection of the pixel opening 16 on the substrate 110. Therefore, the electrical connection between the first signal line 1111 and the third signal line 1121 can be realized through a via at the first overlapping region 12, and this via is not located in the pixel opening 16 region, so that the display of the light-emitting unit 36 corresponding to the pixel opening 16 will not be affected by the unevenness of the film layer above the via.

[0155] The signals in the second signal line 1112 and the fourth signal line 1122 are the same, and a fourth overlapping region 15 is formed at the intersecting position and electrically connected, so that the second signal line 1112 and the fourth signal line 1122 form a mesh structure. The orthographic projection of the fourth overlapping region 15 on the substrate 110 does not overlap with the orthographic projection of the pixel opening 16 on the substrate 110. That is, the electrical connection between the second signal line 1112 and the fourth signal line 1122 is realized through a via at the fourth overlapping region 15, and this via is not located in the pixel opening 16 region, so that the display of the light-emitting unit 36 corresponding to the pixel opening 16 will not be affected by the unevenness of the film layer above the via.

[0156] There is a second overlapping region 13 between the first signal line 1111 and the fourth signal line 1122, and a third overlapping region 14 between the second signal line 1112 and the third signal line 1121. The first signal line 1111 and the fourth signal line 1122 are insulated at the second overlapping region 13, and / or the second signal line 1112 and the third signal line 1121 are insulated at the third overlapping region 14. The orthographic projections of the second overlapping region 13 and the third overlapping region 14 on the substrate 110 are at least partially located within the orthographic projection of the pixel opening 16 on the substrate 110. Therefore, vias do not need to be provided at the positions of the second overlapping region 13 and / or the third overlapping region 14, so that the number of vias can be reduced to reduce the impact on the display yield of the light-emitting unit 36 corresponding to the pixel opening 16.

[0157] On the basis that the above-mentioned display panel 1 provided by the present application realizes that the third signal line 1121 and the fourth signal line 1122 transmit the same signal, and the first signal line 1111 and the third signal line 1121 are electrically connected, and the second signal line 1112 and the fourth signal line 1122 are electrically connected, the orthographic projections of the vias required for electrical connection on the substrate 110 are mostly or all located outside the orthographic projection of the pixel opening 16 on the substrate 110, which improves the problem of large color deviation caused by the influence of the presence of vias on the electrode flatness of the light-emitting unit 36 in the pixel opening 16, thereby improving the display quality of the display panel 1.

[0158] Specifically, the material of the first semiconductor layer 23 includes polysilicon semiconductor, and the material of the second semiconductor layer 26 includes metal oxide semiconductor.

[0159] In the above embodiment, the second type of transistor is an oxide semiconductor transistor, and the second type of transistor can be a double-gate transistor.

[0160] In the above embodiment, a first insulating layer 30 is formed between the first semiconductor layer 23 and the first metal layer 24, a second insulating layer 31 is formed between the first metal layer 24 and the second metal layer 25, a third insulating layer 32 is formed between the second metal layer 25 and the second semiconductor layer 26, a fourth insulating layer 33 is formed between the second semiconductor layer 26 and the third metal layer 27, a fifth insulating layer 34 is formed between the third metal layer 27 and the fourth metal layer 28, a sixth insulating layer 35 is formed between the fourth metal layer 28 and the fifth metal layer 29, and the third signal line 1121 and the fourth signal line 1122 are formed on the fifth metal layer 29.

[0161] In a feasible embodiment, the first signal line 1111 and the second signal line 1112 are formed on the first metal layer 24. The first signal line 1111 and the third signal line 1121 are electrically connected through a first via in the first overlapping region 12, and the second signal line 1112 and the fourth signal line 1122 are electrically connected through a second via in the fourth overlapping region 15. The first via and the second via penetrate through the second insulating layer 31, the third insulating layer 32, the fourth insulating layer 33, the fifth insulating layer 34, and the sixth insulating layer 35.

[0162] In another feasible embodiment, the first signal line 1111 and the second signal line 1112 are formed on the second metal layer 25. The first signal line 1111 and the third signal line 1121 are electrically connected through a first via in the first overlapping region 12, and the second signal line 1112 and the fourth signal line 1122 are electrically connected through a second via in the fourth overlapping region 15. The first via and the second via penetrate through the third insulating layer 32, the fourth insulating layer 33, the fifth insulating layer 34, and the sixth insulating layer 35.

[0163] In another feasible embodiment, the first signal line 1111 and the second signal line 1112 are formed on the fourth metal layer 28. The first signal line 1111 and the third signal line 1121 are electrically connected through a first via in the first overlapping region 12, and the second signal line 1112 and the fourth signal line 1122 are electrically connected through a second via in the fourth overlapping region 15. The first via and the second via penetrate through the sixth insulating layer 35.

[0164] In another feasible implementation, the first signal line 1111 and the second signal line 1112 are formed on the third metal layer 27. The first signal line 1111 and the third signal line 1121 are electrically connected through a first via hole at the first overlapping region 12, and the second signal line 1112 and the fourth signal line 1122 are electrically connected through a second via hole at the fourth overlapping region 15. The first via hole and the second via hole penetrate through the fifth insulating layer 34 and the sixth insulating layer 35.

[0165] In a feasible implementation, as Figure 16 shown, it further includes a light-emitting layer and an isolation structure 37 located on one side of the array substrate 11. The light-emitting layer includes light-emitting units 36, and the isolation structure 37 includes a main body portion and an isolation opening 370 formed in the main body portion. The orthographic projection of the light-emitting unit 36 on the array substrate 11 is located within the orthographic projection of the isolation opening 370 on the array substrate 11.

[0166] Specifically, the light-emitting unit 36 includes a first electrode 361, a light-emitting functional layer 361, and a second electrode 363 that are stacked in a direction away from the substrate.

[0167] In the above implementation, the isolation structure 37 can be used to isolate the second electrode 363 of the light-emitting unit 36 from the light-emitting functional layer 362, thereby achieving the independence of different light-emitting units 36 from each other, improving the crosstalk problem between adjacent light-emitting units 36, and helping to improve the display quality of the display panel 1. At the same time, by using the isolation structure 37, a mask plate does not need to be used during the preparation process of the light-emitting unit 36. On the one hand, the distance between the light-emitting units 36 can be reduced, thereby increasing the aperture ratio. On the other hand, costs can be saved.

[0168] Specifically, the isolation structure 37 includes a first isolation portion 371 and a second isolation portion 372. The second isolation portion 372 is located on the side of the first isolation portion 371 away from the substrate 110, and the orthographic projection of the second isolation portion 372 on the substrate 110 covers the orthographic projection of the first isolation portion 371 on the substrate 110.

[0169] In the above implementation, a stepped portion can be formed between the second isolation portion 372 and the first isolation portion 371 in the isolation structure 37, and the light-emitting functional layer 362 and the second electrode 363 can be isolated at the stepped portion to achieve the independence of different light-emitting units 36 from each other. Further optionally, the second electrode 362 is electrically connected to the first isolation portion 371, which helps to achieve the transmission requirement of the power signal required inside the second electrode 362.

[0170] Patent PCT / CN2023 / 134518, Patent 202310759370.2, Patent 202310740412.8, Patent 202310707209.0, and Patent 202311346196.5 describe related technical solutions of the isolation structure, the content of which is incorporated herein by reference for reference purposes.

[0171] The present application also provides a display device 2, as Figure 17 shown, including any one of the display panels 1 provided in the above embodiments of the present application.

[0172] The color deviation problem of the display device 2 is improved, and the display quality is enhanced, which helps to further improve the user experience.

[0173] The display device 2 may be a mobile terminal such as a mobile phone or a laptop computer, or a fixed terminal such as a television or a computer monitor, or may also be a wearable device such as a watch, etc., and the present application does not make any particular limitations.

[0174] According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments. Obviously, many modifications and variations can be made based on the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, Comprising: An array substrate, the array substrate includes a substrate and a first conductive layer, an insulating layer, and a second conductive layer sequentially stacked on one side of the substrate. The first conductive layer includes a first signal line and a second signal line extending in a first direction, and the second conductive layer includes a third signal line and a fourth signal line extending in a second direction. The first direction intersects the second direction. The first signal line and the second signal line are arranged along the second direction, and the third signal line and the fourth signal line are arranged along the first direction, and the third signal line and the fourth signal line transmit the same signal; Along the direction perpendicular to the substrate, there is a first overlapping region between the first signal line and the third signal line, a second overlapping region between the first signal line and the fourth signal line, a third overlapping region between the second signal line and the third signal line, and a fourth overlapping region between the second signal line and the fourth signal line. The first signal line and the third signal line are electrically connected in the first overlapping region, the first signal line and the fourth signal line are insulated in the second overlapping region and / or the second signal line and the third signal line are insulated in the third overlapping region, and the second signal line and the fourth signal line are electrically connected in the fourth overlapping region. The orthographic projections of the first overlapping region and the fourth overlapping region on the substrate are both located outside the orthographic projection of the pixel opening on the substrate, and the orthographic projections of the second overlapping region and the third overlapping region on the substrate are both at least partially located within the orthographic projection of the pixel opening on the substrate, where the pixel opening is located on one side of the array substrate in the direction from the substrate to the insulating layer.

2. The display panel according to claim 1, wherein The pixel opening includes a first pixel opening, and the orthographic projections of the second overlapping region and the third overlapping region on the substrate are both at least partially located within the orthographic projection of the first pixel opening on the substrate; Preferably, the first pixel opening is used to accommodate a blue light-emitting unit.

3. The display panel according to claim 2, wherein The pixel opening further includes a second pixel opening. The first pixel opening and the second pixel opening are alternately arranged along the second direction, and the first pixel opening and the second pixel opening are also alternately arranged along the first direction. The first overlapping region and the fourth overlapping region are located between the adjacent first pixel opening and the second pixel opening along the second direction; Preferably, the second pixel opening is used to accommodate a red light-emitting unit.

4. The display panel according to claim 3, wherein Multiple first pixel openings and second pixel openings are alternately arranged along the second direction to form a first pixel column. Among two adjacent first pixel columns, the first overlapping region and the third overlapping region are located in one of the first pixel columns, and the second overlapping region and the fourth overlapping region are located in the other first pixel column.

5. The display panel according to claim 4, wherein, The pixel opening further includes a third pixel opening. Multiple third pixel openings are arranged along the second direction to form a second pixel column. The first pixel column and the second pixel column are alternately arranged along the first direction.

6. The display panel according to claim 5, wherein Two of the first pixel openings and two of the second pixel openings are disposed on the periphery of the third pixel opening, and the two first pixel openings and the two second pixel openings are alternately distributed on the periphery of the third pixel opening.

7. The display panel according to claim 5, characterized in that, The orthographic projection of the first signal line on the substrate does not overlap with the orthographic projections of the second pixel opening and the third pixel opening on the substrate, and the orthographic projection of the first signal line on the substrate passes through the orthographic projection of the first pixel opening on the substrate along the first direction; Preferably, the orthographic projection of the second signal line on the substrate does not overlap with the orthographic projections of the second pixel opening and the third pixel opening on the substrate, and the orthographic projection of the second signal line on the substrate passes through the orthographic projection of the first pixel opening on the substrate along the first direction; Preferably, the orthographic projection of the third signal line on the substrate does not overlap with the orthographic projection of the third pixel opening on the substrate, and the orthographic projection of the third signal line on the substrate passes through the orthographic projections of the first pixel opening and the second pixel opening on the substrate along the second direction; Preferably, the orthographic projection of the fourth signal line on the substrate does not overlap with the orthographic projection of the third pixel opening on the substrate, and the orthographic projection of the fourth signal line on the substrate passes through the orthographic projections of the first pixel opening and the second pixel opening on the substrate along the second direction.

8. The display panel according to claim 1, wherein The first signal line and the fourth signal line are insulated in the second overlapping region, and the second signal line and the third signal line are insulated in the third overlapping region; Alternatively, the first signal line and the fourth signal line are insulated in the second overlapping region, and the second signal line and the third signal line are electrically connected in the third overlapping region; Alternatively, the first signal line and the fourth signal line are electrically connected in the second overlapping region, and the second signal line and the third signal line are insulated in the third overlapping region; Alternatively, the first signal line and the fourth signal line are insulated in part of the second overlapping region and are electrically connected in part of the preset second overlapping region, and the second signal line and the third signal line are insulated in part of the third overlapping region and are electrically connected in part of the preset third overlapping region; Preferably, the sum of the number of parts of the preset second overlapping region and the number of parts of the preset third overlapping region is half or one-fourth of the sum of the number of the second overlapping region and the number of the third overlapping region.

9. The display panel according to claim 5, wherein, The first conductive layer further includes a fifth signal line and a sixth signal line extending along the first direction, the second conductive layer further includes a seventh signal line and an eighth signal line extending along the second direction, the fifth signal line and the sixth signal line are arranged along the second direction, the seventh signal line and the eighth signal line are arranged along the first direction, and the seventh signal line and the eighth signal line transmit the same signal.

10. The display panel according to claim 9, wherein, The third signal line and the fourth signal line are arranged adjacent to each other along the first direction, and the seventh signal line and the eighth signal line are arranged adjacent to each other along the first direction; the fifth signal line is located between the adjacent first signal line and the second signal line, the sixth signal line is located between the adjacent first signal line and the second signal line, and the first signal line or the second signal line is arranged between the fifth signal line and the sixth signal line.

11. The display panel according to claim 10, characterized in that, The orthographic projection of the fifth signal line on the substrate does not overlap with the orthographic projections of the first pixel opening and the second pixel opening on the substrate, and the orthographic projection of the first signal line on the substrate passes through the orthographic projection of the third pixel opening on the substrate along the first direction; Preferably, the orthographic projection of the sixth signal line on the substrate does not overlap with the orthographic projections of the first pixel opening and the second pixel opening on the substrate, and the orthographic projection of the sixth signal line on the substrate passes through the orthographic projection of the third pixel opening on the substrate along the first direction; Preferably, the orthographic projection of the seventh signal line on the substrate does not overlap with the orthographic projection of the third pixel opening on the substrate, and the orthographic projection of the seventh signal line on the substrate passes through the orthographic projections of the first pixel opening and the second pixel opening on the substrate along the second direction; Preferably, the orthographic projection of the eighth signal line on the substrate does not overlap with the orthographic projection of the third pixel opening on the substrate, and the orthographic projection of the eighth signal line on the substrate passes through the orthographic projections of the first pixel opening and the second pixel opening on the substrate along the second direction.

12. The display panel according to claim 11, wherein The first signal line further includes a first extension portion, the first extension portion is connected to the second overlapping region and is arranged with the second overlapping region along the second direction. At least a part of the orthographic projection of the first extension portion on the substrate is located outside the orthographic projection of the first pixel opening on the substrate. The first extension portion is electrically connected to the fourth signal line through a first through hole, and the orthographic projection of the first through hole on the substrate does not overlap with the orthographic projection of the first pixel opening on the substrate; Preferably, the fifth signal line includes a first partition region for accommodating the first extension portion, and at least a part of the first extension portion is located in the first partition region.

13. The display panel according to claim 11, wherein The second signal line further includes a second extension portion, the second extension portion is connected to the third overlapping region and is arranged with the third overlapping region along the second direction. At least a part of the orthographic projection of the second extension portion on the substrate is located outside the orthographic projection of the first pixel opening on the substrate. The second extension portion is electrically connected to the third signal line through a second through hole, and the orthographic projection of the second through hole on the substrate does not overlap with the orthographic projection of the first pixel opening on the substrate; Preferably, the sixth signal line includes a second partition region for accommodating the second extension portion, and at least a part of the second extension portion is located in the second partition region.

14. The display panel according to claim 9, wherein, The fifth signal line and the seventh signal line have a fifth overlapping region, the fifth signal line and the eighth signal line have a sixth overlapping region, the sixth signal line and the seventh signal line have a seventh overlapping region, the sixth signal line and the eighth signal line have an eighth overlapping region, the fifth signal line and the seventh signal line are electrically connected in the fifth overlapping region, the sixth signal line and the eighth signal line are electrically connected in the eighth overlapping region, and / or, the fifth signal line and the eighth signal line are electrically connected in the sixth overlapping region, the sixth signal line and the seventh signal line are electrically connected in the seventh overlapping region.

15. The display panel according to claim 9, wherein The first reset signal is provided in the third signal line, and the second reset signal is provided in the seventh signal line; Preferably, it further includes a plurality of driving circuits, the driving circuits are electrically connected to at least one light-emitting unit, and each driving circuit includes a first light-emitting control module, a first initialization module, and a second initialization module; The control end of the second initialization module is electrically connected to the first scanning signal line, the first end of the second initialization module is electrically connected to the second reset signal line, and the second end of the second initialization module is electrically connected to the first end of the first light-emitting control module; The control end of the first initialization module is electrically connected to the first scanning signal line, the first end of the first initialization module is electrically connected to the first reset signal line, and the second end of the first initialization module is electrically connected to the second end of the first light-emitting control module and the light-emitting unit.

16. The display panel according to claim 1, wherein It further includes a first high-level signal line located in the second conductive layer. The first high-level signal line extends along the second direction, and in the orthographic projection of the first high-level signal line on the substrate, the part located within the orthographic projections of the second pixel opening and the first pixel opening on the substrate is symmetric about the symmetry axis parallel to the second direction.

17. A display panel, characterized in that, The display panel includes an array substrate, and the array substrate includes a substrate and a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer stacked in a direction away from the substrate, wherein: The array substrate includes a first type of transistor, a second type of transistor, and a capacitor. The first semiconductor layer is used to form the source region, drain region, and channel region of the first type of transistor. The first metal layer is used to form the gate of the first type of transistor and the first electrode plate of the capacitor. The second metal layer is used to form the bottom gate of the second type of transistor. The second semiconductor layer is used to form the source region, drain region, and channel region of the second type of transistor. The third metal layer is used to form the top gate of the second type of transistor. The fourth metal layer is used to form the source electrodes and drain electrodes of the first type of transistor and the second type of transistor; Among them, a first signal line and a second signal line extending in a first direction are formed in one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer. The first signal line and the second signal line are arranged along a second direction. The fourth metal layer is formed with a third signal line and a fourth signal line extending in the second direction. The third signal line and the fourth signal line are arranged along the first direction. The first direction intersects the second direction. The third signal line and the fourth signal line transmit the same signal; Along a direction perpendicular to the substrate, there is a first overlapping region between the first signal line and the third signal line, a second overlapping region between the first signal line and the fourth signal line, a third overlapping region between the second signal line and the third signal line, and a fourth overlapping region between the second signal line and the fourth signal line. The first signal line and the third signal line are electrically connected in the first overlapping region. The first signal line and the fourth signal line are insulated in the second overlapping region and / or the second signal line and the third signal line are insulated in the third overlapping region. The second signal line and the fourth signal line are electrically connected in the fourth overlapping region. The orthographic projections of the first overlapping region and the fourth overlapping region on the substrate are both located outside the orthographic projection of the pixel opening on the substrate. The orthographic projections of the second overlapping region and the third overlapping region on the substrate are both at least partially located within the orthographic projection of the pixel opening on the substrate.

18. The display panel according to claim 17, wherein a first insulating layer is formed between the first semiconductor layer and the first metal layer, a second insulating layer is formed between the first metal layer and the second metal layer, a third insulating layer is formed between the second metal layer and the second semiconductor layer, a fourth insulating layer is formed between the second semiconductor layer and the third metal layer, a fifth insulating layer is formed between the third metal layer and the fourth metal layer, a sixth insulating layer is formed between the fourth metal layer and the fifth metal layer. The third signal line and the fourth signal line are formed in the fifth metal layer; the first signal line and the second signal line are formed in the first metal layer. The first signal line and the third signal line are electrically connected through a first via in the first overlapping region. The second signal line and the fourth signal line are electrically connected through a second via in the fourth overlapping region. The first via and the second via penetrate through the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer; alternatively, the first signal line and the second signal line are formed in the second metal layer. The first signal line and the third signal line are electrically connected through a first via in the first overlapping region. The second signal line and the fourth signal line are electrically connected through a second via in the fourth overlapping region. The first via and the second via penetrate through the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer; Alternatively, the first signal line and the second signal line are formed on the fourth metal layer. The first signal line and the third signal line are electrically connected through a first via hole at the first overlapping region, and the second signal line and the fourth signal line are electrically connected through a second via hole at the fourth overlapping region. The first via hole and the second via hole penetrate through the sixth insulating layer; Alternatively, the first signal line and the second signal line are formed on the third metal layer. The first signal line and the third signal line are electrically connected through a first via hole at the first overlapping region, and the second signal line and the fourth signal line are electrically connected through a second via hole at the fourth overlapping region. The first via hole and the second via hole penetrate through the fifth insulating layer and the sixth insulating layer; Preferably, the material of the first semiconductor layer includes polysilicon semiconductor, and the material of the second semiconductor layer includes metal oxide semiconductor.

19. The display panel according to claim 17, wherein It further includes a light-emitting layer and an isolation structure on one side of the array substrate. The light-emitting layer includes light-emitting units, and the isolation structure includes a body portion and an isolation opening formed in the body portion. The orthographic projection of the light-emitting unit on the array substrate is located within the orthographic projection of the isolation opening on the array substrate; Preferably, the body portion includes a first isolation portion and a second isolation portion. The second isolation portion is located on a side of the first isolation portion away from the array substrate, and the orthographic projection of the second isolation portion on the array substrate covers the orthographic projection of the first isolation portion on the array substrate; Preferably, the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate, and the second electrode is electrically connected to the first isolation portion.

20. A display device, characterized in that, It includes a display panel according to any one of claims 1-19.

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