Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a non-display area surrounding the display area; a pixel disposed in the display area of the substrate and including at least one transistor and a light emitting diode; a touch sensor unit disposed on the pixel and including at least one touch electrode; a common power line disposed in the non-display area of the substrate and connected to the light emitting diodes; and a gate driving circuit, which is disposed in the non-display area of the substrate. The common power line and the gate driving circuit overlap each other in at least a portion of the non-display area.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0196633, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device having a reduced bezel area. Background art

[0004] With the progress of technology in modern society, display devices have been used in various forms to provide information to users. Display devices are also included in various electronic devices that receive user input and use advanced technology to provide information in response to the received input, and also included in electronic display boards that unidirectionally transmit visual information.

[0005] Meanwhile, in a display device, it is necessary to provide a minimum bezel area (e.g., non - display area) to ensure reliability, such as moisture penetration prevention. However, since the non - display area does not display an image, it is necessary to increase the screen immersion feeling and enhance the aesthetic sense by increasing the size of the display area and reducing the size of the non - display area. Summary of the invention

[0006] One object to be achieved by the present disclosure is to provide a display device having a minimized non - display area as a bezel area.

[0007] Another object to be achieved by the present disclosure is to provide a display device in which the resistance of a common power line can be reduced.

[0008] The objects of the exemplary embodiments of the present disclosure are not limited to the above - mentioned objects, and those skilled in the art can clearly understand other objects not mentioned above from the following description.

[0009] A display device according to an exemplary embodiment of the present disclosure includes a substrate, pixels, a touch sensor unit, a common power line, and a gate driving circuit. The substrate includes a display area and a non - display area surrounding the display area. The pixels are disposed in the display area of the substrate and include at least one transistor and a light - emitting diode. The touch sensor unit is disposed on the pixels and includes at least one touch electrode. The common power line is disposed in the non - display area of the substrate and is connected to the light - emitting diode. The gate driving circuit is disposed in the non - display area of the substrate. The common power line and the gate driving circuit may overlap each other in at least a part of the non - display area.

[0010] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0011] According to the present disclosure, a common power line and a gate driving circuit are arranged to overlap each other in a non-display area. Accordingly, the size of the non-display area can be minimized, and the width of the bezel can be minimized.

[0012] According to the present disclosure, the resistance of the common power line is reduced by wirings provided in the non-display area. Accordingly, image quality defects such as blurring caused by voltage variations in the common power line can be suppressed.

[0013] According to the present disclosure, wirings connected to the common power line in the non-display area are arranged to overlap the common power line. Accordingly, the resistance of the common power line can be reduced without increasing the width of the common power line or the width of the bezel.

[0014] According to the present disclosure, potential defects (such as image quality defects) of the display device can be minimized. Accordingly, the lifespan of the display device can be increased, and the display device can be driven with low power consumption in terms of energy saving in production.

[0015] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 2 is a circuit diagram showing an example of a pixel of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 3 is a diagram showing Figure 1 an enlarged view of an example of a partial EA;

[0020] Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 ;

[0021] Figure 5 is a cross-sectional view taken along line II-II' of Figure 1 ;

[0022] Figure 6 is a cross-sectional view taken along line III-III' of Figure 1 ;

[0023] Figure 7 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure;

[0024] Figure 8 is a plan view of a display device according to still another exemplary embodiment of the present disclosure; and

[0025] Figure 9 is a cross-sectional view taken along line IV-IV' of Figure 8 Detailed Description

[0026] Advantages and features of the present disclosure and methods for achieving these advantages and features will be apparent by referring to the exemplary embodiments and the accompanying drawings described in detail below. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples, so that those skilled in the art can fully understand the disclosure content and the scope of the present disclosure.

[0027] Shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0028] Even if not explicitly stated, components are construed to include a normal error range.

[0029] When describing the positional relationship between two parts using terms such as "on", "above", "below", and "next to", one or more parts may be located between these two parts, unless these terms are used together with the terms "adjacent to" or "directly".

[0030] When an element or layer is disposed "on" another element or layer, other layers or other elements may be directly interposed on or between the other element.

[0031] Although various components are described using terms such as "first", "second", etc., these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.​

[0032] Throughout the specification, like reference numerals generally denote like elements.

[0033] For ease of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0034] The features of the various embodiments of the present disclosure may be partially or completely combined or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0035] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0036] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 is a circuit diagram showing an example of a pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 3 shows Figure 1 an enlarged view of an example of a partial EA of

[0037] The display device 1000 according to an exemplary embodiment of the present disclosure may be an electroluminescent display device. The electroluminescent display device may be an organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device.

[0038] Hereinafter, for ease of description, the lateral direction on the plane is defined as the first direction X, and the longitudinal direction on the plane is defined as the second direction Y. In addition, the normal direction of the plane defined by the first direction X and the second direction Y (for example, the thickness direction of the display device 1000) may be defined as the third direction Z.

[0039] Referring to Figure 1 , the display device 1000 according to an exemplary embodiment of the present disclosure may include a substrate 100, a pixel array layer 120, a touch sensor unit 140, and a common power line CPL. In some exemplary embodiments, the display device 1000 may further include an encapsulation layer disposed between the pixel array layer 120 and the touch sensor unit 140.

[0040] The substrate 100 is a base layer and may include an insulating material. The substrate 100 may include a transparent material. For example, the substrate 100 may include glass or plastic.

[0041] Meanwhile, Figure 1It is shown that the substrate 100 has a rounded rectangular shape, and each of the corner portions thereof is rounded with a certain radius of curvature. However, the shape of the substrate 100 is not limited thereto. The substrate 100 may have various shapes.

[0042] The substrate 100 may include a display area AA and a non-display area NA.

[0043] The display area AA may be defined as an area for displaying an image. The display area AA may have a rectangular shape, a rounded rectangular shape, or a non-rectangular shape with at least six sides on a plane, and each of the corner portions of the rounded rectangular shape is rounded with a certain radius of curvature. In this case, the display area AA having a non-rectangular shape may include at least one protrusion or at least one notch portion. However, the shape of the display area AA is not limited thereto. The shape of the display area AA may vary widely.

[0044] The non-display area NA may be provided to surround the display area AA, and may be defined as an area that does not display an image or a peripheral area.

[0045] The non-display area NA may include a first non-display area NA1 provided at a first edge of the substrate 100 and a second non-display area NA2 provided at a second edge of the substrate 100 opposite to the first non-display area NA1. The non-display area NA may further include a third non-display area NA3 provided at a third edge of the substrate 100 and a fourth non-display area NA4 provided at a fourth edge of the substrate 100 opposite to the third non-display area NA3. For example, the first non-display area NA1 may be an upper edge area of the substrate 100, and the second non-display area NA2 may be a lower edge area of the substrate 100. In addition, the third non-display area NA3 may be a left edge area of the substrate 100, and the fourth non-display area NA4 may be a right edge area of the substrate 100. However, the present disclosure is not limited thereto.

[0046] The pixel array layer 120 may be provided in the display area AA of the substrate 100. For example, the pixel array layer 120 may include a plurality of gate lines, a plurality of data lines, and a plurality of pixels.

[0047] The plurality of gate lines included in the pixel array layer 120 may extend in a first direction X and may be provided in a second direction Y. For example, the display area AA of the substrate 100 may include a plurality of gate lines provided parallel to the first direction X and spaced apart from each other in the second direction Y.

[0048] Multiple data lines included in the pixel array layer 120 may extend in the second direction Y and may be disposed in the first direction X. For example, the display area AA of the substrate 100 may include multiple data lines disposed parallel to the second direction Y and spaced apart from each other in the first direction X.

[0049] Each of the multiple pixels included in the pixel array layer 120 is disposed in a pixel region defined in the display area AA of the substrate 100. In addition, each of the multiple pixels may be electrically connected to at least one of the multiple gate lines and at least one of the multiple data lines. Herein, the pixel region may be defined at the intersection of the gate line and the data line, but is not limited thereto.

[0050] Each pixel may include multiple sub-pixels that emit lights of different colors from each other. For example, each pixel may be implemented with three sub-pixels for blue, red, and green, but is not limited thereto. In some cases, the pixel may further include a sub-pixel for implementing white.

[0051] In the pixel, the region implementing blue may be referred to as a blue sub-pixel, the region implementing red may be referred to as a red sub-pixel, and the region implementing green may be referred to as a green sub-pixel.

[0052] Reference Figure 2 , each of the multiple pixels PX included in the pixel array layer 120 may include a pixel circuit PC electrically connected to the gate line GL and the data line DL, and a light emitting diode (LED) ED connected to the pixel circuit PC.

[0053] Figure 2 The multiple transistors DT and ST shown may include at least one of amorphous silicon, polycrystalline silicon, and oxide semiconductors such as IGZO. The first electrode or the second electrode of each transistor may be a source electrode or a drain electrode. For example, the first electrode may be a source electrode, and the second electrode may be a drain electrode. Alternatively, the first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0054] The pixel circuit PC may control the driving current flowing from the first power supply line providing the first power supply voltage VDD (e.g., high potential power supply voltage) through the LED ED to the second power supply line providing the second power supply voltage VSS (e.g., low potential power supply voltage) in response to the gate signal provided from the gate line GL and based on the data signal provided from the data line DL.

[0055] The pixel circuit PC may include a driving transistor DT, a switching transistor ST, and a storage capacitor CST.

[0056] The driving transistor DT and the storage capacitor CST can be connected to the switching transistor ST. A first electrode of the driving transistor DT can be connected to a first power supply line that provides a first power supply voltage VDD.

[0057] The switching transistor ST can be connected to a gate line GL to receive a gate signal. The switching transistor ST can be turned on or off by the gate signal. A first electrode of the switching transistor ST can be connected to a data line DL. In this case, in response to the turning on of the switching transistor ST, a data signal can be provided to the gate electrode of the driving transistor DT through the switching transistor ST.

[0058] The storage capacitor CST can be provided between the gate electrode and the second electrode of the driving transistor DT. The storage capacitor CST can hold a signal applied to the gate electrode of the driving transistor DT, such as a data signal, within one frame.

[0059] The LED ED can be connected between the pixel circuit PC and a second power supply line that provides a second power supply voltage VSS. For example, the LED ED can include a first electrode connected to the pixel circuit PC (e.g., the driving transistor DT) and a second electrode connected to the second power supply line. The LED ED can emit light in response to a driving current provided from the pixel circuit PC (e.g., the driving transistor DT).

[0060] Reference Figure 1 , the driving current provided to the LED ED can flow to the second power supply line that provides the second power supply voltage VSS, such as a common power supply line CPL.

[0061] The common power supply line CPL can have a constant line width and can be provided to surround at least a part of a display area AA of the substrate 100. For example, the common power supply line CPL can be provided in at least a part of a first non-display area NA1 and in second to fourth non-display areas NA2, NA3, and NA4 so as to surround at least a part of the display area AA. For example, one end of the common power supply line CPL can be provided on one side of the first non-display area NA1, and the other end of the common power supply line CPL can be provided on the other side of the first non-display area NA1. The common power supply line CPL can extend from one side of the first non-display area NA1 to the third non-display area NA3, the second non-display area NA2, the fourth non-display area NA4, and the other side of the first non-display area NA1. Thus, the common power supply line CPL can be provided in a "U" shape in a plan view, at least a part of which is open, but is not limited thereto.

[0062] The touch sensor unit 140 may be disposed on the pixel array layer 120. The touch sensor unit 140 may sense a touch according to a touch object (e.g., a touch position and / or a touch intensity). Herein, the touch object may include a user's finger or a stylus, but is not limited thereto.

[0063] The touch sensor unit 140 may include a touch electrode part, a first wiring part, and a second wiring part. Herein, the first wiring part may also be defined as a touch wiring part, and the second wiring part may also be defined as a dummy pattern unit. Exemplary embodiments of the present disclosure are not limited by the terms used herein.

[0064] The touch electrode part of the touch sensor unit 140 may include a plurality of touch electrodes TE disposed in the display area AA of the substrate 100.

[0065] Reference will be made Figure 3 to the touch electrodes TE in more detail. The plurality of touch electrodes TE may include a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2.

[0066] The plurality of first touch electrodes TE1 may extend in a first direction X and may be disposed to be spaced apart from each other in a second direction Y in the display area AA of the substrate 100. The plurality of first touch electrodes TE1 may be used as touch sensing electrodes or touch driving electrodes to sense the touch position of a touch object.

[0067] Each of the plurality of first touch electrodes TE1 may include a plurality of first electrode patterns EP1 and a plurality of bridging patterns BP.

[0068] The plurality of first electrode patterns EP1 may be disposed to be spaced apart from each other in a first direction X in the display area AA of the substrate 100.

[0069] The plurality of bridging patterns BP may be disposed to be spaced apart from each other in a first direction X in the display area AA of the substrate 100. In addition, each of the plurality of bridging patterns BP may be electrically connected to two first electrode patterns EP1 adjacent to each other in a first direction X. Each of the plurality of bridging patterns BP is disposed to overlap the space between two first electrode patterns EP1 adjacent to each other in a first direction X. Accordingly, each of the plurality of bridging patterns BP may suppress a short circuit at the intersection between the first touch electrode TE1 and the second touch electrode TE2.

[0070] One side of each of the plurality of bridging patterns BP is electrically connected to one of the first electrode patterns EP1 disposed on one side of two first electrode patterns EP1 adjacent to each other in the first direction X. The other side of each of the bridging patterns BP is electrically connected to the other first electrode pattern EP1 disposed on the other side of the two first electrode patterns EP1 adjacent to each other in the first direction X. For example, each of the plurality of bridging patterns BP may be formed in a straight line shape, but is not limited thereto. Each of the plurality of bridging patterns BP may be formed in various shapes such as a curved shape, an angled shape, or a mesh shape to electrically connect the two first electrode patterns EP1 adjacent to each other in the first direction X.

[0071] The plurality of second touch electrodes TE2 may extend in the second direction Y and may be disposed in the display area AA of the substrate 100 to be spaced apart from each other in the first direction X. Accordingly, the plurality of second touch electrodes TE2 may be electrically isolated from the plurality of first touch electrodes TE1. The plurality of second touch electrodes TE2 may be used as touch driving electrodes or touch sensing electrodes to sense the touch position of a touch object.

[0072] Each of the plurality of second touch electrodes TE2 may include a plurality of second electrode patterns EP2 and a plurality of connection lines CL.

[0073] The plurality of second electrode patterns EP2 may be disposed in the display area AA of the substrate 100 to be spaced apart from each other in the second direction Y.

[0074] Each of the plurality of connection lines CL may be disposed between two second electrode patterns EP2 adjacent to each other in the second direction Y to electrically connect the two second electrode patterns EP2 adjacent to each other in the second direction Y. The plurality of connection lines CL may be respectively disposed on the same layer as the plurality of second electrode patterns EP2. For example, the connection lines CL and the second electrode patterns EP2 may be integrally formed. The plurality of connection lines CL may be disposed to intersect the plurality of bridging patterns BP respectively.

[0075] In some exemplary embodiments, the plurality of bridging patterns BP of the first touch electrode TE1 may be changed to the plurality of connection lines CL of the second touch electrode TE2. In addition, the plurality of connection lines CL of the second touch electrode TE2 may be changed to the plurality of bridging patterns BP of the first touch electrode TE1.

[0076] The touch sensor unit 140 may include a first touch electrode layer and a second touch electrode layer. The first touch electrode layer includes a plurality of bridging patterns BP, and the second touch electrode layer includes a plurality of first electrode patterns EP1 and a plurality of second touch electrodes TE2. The touch sensor unit 140 may further include a touch insulating layer disposed between the first touch electrode layer and the second touch electrode layer. Herein, the first touch electrode layer may be disposed below or above the second touch electrode layer, with the touch insulating layer therebetween. For example, the touch sensor unit 140 may include a first touch electrode layer including a plurality of bridging patterns BP, a touch insulating layer disposed on the first touch electrode layer, and a second touch electrode layer disposed on the touch insulating layer and including a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2. As another example, the touch sensor unit 140 may include a first touch electrode layer including a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2, a touch insulating layer disposed on the first touch electrode layer, and a second touch electrode layer disposed on the touch insulating layer and including a plurality of bridging patterns BP.

[0077] The touch insulating layer includes bridge contact holes BCH respectively disposed in the overlapping regions of the first electrode patterns EP1 and the bridging patterns BP. Accordingly, each of the plurality of bridging patterns BP is electrically connected to one side and the other side of a corresponding first electrode pattern EP1 through the bridge contact holes BCH disposed in the touch insulating layer. Accordingly, each of the plurality of bridging patterns BP electrically connects two first electrode patterns EP1 adjacent to each other in the first direction X.

[0078] Each of the plurality of first touch electrodes TE1 and the plurality of second touch electrodes TE2 may have a mesh structure in which metal lines having a very small line width intersect each other. Herein, each of the metal lines may be formed of a single-layer or multi-layer structure of a conductive material such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), titanium / aluminum / titanium (Ti / Al / Ti), or molybdenum / aluminum / molybdenum (Mo / Al / Mo), but is not limited thereto.

[0079] In a plan view, each of the plurality of first electrode patterns EP1 and the plurality of second electrode patterns EP2 may have a polygonal shape, such as a rhombus shape. In this case, each of the plurality of electrode patterns EP1 and EP2 disposed along the edge portion of the display area AA may have a triangular shape. Each of the plurality of first electrode patterns EP1 and the plurality of second electrode patterns EP2 may be simultaneously prepared by a process of forming intersecting mesh-like metal lines and a process of cutting the metal lines disposed on a touch electrode boundary region preset on the display area AA, thereby providing the plurality of first electrode patterns EP1, the plurality of second electrode patterns EP2, and a plurality of connection lines CL.

[0080] The display device 1000 according to an exemplary embodiment of the present disclosure may sense a touch by using a mutual capacitance between a first touch electrode TE1 and a second touch electrode TE2. The mutual capacitance is mainly generated in an outer portion of each of the first touch electrode TE1 and the second touch electrode TE2 that are adjacent to each other, and a touch boundary region is interposed between the first touch electrode TE1 and the second touch electrode TE2. Accordingly, in the display device 1000, a cut portion of a metal line disposed on the outer portion of each of the first touch electrode TE1 and the second touch electrode TE2 is formed as a protrusion to increase the area or length of each outer portion of the first touch electrode TE1 and the second touch electrode TE2. Accordingly, the mutual capacitance generated in the touch boundary region or the sensing region between the first touch electrode TE1 and the second touch electrode TE2 can be increased. Accordingly, touch sensitivity can be improved.

[0081] The first wiring portion of the touch sensor unit 140 may be electrically connected to a touch electrode TE included in the touch sensor unit and disposed in the non-display area NA of the substrate 100. For example, the first wiring portion may include a plurality of first wirings RL1.

[0082] Each of the plurality of first wirings RL1 may be disposed to surround at least a part of the display area AA of the substrate 100. For example, each of the plurality of first wirings RL1 may be disposed in at least a part of the first non-display area NA1 and in the second to fourth non-display areas NA2, NA3, and NA4.

[0083] Some of the plurality of first wirings RL1 may be electrically connected to a plurality of first touch electrodes TE1 included in the touch sensor unit. In addition, other first wirings RL1 of the plurality of first wirings RL1 may be electrically connected to a plurality of second touch electrodes TE2 included in the touch sensor unit.

[0084] For example, each of the plurality of first wirings RL1 electrically connected to the plurality of first touch electrodes TE1 may extend from the first non-display area NA1 to the third non-display area NA3. In addition, each of the plurality of first wirings RL1 electrically connected to the plurality of first touch electrodes TE1 may be connected one-to-one to a first touch electrode TE1 among the plurality of first touch electrodes TE1 included in the touch sensor unit and provided on one side of the display area AA (for example, the side adjacent to the third non-display area NA3). In addition, each of the plurality of first wirings RL1 electrically connected to the plurality of second touch electrodes TE2 may extend from the first non-display area NA1 to the fourth non-display area NA4 and the second non-display area NA2. In addition, each of the plurality of first wirings RL1 electrically connected to the plurality of second touch electrodes TE2 may be connected one-to-one to a second touch electrode TE2 among the plurality of second touch electrodes TE2 included in the touch sensor unit and provided on the other side of the display area AA (for example, the side adjacent to the second non-display area NA2).

[0085] For another example, each of the plurality of first wirings RL1 electrically connected to the plurality of first touch electrodes TE1 may extend from the first non-display area NA1 to the fourth non-display area NA4. In addition, each of the plurality of first wirings RL1 electrically connected to the plurality of first touch electrodes TE1 may be connected one-to-one to a first touch electrode TE1 among the plurality of first touch electrodes TE1 included in the touch sensor unit and provided on one side of the display area AA (for example, the side adjacent to the fourth non-display area NA4). In addition, each of the plurality of first wirings RL1 electrically connected to the plurality of second touch electrodes TE2 may extend from the first non-display area NA1 to the third non-display area NA3 and the second non-display area NA2. In addition, each of the plurality of first wirings RL1 electrically connected to the plurality of second touch electrodes TE2 may be connected one-to-one to a second touch electrode TE2 among the plurality of second touch electrodes TE2 included in the touch sensor unit and provided on the other side of the display area AA (for example, the side adjacent to the second non-display area NA2).

[0086] However, the above settings of the plurality of first wirings RL1 and the connection relationships between the plurality of first wirings RL1 and the plurality of touch electrodes TE1 and TE2 are merely examples. The present disclosure is not limited thereto.

[0087] Meanwhile, for ease of description, Figure 1Two wirings RL1 are shown to be provided on the substrate 100. However, the number of the plurality of first wirings RL1 is not limited thereto. For example, according to the above connection relationship between the plurality of first wirings RL1 and the plurality of touch electrodes TE1 and TE2, the plurality of first wirings RL1 can be provided on the substrate 100 to be numerically corresponding to the plurality of touch electrodes TE1 and TE2. For example, when the first touch electrode TE1 is provided in n (n is an integer greater than 0) rows along the second direction Y in the display area AA, the number of the first wirings RL1 electrically connected to the plurality of first touch electrodes TE1 can be n. In addition, when the second touch electrode TE2 is provided in m (m is an integer greater than 0) columns along the first direction X in the display area AA, the number of the first wirings RL1 electrically connected to the plurality of second touch electrodes TE2 can be m.

[0088] The first wiring RL1 included in the first wiring portion can be made of the same material as the plurality of touch electrodes TE1 and TE2 included in the touch electrode layer, and is provided on the same layer as the plurality of touch electrodes TE1 and TE2 included in the touch electrode layer. For example, the first wiring RL1 can be formed by the same process as the plurality of touch electrodes TE1 and TE2. Therefore, the first wiring portion can be formed together with the touch electrode layer without any additional process. However, the present disclosure is not limited thereto.

[0089] The second wiring portion of the touch sensor unit 140 can include a second wiring RL2. In the present disclosure, the second wiring RL2 can also be defined as a dummy pattern.

[0090] The second wiring RL2 can be provided to overlap with a common power line CPL provided along the second to fourth non-display areas NA2, NA3, and NA4 of the substrate 100, and can be electrically connected to the common power line CPL.

[0091] The second wiring RL2 can have a constant line width, and can be provided to surround at least a part of the display area AA of the substrate 100. For example, the second wiring RL2 can be provided in at least a part of the first non-display area NA1 and in the second to fourth non-display areas NA2, NA3, and NA4, so as to surround at least a part of the display area AA. For example, one end of the second wiring RL2 can be provided on one side of the first non-display area NA1, and the other end of the second wiring RL2 can be provided on the other side of the first non-display area NA1. The second wiring RL2 can extend from one side of the first non-display area NA1 to the third non-display area NA3, the second non-display area NA2, the fourth non-display area NA4, and the other side of the first non-display area NA1. Therefore, in a plan view, the second wiring RL2 can be provided in a "U" shape, at least a part of which is open, but is not limited thereto.

[0092] The second wiring RL2 may be set to overlap with the common power supply line CPL. In addition, the second wiring RL2 may be electrically connected to the common power supply line CPL in a contact area that is part of the area where the common power supply line CPL is provided. For example, the second wiring RL2 may be electrically connected to the common power supply line CPL in a contact area in the first non-display area NA1 and / or the second non-display area NA2, but is not limited thereto. For example, the second wiring RL2 may be electrically connected to the common power supply line CPL throughout the area where the common power supply line CPL is provided.

[0093] The second wiring RL2 may be electrically connected to the common power supply line CPL in the non-display area NA of the substrate 100 to reduce the resistance of the common power supply line CPL or the line resistance value. Therefore, image quality defects such as blurring caused by voltage variations in the common power supply line CPL can be suppressed. In addition, the second wiring RL2 may be set to overlap with the common power supply line CPL so as to reduce the resistance of the common power supply line CPL without increasing the bezel width of the display device 1000.

[0094] The second wiring RL2 included in the second wiring portion may be made of the same material as the plurality of touch electrodes TE1 and TE2 included in the touch electrode layer, and is provided on the same layer as the plurality of touch electrodes TE1 and TE2 included in the touch electrode layer. For example, the second wiring RL2 may be formed by the same process as the plurality of touch electrodes TE1 and TE2. Therefore, the second wiring portion may be formed together with the touch electrode layer without any additional process. However, the present disclosure is not limited thereto.

[0095] The manufacturing process of the touch sensor unit 140 may include a process of depositing a conductive material on the entire surface of the substrate 100, and a process of patterning the deposited conductive material into a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2. During the patterning process of the manufacturing process of the touch sensor unit 140, the conductive material deposited in the non-display area NA overlapping with the common power supply line CPL of the substrate 100 is not removed but left. Thereby, the second wiring RL2 can be formed. Therefore, the conductive material not removed by the patterning process of the touch sensor unit 140 is used for the second wiring RL2 to reduce the resistance of the common power supply line CPL. Therefore, the second wiring RL2 for reducing the resistance of the common power supply line CPL can be formed without any additional deposition process and patterning process.

[0096] Reference Figure 1 , the display device 1000 may further include a pad portion PP, a gate driving circuit 200, an integrated circuit 400, and a flexible film 500.

[0097] The pad portion PP may include a plurality of pads disposed in the non-display area NA of the substrate 100. For example, the pad portion PP may include a plurality of common power pads, a plurality of data input pads, a plurality of power pads, a plurality of control signal input pads, and a plurality of touch drive pads disposed in the first non-display area NA1 of the substrate 100. However, this is merely an example, and the present disclosure is not limited thereto.

[0098] The gate driving circuit 200 is disposed in the non-display area NA of the substrate 100 and may be electrically connected to a plurality of gate lines GL. The gate driving circuit 200 may generate a gate signal based on a gate control signal provided from the integrated circuit 400 and sequentially output the generated gate signal through the plurality of gate lines GL. For example, the gate driving circuit 200 may include a shift register.

[0099] The gate driving circuit 200 may be disposed in the non-display area NA corresponding to at least one side of the display area AA. For example, two gate driving circuits 200 may be disposed in the third non-display area NA3 and the fourth non-display area NA4 of the substrate 100. The gate driving circuit 200 may be configured as an integrated circuit in the third non-display area NA3 and the fourth non-display area NA4 of the substrate 100 in the same process as the process of manufacturing the pixel array layer 120 (i.e., the process of manufacturing thin film transistors). However, this is merely an example, and one gate driving circuit 200 may be disposed in the third non-display area NA3 or the fourth non-display area NA4 of the substrate 100.

[0100] In this document, the common power line CPL may be disposed to at least partially overlap with the gate driving circuit 200. For example, the common power line CPL disposed in the third non-display area NA3 and the fourth non-display area NA4 may be disposed to overlap with the gate driving circuit 200. Accordingly, the sizes of the third non-display area NA3 and the fourth non-display area NA4 of the substrate 100 may be minimized. Accordingly, the bezel width of the display device 1000 may be minimized compared to the case where the common power line CPL is disposed outside or inside the gate driving circuit 200.

[0101] In addition, the first wiring RL1 and the second wiring RL2 can be disposed between the display area AA and the dam structure DM so as to overlap with the gate driving circuit 200 in the third non-display area NA3 and the fourth non-display area NA4. In particular, as described above, the second wiring RL2 is disposed to overlap with the common power line CPL. Therefore, at least a part of the second wiring RL2 (for example, the second wiring RL2 disposed to overlap with the common power line CPL in the third non-display area NA3 and the fourth non-display area NA4) can be disposed to overlap with the gate driving circuit 200. Therefore, the border width caused by the setting areas of the plurality of first wirings RL1 and the second wiring RL2 can be minimized according to the increase of the third non-display area NA3 and the fourth non-display area NA4 of the substrate 100.

[0102] The integrated circuit 400 can be mounted on the flexible film 500. The integrated circuit 400 can receive various power, timing synchronization signals, and digital image data through the pad portion PP, and generate gate control signals based on the timing synchronization signals to control the driving of the gate driving circuit 200. At the same time, the integrated circuit 400 can convert the digital image data into an analog data signal (data voltage) and provide the analog data signal to the corresponding data line DL.

[0103] The integrated circuit 400 can include a touch driving circuit. The integrated circuit 400 can provide a touch driving pulse to each of the plurality of second touch electrodes TE2 through the pad portion PP and the first wiring RL1 among the plurality of first wirings RL1 that is electrically connected to the second touch electrode TE2. In addition, the integrated circuit 400 can sense a change in the capacitance between the first touch electrode TE1 and the second touch electrode TE2 through the pad portion PP and the first wiring RL1 among the plurality of first wirings RL1 that is electrically connected to the first touch electrode TE1, thereby generating touch data. Then, the integrated circuit 400 can provide the generated touch data to a host circuit. The host circuit is configured to calculate touch position information about a touch object based on the touch data provided from the integrated circuit 400 and execute an application program associated with the calculated touch position information.

[0104] The flexible film 500 can be attached to the pad portion PP. The flexible film 500 can be used to electrically connect the display driving circuit to the pad portion PP and electrically connect the pad portion PP to the integrated circuit 400.

[0105] Reference Figure 1 , the display device 1000 may further include a dam structure DM.

[0106] The dam-shaped structure DM can be disposed in the non-display area NA of the substrate 100 to suppress the overflow of the encapsulation layer disposed on the pixel array layer 120. For example, the dam-shaped structure DM can be disposed in the non-display area NA (e.g., the first to fourth non-display areas NA1, NA2, NA3, and NA4) to surround the entire display area AA.

[0107] Meanwhile, Figure 1 it is shown that the dam-shaped structure DM is disposed in the outermost portion. However, the present disclosure is not limited thereto. For example, the dam-shaped structure DM can be disposed between the display area AA and the gate driving circuit 200.

[0108] Hereinafter, reference will be made to Figures 4 to 6 describe in more detail the cross-sectional structure of the display device 1000 according to an exemplary embodiment of the present disclosure.

[0109] Figure 4 is a cross-sectional view taken along Figure 1 the line I-I'. Figure 5 is a cross-sectional view taken along Figure 1 the line II-II'. Figure 6 is a cross-sectional view taken along Figure 1 the line III-III';

[0110] First, reference will be made to Figures 1 to 4 describe the cross-sectional structure of the display area AA, the third non-display area NA3, and / or the fourth non-display area NA4 of the substrate 100 in the display device. The display device 1000 according to an exemplary embodiment of the present disclosure may include a substrate 100, a pixel array layer 120, an encapsulation layer 130, and a touch sensor unit 140. The display device 1000 may further include a dam-shaped structure DM.

[0111] The substrate 100 is a base layer and can be made of a plastic material or a glass material.

[0112] For example, the substrate 100 may be made of an opaque or colored polyimide. For example, the substrate 100 made of polyimide may be prepared by curing a polyimide resin coated to have a certain thickness on the front surface of a release layer provided on a relatively thick carrier substrate. In this case, the carrier glass substrate can be separated from the substrate 100 by releasing the release layer through a laser release process. The display device 1000 may further include a backplane coupled to the rear surface of the substrate 100 in the thickness direction of the substrate 100 (e.g., the third direction Z). The backplane may hold the substrate 100 in a planar state. For example, the backplane may include polyethylene terephthalate. The backplane may be laminated on the rear surface of the substrate 100 separated from the carrier glass substrate.

[0113] Again, for example, the substrate 100 may be a flexible glass substrate. For example, the glass substrate 100 may be a thin glass substrate with a thickness of 100 micrometers or less. Alternatively, the glass substrate 100 may be a carrier glass substrate that has been etched by a substrate etching process to have a thickness of 100 micrometers or less.

[0114] The substrate 100 may include a display area AA and a non-display area NA surrounding the display area AA.

[0115] A buffer film may be provided on one surface of the substrate 100. A buffer layer may be provided on one surface of the substrate 100 to inhibit moisture from penetrating through the substrate where moisture easily penetrates into the pixel array layer 120. For example, the buffer film may be composed of a plurality of inorganic films laminated alternately. For example, the buffer film may be a multilayer film in which one or more inorganic films such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiON) are laminated alternately. However, the present disclosure is not limited thereto. If necessary, the buffer film may be omitted.

[0116] The pixel array layer 120 may be provided on the substrate 100. The pixel array layer 120 may include a thin film transistor TFT, a gate insulating layer 121, an interlayer insulating layer 123, a first planarization layer 125, a second planarization layer 127, a bank pattern 129, and an LED ED.

[0117] The thin film transistor TFT may be provided in a pixel region PA defined in the display area AA of the substrate 100. Meanwhile, Figure 4 The illustrated thin film transistor TFT may be a driving transistor DT electrically connected to the LED ED.

[0118] The thin film transistor TFT may include a semiconductor layer SCL provided on the substrate 100 or the buffer film, a gate electrode GE, a source electrode SE, and a drain electrode DE.Figure 4 It is shown that the thin film transistor (TFT) has a top-gate structure, in which the gate electrode (GE) is disposed on the semiconductor layer (SCL). However, the present disclosure is not limited thereto. The thin film transistor (TFT) may have a bottom-gate structure, in which the gate electrode (GE) is disposed below the semiconductor layer (SCL). Alternatively, the thin film transistor (TFT) may have a double-gate structure, in which the gate electrode (GE) is disposed on and below the semiconductor layer (SCL).

[0119] The semiconductor layer (SCL) may be disposed on the substrate 100 or the buffer film. The semiconductor layer (SCL) may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic-based semiconductor material. In addition, the semiconductor layer (SCL) may have a single-layer structure or a multi-layer structure. A light-shielding layer for blocking external light incident on the semiconductor layer (SCL) may be further disposed between the buffer film and the semiconductor layer (SCL).

[0120] The gate insulating layer 121 may be disposed over the entire substrate 100 to cover the semiconductor layer (SCL). The gate insulating layer 121 may include an inorganic layer, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer film thereof. However, the material of the gate insulating layer 121 is not limited thereto.

[0121] The gate electrode (GE) may be disposed on the gate insulating layer 121 to overlap with the semiconductor layer (SCL). For example, the gate electrode (GE) may be composed of a single layer or a multi-layer made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, the material of the gate electrode (GE) is not limited thereto. In some exemplary embodiments, the gate electrode (GE) may be prepared together with the gate line (GL).

[0122] The interlayer insulating layer 123 may be disposed over the entire substrate 100 to cover the gate electrode (GE) and the gate insulating layer 121. The interlayer insulating layer 123 may provide a flat surface on the gate electrode (GE) and the gate insulating layer 121. However, the present disclosure is not limited thereto. The interlayer insulating layer 123 may be conformally formed to have a constant thickness on the upper surface of the components disposed therebelow.

[0123] The source electrode (SE) and the drain electrode (DE) may be disposed on the interlayer insulating layer 123 to overlap with the semiconductor layer (SCL), with the gate electrode (GE) interposed between the source electrode (SE) and the drain electrode (DE). In some exemplary embodiments, the source electrode (SE) and the drain electrode (DE) may be prepared together with the data line (DL). For example, the source electrode (SE), the drain electrode (DE), and the data line (DL) may be simultaneously prepared by a process of patterning the source-drain material.

[0124] The source electrode SE and the drain electrode DE can be connected to the semiconductor layer SCL through contact holes penetrating the interlayer insulating layer 123 and the gate insulating layer 121, respectively. For example, the source electrode SE can be connected to the source region of the semiconductor layer SCL through contact holes penetrating the interlayer insulating layer 123 and the gate insulating layer 121. In addition, the drain electrode DE can be connected to the drain region of the semiconductor layer SCL through contact holes penetrating the interlayer insulating layer 123 and the gate insulating layer 121.

[0125] Each of the source electrode SE and the drain electrode DE can be composed of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0126] The thin-film transistor TFT disposed in the pixel region PA of the substrate 100 as described above can constitute the pixel circuit PC of the pixel PX.

[0127] In addition, the gate driving circuit 200 can be disposed in the gate driving circuit regions defined in each of the third non-display region NA3 and the fourth non-display region NA4 of the substrate 100. The gate driving circuit 200 can include at least one transistor. For example, the gate driving circuit 200 can include at least one transistor having a structure substantially the same as or similar to the structure of the thin-film transistor TFT disposed in the pixel region PA. However, the present disclosure is not limited thereto.

[0128] The first planarization layer 125 can be disposed on the interlayer insulating layer 123. For example, the first planarization layer 125 can be disposed on the interlayer insulating layer 123 to cover the thin-film transistor TFT and the gate driving circuit 200. The first planarization layer 125 can provide a flat surface on the thin-film transistor TFT and the gate driving circuit 200.

[0129] For example, the first planarization layer 125 can be configured as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, the material of the first planarization layer 125 is not limited thereto.

[0130] The common power line CPL can be disposed on the first planarization layer 125. For example, the common power line CPL can be disposed on the first planarization layer 125 in each of the third non-display region NA3 and the fourth non-display region NA4. For example, the common power line CPL can be disposed to overlap with the gate driving circuit 200 disposed in each of the third non-display region NA3 and the fourth non-display region NA4.

[0131] The common power line CPL may include the same material as the source electrode SE and the drain electrode DE of the thin film transistor TFT. For example, the common power line CPL may be composed of a single layer or multiple layers made of molybdenum (MO), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0132] The second planarization layer 127 may be disposed on the first planarization layer 125. For example, the second planarization layer 127 may be disposed on the first planarization layer 125 to cover the common power line CPL. The second planarization layer 127 may provide a flat surface on the common power line CPL. The second planarization layer 127 may be made of the same material as the first planarization layer 125, but is not limited thereto.

[0133] Meanwhile, Figure 4 It is shown that the common power line CPL is disposed on the first planarization layer 125. However, the present disclosure is not limited thereto. For example, the common power line CPL may be simultaneously disposed on the interlayer insulating layer 123 through the same process as the source electrode SE and the drain electrode DE of the thin film transistor TFT. In this case, the second planarization layer 127 may be omitted.

[0134] The dam pattern 129 may be disposed on the second planarization layer 127. The dam pattern 129 is disposed on the second planarization layer 127 to define an opening area OA inside the pixel area PA of the display area AA. Meanwhile, in the present disclosure, the dam pattern 129 may also be defined as a pixel defining film, and the opening area OA may also be defined as an emission area. In the present disclosure, the dam pattern 129 may also be defined as a dam layer.

[0135] The LED ED is disposed on the thin film transistor TFT and may include a first electrode AE, an emission layer EL, and a second electrode CE. Meanwhile, in the present disclosure, the first electrode AE may also be defined as an anode or a pixel driving electrode, and the second electrode CE may also be defined as a cathode or a common electrode.

[0136] The first electrode AE may be disposed on the second planarization layer 127. For example, a part of the first electrode AE may be disposed on the second planarization layer 127 to overlap at least a part of the opening area OA of the pixel area PA. In addition, another part of the first electrode AE may be disposed on the second planarization layer 127 to overlap at least a part of an area other than the opening area OA of the pixel area PA.

[0137] The first electrode AE can be connected to the source electrode SE of the thin film transistor TFT through a first contact hole CNT1 that penetrates the second planarization layer 127 and the first planarization layer 125. In this case, the edge portions of the first electrode AE except for the portion overlapping with the opening region OA of the pixel region PA can be covered by the dam pattern 129. The dam pattern 129 can cover the edge portions of the first electrode AE to define the opening region OA of the pixel region PA.

[0138] The first electrode AE can include a metal material having a high reflectivity. For example, the first electrode AE can have a multilayer structure, such as a laminated structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a laminated structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), an APC (Ag / Pd / Cu) alloy, and a laminated structure of an APC alloy and ITO (ITO / APC / ITO). Alternatively, the first electrode AE can have a single-layer structure including an alloy of one or two or more selected from silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), and barium (Ba). However, the present disclosure is not limited thereto.

[0139] The emission layer EL can be disposed over the entire display area AA of the substrate 100 to cover the first electrode AE and the dam pattern 129. The emission layer EL can include two or more emission portions for emitting white light.

[0140] For example, the emission layer EL can include a first emission portion and a second emission portion to emit white light by combining the first light and the second light. Herein, the first emission portion can be configured to emit the first light and can include one of a blue emission portion, a green emission portion, a red emission portion, a yellow emission portion, and a yellow-green emission portion. The second emission portion can include an emission portion configured to emit the second light, and the second light has a complementary color relationship with the first light among the blue emission portion, the green emission portion, the red emission portion, the yellow emission portion, and the yellow-green emission portion.

[0141] Again, for example, the emission layer EL can include one of a blue emission portion, a green emission portion, and a red emission portion to emit light of a color corresponding to the color set for the pixel PX. For example, the emission layer EL can include one of an organic emission layer, an inorganic emission layer, and a quantum dot emission layer. The emission layer EL can have a laminated or hybrid structure of an organic emission layer or an inorganic emission layer and a quantum dot emission layer.

[0142] However, the emission portions included in the emission layer EL are not limited thereto. The emission portions can be configured in various forms.

[0143] In addition, the LED ED may further include a functional layer for enhancing the emission efficiency and / or lifetime of the emission layer EL.

[0144] The second electrode CE may be disposed on the emission layer EL. The second electrode CE may be electrically connected to the emission layer EL. For example, the second electrode CE may be commonly connected to the emission layer EL provided in each pixel region PA in the entire display area AA of the substrate 100.

[0145] The second electrode CE may include a transparent conductive material or a semi-transmissive conductive material capable of transmitting light. When the second electrode CE is made of a semi-transmissive conductive material, the emission efficiency of the light emitted from the LED ED can be improved by a microcavity. For example, the semi-transmissive conductive material may include magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0146] In addition, a cover layer may be further disposed on the second electrode CE, and the cover layer is configured to adjust the refractive index of the light emitted from the LED ED and improve the emission efficiency of the light.

[0147] In addition, the common power supply connection line CPCL may be disposed on the second planarization layer 127. For example, the common power supply connection line CPCL may be disposed in the third non-display area NA3 and the fourth non-display area NA4.

[0148] The common power supply connection line CPCL may be disposed on the same layer as the first electrode AE. For example, the first electrode AE may be made of the same material as the common power supply connection line CPCL at the same time.

[0149] The common power supply connection line CPCL may be disposed to overlap at least a part of the gate driving circuit 200 and the common power supply line CPL. For example, the common power supply connection line CPCL may be disposed to overlap the gate driving circuit 200 and the common power supply line CPL in the third non-display area NA3 and the fourth non-display area NA4. In addition, the common power supply connection line CPCL may be electrically connected to the common power supply line CPL.

[0150] The edge portion of the second electrode CE provided in each of the third non-display area NA3 and the fourth non-display area NA4 of the substrate 100 may be electrically connected to the common power supply connection line CPCL through the second contact hole CNT2 penetrating the dam pattern 129.

[0151] Reference Figure 5 and Figure 6 and, the edge portion of the second electrode CE provided in each of the first non-display area NA1 and the second non-display area NA2 of the substrate 100 may also be electrically connected to the common power supply connection line CPCL through the second contact hole CNT2 penetrating the dam pattern 129.

[0152] Return reference Figure 4 , the common power connection line CPCL in the third non-display region NA3 and the fourth non-display region NA4 can be electrically connected to the common power line CPL through the third contact hole CNT3 that penetrates the second planarization layer 127.

[0153] Therefore, the second electrode CE is electrically connected to the common power line CPL through the common power connection line CPCL. Therefore, the pad portion PP can receive a constant common power supply voltage, such as the second power supply voltage VSS, through the common power line CPL and the common power connection line CPCL.

[0154] In this article, the common power line CPL for supplying a constant common power supply voltage (e.g., the second power supply voltage VSS) to the second electrode CE is arranged to overlap at least a part of the gate driving circuit 200 in the third non-display region NA3 and the fourth non-display region NA4 of the substrate 100. Therefore, the sizes of the third non-display region NA3 and the fourth non-display region NA4 of the substrate 100 can be minimized. Therefore, the bezel width of the display device 1000 can be minimized.

[0155] Meanwhile, reference Figure 5 , the common power connection line CPCL arranged in the first non-display region NA1 of the substrate 100 can extend from the outer part of the display region AA so as to cover the dam structure DM, for example, the side surfaces of the first layer and the second layer of the dam structure DM and the upper surface of the second layer. In addition, the common power connection line CPCL can be electrically connected to the common power line CPL through the fourth contact hole CNT4 that penetrates the second planarization layer 127. Reference Figure 6 , the common power connection line CPCL arranged in the second non-display region NA2 of the substrate 100 can extend from the outer part of the display region AA so as to cover the dam structure DM, for example, the side surfaces of the first layer and the second layer of the dam structure DM and the upper surface of the second layer. In addition, the common power connection line CPCL can be electrically connected to the common power line CPL through the fifth contact hole CNT5 that penetrates the second planarization layer 127.

[0156] An encapsulation layer 130 can be provided to surround the pixel array layer 120. The encapsulation layer 130 can be used to inhibit the penetration of oxygen or moisture into the LEDED.

[0157] The encapsulation layer 130 can include a first inorganic encapsulation layer 131, an organic encapsulation layer 133 on the first inorganic encapsulation layer 131, and a second inorganic encapsulation layer 135 on the organic encapsulation layer 133.

[0158] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 135 can be used to inhibit the penetration of moisture or oxygen. For example, each of the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 135 can include an inorganic material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 135 can be prepared by a chemical vapor deposition process or an atomic layer deposition process.

[0159] The organic encapsulation layer 133 can be disposed between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 135. The organic encapsulation layer 133 can be formed to have a greater thickness than the first inorganic encapsulation layer 131 and / or the second inorganic encapsulation layer 135. Thus, the organic encapsulation layer 133 can cover particles that may be generated during the manufacturing process. The organic encapsulation layer 133 can include an organic material such as silicon oxycarbide (SiOCx), acrylic, or epoxy resin. The organic encapsulation layer 133 can be prepared by a coating process such as an inkjet coating process or a slot coating process.

[0160] The dam structure DM can be disposed in the non-display area NA of the substrate 100 to inhibit the overflow of the organic encapsulation layer 133. For example, the dam structure DM can be disposed to surround the display area AA outside the gate driving circuit 200 and the common power line CPL disposed in the non-display area NA.

[0161] The dam structure DM can have a four-layer structure vertically laminated on the substrate 100. For example, the dam structure DM can include a first layer made of the same material as the first planarization layer 125 and a second layer made of the same material as the second planarization layer 127. Moreover, the dam structure DM can include a third layer made of the same material as the dam pattern 129 and a fourth layer configured as a spacer SP.

[0162] The first layer can have a trapezoidal cross-sectional structure laminated on the interlayer insulating layer 123. The second layer can have a trapezoidal cross-sectional structure laminated on the second layer. The third layer can have a trapezoidal cross-sectional structure laminated on the second layer. The fourth layer can have a trapezoidal cross-sectional structure laminated on the third layer. Meanwhile, in some exemplary embodiments, when the thickness of the organic encapsulation layer 133 is small enough to easily control the diffusibility of the organic encapsulation layer 133, the dam structure DM can be formed to have a relatively small height. For example, in this case, the fourth layer can be omitted.

[0163] The dam-shaped structure DM may be completely covered by the first inorganic encapsulation layer 131 and / or the second inorganic encapsulation layer 135. The organic encapsulation layer 133 may be in contact with a part of the inner wall surface and a part of the upper wall surface of the dam-shaped structure DM. However, the present disclosure is not limited thereto. The organic encapsulation layer 133 may be arranged to be in contact with only a part of the inner wall surface of the dam-shaped structure DM.

[0164] The touch sensor unit 140 is disposed on the encapsulation layer 130 and may include a touch buffer layer TBL, a touch electrode portion TEP, a first wiring portion TRP1, a second wiring portion TRP2, and a touch protection layer TPL.

[0165] The touch buffer layer TBL may be arranged to cover the encapsulation layer 130. The touch buffer layer TBL may provide a flat surface on the encapsulation layer 130. For example, as Figure 4 shown, the touch buffer layer TBL may be completely disposed in the display area AA, the third non-display area NA3, and the fourth non-display area NA4 so as to cover the encapsulation layer 130.

[0166] The touch buffer layer TBL may be made of an inorganic material or an organic material. The touch buffer layer TBL may be prepared by a chemical vapor deposition process.

[0167] The touch electrode portion TEP is disposed on the touch buffer layer TBL in the display area AA and may include a plurality of touch electrodes TE.

[0168] Reference will be made to Figure 5 and Figure 6 as well as Figure 4 to describe the touch electrode portion TEP in more detail. The touch electrode portion TEP may include a first touch electrode layer, a touch insulation layer TIL, and a second touch electrode layer.

[0169] The first touch electrode layer may include a plurality of bridging patterns BP disposed on the touch buffer layer TBL. Each of the plurality of bridging patterns BP may be disposed on the touch buffer layer TBL to overlap with the dam pattern 129 disposed in the display area AA.

[0170] The touch insulation layer TIL may be disposed on the touch buffer layer TBL to surround the plurality of bridging patterns BP. Herein, as Figure 4 shown, the touch insulation layer TIL may include bridge contact holes BCH for exposing one side and the other side of each of the plurality of bridging patterns BP.

[0171] The touch insulation layer TIL may contain an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). However, the material of the touch insulation layer TIL is not limited thereto.

[0172] The second touch electrode layer may include a plurality of first electrode patterns EP1 and a plurality of second touch electrodes TE2.

[0173] The plurality of first electrode patterns EP1 may be disposed on the touch insulating layer TIL to be spaced apart from each other in a first direction X and a second direction Y. In this case, as Figure 4 shown, two first electrode patterns EP1 adjacent to each other in the first direction X may be electrically connected to a bridging pattern BP through a bridge contact hole BCH. Accordingly, the plurality of first electrode patterns EP1 disposed in the first direction X are electrically connected to the plurality of bridging patterns BP, thereby forming a first touch electrode TE1.

[0174] The plurality of second touch electrodes TE2 may extend along the second direction Y and may be disposed on the touch insulating layer TIL to be spaced apart from each other in the first direction X. Accordingly, the plurality of second touch electrodes TE2 may be electrically isolated from the plurality of first touch electrodes TE1. For example, as Figure 5 and Figure 6 shown, each of the plurality of second touch electrodes TE2 may include a plurality of second electrode patterns EP2 disposed on the touch insulating layer TIL to be spaced apart from each other in the second direction Y. Moreover, each of the plurality of second touch electrodes TE2 may include a plurality of connection lines CL disposed between and electrically connecting two second electrode patterns EP2 adjacent to each other in the second direction Y. Accordingly, the plurality of second electrode patterns EP2 disposed in the second direction Y are electrically connected to the plurality of connection lines CL, thereby forming a second touch electrode TE2.

[0175] Referring to Figure 1 and Figures 4 to 6 , a first wiring portion TRP1 may be disposed in a non-display area NA (e.g., first to fourth non-display areas NA1, NA2, NA3, and NA4) to surround a display area AA of the substrate 100. The first wiring portion TRP1 may include a plurality of first wirings RL1 that electrically connect the touch electrode TE to a pad portion PP.

[0176] Each of the plurality of first wirings RL1 may be disposed on the touch insulating layer TIL in the first to fourth non-display areas NA1, NA2, NA3, and NA4.

[0177] As described above with reference to Figure 1 , each of the plurality of first wirings RL1 may be electrically connected to the pad portion PP.

[0178] In addition, as Figure 4As shown, some of the plurality of first wirings RL1 (e.g., the first wirings RL1 provided in the third non-display area NA3 and / or the fourth non-display area NA4) can be electrically connected to the plurality of first touch electrodes TE1 respectively. For example, the first wirings RL1 provided in the third non-display area NA3 and / or the fourth non-display area NA4 can extend from the third non-display area NA3 and / or the fourth non-display area NA4 to the display area AA where the touch electrode portion TEP is provided. Therefore, the first wiring RL1 can be electrically connected to the corresponding first touch electrode TE1.

[0179] In addition, as Figure 6 shown, some of the plurality of first wirings RL1 (e.g., the first wirings RL1 provided in the second non-display area NA2) can be electrically connected to the plurality of second touch electrodes TE2 respectively. For example, the first wirings RL1 provided in the second non-display area NA2 can extend from the second non-display area NA2 to the display area AA where the touch electrode portion TEP is provided. Therefore, the first wiring RL1 can be electrically connected to the corresponding second touch electrode TE2.

[0180] Referring to Figures 4 to 6 , each of the plurality of first wirings RL1 can include a lower touch wiring LRL and an upper touch wiring URL.

[0181] The lower touch wiring LRL is provided on the touch buffer layer TBL and can be made of the same conductive material as the bridging pattern BP. The lower touch wiring LRL can be made of the same material as the bridging pattern BP and be provided on the same layer as the bridging pattern BP. For example, the lower touch wiring LRL can be made of the same conductive material as the bridging pattern BP simultaneously.

[0182] The upper touch wiring URL can be provided on the touch insulation layer TIL to overlap with the lower touch wiring LRL. In addition, the upper touch wiring URL can be electrically connected to the lower touch wiring LRL through a line contact portion LCP that penetrates the touch insulation layer TIL. The upper touch wiring URL can be made of the same conductive material as the electrode patterns EP1 and EP2 of the touch electrode TE. The upper touch wiring URL can be made of the same material as the electrode patterns EP1 and EP2 of the touch electrode TE and be provided on the same layer as the electrode patterns EP1 and EP2 of the touch electrode TE. For example, the upper touch wiring URL can be made of the same conductive material as the electrode patterns EP1 and EP2 of the touch electrode TE simultaneously.

[0183] The line contact portion LCP can include a slit having a linear or dotted shape. Therefore, the upper touch wiring URL can be electrically connected to the lower touch wiring LRL through the line contact portion LCP. Therefore, the resistance of the upper touch wiring URL can be reduced through the lower touch wiring LRL.

[0184] Reference Figure 1 and Figures 4 to 6 ,the second wiring portion TRP2 can be disposed in the non-display area NA (e.g., the first to fourth non-display areas NA1, NA2, NA3, and NA4) so as to surround the display area AA of the substrate 100. The second wiring portion TRP2 can include a second wiring RL2.

[0185] Reference Figure 4 ,a part of the second wiring RL2 (e.g., the second wiring RL2 disposed in the third non-display area NA3 and the fourth non-display area NA4) can overlap with the gate driving circuit 200 and the common power line CPL. The second wiring RL2 can be disposed outside the first wiring portion TRP1 of the non-display area NA so as to overlap with the gate driving circuit 200 and the common power line CPL.

[0186] The second wiring RL2 of the second wiring portion TRP2 can be made of the same conductive material as the touch electrode TE and / or the first wiring RL1. The second wiring RL2 can be made of the same material as the touch electrode TE and / or the first wiring RL1, and be disposed on the same layer as the touch electrode TE and / or the first wiring RL1. For example, the second wiring RL2 can be made of the same conductive material as the touch electrode TE and / or the first wiring RL1 at the same time.

[0187] For example, the second wiring RL2 can have a single-layer structure, which is made of the same material as one of the bridge pattern BP, the electrode patterns EP1 and EP2, the lower touch wiring LRL, and the upper touch wiring URL at the same time. However, the structure of the second wiring RL2 is not limited thereto. Similar to the first wiring RL1, the second wiring RL2 can have a double-layer structure including a lower wiring and an upper wiring.

[0188] The second wiring RL2 is electrically connected to the common power line CPL in at least a part of the non-display area NA. Therefore, the resistance of the common power line CPL can be reduced.

[0189] For example, reference Figure 1 and Figure 5 ,the second wiring RL2 can be disposed in the first non-display area NA1 so as to overlap with the common power line CPL. The second wiring RL2 can extend to the first contact area CA1 in the first non-display area NA1 of the substrate 100. Therefore, the second wiring RL2 in the first contact area CA1 can be electrically connected to the common power line CPL through the first common contact hole CCNT1 penetrating the touch buffer layer TBL and the encapsulation layer 130.

[0190] More specifically, as Figure 5As shown, the common power supply line CPL can extend from the first non-display area NA1 to the first contact area CA1 in the first non-display area NA1 of the substrate 100 through the dam-like structure DM (e.g., the upper surface and side surface of the first layer of the dam-like structure DM). The first contact area CA1 can be located outside the dam-like structure DM in the first non-display area NA1. Herein, the second wiring RL2 can be electrically connected to the common power supply line CPL through the first common contact hole CCNT1 that exposes at least a part of the common power supply line CPL in the first contact area CA1 of the first non-display area NA1.

[0191] Accordingly, the second wiring RL2 is electrically connected to the common power supply line CPL in the first non-display area NA1 (e.g., the first contact area CA1) corresponding to the upper edge area of the display device 1000. Thus, the resistance of the common power supply line CPL can be reduced.

[0192] As described above, the second wiring RL2 can be disposed to overlap with the gate driving circuit 200 and the common power supply line CPL in the non-display area NA. In addition, the second wiring RL2 can be electrically connected to the common power supply line CPL in at least a part of the non-display area NA (e.g., the first non-display area NA1). Thus, the resistance of the common power supply line CPL can be reduced without increasing the bezel width of the display device 1000.

[0193] Reference Figures 4 to 6 , the touch protection layer TPL can be disposed to cover components included in the touch sensor unit 140, e.g., the touch electrode part TEP, the first wiring part TRP1, and the second wiring part TRP2. The touch protection layer TPL can be made of an organic material and can be used to flatten the upper part of the touch sensor unit 140, but is not limited thereto.

[0194] As described above, in the display device 1000 according to an exemplary embodiment of the present disclosure, the resistance of the common power supply line CPL can be reduced by the second wiring part TRP2 (e.g., the second wiring RL2) disposed in the non-display area NA of the substrate 100. Thus, image quality defects such as blurring caused by voltage variations in the common power supply line CPL can be suppressed.

[0195] In addition, in the display device 1000 according to an exemplary embodiment of the present disclosure, the second wiring RL2 is disposed to overlap with the common power supply line CPL in the non-display area NA. Thus, the resistance of the common power supply line CPL can be reduced without increasing the width of the common power supply line CPL or without increasing the bezel width.

[0196] In addition, in the display device 1000 according to an exemplary embodiment of the present disclosure, the common power line CPL is disposed to overlap with the gate driving circuit 200 in the non-display area NA (for example, the third non-display area NA3 and the fourth non-display area NA4 corresponding to the left and right edges of the display device 1000). Accordingly, the sizes of the third non-display area NA3 and the fourth non-display area NA4 of the substrate 100 can be minimized. Accordingly, the bezel width of the display device 1000 can be minimized.

[0197] Figure 7 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0198] Figure 7 illustrates the above reference Figure 6 a modified example of the cross-sectional structure of the display device 1000_1 in the display area AA and the second non-display area NA2 of the substrate 100 described above. Accordingly, for ease of description, repeated descriptions will be omitted.

[0199] Reference Figure 7 , the second wiring RL2 can be electrically connected to the common power line CPL_1 in at least a part of the non-display area NA (for example, the second non-display area NA2).

[0200] For example, referring to Figure 7 , the second wiring RL2 can be disposed to overlap with the common power line CPL_1 in the second non-display area NA2. In addition, the second wiring RL2 can extend to the second contact area CA2 in the second non-display area NA2 of the substrate 100. Accordingly, the second wiring RL2 in the second contact area CA2 can be electrically connected to the common power line CPL_1 through the second common contact hole CCNT2 penetrating the touch buffer layer TBL and the encapsulation layer 130.

[0201] More specifically, as Figure 7 shown, the common power line CPL_1 can extend from the second non-display area NA2 to the second contact area CA2 in the second non-display area NA2 of the substrate 100 through the dam structure DM (for example, the upper surface and the side surface of the first layer of the dam structure DM). The second contact area CA2 can be located outside the dam structure DM in the second non-display area NA2. Herein, the second wiring RL2 can be electrically connected to the common power line CPL_1 through the second common contact hole CCNT2 exposing at least a part of the common power line CPL_1 in the second contact area CA2 of the second non-display area NA2.

[0202] Accordingly, the second wiring RL2 in the above reference Figure 7In the second non-display region NA2 (e.g., the second contact region CA2) corresponding to the lower edge region of the described display device 1000_1, and in the first non-display region NA1 corresponding to the upper edge region of the display device 1000 described above, it is electrically connected to the common power line CPL_1. Therefore, the resistance of the common power line CPL_1 can be further reduced. Figure 5 In the first non-display region NA1 corresponding to the upper edge region of the described display device 1000, it is electrically connected to the common power line CPL_1. Therefore, the resistance of the common power line CPL_1 can be further reduced.

[0203] Figure 8 is a plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 9 is Figure 8 a cross-sectional view taken along line IV-IV'.

[0204] Figure 8 and Figure 9 A modified example of the connection relationship between the common power line CPL_2 and the second wiring RL2_1 is shown. Therefore, for ease of description, repeated descriptions will be omitted. Figures 1 to 6

[0205] Figure 8 Reference , a display device 1000_2 according to another exemplary embodiment of the present disclosure may include a substrate 100, a pixel array layer 120, a touch sensor unit 140, and a common power line CPL_2.

[0206] The common power line CPL_2 may have a constant line width and may be arranged to surround at least a part of the display area AA of the substrate 100. For example, the common power line CPL_2 may be arranged to surround at least a part of the display area AA in at least a part of the first non-display region NA1 and in the third and fourth non-display regions NA3 and NA4. For example, two common power lines CPL_2 may be arranged on both sides of the display area AA of the substrate 100. One end of one of the two common power lines CPL_2 may be arranged on one side of the first non-display region NA1, and the other end may be arranged in the third non-display region NA3. In addition, one end of the other of the two common power lines CPL_2 may be arranged on one side of the first non-display region NA1, and the other end may be arranged in the fourth non-display region NA4. Therefore, the common power line CPL_2 may have a shape that is at least partially open in the plan view and may be arranged in the first non-display region NA1 and the second non-display region NA2, but is not limited thereto.

[0207] ​The second wiring RL2_1 may be set to overlap with the common power supply line CPL_2. In addition, the second wiring RL2_1 may be electrically connected to the common power supply line CPL_2 in a contact area that is part of the area where the common power supply line CPL_2 is set. For example, the second wiring RL2_1 may be set to overlap with the common power supply line CPL_2 in the first non-display area NA1, the third non-display area NA3, and the fourth non-display area NA4. In addition, as described above with reference to Figures 1 to 6 it is described, the second wiring RL2_1 may be electrically connected to the common power supply line CPL_2 in the first non-display area NA1.

[0208] In addition, the second wiring RL2_1 may be electrically connected to the pad portion PP to receive a common power supply voltage, such as the second power supply voltage VSS. Herein, in the second non-display area NA2, the second wiring RL2_1 may be electrically connected to the common power supply connection line CPCL_1, and the common power supply connection line CPCL_1 is electrically connected to the second electrode CE of the LED ED. Therefore, the second electrode CE of the LED ED provided in the display area AA is electrically connected to the second wiring RL2_1 through the common power supply connection line CPCL_1. Therefore, the second wiring RL2_1 may receive a common power supply voltage, such as the second power supply voltage VSS, through the pad portion PP, the second wiring RL2_1, and the common power supply connection line CPCL_1.

[0209] This will be described in Figure 9 more detail. The common power supply line CPL_2 is not provided in the second non-display area NA2, and the common power supply connection line CPCL_1 may be directly electrically connected to the second wiring RL2_1 of the second wiring portion TRP2_1.

[0210] For example, the common power supply connection line CPCL_1 provided in the second non-display area NA2 of the substrate 100 may extend from the second non-display area NA2 to the third contact area CA3 in the second non-display area NA2 of the substrate 100 through a dam structure DM (for example, the side surfaces of the first layer and the second layer and the upper surface of the second layer of the dam structure DM). The third contact area CA3 may be located outside the dam structure DM in the second non-display area NA2. Herein, the second wiring RL2_1 may be electrically connected to the common power supply connection line CPCL_1 through a third common contact hole CCNT3 that exposes at least a part of the common power supply connection line CPCL_1 in the third contact area CA3 of the second non-display area NA2.

[0211] Accordingly, the second wiring RL2_1 is electrically connected to the common power connection line CPCL_1 in the second non-display area NA2 (e.g., the third contact area CA3) corresponding to the lower edge area of the display device 1000_2. Accordingly, the second electrode CE of the LED ED can receive a constant common power supply voltage, e.g., the second power supply voltage VSS, through the pad portion PP, the second wiring RL2_1, and the common power connection line CPCL_1.

[0212] In this document, the second wiring RL2_1 is directly connected to the common power connection line CPCL_1 which is connected to the second electrode CE, without disposing the common power line CPL_1 in the second non-display area NA2 to provide the common power supply voltage, e.g., the second power supply voltage VSS. Accordingly, the bezel width of the display device 1000_2 corresponding to the second non-display area NA2 can be further reduced.

[0213] Exemplary embodiments of the present disclosure may also be described as follows:

[0214] According to an aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area surrounding the display area; pixels disposed in the display area of the substrate and including at least one transistor and a light-emitting diode; a touch sensor unit disposed on the pixels and including at least one touch electrode; a common power line disposed in the non-display area of the substrate and connected to the light-emitting diode; and a gate driving circuit disposed in the non-display area of the substrate. The common power line and the gate driving circuit overlap each other in at least a part of the non-display area.

[0215] The non-display area may include a first non-display area provided at a first edge of the substrate, a second non-display area provided at a second edge of the substrate opposite to the first non-display area, a third non-display area provided at a third edge of the substrate, and a fourth non-display area provided at a fourth edge of the substrate opposite to the third non-display area.

[0216] The gate driving circuit may be disposed in the third non-display area and the fourth non-display area, the common power line may be disposed in a part of the first non-display area and in the second non-display area to the fourth non-display area, and the gate driving circuit and the common power line overlap each other in at least one of the third non-display area and the fourth non-display area.

[0217] The touch sensor unit may include: a touch electrode part including at least one touch electrode; a first wiring part including a first wiring provided in a part of the first non-display area and in the second to fourth non-display areas; and a second wiring part including a second wiring provided in a part of the first non-display area and in the second to fourth non-display areas, and the second wiring overlaps with the common power supply line.

[0218] The gate driving circuit and the second wiring may overlap with each other in at least one of the third non-display area and the fourth non-display area.

[0219] The second wiring may be provided outside the first wiring.

[0220] The display device may further include a dam structure provided in the first to fourth non-display areas and outside the gate driving circuit and the common power supply line.

[0221] The display device may further include a pad part provided in the first non-display area. The common power supply line may be electrically connected to the pad part to receive a common power supply voltage.

[0222] The gate driving circuit and the at least one transistor are provided on the same layer.

[0223] The display device may further include a planarization layer provided on the at least one transistor, an interlayer insulating layer provided on the planarization layer, and a bank layer provided on the interlayer insulating layer and defining a pixel area of the pixel and an opening area inside the pixel area. The light emitting diode may include: a first electrode provided on the interlayer insulating layer and connected to the at least one transistor through a first contact hole penetrating the interlayer insulating layer and the planarization layer; an emission layer provided on the first electrode and in contact with the first electrode in the opening area; and a second electrode provided on the emission layer.

[0224] The display device may further include a common power supply connection line provided on the interlayer insulating layer in the non-display area. The second electrode may be in contact with the common power supply connection line through a second contact hole penetrating the bank layer in the non-display area.

[0225] The common power supply connection line may be in contact with the common power supply line through a third contact hole penetrating the interlayer insulating layer in the third non-display area and the fourth non-display area.

[0226] The display device may further include: an encapsulation layer that extends into the non-display area while covering the pixels in the display area; and a dam structure disposed in the non-display area.

[0227] The touch sensor unit may include a first touch electrode and a second touch electrode disposed on the encapsulation layer in the display area, a first wiring disposed on the encapsulation layer in the non-display area, and a second wiring disposed on the encapsulation layer and outside the first wiring in the non-display area.

[0228] The second wiring may extend to a first contact area in the first non-display area, where at least a portion of the common power supply line is exposed, and the second wiring contacts the common power supply line in the first contact area. The first contact area may be disposed outside the dam structure.

[0229] The second wiring may extend to a second contact area in the second non-display area, where at least a portion of the common power supply line is exposed, and the second wiring may contact the common power supply line in the second contact area. The second contact area may be disposed outside the dam structure.

[0230] The gate driving circuit may be disposed in the third non-display area and the fourth non-display area. The common power supply line may be disposed in a part of the first non-display area and in the third non-display area and the fourth non-display area. The gate driving circuit and the common power supply line may overlap each other in at least one of the third non-display area and the fourth non-display area.

[0231] The second wiring may extend to a third contact area in the second non-display area, where at least a portion of the common power supply connection line is exposed, and the second wiring may contact the common power supply connection line in the third contact area. The third contact area may be disposed outside the dam structure.

[0232] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate including a display area and a non-display area surrounding the display area; pixels disposed in the display area of the substrate and each including at least one transistor and a light-emitting diode; a touch sensor unit disposed on the pixels and including at least one touch electrode; a common power line disposed in the non-display area of the substrate and connected to the light-emitting diode; and a gate driving circuit disposed in the non-display area of the substrate, wherein the common power line and the gate driving circuit overlap each other in at least a part of the non-display area.

2. The display device according to claim 1, wherein, The non-display area includes: a first non-display area disposed at a first edge of the substrate; a second non-display area disposed at a second edge of the substrate and opposite to the first non-display area; a third non-display area disposed at a third edge of the substrate; and a fourth non-display area disposed at a fourth edge of the substrate and opposite to the third non-display area.

3. The display device according to claim 2, wherein, The gate driving circuit is disposed in the third non-display area and the fourth non-display area, the common power line is disposed in a part of the first non-display area and in the second non-display area to the fourth non-display area, wherein the gate driving circuit and the common power line overlap each other in at least one of the third non-display area and the fourth non-display area.

4. The display device according to claim 3, wherein, The touch sensor unit includes: a touch electrode part including at least one touch electrode; a first wiring part including a first wiring disposed in a part of the first non-display area and in the second non-display area to the fourth non-display area; and a second wiring part including a second wiring disposed in a part of the first non-display area and in the second non-display area to the fourth non-display area, wherein the second wiring overlaps with the common power line.

5. The display device according to claim 4, wherein, The gate driving circuit and the second wiring overlap each other in at least one of the third non-display area and the fourth non-display area.

6. The display device according to claim 4, wherein, The second wiring is disposed outside the first wiring.

7. The display device according to claim 2, further comprising: a dam structure disposed in the first non-display area to the fourth non-display area and outside the gate driving circuit and the common power line.

8. The display device according to claim 2, further comprising: a pad part disposed in the first non-display area, wherein the common power line is electrically connected to the pad part to receive a common power voltage.

9. The display device according to claim 2, wherein, The gate driving circuit and the at least one transistor are disposed on the same layer.

10. The display device according to claim 2, further comprising: A planarization layer, the planarization layer being disposed on the at least one transistor; An interlayer insulating layer, the interlayer insulating layer being disposed on the planarization layer; And A partition layer, the partition layer being disposed on the interlayer insulating layer and defining a pixel region of the pixel and an opening region inside the pixel region, Wherein, the light-emitting diode includes: A first electrode, the first electrode being disposed on the interlayer insulating layer and connected to the at least one transistor through a first contact hole penetrating the interlayer insulating layer and the planarization layer; An emission layer, the emission layer being disposed on the first electrode and in contact with the first electrode in the opening region; and A second electrode, the second electrode being disposed on the emission layer.

11. The display device according to claim 10, further comprising: A common power supply connection line, the common power supply connection line being disposed on the interlayer insulating layer in the non-display region, Wherein, the second electrode is in contact with the common power supply connection line through a second contact hole penetrating the partition layer in the non-display region.

12. The display device according to claim 11, wherein, The common power supply connection line is in contact with the common power supply line through a third contact hole penetrating the interlayer insulating layer in the third non-display region and the fourth non-display region.

13. The display device according to claim 12, further comprising: An encapsulation layer, the encapsulation layer extending to the non-display region while covering the pixels in the display region; And A dam structure, the dam structure being disposed in the non-display region.

14. The display device according to claim 13, wherein, The touch sensor unit includes: A first touch electrode and a second touch electrode, the first touch electrode and the second touch electrode being disposed on the encapsulation layer in the display region; A first wiring, the first wiring being disposed on the encapsulation layer in the non-display region; and A second wiring, the second wiring being disposed on the encapsulation layer and outside the first wiring in the non-display region.

15. The display device according to claim 14, wherein, The second wiring extends to a first contact region in the first non-display region, wherein in the first contact region, at least a part of the common power supply line is exposed, and the second wiring is in contact with the common power supply line in the first contact region, Wherein, the first contact region is disposed outside the dam structure.

16. The display device according to claim 14, wherein, The second wiring extends to a second contact region in the second non-display region, wherein in the second contact region, at least a part of the common power supply line is exposed, and the second wiring is in contact with the common power supply line in the second contact region, Wherein, the second contact region is disposed outside the dam structure.

17. The display device according to claim 2, wherein, The gate driving circuit is disposed in the third non-display region and the fourth non-display region, The common power supply line is disposed in a part of the first non-display region and in the third non-display region and the fourth non-display region, Wherein, the gate driving circuit and the common power supply line overlap with each other in at least one of the third non-display region and the fourth non-display region.

18. The display device according to claim 14, wherein, The second wiring extends to a third contact region in the second non-display region, wherein at least a part of the common power supply connection line is exposed in the third contact region, and the second wiring contacts the common power supply connection line in the third contact region. Wherein, the third contact region is provided outside the dam structure.

19. The display device according to claim 11, wherein, The common power supply connection line is arranged to overlap at least a part of the gate driving circuit and the common power supply line.

20. The display device according to claim 19, wherein, The common power supply connection line is arranged to overlap the gate driving circuit and the common power supply line in the third non-display region and the fourth non-display region.

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