Manufacturing method of semiconductor packaging structure and semiconductor packaging structure

Abstract

The invention discloses a manufacturing method of a semiconductor packaging structure and the semiconductor packaging structure, and the manufacturing method of the semiconductor packaging structure comprises the following steps: providing a wafer-level chip, the functional surface of the wafer-level chip being provided with an isolation voltage-withstanding layer; cutting the wafer level chip to obtain a plurality of single chips; wherein each chip comprises a back surface opposite to the functional surface and a side surface connected with the functional surface and the back surface; fixing the plurality of chips on the mounting surface of the same carrier plate, wherein the functional surfaces of the chips face the mounting surface of the carrier plate; at least forming a voltage-withstanding layer on the side surface of the chip; separating the carrier plate and the chips, and cutting an area between the adjacent chips to obtain a single chip structure; an isolation voltage-resistant layer is formed on the chip structure so as to realize an insulation and voltage-resistant function between the chip structure and the base island.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and particularly to a chip packaging structure and a wafer-level packaging method. Background Art

[0002] In the prior art, in order to ensure good voltage withstand characteristics during the packaging of Hall sensor chips, an insulating voltage withstand layer needs to be inserted between the chip and the base island, and the insulating voltage withstand layer needs to be larger than the chip size. The materials of the commonly used insulating voltage withstand layers are mainly substrates or polyimide films. The biggest limitation of these two types is their very low voltage withstand breakdown life. Moreover, in order to ensure good insulation, there are great requirements for the thickness of the voltage withstand layer. Currently, the thinnest on the market can only reach 75 μm. Due to the relatively large thickness of the voltage withstand layer, the Hall points of the chip are farther from the base island, thus reducing the coupling coefficient value. Moreover, the processing of the insulating voltage withstand layer adds a mounting process. Due to the limitation of control capabilities, the quality of mounting is difficult to be perfect, and there are defects such as tiny air bubbles, which have an obvious impact on the quality of the product. Summary of the Invention

[0003] One of the purposes of the present invention is to provide a manufacturing method of a semiconductor packaging structure to at least solve the technical problem in the prior art that an insulating voltage withstand film needs to be mounted between the chip and the base island.

[0004] To achieve the above-mentioned one of the invention purposes, an embodiment of the present invention provides a manufacturing method of a semiconductor packaging structure, including the following steps:

[0005] Provide a wafer-level chip, wherein the functional surface of the wafer-level chip has an isolation voltage withstand layer;

[0006] Cut the wafer-level chip to obtain a plurality of single chips; each of the chips includes a back surface opposite to the functional surface and a side surface connecting the functional surface and the back surface;

[0007] Fix a plurality of the chips on the mounting surface of the same carrier board, wherein the functional surface of the chip faces the mounting surface of the carrier board;

[0008] Form a voltage withstand layer at least on the side surface of the chip;

[0009] Separate the carrier board and the chip, and cut the area between adjacent chips to obtain single chip structures.

[0010] As a further improvement of an embodiment of the present invention, the step of providing a wafer-level chip includes:

[0011] Deposit a silicon dioxide material on the functional surface of the wafer-level chip, and the wafer-level chip includes a pad area provided on the functional surface;

[0012] Etch the silicon dioxide material on the surface of the pad area to expose the pad area.

[0013] As a further improvement of an embodiment of the present invention, forming a voltage-resistant layer at least on the side of the chip includes: depositing silicon dioxide material on the mounting surface of the carrier board and the area between adjacent chips to form the voltage-resistant layer; wherein the voltage-resistant layer connects two adjacent chips.

[0014] As a further improvement of an embodiment of the present invention, forming a voltage-resistant layer at least on the side of the chip includes: fabricating a voltage-resistant layer on the side and back of the chip.

[0015] As a further improvement of an embodiment of the present invention, fixing a plurality of the chips to the mounting surface of the same carrier board includes: pasting the functional surfaces of a plurality of the chips to the mounting surface of the same carrier board, wherein the mounting surface of the carrier board has an adhesive film.

[0016] As a further improvement of an embodiment of the present invention, separating the carrier board and the chip includes: heating the carrier board to separate the adhesive film from the chip.

[0017] As a further improvement of an embodiment of the present invention, the following steps are further included:

[0018] Provide a lead frame, the lead frame includes pins, a base island and metal wires; wherein the pins include opposite first and second surfaces, and the base island includes opposite third and fourth surfaces;

[0019] Arrange the chip structure on the third surface of the base island, with the isolation voltage-resistant layer facing the third surface, and the chip structure includes a pad area located on the functional surface;

[0020] Connect the metal wires to the pad area of the chip structure and the second surface of the pins, and the third surface of the base island and the second surface of the pins are located on opposite sides of the lead frame.

[0021] As a further improvement of an embodiment of the present invention, arranging the chip structure on the third surface of the base island includes:

[0022] Turn the third surface of the base island and the first surface of the pins upwards; the third surface of the base island and the first surface of the pins are the front of the lead frame;

[0023] Turn the isolation voltage-resistant layer of the chip structure downwards to bond the isolation voltage-resistant layer to the third surface of the base island.

[0024] As a further improvement of an embodiment of the present invention, before connecting the metal wires to the pad area of the chip structure and the second surface of the pins includes:

[0025] Flip the lead frame and the chip structure so that the fourth surface of the base island and the second surface of the pins face upward, and the pad area of the chip structure faces upward; wherein the fourth surface of the base island and the second surface of the pins are the back surfaces of the lead frame.

[0026] To achieve one of the above-mentioned invention purposes, an embodiment of the present invention provides a semiconductor package structure, which is fabricated by using the manufacturing method of the semiconductor package structure described in any one of the above technical solutions. The semiconductor package structure includes a lead frame and the chip structure disposed on the lead frame.

[0027] As a further improvement of an embodiment of the present invention, the chip structure includes a functional area and a pad area disposed on the functional surface. The pad area is located outside the functional area and is exposed.

[0028] As a further improvement of an embodiment of the present invention, the isolation and voltage withstand layer is a silicon dioxide layer, and the thickness of the isolation and voltage withstand layer is not less than 20um.

[0029] As a further improvement of an embodiment of the present invention, the voltage withstand layer is a silicon dioxide layer, and the thickness of the voltage withstand layer is not less than 20um.

[0030] As a further improvement of an embodiment of the present invention, the lead frame includes pins and a base island. The pad area extends beyond the outer edge of the base island to be exposed, and the pad area extends beyond the outer edge of the base island by not less than 400um.

[0031] Compared with the prior art, the present invention provides a manufacturing method of a semiconductor package structure. The functional surface of the chip structure is formed with an isolation and voltage withstand layer, and the side surface is also formed with a voltage withstand layer, eliminating the step of mounting an isolation and voltage withstand film, preventing mounting defects, and the above isolation and voltage withstand layer is thinner and more voltage-resistant. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1a is a schematic diagram of a semiconductor package structure in an embodiment of the present invention.

[0033] Figure 1b is a flowchart of a manufacturing method of a semiconductor package structure in an embodiment of the present invention.

[0034] Figure 2 is a schematic diagram of a wafer-level chip in an embodiment of the present invention.

[0035] Figure 3 is a schematic diagram of fabricating a chip structure in an embodiment of the present invention.

[0036] Figure 4 is a schematic diagram of a chip structure in an embodiment of the present invention.

[0037] Figure 5 It is a schematic diagram of a lead frame in an embodiment of the present invention.

[0038] Figure 6 It is a schematic diagram of manufacturing a lead frame in an embodiment of the present invention.

[0039] Figure 7 It is a schematic diagram of the cooperation between a chip structure and a lead frame in an embodiment of the present invention.

[0040] Figure 8 It is a schematic diagram of a metal wire connecting a pad region and a pin in an embodiment of the present invention. Specific Embodiments

[0041] The present invention will be described in detail below in conjunction with the specific embodiments shown in the drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional transformation made by those of ordinary skill in the art based on these embodiments is included in the protection scope of the present invention.

[0042] It should be noted that the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or device. In addition, the terms "first", "second", "third", "fourth", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0043] The term "connected", "connected to" or any other variant is intended to cover various relative positions of existing connection relationships, so as to include direct connection or indirect connection. Among them, direct connection can be formed through the construction of a gas pipeline, and indirect connection can be a connection relationship constructed through devices such as valve bodies and sensors, can be a connection relationship constructed through gas pipeline components such as a brake control unit, or can be a connection relationship constructed through other media such as air.

[0044] Please refer to Figure 1a , which is a schematic diagram of a semiconductor package structure 100 provided by an embodiment of the present invention, specifically a Hall sensor chip package structure.

[0045] The semiconductor package structure 100 includes a lead frame 10 and a chip structure 30 disposed on the lead frame 10, and the chip structure 30 is a Hall sensor chip.

[0046] The lead frame 10 includes pins 11, a base island 13, and metal wires 15. The chip structure 30 is disposed on the base island 30 and is bonded to the pins 11 through the metal wires 15 to achieve electrical connection. Obviously, the semiconductor package structure 100 is formed by a wire bonding process in this application.

[0047] Specifically, this application is a magnetic current sensor. In this application, the lead frame 10 is made of a low-magnetic or non-magnetic copper foil material. For example, copper grades such as C192 / C151 / KFC / EFTEC64T can be optionally used. The initial frame can be fabricated by an etching process of exposure and development, or can also be formed by die stamping. The metal wires 15 are used to electrically connect the chip structure 30 and the pins 11. Gold wires or copper wires can be optionally used to ensure good electrical conductivity.

[0048] In the prior art, the semiconductor package structure usually further includes an insulating and voltage-resistant film disposed between the chip structure 30 and the base island 13, such as a polyimide film, a substrate, a glass silicon wafer, etc. The insulating and voltage-resistant film is usually pasted on the base island 13. The mucosal process of the lead frame 10 is likely to introduce interface defects, such as mounting bubbles. This application eliminates the setting of the film and optimizes the process of laminating the film on the surface of the lead frame 10 to avoid obvious interface defects.

[0049] In this application, an isolation and voltage-resistant layer 50 is formed on the surface of the chip structure 30 to replace the insulating and voltage-resistant film to achieve insulation and voltage resistance functions, with a thinner thickness and a higher voltage resistance value. Hereinafter, the forming method of the isolation and voltage-resistant layer 50 will be described in detail.

[0050] Please refer to Figure 1b , a manufacturing method of a semiconductor package structure 100, includes the following steps:

[0051] S1: Provide a wafer-level chip 200, wherein the functional surface of the wafer-level chip 200 has an isolation and voltage-resistant layer 50; as shown in combination Figure 2 , it is equivalent to first fabricating the isolation and voltage-resistant layer 50 on the functional surface of the array chip 200a.

[0052] The isolation and voltage-resistant layer 50 is preferably a silicon dioxide layer, and the thickness is not less than 20um, which has a higher voltage resistance value compared to a polyimide film, a substrate, a glass silicon wafer, etc.

[0053] Among them, providing the wafer-level chip 200 includes:

[0054] Depositing silicon dioxide material on the functional surface of the wafer-level chip 200. The wafer-level chip 200 includes a pad area disposed on the functional surface. It can be understood that each single chip 200a should have a pad area 31. The material of the isolation and voltage-resistant layer 50 is silicon dioxide, and the voltage resistance can withstand a surge of more than 10KV.

[0055] Etch the silicon dioxide material on the surface of the pad region 31 to expose the pad region 31. It can be understood that the functional surface needs to expose the pad region 31 for subsequent welding.

[0056] Above, the initial wafer manufacturer or packaging manufacturer can grow a silicon dioxide layer with a thickness of not less than 20um on the functional surface of the chip through the silicon dioxide deposition process. This layer can achieve insulation and voltage withstand protection between the subsequent chip structure 30 and the base island 13. The silicon dioxide can withstand 500V / um, so only a 20um silicon dioxide layer thickness is required to meet a surge of not less than 10KV. Compared with separately making an insulation and voltage withstand film with a thickness exceeding 75um, a silicon dioxide layer of not less than 20um can more effectively improve the voltage withstand value and coupling coefficient value.

[0057] S2: Cut the wafer-level chip 200 to obtain a number of single chips 200a; Combine Figure 3 As shown, each of the chips 200a includes a back surface opposite to the functional surface and a side surface connecting the functional surface and the back surface; It can be understood that the functional surface of each obtained chip 200a has an isolation and voltage withstand layer 50.

[0058] S3: Fix a number of the chips 200a on the mounting surface of the same carrier 300, with the functional surface of the chip 200a facing the mounting surface of the carrier 300. Specifically, it includes: pasting the functional surfaces of a number of the chips 200a on the mounting surface of the same carrier 300, where the mounting surface of the carrier 300 has an adhesive film.

[0059] Combine Figure 3 As shown, provide a carrier 300. The material of the carrier 300 can be selected as a steel plate, silicon, or glass substrate. One side surface of the carrier 300 has an adhesive film to form a mounting surface for fixing and installing the chip 200a.

[0060] S4: Form a voltage withstand layer 50a at least on the side surface of the chip 200a. The functional surface of the above chip 200a has an isolation and voltage withstand layer 50. During cutting, the side surface of the chip 200a has exposed silicon material. To achieve more comprehensive protection of the chip 200a, a voltage withstand layer 50a also needs to be formed on the surrounding side surfaces of the chip 200a.

[0061] The voltage withstand layer 50a is preferably a silicon dioxide layer with a thickness of not less than 20um, which has a higher voltage withstand value compared to polyimide films, substrates, glass silicon wafers, etc.

[0062] Among them, forming a voltage-resistant layer 50a on at least the side surface of the chip 200a includes: depositing a silicon dioxide material on the mounting surface of the carrier board 300 and the area between adjacent chips 200a to form the voltage-resistant layer 50a; the voltage-resistant layer 50a connects two adjacent chips 200a.

[0063] Continue to combine Figure 3 , the deposited silicon dioxide covers the area between adjacent chips 200a to wrap the side surface of the chip 200a, forming the voltage-resistant layer 50a. The distance between the voltage-resistant layers 50a between adjacent chips 200a needs to be not less than 80 um. In this way, after cutting, the thickness of the isolation voltage-resistant layer 50a on the side surface of each chip structure 30 can be ensured to be not less than 20 um, ensuring a sufficient voltage-resistant value.

[0064] Among them, the manufacturing method of the semiconductor packaging structure 100 includes the steps of: forming a voltage-resistant layer 50a on the side surface and the back surface of the chip 200a. Specifically, it includes: depositing a silicon dioxide material on the mounting surface of the carrier board 300, the area between adjacent chips 200a, and the back surface of the chip 200a to form the voltage-resistant layer 50a. The thickness of the voltage-resistant layer 50a formed on the back surface of 200a is not less than 20 um.

[0065] Combine Figure 3-4 As shown, the deposited silicon dioxide completely wraps the side surface and the back surface of the chip 200a. Coupled with the isolation voltage-resistant layer 50 set in advance on the functional surface, equivalently, each surface of the chip 200a is wrapped by a silicon dioxide layer, realizing a better isolation and voltage-resistant function.

[0066] In this application, the isolation voltage-resistant layer 50 and the voltage-resistant layer 50a are preferably made of silicon dioxide material. In other embodiments, materials with high voltage-resistant life such as alumina or benzocyclobutene (BCB) can also be selected. The high-voltage life of such materials is dozens or hundreds of times that of conventional polyimide films and substrates. Generally, silicon dioxide and alumina can be made by deposition, while special polymer films such as benzocyclobutene (BCB) can be made by coating processes.

[0067] S5: Separate the carrier board 300 and the chip 200a, and cut the area between adjacent chips 200a to obtain single-chip structures 30. Specifically, it includes the steps of: heating the carrier board 300 to separate the adhesive film from the chip 200a. A number of chips 200a connected by the voltage-resistant layer 50a are formed into chip structures 30 after being cut again. The chip structure 30 includes an isolation voltage-resistant layer 50 on the functional surface and voltage-resistant layers 50a on the side surface and the back surface.

[0068] Thus, this application optimizes on the traditional insulating and voltage-withstanding film of the magnetoelectric current, eliminates the use of conventional insulating and voltage-withstanding films, greatly simplifies the packaging process flow and difficulty, reduces interface defects, and improves the performance of the product. When manufacturing the isolation voltage-withstanding layer 50, a wafer-level processing technology is adopted, which is more advanced, and the precision and quality are well improved. Under the same voltage-withstanding requirements, a thinner isolation voltage-withstanding layer 50 is manufactured, so that the functional surface of the chip structure 30 is closer to the base island 13, improving the coupling coefficient of the product. Materials such as silicon dioxide are used as the insulating and voltage-withstanding layer, and its voltage-withstanding life characteristics are much higher than those of polymer materials such as polyimide. A greater improvement lies in the good high-voltage reliability and long life of the product.

[0069] The manufacturing method of the semiconductor packaging structure 100 described in this application further includes the following steps:

[0070] S6: Provide a lead frame 10, wherein the lead frame 10 includes pins 11, a base island 13, and metal wires 15; wherein the pins 11 include opposite first and second faces, and the base island 13 includes opposite third and fourth faces. Combine Figure 5-6 As shown, the lead frame 10 is formed by etching or stamping a copper foil material. A plurality of the pins 11 are strip-shaped, and the pins 11 and the base island 13 of the initial frame are both connected to the outer frame, forming an overall arrangement distribution.

[0071] Among them, the step of providing the lead frame 10 includes:

[0072] Provide an initial frame 10a, including initial pins 11a and a base island 13; Combine Figure 6 As shown in c, although the initial frame 10a is also a three-dimensional structure, the front faces of the initial pins 11a and the base island 13 are in the same plane, and the back faces of the initial pins 11a and the base island 13 are also in the same plane.

[0073] Bend the initial pins 11a to obtain the pins 11, and the degree of bending needs to be controlled during bending. Combine Figure 6 As shown in d, the initial pins 11a are formed into pins 11 after two bends. The pins 11 include outer pin portions 111, connecting portions 112, and inner pin portions 113. The outer pin portions 111 are arranged away from the base island 13, the inner pin portions 113 are arranged close to the base island, and the connecting portions 112 connect the inner pin portions 113 and the outer pin portions 111.

[0074] Among them, providing the initial frame 10a includes: electroplating a coating 110 at the end of the second face of the initial pins 11a, and the coating 110 is used to connect the pad area 31.

[0075] Specifically, combine Figure 6As shown in Figure a-6b, a copper foil material is provided. The copper foil material is formed into an initial pin 11a through etching or stamping. Electroplating is performed on the second side of the initial pin 11a near the end of the base island 13 to obtain a plating layer 110. The plating layer 110 does not contain magnetic materials such as nickel. A silver plating layer can generally meet the requirements of subsequent packaging and soldering. In other embodiments, a gold plating layer with better conductivity can also be selected.

[0076] It can be understood that electroplating the initial pin 11a is simpler than electroplating the bent pin 11. After electroplating, the initial pin 11a is dimpled, that is, bent, to obtain the final pin 11 structure, so as to reserve a wire bonding space on the back side of the lead frame 10.

[0077] S7: The chip structure 30 is disposed on the third side of the base island 13, where the isolation and voltage withstand layer 50 of the chip structure faces the third side. The chip structure 30 includes a pad area 31 on the functional surface. The electroplating and bending processes of the above-mentioned lead frame 10 are both performed on the back side of the lead frame 10. Next, in combination with Figure 7 As shown, the lead frame 10 is flipped to dispose the chip structure 30 on the front side of the lead frame 10, which is equivalent to disposing the chip structure 30 on the third side of the base island 13. It can be seen that the plating layer 110 is located on the second side of the pin 11, that is, the back side of the lead frame 10, while the chip structure 30 is located on the third side of the base island, that is, the front side of the lead frame 10.

[0078] Among them, disposing the chip structure 30 on the third side of the base island includes the steps of:

[0079] Turn the third side of the base island 13 and the first side of the pin 11 upward; the third side of the base island 13 and the first side of the pin 11 are the front side of the lead frame; that is, turn the front side of the lead frame 10 upward.

[0080] Turn the isolation and voltage withstand layer 50 of the chip structure 30 downward to bond the isolation and voltage withstand layer 50 to the third side of the base island 13. The isolation and voltage withstand layer 50 of the chip structure 30 is directly pasted at a specified position of the base island 13, and a non-conductive glue can be selected as the adhesive.

[0081] S8: Connect the metal wire 15 to the pad area 31 of the chip structure 30 and the second side of the pin 11, where the third side of the base island 13 and the second side of the pin 11 are located on opposite sides of the lead frame 10. In combination with Figure 8 As shown, the functional surface of the chip structure 30 faces the base island 13, so that the distance from the base island 13 is closer. The metal wire 15 connects the pad area 11 and the plating layer 110 on the back side of the lead frame 10. When welding the metal wire 15, the wire arc height of the metal wire 15 needs to be controlled.

[0082] Before the lead metal wire connects the pad region and the second surface of the pin, the following steps are included:

[0083] Flip the lead frame 10 and the chip structure 30 so that the fourth surface of the base island 13 and the second surface of the pin 11 face upward, and the pad region 31 of the chip structure 30 faces upward; wherein the fourth surface of the base island 13 and the second surface of the pin 11 are the back surfaces of the lead frame 10. That is, turn the back surface of the lead frame 10 upward and perform the wire bonding operation.

[0084] It can be understood that before wire bonding, the isolation withstand voltage layer 50 and the chip structure 30 are set, and operations need to be performed on the front surface of the lead frame 10. Therefore, when performing wire bonding, it is necessary to flip the lead frame 10 to the back surface for operation.

[0085] When flipping, the lead frame 10 can be flipped by a carrier / fixture so that the pad region 31 and the plating layer 110 face upward. When welding the metal wire 15, since the chip structure 30 is flipped to be located below, in order to avoid damaging the chip structure 30 due to the acting force during wire bonding welding, the chip structure 30 can be carried by a special hot plate to avoid the chip structure 30 being suspended and damaged. The above-mentioned chip structure 30 reverse bonding process only needs to be paired with two flips of the lead frame 10, and the packaging process is simple, greatly improving the coupling coefficient of the packaged product.

[0086] After the wire bonding between the chip structure 30 and the pin 11 is completed, a further encapsulation process can be performed to ensure the stability of the connection between the lead frame 10 and the chip structure 30, and to protect the lead frame 10 and the chip structure 30 inside, etc. Refer to Figure 7-8 As shown, the dashed outer frame indicates the outer border of the finished encapsulation body 60.

[0087] It can be understood that for the finished product of the semiconductor packaging structure formed after the above encapsulation, there is a certain positional relationship among the inner pin part 111, the metal wire 15, and the encapsulation body 60 to ensure reasonable space utilization.

[0088] In one embodiment, the minimum vertical distance A between the first surface of the pin 11 and the front surface of the encapsulation body 60 is not less than 100 um, and the front surface of the encapsulation body 60 and the front surface of the lead frame 10 face the same side; more specifically, the vertical distance A between the first surface of the inner pin part 113 and the front surface of the encapsulation body 60 is not less than 100 um. In this way, the concave area of the pin 11 and the wire bonding area of the metal wire 15 can be controlled, the space can be reasonably utilized, which is beneficial to the compactness and miniaturization of the semiconductor packaging structure 100.

[0089] In this application, the metal wire 15 is on the back side of the lead frame 10. The vertical distance B between the second surface of the inner lead portion 113 and the back surface of the encapsulant 60 needs to further consider the height of the arc-shaped metal wire 15. The front surface of the encapsulant 60 corresponds to and faces the same side as the front surface of the lead frame 10. It can be understood that the semiconductor package structure 100 is a three-dimensional structure. The front surface of the encapsulant 60 and the front surface of the lead frame 10 are not necessarily in the same plane, but can be reasonably considered to face the same side. Specifically, it can be considered to face the front side of the semiconductor package structure 100.

[0090] In one embodiment, the metal wire 15 is arc-shaped after connecting the pad region 31 and the second surface of the lead 11. The minimum vertical distance between the metal wire 15 and the back surface of the encapsulant 60 is not less than 100 um. Specifically, the metal wire 15 has a highest point C in the thickness direction of the lead frame 10. The vertical distance between the highest point C and the back surface of the encapsulant 60 is not less than 100 um. Above, for the area control of wire bonding, the height control of the highest point of the metal wire 15 along the thickness direction between its two ends is not less than 90 um, and the distance between the highest point C of the wire arc and the back surface of the encapsulant 60 is not less than 100 um.

[0091] The semiconductor package structure 100 of this application is made by using the manufacturing method of the semiconductor package structure 100 described in any one of the above technical solutions. The semiconductor package structure 100 includes the above-mentioned lead frame 10 and the chip structure 30 disposed on the lead frame 10.

[0092] The lead 11 includes opposite first and second surfaces. The base island 13 includes opposite third and fourth surfaces. The first surface and the third surface are the front surfaces of the lead frame 10, and the second surface and the fourth surface are the back surfaces of the lead frame 10. In other words, the first surface and the third surface are on the front side of the lead frame 10, and the second surface and the fourth surface are on the back side of the lead frame 10.

[0093] The functional surface of the chip structure 30 faces the third surface of the base island 13. The functional surface includes a pad region 31. The metal wire 15 connects the pad region 31 and the second surface of the lead 11. Equivalently, the metal wire 15 is on the back side of the lead frame 10.

[0094] In the prior art, on the front side of the lead frame 10, an isolation and voltage withstand film and a chip structure are usually sequentially disposed on the third surface of the base island. For the convenience of subsequent wire bonding, the chip structure is usually also directly attached to the isolation and voltage withstand film. Equivalently, the functional surface of the chip structure faces upward and thus deviates from the third surface of the base island. The functional surface of the chip structure faces upward and thus performs wire bonding with the first surface of the lead. In this way, the vertical distance between the Hall point on the functional surface of the chip structure and the base island is too large, affecting the coupling coefficient value.

[0095] In this application, the chip structure 30 is reversely attached to the base island 13, and the isolation and voltage withstand layer 50 is pasted on the third side of the base island. At this time, the functional surface of the chip structure 30 and the second surface of the lead 11 are on the same side and are correspondingly located on the back side of the lead frame 10. Therefore, the metal wire 15 electrically connects the pad area 31 and the second surface of the lead 11.

[0096] The chip structure 30 includes a functional area 32 and a pad area 31 provided on the functional surface. The pad area 31 is provided outside the functional area 32 and is exposed. It can be understood that when the pad area 31 is provided on the functional surface and the functional surface faces the base island 13, in order to ensure the function of the pad area 31, the pad area 31 cannot be blocked by the base island 13. Therefore, the pad area 31 is set to be outside and exposed. More specifically, it is exposed between the outer edge of the base island 13 and the lead 11 to facilitate subsequent bonding connection of the metal wire 15.

[0097] In one embodiment, the pad area 31 is exposed at the outer edge of the base island 13, and the pad area 31 extends beyond the outer edge of the base island by not less than 400 um to ensure good insulation performance between the chip structure 30 and the base island 13.

[0098] The beneficial effects of the present invention are as follows: The chip structure 30 is formed with an isolation and voltage withstand layer 50. When manufacturing the isolation and voltage withstand layer 50, a wafer-level processing technology is adopted, which is more advanced, and the accuracy and quality are well improved; The process of laminating the film on the lead frame 10 is optimized, reducing the interface defects and improving the performance of the product; Under the condition of meeting the same voltage withstand requirements, a thinner isolation and voltage withstand layer 50 is manufactured, and the functional surface of the chip structure 30 is closer to the base island 13, improving the coupling coefficient of the product; Materials such as silicon dioxide are used as the insulation and voltage withstand layer, and its voltage withstand life characteristics are much higher than those of polymer materials such as polyimide. The final product has good high-voltage reliability and a long life.

[0099] It can be formed corresponding to any of the technical solutions provided above, and will not be elaborated here.

[0100] It should be understood that although this specification is described according to the embodiments, not each embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0101] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present invention, and they are not used to limit the protection scope of the present invention. Any equivalent embodiments or changes made without departing from the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A manufacturing method of a semiconductor packaging structure, characterized in that, The method includes the following steps: Provide a wafer-level chip, wherein an isolation voltage withstand layer is provided on the functional surface of the wafer-level chip; Cut the wafer-level chip to obtain a plurality of single chips; each of the chips includes a back surface opposite to the functional surface and a side surface connecting the functional surface and the back surface; Fix a plurality of the chips on the mounting surface of the same carrier, wherein the functional surface of the chip faces the mounting surface of the carrier; Form a voltage withstand layer at least on the side surface of the chip; Separate the carrier and the chips, and cut the area between adjacent chips to obtain a plurality of single chip structures.

2. The manufacturing method of the semiconductor packaging structure according to claim 1, wherein, Providing the wafer-level chip includes: Deposit a silicon dioxide material on the functional surface of the wafer-level chip, wherein the wafer-level chip includes a pad area provided on the functional surface; Etch the silicon dioxide material on the surface of the pad area to expose the pad area.

3. The method for manufacturing a semiconductor package structure according to claim 1, wherein Forming a voltage withstand layer at least on the side surface of the chip includes: depositing a silicon dioxide material on the mounting surface of the carrier and the area between adjacent chips to form the voltage withstand layer; wherein the voltage withstand layer connects two adjacent chips.

4. The method for manufacturing the semiconductor package structure according to claim 1, wherein, Forming a voltage withstand layer at least on the side surface of the chip includes: forming a voltage withstand layer on the side surface and the back surface of the chip.

5. The manufacturing method of the semiconductor package structure according to claim 1, wherein Fixing a plurality of the chips on the mounting surface of the same carrier includes: pasting the functional surfaces of a plurality of the chips on the mounting surface of the same carrier, wherein the mounting surface of the carrier has a film.

6. The method for manufacturing a semiconductor package structure according to claim 5, wherein, Separating the carrier and the chips includes: heating the carrier to separate the film from the chips.

7. The method for manufacturing a semiconductor package structure according to claim 1, wherein, The method further includes the following steps: Provide a lead frame, the lead frame includes pins, a base island and metal wires; wherein the pins include opposite first and second surfaces, and the base island includes opposite third and fourth surfaces; Dispose the chip structure on the third surface of the base island, wherein the isolation voltage withstand layer of the chip structure faces the third surface, and the chip structure includes a pad area located on the functional surface; Connect the pad area of the chip structure and the second surface of the pin with a metal wire, wherein the third surface of the base island and the second surface of the pin are located on opposite sides of the lead frame.

8. The method for manufacturing a semiconductor package structure according to claim 7, wherein, Disposing the chip structure on the third surface of the base island includes: Turn the third surface of the base island and the first surface of the pin upward; wherein the third surface of the base island and the first surface of the pin are the front surface of the lead frame; Turn the isolation voltage withstand layer of the chip structure downward to bond the isolation voltage withstand layer to the third surface of the base island.

9. The method for manufacturing a semiconductor package structure according to claim 8, wherein, Before connecting the pad area of the chip structure and the second surface of the pin with a metal wire: Flip the lead frame and the chip structure so that the fourth surface of the base island and the second surface of the pin face upward, and the pad area of the chip structure faces upward; wherein the fourth surface of the base island and the second surface of the pin are the back surface of the lead frame.

10. A semiconductor package structure, characterized in that, Manufactured by using the manufacturing method of the semiconductor package structure according to any one of claims 1-9, the semiconductor package structure includes a lead frame and the chip structure disposed on the lead frame.

11. The semiconductor package structure according to claim 10, wherein The chip structure includes a functional area and a pad area provided on the functional surface, and the pad area is located outside the functional area and is exposed.

12. The semiconductor package structure according to claim 10, wherein, The isolation and voltage withstand layer is a silicon dioxide layer, and the thickness of the isolation and voltage withstand layer is not less than 20 um.

13. The semiconductor package structure according to claim 10, wherein The voltage withstand layer is a silicon dioxide layer, and the thickness of the voltage withstand layer is not less than 20 um.

14. The semiconductor package structure according to claim 11, wherein, The lead frame includes pins and a base island, the pad area extends beyond the outer edge of the base island to be exposed, and the pad area extends beyond the outer edge of the base island by not less than 400 um.

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