Semiconductor packaging structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a lead frame and a chip structure arranged on the lead frame, the lead frame comprises pins, a base island and a metal wire, the semiconductor packaging structure comprises an isolation voltage-withstanding layer at least arranged between the base island and the chip structure, and the isolation voltage-withstanding layer is connected with the chip structure and the base island; the pin comprises a first surface and a second surface which are opposite, the base island comprises a third surface and a fourth surface which are opposite, the first surface and the third surface are front surfaces of the lead frame, and the second surface and the fourth surface are back surfaces of the lead frame; the functional surface of the chip structure faces the third surface of the base island, the functional surface comprises a welding pad area, and a metal wire is connected with the welding pad area and the second surface of the pin; the functional surface of the chip structure is closer to the base island, and the coupling coefficient of the semiconductor packaging structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing and packaging, and particularly to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] In the prior art, a semiconductor packaging structure includes a lead frame and a chip. The lead frame includes pins and a base island. The lead frame is divided into a front side and a back side. During the packaging process, a polyimide film and the chip are usually pasted onto the front side of the base island in sequence, with the functional side of the chip facing upward to facilitate the connection of leads to the front side of the pins. Thus, the distance between the functional side of the chip and the base island includes the thickness of the chip itself and the thickness of the polyimide film. This results in a large vertical distance between the functional side of the chip and the base island, affecting the coupling coefficient of the product. Summary of the Invention

[0003] One object of the present invention is to provide a semiconductor packaging structure to at least solve the technical problem of the large vertical distance between the functional side of the chip and the base island in the prior art.

[0004] To achieve the above object of the present invention, an embodiment of the present invention provides a semiconductor packaging structure, including a lead frame and a chip structure disposed on the lead frame. The lead frame includes pins, a base island, and metal wires. The semiconductor packaging structure includes at least an isolation and voltage withstand layer disposed between the base island and the chip structure, and the isolation and voltage withstand layer connects the chip structure and the base island. The pins include opposite first and second surfaces, the base island includes opposite third and fourth surfaces, the first surface and the third surface are the front side of the lead frame, and the second surface and the fourth surface are the back side of the lead frame. The functional side of the chip structure faces the third surface of the base island, the functional side includes a pad area, and the metal wires connect the pad area and the second surface of the pins.

[0005] As a further improvement of an embodiment of the present invention, the pad area is disposed in the outer area of the functional area, and the pad area extends beyond the outer edge of the base island.

[0006] As a further improvement of an embodiment of the present invention, the pad area extends beyond the outer edge of the base island by not less than 400 um.

[0007] As a further improvement of an embodiment of the present invention, the pad area is exposed between the base island and the pins. The pins include a plating layer disposed at the end of the second surface close to the base island side, and the metal wires connect the plating layer and the pad area.

[0008] As a further improvement of an embodiment of the present invention, the pins include an outer pin portion and an inner pin portion bent from the outer pin portion, and the plating layer is disposed on the inner pin portion.

[0009] As a further improvement of an embodiment of the present invention, the first surface of the outer lead portion and the third surface of the base island are located in the same plane, and the chip structure and the inner lead portion are located on the same side of this plane.

[0010] As a further improvement of an embodiment of the present invention, the lead includes a connecting portion and an inner lead portion that are sequentially bent from the outer lead portion, and the outer lead portion, the connecting portion, and the inner lead portion are parallel to each other.

[0011] As a further improvement of an embodiment of the present invention, the semiconductor package structure further includes a molding compound disposed outside the lead frame and the chip structure. The minimum vertical distance between the first surface of the lead and the front surface of the molding compound is not less than 100 μm, and the front surface of the molding compound corresponds to and faces the same side as the front surface of the lead frame.

[0012] As a further improvement of an embodiment of the present invention, the metal wire is arc-shaped after connecting the pad region and the second surface of the lead, and the minimum vertical distance between the metal wire and the back surface of the molding compound is not less than 100 μm.

[0013] To achieve one of the above-mentioned invention purposes, an embodiment of the present invention provides a manufacturing method of a semiconductor package structure, including the following steps:

[0014] Provide a lead frame, the lead frame includes leads, a base island, and metal wires. The leads include opposite first and second surfaces, the base island includes opposite third and fourth surfaces, the first surface and the third surface are the front surfaces of the lead frame, and the second surface and the fourth surface are the back surfaces of the lead frame;

[0015] Provide a chip structure, the chip structure includes a functional surface and a pad region located on the functional surface, and the functional surface of the chip structure faces the third surface of the base island;

[0016] Set an isolation and voltage withstand layer to connect the chip structure and the base island, wherein at least part of the isolation and voltage withstand layer is located between the chip structure and the base island;

[0017] Connect the metal wire to the pad region and the second surface of the lead.

[0018] As a further improvement of an embodiment of the present invention, providing a lead frame includes:

[0019] Provide an initial frame, the initial frame includes initial leads and a base island, and the initial leads include opposite first and second surfaces corresponding to the leads;

[0020] Bend the initial leads to obtain the leads.

[0021] As a further improvement of an embodiment of the present invention, the initial framework is provided to include: plating the end of the second side of the initial pin near the base island to form a coating layer, and connecting the coating layer and the pad area with a metal wire.

[0022] As a further improvement of an embodiment of the present invention, an isolation and voltage withstand layer is provided to connect the chip structure and the base island, including: separately providing a thin film as the isolation and voltage withstand layer to connect the chip structure and the base island, or forming the isolation and voltage withstand layer on the functional surface and the side surface of the chip structure to connect the chip structure and the base island.

[0023] As a further improvement of an embodiment of the present invention, forming the isolation and voltage withstand layer on the functional surface and the side surface of the chip structure to connect the chip structure and the base island includes:

[0024] Turn the third side of the base island and the first side of the pin upward;

[0025] Turn the functional surface of the chip structure downward to fix the isolation and voltage withstand layer on the third side of the base island.

[0026] As a further improvement of an embodiment of the present invention, separately providing a thin film as the isolation and voltage withstand layer to connect the chip structure and the base island includes:

[0027] Turn the third side of the base island and the first side of the pin upward;

[0028] Fix the thin film on the third side of the base island;

[0029] Turn the functional surface of the chip structure downward to fix the functional surface on the thin film.

[0030] As a further improvement of an embodiment of the present invention, before connecting the metal wire to the pad area and the second side of the pin, it includes:

[0031] Flip the lead frame and the chip structure, with the fourth side of the base island and the second side of the pin upward, and the pad area upward.

[0032] Compared with the prior art, the present invention provides a semiconductor package structure, in which the functional surface of the chip is reversely attached to the base island, and the pad area on the functional surface is connected to the back of the lead frame, reducing the vertical distance between the functional surface of the chip and the base island and increasing the coupling coefficient value of the product. Description of the Drawings

[0033] Figure 1a It is a schematic diagram of the semiconductor package structure in an embodiment of the present invention.

[0034] Figure 1bIt is a flowchart of a manufacturing method of a semiconductor package structure in an embodiment of the present invention.

[0035] Figure 2 It is a schematic diagram of a lead frame in an embodiment of the present invention.

[0036] Figure 3 It is a schematic diagram of manufacturing a lead frame in an embodiment of the present invention.

[0037] Figure 4 It is a schematic diagram of setting an isolation voltage withstand layer on a lead frame in an embodiment of the present invention.

[0038] Figure 5 It is a schematic diagram of setting a chip structure on an isolation voltage withstand layer in an embodiment of the present invention.

[0039] Figure 6 It is a schematic diagram of connecting a metal wire to a pad area and a pin in an embodiment of the present invention.

[0040] Figure 7 It is a schematic diagram of the cooperation between a chip structure and a lead frame in another embodiment of the present invention.

[0041] Figure 8 It is a schematic diagram of connecting a metal wire to a pad area and a pin in another embodiment of the present invention.

[0042] Figure 9 It is a schematic diagram of a wafer-level chip in another embodiment of the present invention.

[0043] Figure 10 It is a schematic diagram of the step of forming an isolation voltage withstand layer on a chip structure in another embodiment of the present invention. Detailed Embodiments

[0044] The present invention will be described in detail below in conjunction with the specific embodiments shown in the drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional transformation made by those of ordinary skill in the art based on these embodiments is included in the protection scope of the present invention.

[0045] It should be noted that the term "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. In addition, the terms "first", "second", "third", "fourth", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0046] The term "connected", "connected to" or any other variant is intended to cover various relative positions of connection relationships, so as to include direct connection or indirect connection. Among them, the direct connection can be formed by constructing an air pipeline, and the indirect connection can be a connection relationship constructed by devices such as valve bodies and sensors, can be a connection relationship constructed by air circuit components such as a brake control unit, or can be a connection relationship constructed by any other medium such as air.

[0047] Please refer to Figure 1a , which is a schematic diagram of a semiconductor packaging structure 100 provided by an embodiment of the present application, specifically a Hall sensor chip packaging structure.

[0048] The semiconductor packaging structure 100 includes a lead frame 10 and a chip structure 30 disposed on the lead frame 10, and the chip structure 30 is a Hall sensor chip.

[0049] The lead frame 10 includes pins 11, a base island 13 and metal wires 15. The chip structure 30 is disposed on the base island 30 and is bonded to the pins 11 through the metal wires 15 to achieve electrical connection. Obviously, the semiconductor packaging structure 100 is fabricated by a wire bonding process in the present application.

[0050] The semiconductor packaging structure 100 includes at least an isolation and voltage withstand layer 50 disposed between the base island 13 and the chip structure 30. The isolation and voltage withstand layer 50 connects the chip structure 30 and the base island 13. In practical applications, insulation isolation needs to be performed between the base island 13 and the chip structure 30, and the base island 13 is the high-voltage side and the pins 11 are the low-voltage side, and there is a large voltage difference between the base island 13 and the chip structure 30. For example, when the semiconductor packaging structure 100 is applied to the photovoltaic field, a voltage of up to two thousand volts will be applied continuously. Therefore, the intermediate isolation and voltage withstand layer 50 needs to be composed of a material with good voltage withstand performance to avoid breakdown between the base island 13 and the chip structure 30. In the prior art, the materials used for the isolation and voltage withstand layer 50 can be selected as polyimide film, substrate, glass silicon wafer, etc. In another embodiment described below, the isolation and voltage withstand layer 50 can also be formed on the chip structure 30, which will be described in detail below.

[0051] Specifically, the present application is a magnetic current sensor. In the present application, the lead frame 10 is made of a low-magnetic or non-magnetic copper foil material. For example, copper grades such as C192 / C151 / KFC / EFTEC64T can be optionally used. The initial frame can be fabricated by an etching process of exposure and development, or can also be formed by stamping with a mold. The metal wires 15 are used to electrically connect the chip structure 30 and the pins 11, and gold wires or copper wires can be optionally used to ensure good electrical conductivity.

[0052] Specifically, in combination with Figure 2As shown, a number of pins 11 are arranged horizontally. Each individual pin 11 is in the shape of a long strip. In practical applications, the conventional dimensions of the formed pins 11 are 78mm * 258mm, 86mm * 290mm, and generally do not exceed 100mm * 300mm.

[0053] The pin 11 includes an opposite first surface and a second surface. The base island 13 includes an opposite third surface and a fourth surface. The first surface and the third surface are the front surfaces of the lead frame 10, and the second surface and the fourth surface are the back surfaces of the lead frame 10. In other words, the first surface and the third surface are on the same side of the lead frame 10, and the second surface and the fourth surface are on the opposite side of the lead frame 10.

[0054] The functional surface of the chip structure 30 faces the third surface of the base island 13. The functional surface includes a pad area 31. The metal wire 15 connects the pad area 31 and the second surface of the pin 11. Equivalently, the metal wire 15 is located on the back side of the lead frame 10.

[0055] In the prior art, on the front side of the lead frame 10, an isolation withstand voltage film and a chip structure are usually arranged in sequence on the third surface of the base island. For subsequent wire bonding, the chip structure is usually also directly attached to the isolation withstand voltage film, which means that the functional surface of the chip structure faces upward and thus deviates from the third surface of the base island. The functional surface of the chip structure faces upward and thus performs wire bonding with the first surface of the pin. In this way, the vertical distance between the Hall point on the functional surface of the chip structure and the base island is too large, affecting the coupling coefficient value.

[0056] In this application, the chip structure 30 is reversely attached to the base island, and the functional surface of the chip structure 30 faces the third surface of the base island. At this time, the functional surface of the chip structure 30 and the second surface of the pin 11 are on the same side and are correspondingly located on the back side of the lead frame 10. Therefore, the metal wire 15 electrically connects the pad area 31 and the second surface of the pin 11.

[0057] In this way, the functional surface of the chip structure 30 is closer to the base island 13, and the coupling coefficient value between the chip structure 30 and the base island 13 is high. Specifically, the coupling coefficient value can be increased from 1.5 - 2.0 G / A to more than 3.5 G / A, and the creepage distance is increased from 1 mm to at least 8 mm, breaking through the bottleneck of insufficient withstand voltage and greatly improving the product performance.

[0058] The pad area 31 is arranged in the outer area of the functional surface, and the pad area 31 extends beyond the outer edge of the base island 13. It can be understood that when the pad area 31 is arranged on the functional surface and the functional surface faces the base island 13, in order to ensure the function of the pad area 31, the pad area 31 cannot be covered by the base island 13. Therefore, the pad area 31 is arranged to extend beyond the outer edge of the base island 13 and is exposed at the outer edge of the base island 13 to facilitate subsequent bonding connection of the metal wire 15.

[0059] In one embodiment, the solder pad region 31 extends beyond the outer edge of the base island by no less than 400 μm to ensure good insulation performance between the chip structure 30 and the base island 13.

[0060] In one embodiment, the solder pad region 31 is exposed between the base island 13 and the lead 11. The lead 11 includes a plating layer 110 provided at the end of the second side close to the base island. The metal wire 15 connects the plating layer 110 and the solder pad region 31. To ensure a better electrical connection effect between the chip structure 30 and the lead 11, the end of the second side of the lead 11 is electroplated with the plating layer 110. Generally, the plating layer 110 does not contain magnetic materials such as nickel, and a silver plating layer or a gold plating layer can be optionally adopted.

[0061] In one embodiment, the lead 11 includes an outer lead portion 111 and an inner lead portion 113 bent from the outer lead portion 111, and the plating layer 110 is provided on the inner lead portion 113. The lead 11 is formed by bending the initial lead 11a of the initial frame. The inner lead portion 113 is located on the side close to the base island 13, and the outer lead portion 111 is located on the side away from the base island 13.

[0062] The first surface of the outer lead portion 111 and the third surface of the base island 13 are in the same plane, and the chip structure 30 and the inner lead portion 113 are on the same side of this plane. It can be understood that the lead 11 and the base island 13 are originally formed by etching or stamping copper foil, and the formed initial frame 10a has a certain thickness. However, in the case of no bending, the front surfaces of the initial frame 10a are in the same plane, and the back surfaces of the initial frame 10a are also in the same plane. After the initial lead 11a of the initial frame 10a is bent, a more three-dimensional structure of the lead frame 10 is formed.

[0063] Specifically, the lead 11 is bent to form a recessed inner lead portion 113. The inner lead portion 113 is bent in the direction towards the front side of the lead frame 10. The base island 13 is not bent. The third surface of the base island 13 and the first surface of the outer lead portion 111 are still in the same plane, while the inner lead portion 111 deviates from this plane after bending and deviates to the same side as the chip structure 30 in this plane.

[0064] It can be seen that both the inner lead portion 113 and the chip structure 30 are biased towards the front side of the lead frame 10. The back side of the lead frame 10 reserves more wire bonding space for the subsequent metal wire 15. The highest point C of the arc-shaped metal wire 15 will not protrude too far on the back side of the lead frame 10, which is beneficial to the miniaturization of the packaging structure.

[0065] In one embodiment, the pin 11 includes a connecting portion 112 and an inner pin portion 113 that are sequentially bent from the outer pin portion 111, and the outer pin portion 111, the connecting portion 112, and the inner pin portion 113 are parallel to each other. In order to reserve a relatively sufficient wire bonding space, the pin 11 can also be subjected to a two-stage bending process. First, the connecting portion 112 is bent, and then the inner pin portion 113 is bent. The inner pin portion 113, the connecting portion 112, and the outer pin portion 111 formed by bending are parallel to each other.

[0066] The semiconductor package structure 100 further includes a molding compound 60 disposed outside the lead frame 10 and the chip structure 30. Combining Figures 4 - 6 , the outer dotted line indicates the outer border of the finished molding compound 60. In actual applications, after the lead frame 10 and the chip structure 30 are wire-bonded, a molding process is required to ensure the stability of the connection between the lead frame 10 and the chip structure 30, and to protect the lead frame 10 and the chip structure 30 therein.

[0067] The minimum vertical distance A between the first surface of the pin 11 and the front surface of the molding compound 60 is not less than 100 μm, and the front surface of the molding compound 60 and the front surface of the lead frame 10 face the same side; more specifically, the vertical distance A between the first surface of the inner pin portion 113 and the front surface of the molding compound 60 is not less than 100 μm. In this way, the concave area of the pin 11 and the wire bonding area of the metal wire 15 are controlled, and the space is reasonably utilized, which is beneficial to the compactness and miniaturization of the semiconductor package structure 100.

[0068] Since the metal wire 15 is on the back side of the lead frame 10 in this application, the vertical distance B between the second surface of the inner pin portion 113 and the back surface of the molding compound 60 needs to further consider the height of the arc-shaped metal wire 15. Combining Figure 8 As shown, the front surface of the molding compound 60 and the front surface of the lead frame 10 face the same side. It can be understood that the semiconductor package structure 100 is a three-dimensional structure, and the front surface of the molding compound 60 and the front surface of the lead frame 10 are not necessarily in the same plane, but can be reasonably considered to face the same side. Specifically, it can be considered to face the front side of the semiconductor package structure 100.

[0069] The metal wire 15 is arc-shaped after connecting the pad area 31 and the second surface of the pin 11, and the minimum vertical distance between the metal wire 15 and the back surface of the molding compound 60 is not less than 100 μm. Specifically combining Figure 6As shown, the metal wire 15 protrudes with the highest point C in the thickness direction of the lead frame 10, and the vertical distance between the highest point C and the back surface of the plastic package 60 is not less than 100 um. Above, for the area control of wire bonding, the height control of the highest point of the metal wire 15 in the thickness direction between its two ends is not less than 90 um, and the distance between the highest point C and the back surface of the plastic package 60 is not less than 100 um.

[0070] The semiconductor package structure 100 of the present application also belongs to the quad flat no-lead (QFN) package. Compared with the traditional standard operating procedure (SOP) magnetic current package, the novel semiconductor package structure of the present application greatly improves the impedance and thermal effect. Under the structure of the same thickness, the impedance of this structure is reduced from 600 uohm to 53 uohm compared with the SOP. And because the base island 13 can be directly soldered on the PCB board, its heat dissipation performance is several times that of the SOP magnetic current package. It greatly expands the application range of the product and solves the pain points of large current magnetic sensors on the market. Using the QFN package category, the equipment and fixtures for packaging have strong reusability. If you need to develop an SOP product, the upfront investment cost is high, while the QFN investment cost is low, and the verification cycle is also greatly shortened.

[0071] Please refer to Figure 1b , the present application relates to a manufacturing method of a semiconductor package structure 100, including the following steps:

[0072] S1: Provide a lead frame 10, the lead frame 10 includes pins 11, a base island 13 and a metal wire 15, the pins 11 include opposite first and second surfaces, the base island 13 includes opposite third and fourth surfaces, the first surface and the third surface are the front surface of the lead frame 10, and the second surface and the fourth surface are the back surface of the lead frame 10. Combining Figure 3 As shown, the lead frame 10 is formed by etching or stamping a copper foil material, and several of the pins 11 are strip-shaped. The pins 11 and the base island 13 of the initial frame are both connected to the outer frame to form an overall arrangement and distribution.

[0073] Among them, the step of providing the lead frame 10 includes:

[0074] Provide an initial frame 10a, the initial frame 10a includes initial pins 11a and a base island 13, and the initial pins include opposite first and second surfaces corresponding to the pins; Combining Figure 3 As shown in c, although the initial frame 10a is also a three-dimensional structure, the front surfaces of the initial pins 11a and the base island 13 are in the same plane, and the back surfaces of the initial pins 11a and the base island 13 are also in the same plane.

[0075] Bend the initial pins 11a to obtain the pins 11, and the degree of bending needs to be controlled during bending. CombiningFigure 3 As shown in Fig. d, the initial pin 11a is bent twice to form the pin 11. The pin 11 includes an outer pin portion 111, a connecting portion 112, and an inner pin portion 113. The outer pin portion 111 is disposed away from the base island, the inner pin portion 113 is disposed close to the base island, and the connecting portion 112 connects the inner pin portion 113 and the outer pin portion 111.

[0076] Among them, providing the initial frame 10a includes: electroplating a coating 110 on the end of the second side of the initial pin 11a close to the base island, and the metal wire 15 connects the coating 110 and the pad region 31.

[0077] Specifically, as Figure 3 shown in Fig. a-3b, a copper foil material is provided. The copper foil material is formed into the initial pin 11a through etching or stamping. Electroplating is performed on the end of the second side of the initial pin 11a and close to the base island 13 to obtain the coating 110. The coating 110 is a non-magnetic material such as nickel-free. Usually, a silver coating can meet the subsequent packaging and welding requirements. In other embodiments, a gold coating with better conductivity can also be selected.

[0078] It can be understood that electroplating the initial pin 11a is simpler in operation than electroplating the bent pin 11. After electroplating, the initial pin 11a is dimpled, that is, bent, to obtain the final pin 11 structure, so as to reserve the wire bonding space on the back side of the lead frame 10.

[0079] S2: Provide the chip structure 30. The chip structure 30 includes a functional surface and a pad region 31 located on the functional surface. The functional surface of the chip structure 30 faces the third surface of the base island 13. The chip structure 30 can be a single chip structure directly provided by a wafer manufacturer, or a single chip structure obtained by cutting a wafer-level chip after reprocessing as needed. The functional surface of each chip structure 30 includes a functional area and a pad region 31. It can be understood that the functional area includes Hall sensing points.

[0080] It can be understood that there is no necessary sequence relationship between providing the lead frame 10 and providing the chip structure 30.

[0081] S3: Set the isolation and voltage withstand layer 50 to connect the chip structure 30 and the base island 13, and at least part of the isolation and voltage withstand layer 50 is located between the chip structure 30 and the base island 13.

[0082] The electroplating and bending processes of the above-mentioned lead frame 10 are both carried out on the back side of the lead frame 10. Next, the lead frame 10 is flipped to provide an isolation and voltage withstand layer 50 on the front side of the lead frame 10, which is equivalent to providing an isolation and voltage withstand layer 50 on the third side of the base island 13. It can be seen that the plating layer 110 is located on the second side of the pin 11, that is, the back side of the lead frame 10, while the isolation and voltage withstand layer 50 is located on the third side of the base island, that is, the front side of the lead frame 10.

[0083] Among them, the step of providing the isolation and voltage withstand layer 50 to connect the chip structure 30 and the base island 13 includes: separately providing a thin film as the isolation and voltage withstand layer 50 to connect the chip structure 30 and the base island 13, or forming an isolation and voltage withstand layer 50 on the functional surface and side surface of the chip structure 30 to connect the chip structure 30 and the base island 13.

[0084] When the isolation and voltage withstand layer 50 is a separate thin film, the material of the thin film can be selected from polyimide film, or substrates, glass, sapphire and other other insulating and voltage withstand materials. The specific thin film is selected by different manufacturers. More specifically, when the fixation of the thin film to the base island 13 is completed by the frame manufacturer, the material of the thin film selected by the frame manufacturer is usually a high molecular voltage withstand film such as polyimide; when the fixation of the thin film to the base island 13 is completed by the packaging manufacturer, in addition to the polyimide film, the packaging manufacturer can also select substrates, glass, sapphire, etc.

[0085] When the isolation and voltage withstand layer 50 is a separate thin film, in order to consider the insulation and voltage withstand requirements between the chip structure 30 and the base island 13, the isolation and voltage withstand layer 50 should be larger than the size of the functional area of the chip structure 30, and only the pad area 31 should exceed the isolation and voltage withstand layer 50. The distance between the outer edge of the isolation and voltage withstand layer 50 and the outer edge of the base island 13 needs to be not less than 400um, and the pad area 31 should also be at a certain distance from the outer edge of the isolation and voltage withstand layer 50.

[0086] When the isolation and voltage withstand layer 50 is a separate thin film, the isolation and voltage withstand layer 50 is pasted on the third side of the base island 13. The specific pasting glue can be selected according to the material of the isolation and voltage withstand layer 50. For example, when using a polyimide film, a non-conductive glue that combines well with polyimide needs to be used, while for an isolation and voltage withstand layer 50 made of materials such as glass and substrate, a semiconductor-related binder needs to be used.

[0087] When the isolation and voltage withstand layer 50 is a separate thin film, the step of separately providing a thin film as the isolation and voltage withstand layer 50 to connect the chip structure 30 and the base island 13 includes:

[0088] Turn the third side of the base island 13 and the first side of the pin 11 upward; the third side of the base island 13 and the first side of the pin 11 are the front side of the lead frame 10; that is, turn the front side of the lead frame 10 upward.

[0089] Fix the thin film to the third surface of the base island 13; Combine Figure 4 As shown, paste the polyimide thin film or glass or substrate to the base island 13.

[0090] Turn the functional surface of the chip structure 30 downward to fix the functional surface to the thin film.

[0091] Combine Figure 5 As shown, bond the chip structure 30 at the third surface of the base island 13 and the designated position of the isolation and voltage withstand layer 50 (the functional area of the chip structure matches the design of the base island 13). For the weldability of the adhesive, it is selected according to the materials of the isolation and voltage withstand layer 50 and the chip structure 30 used. For example, if a polyimide voltage withstand thin film is used, a non-conductive glue with good bonding to polyimide is required, while if materials such as glass are used, a semiconductor-related adhesive is required.

[0092] In addition, the thickness uniformity of the non-conductive glue bonding layer is also considered. As much as possible, the flatness is within ±3um to reduce the subsequent processing risks. The overflow of the glue is also controlled and processed to avoid affecting the next welding.

[0093] Above, the functional surface of the chip structure 30 is inversely pasted on the isolation and voltage withstand layer 50, so that the Hall points on the functional surface can be close enough to the base island 13, which has a great promoting effect on the coupling coefficient value of the packaging structure.

[0094] When forming the isolation and voltage withstand layer 50 on the functional surface and the side surface of the chip structure 30, cancel the thin film setting. In the prior art, when using a thin film or a substrate or glass as the isolation and voltage withstand layer 50, the thinnest isolation and voltage withstand layer 50 is also 75um, and the distance between the chip structure 30 and the base island 13 is large, and the coupling coefficient is low.

[0095] When forming the isolation and voltage withstand layer 50 on the functional surface and the side surface of the chip structure 30, the isolation and voltage withstand layer 50 is a silicon dioxide layer. As long as the thickness of the silicon dioxide layer is greater than 20um, the voltage withstand can be increased from 100Vrms to more than 5000Vrms.

[0096] When forming the isolation and voltage withstand layer 50 on the functional surface and the side surface of the chip structure 30, forming the isolation and voltage withstand layer 50 on the functional surface and the side surface of the chip structure 30 to connect the chip structure 30 and the base island 13 includes the steps of:

[0097] Turn the third surface of the base island 13 and the first surface of the lead 11 upward; The third surface of the base island 13 and the first surface of the lead 11 are the front surface of the lead frame 10; That is, turn the front surface of the lead frame 10 upward.

[0098] Place the functional surface of the chip structure 30 downward to fix the isolation withstand voltage layer 50 on the third surface of the base island 13. Combine Figure 7 As shown, at this time, the isolation withstand voltage layer 50 is formed on the functional surface of the chip structure 30. It is only necessary to directly place the functional surface of the chip structure 30 downward and paste it onto the base island 13.

[0099] S4: Connect the bonding pad area 31 and the second surface of the lead 11 with a metal wire 15. The third surface of the base island 13 and the second surface of the lead 11 are located on the opposite sides of the lead frame 10. Combine Figure 6 、 Figure 8 As shown, the functional surface of the chip structure 30 faces the base island 13, so the distance from the base island 13 is closer. The metal wire 15 connects the bonding pad area 11 and the plating layer 110 on the back of the lead frame 10. When welding the metal wire 15, the height of the arc-shaped metal wire 15 needs to be controlled.

[0100] Among them, before connecting the bonding pad area 31 and the second surface of the lead 11 with the metal wire 15, the steps include:

[0101] Flip the lead frame 10 and the chip structure 30, the fourth surface of the base island 13 and the second surface of the lead 11 face upward, and the bonding pad area 31 faces upward; the fourth surface of the base island 13 and the second surface of the lead 11 are the back of the lead frame 10. That is, turn the back of the lead frame 10 upward and perform the wire bonding operation.

[0102] It can be understood that before wire bonding, the isolation withstand voltage layer 50 and the chip structure 30 are set, and it is necessary to operate on the front of the lead frame 10. Therefore, when wire bonding, it is necessary to flip the lead frame 10 to the back for operation.

[0103] When flipping, the lead frame 10 can be flipped through a carrier / fixture so that the bonding pad area 31 and the plating layer 110 face upward. When welding the metal wire 15, since the chip structure 30 is flipped to the lower position, in order to avoid damaging the chip structure 30 by the force during wire bonding welding, the chip structure 30 can be carried by a special hot plate to avoid the chip structure 30 being suspended and damaged.

[0104] After the wire bonding between the chip structure 30 and the lead 11 is completed, a further encapsulation process can be performed. It can be understood that in the finished product of the finally formed semiconductor package structure, there is a certain positional relationship between the inner lead part 111, the metal wire 15, and the encapsulation body 60 to ensure reasonable space utilization.

[0105] This application also relates to a method for forming an isolation withstand voltage layer 50 on a chip structure 30. Combine Figures 9 - 10 As shown, the steps include:

[0106] S10: Provide a wafer-level chip 200, where the functional surface of the wafer-level chip 200 has an isolation and voltage withstand layer 50; as shown in combination Figure 9 It is equivalent to first fabricating an isolation and voltage withstand layer 50 on the functional surface of the array chip 200a.

[0107] Among them, providing the wafer-level chip 200 includes the steps of:

[0108] Deposit a silicon dioxide material on the functional surface of the wafer-level chip 200. The wafer-level chip 200 includes a pad area disposed on the functional surface. It can be understood that each single chip 200a should have a pad area 31. The material of the isolation and voltage withstand layer 50 is silicon dioxide, and the voltage withstand can resist a surge of more than 10 KV.

[0109] Etch the silicon dioxide material on the surface of the pad area 31 to expose the pad area 31. The functional surface needs to expose the pad area 31 for subsequent welding.

[0110] Above, the initial wafer manufacturer or packaging manufacturer can grow a silicon dioxide layer with a thickness of not less than 20 um on the functional surface of the chip through a silicon dioxide deposition process. This layer can achieve insulation and voltage withstand protection between the subsequent chip structure 30 and the base island 13, and the voltage withstand value can be increased to more than 5000 Vrms.

[0111] S20: Cut the wafer-level chip 200 to obtain a number of single chips 200a; as shown in combination Figure 10 It is shown that each of the chips 200a includes a back surface opposite to the functional surface and a side surface connecting the functional surface and the back surface. It can be understood that the functional surface of each obtained chip 200a has an isolation and voltage withstand layer 50.

[0112] S30: Fix a number of the chips 200a on the mounting surface of the same carrier board 300, where the functional surface of the chip 200a faces the mounting surface of the carrier board 300. Specifically, it includes: pasting the functional surface of the chip 200a on the mounting surface of the carrier board 300, and the mounting surface of the carrier board 300 has an adhesive film.

[0113] In combination with Figure 10 It is shown that a carrier board 300 is provided. The material of the carrier board 300 can be selected from a steel plate, silicon or a glass substrate. One side surface of the carrier board 300 has an adhesive film, thus forming a mounting surface for fixing and installing the chip 200a.

[0114] S40: Form an isolation and voltage withstand layer 50 at least on the side surface of the chip 200a. The functional surface of the above chip 200a has an isolation and voltage withstand layer 50. During cutting, the side surface of the chip 200a has exposed silicon material. In order to achieve more comprehensive protection of the chip 200a, an isolation and voltage withstand layer 50 needs to be formed on the peripheral side surfaces of the chip 200a.

[0115] Among them, forming the isolation and voltage withstand layer 50 on at least the side surface of the chip 200a includes: depositing a silicon dioxide material on the mounting surface of the carrier board 300 and the area between adjacent chips 200a to form the isolation and voltage withstand layer 50; the isolation and voltage withstand layer 50 connects two adjacent chips 200a.

[0116] Continuing to combine Figure 3 , the deposited silicon dioxide covers the area between adjacent chips 200a to wrap the side surface of the chip 200a, forming the isolation and voltage withstand layer 50 on the side surface. The distance between the isolation and voltage withstand layers 50 between adjacent chips 200a needs to be not less than 80um. In this way, after cutting, the thickness of the isolation and voltage withstand layer 50 on the side surface of each chip structure 30 can be ensured to be not less than 20um, ensuring a good voltage withstand value.

[0117] Among them, the manufacturing method of the semiconductor packaging structure 100 includes the steps of: manufacturing the isolation and voltage withstand layer 50 on the side surface and the back surface of the chip 200a. Specifically, it includes: depositing a silicon dioxide material on the mounting surface of the carrier board 300, the area between adjacent chips 200a, and the back surface of the chip 200a to form the isolation and voltage withstand layer 50. The thickness of the isolation and voltage withstand layer 50 formed on the back surface of 200a is not less than 20um.

[0118] Combined with Figure 10 as shown, the deposited silicon dioxide completely wraps the side surface and the back surface of the chip 200a. Coupled with the isolation and voltage withstand layer 50 previously provided on the functional surface, equivalently, each surface of the chip 200a is wrapped by a silicon dioxide layer, realizing a good isolation and voltage withstand function.

[0119] In this application, the isolation and voltage withstand layer 50 is preferably made of a silicon dioxide material. In other embodiments, materials with high voltage withstand life such as aluminum oxide or benzocyclobutene (BCB) can also be selected. The high voltage life of such materials is dozens or hundreds of times that of conventional polyimide films and substrates. Generally, silicon dioxide and aluminum oxide can be fabricated by deposition, while special polymer films such as benzocyclobutene (BCB) can be fabricated by coating processes.

[0120] S50: Separate the carrier board 300 and the chip 200a, and cut the area between adjacent chips 200a to obtain single-chip structures 30. Specifically, it includes the steps of: heating the carrier board 300 to separate the adhesive film from the chip 200a. A plurality of chips 200a connected by the isolation and voltage withstand layer 50 are formed into chip structures 30 after re-cutting. The chip structures 30 include the isolation and voltage withstand layer 50 located on the functional surface, the side surface, and the back surface.

[0121] The functional surface of the formed chip structure 30 can directly face the third surface of the base island 13, and the isolation and voltage withstand layer 50 is pasted on the third surface of the base island 13, without the need to separately set an isolation and voltage withstand film. Moreover, it is thinner than the isolation and voltage withstand film, has a better voltage withstand effect, and is not easily broken down. The thinner thickness further reduces the vertical distance between the functional surface of the chip structure 30 and the base island 13, and improves the coupling coefficient value.

[0122] The beneficial effects of the present invention are as follows: the functional surface of the chip structure 30 is reversely attached to the third surface of the base island 13, the vertical distance between the functional surface and the base island 13 is reduced, the coupling coefficient value is increased, and the performance is improved; after the chip structure 30 is reversely attached to the base island 13, when the lead metal wire 15 connects the pad area 31 and the plating layer 110, only the carrier / fixture needs to be flipped to perform the process of wire bonding on the back of the lead frame 10, and the packaging process is simple; after the pin 11 is bent, a wire bonding space is reserved for the metal wire 15; the chip structure 30 forms an isolation and voltage withstand layer 50, which improves the voltage withstand value of the product, and reducing the vertical distance between the functional surface and the base island 13 also improves the coupling coefficient value.

[0123] It can be formed corresponding to any of the technical solutions provided above, and will not be elaborated here.

[0124] It should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0125] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present invention, and they are not used to limit the protection scope of the present invention. Any equivalent embodiments or changes made without departing from the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor package structure, characterized in that, It includes a lead frame and a chip structure disposed on the lead frame. The lead frame includes pins, a base island, and metal wires. The semiconductor package structure includes an isolation and voltage withstand layer disposed at least between the base island and the chip structure. The isolation and voltage withstand layer connects the chip structure and the base island. The pins include opposite first and second faces. The base island includes opposite third and fourth faces. The first face and the third face are the front faces of the lead frame, and the second face and the fourth face are the back faces of the lead frame. The functional face of the chip structure faces the third face of the base island. The functional face includes a pad area, and the metal wire connects the pad area and the second face of the pin.

2. The semiconductor package structure according to claim 1, wherein The pad area is disposed in the outer area of the functional area, and the pad area extends beyond the outer edge of the base island.

3. The semiconductor package structure according to claim 2, wherein The pad area extends beyond the outer edge of the base island by not less than 400um.

4. The semiconductor package structure according to claim 1, wherein The pad area is exposed between the base island and the pins. The pins include a plating layer disposed at the end of the second face close to the base island side. The metal wire connects the plating layer and the pad area.

5. The semiconductor package structure according to claim 4, wherein The pins include an outer pin portion and an inner pin portion formed by bending from the outer pin portion. The plating layer is disposed on the inner pin portion.

6. The semiconductor package structure according to claim 5, wherein, The first face of the outer pin portion and the third face of the base island are in the same plane, and the chip structure and the inner pin portion are on the same side of this plane.

7. The semiconductor package structure according to claim 5, wherein, The pins include a connecting portion and an inner pin portion formed by bending in sequence from the outer pin portion. The outer pin portion, the connecting portion, and the inner pin portion are parallel to each other.

8. The semiconductor package structure according to claim 1, wherein The semiconductor package structure further includes a plastic package disposed outside the lead frame and the chip structure. The minimum vertical distance between the first face of the pin and the front face of the plastic package is not less than 100um. The front face of the plastic package corresponds to and faces the same side as the front face of the lead frame.

9. The semiconductor package structure according to claim 8, wherein After the metal wire connects the pad area and the second face of the pin, it is in an arc shape. The minimum vertical distance between the metal wire and the back face of the plastic package is not less than 100um.

10. A manufacturing method of a semiconductor package structure, characterized in that, It includes the following steps: Provide a lead frame. The lead frame includes pins, a base island, and metal wires. The pins include opposite first and second faces. The base island includes opposite third and fourth faces. The first face and the third face are the front faces of the lead frame, and the second face and the fourth face are the back faces of the lead frame. Provide a chip structure. The chip structure includes a functional face and a pad area located on the functional face. The functional face of the chip structure faces the third face of the base island. Set an isolation and voltage withstand layer to connect the chip structure and the base island, wherein at least part of the isolation and voltage withstand layer is located between the chip structure and the base island. Lead a metal wire to connect the pad area and the second face of the pin.

11. The manufacturing method of the semiconductor package structure according to claim 10, wherein Providing a lead frame includes: Provide an initial frame. The initial frame includes initial pins and a base island. The initial pins include opposite first and second faces corresponding to the pins. Bend the initial pins to obtain the pins.

12. The manufacturing method of the semiconductor package structure according to claim 11, wherein, Providing an initial frame includes: electroplating the end of the second face of the initial pins close to the base island side to form a plating layer, and the metal wire connects the plating layer and the pad area.

13. The manufacturing method of the semiconductor packaging structure according to claim 10, wherein Providing an isolation withstand voltage layer to connect the chip structure and the base island includes: separately providing a thin film as the isolation withstand voltage layer to connect the chip structure and the base island, or forming an isolation withstand voltage layer on the functional surface and the side surface of the chip structure to connect the chip structure and the base island.

14. The manufacturing method of the semiconductor packaging structure according to claim 13, wherein, Forming an isolation withstand voltage layer on the functional surface and the side surface of the chip structure to connect the chip structure and the base island includes: Turning the third surface of the base island and the first surface of the lead upward; Turning the functional surface of the chip structure downward to fix the isolation withstand voltage layer on the third surface of the base island.

15. The manufacturing method of the semiconductor package structure according to claim 13, characterized in that, Separately providing a thin film as the isolation withstand voltage layer to connect the chip structure and the base island includes: Turning the third surface of the base island and the first surface of the lead upward; Fixing the thin film on the third surface of the base island; Turning the functional surface of the chip structure downward to fix the functional surface on the thin film.

16. The manufacturing method of the semiconductor package structure according to claim 10, characterized in that, Before connecting the bonding pad area and the second surface of the lead by a metal wire includes: Flipping the lead frame and the chip structure so that the fourth surface of the base island and the second surface of the lead face upward, and the bonding pad area faces upward.

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