Scanning image data to pixel array at intermediate scan rate during transitions between different refresh rates

Abstract

In general, the subject matter described in this disclosure may be embodied in techniques for operating a display device that includes an array of pixels. When the display device is operating at a first refresh rate, a first frame is programmed to the array, including scanning the first frame line by line to the array of pixels at a first scan rate. An indication is received that the display device is to transition from a first refresh rate to a second refresh rate. The intermediate frame is then programmed to the pixel array, including scanning the intermediate frame line by line to the pixel array at an intermediate scan rate. When the display device is operating at a second refresh rate, a second frame is then programmed to the pixel array, including by scanning the second frame line by line to the pixel array at a second scan rate.

Description

Technical Field

[0001] This document generally relates to the operation of display devices. Background Art

[0002] Some electronic devices with display devices can operate the display device at a variety of different refresh rates, such that the electronic device can update frames of visual content at different refresh rates. For example, a display device can update image content at a relatively low refresh rate (e.g., 60 Hz) when presenting a user interface of a word processing application, while the same display device can update image content at a relatively high refresh rate (e.g., 120 Hz) when presenting a user interface of a game that provides an immersive visual experience. Summary of the Invention

[0003] This document describes techniques, methods, systems, and other mechanisms for scanning image data into a pixel array at an intermediate scan rate during a transition between different refresh rates.

[0004] A display device of a computing device can be configured to present frames of image content at a first refresh rate and at a second refresh rate. When presenting a frame of image content at the first refresh rate, the display device can program the frame of image content into the pixel array at a first scan rate. When presenting a frame of image content at the second refresh rate, the display device can program the frame of image content into the pixel array at a second scan rate different from the first scan rate.

[0005] When the computing device determines to switch from the first refresh rate to the second refresh rate, the computing device can present one or more frames of image content during an intermediate transition period. The display device can program such one or more frames of image content into the pixel array by scanning the one or more frames of image content to be presented during the intermediate transition period into the pixel array at an intermediate scan rate that is between the first scan rate and the second scan rate.

[0006] In certain cases, a particular implementation can achieve one or more of the following advantages. Scanning frames of image content into the pixel array at different refresh rates can provide energy savings, which can extend the battery life of a mobile computing device. An oscillator that generates a clock signal can operate at a particular scan rate for a particular refresh rate, where the clock signal defines the scan rate at which image content is scanned line by line into the pixel array. When the computing device switches to a lower refresh rate, the oscillator can output the clock signal at a lower frequency, such that the scan rate at which image content is scanned into the pixel array is also lower. Operating the clock signal at an intermediate frequency during a transition between refresh rates can avoid visual artifacts (e.g., user-perceivable flicker) that might otherwise occur during a transition between refresh rates.

[0007] As a supplementary description of the embodiments described below, the present disclosure describes the following embodiments.

[0008] Embodiment 1 is a method of operating a display device including a pixel array, the method comprising: when the display device is operating at a first refresh rate, programming a first image content frame into the pixel array, including scanning the first image content frame line by line into the pixel array at a first scan rate, wherein the image content presented by the pixel array is refreshed at the first refresh rate; activating the pixel array to present the first image content frame scanned into the pixel array at the first scan rate; receiving an indication that the display device is to transition from the first refresh rate to a second refresh rate, wherein the image content presented by the pixel array is refreshed at the second refresh rate; in response to receiving the indication that the display device is to transition from the first refresh rate to the second refresh rate, programming an intermediate image content frame into the pixel array, including scanning the intermediate image content frame line by line into the pixel array at an intermediate scan rate, the intermediate scan rate being between the first scan rate and the second scan rate; activating the pixel array to present the intermediate image content frame scanned into the pixel array at the intermediate scan rate; after the display device has presented the intermediate image content frame and when the display device is operating at the second refresh rate, programming a second image content frame into the pixel array, including scanning the second image content frame line by line into the pixel array at the second scan rate; and activating the pixel array to present the second image content frame scanned into the pixel array at the second scan rate.

[0009] Embodiment 2 is the method according to Embodiment 1, wherein: the first frame, the intermediate frame, and the second frame are frames in a frame sequence presented by the display device.

[0010] Embodiment 3 is the method according to any one of Embodiments 1 to 2, wherein: scanning the first image content frame line by line into the pixel array at the first scan rate includes: (i) scanning the first line of the first image content frame into the first line of the pixel array at a first time; and (ii) scanning the second line of the first image content frame into the second line of the pixel array at a second time; and the difference between the first time and the second time is defined by the first scan rate.

[0011] Embodiment 4 is the method according to any one of Embodiments 1 to 3, wherein: the first refresh rate is lower than the second refresh rate; the first scan rate is lower than the intermediate scan rate; and the second scan rate is higher than the intermediate scan rate.

[0012] Embodiment 5 is the method according to Embodiment 4, wherein: the first refresh rate is a frequency between 60 Hz and 100 Hz; and the second refresh rate is twice the first refresh rate.

[0013] Example 6 is the method according to any one of Examples 4 to 5, wherein: the display device presents the first image content frame having a first number of differential activations; and the display device presents the second image content frame having a second number of differential activations, the second number of differential activations being less than the first number of differential activations.

[0014] Example 7 is the method according to Example 6, wherein: the display device presents the intermediate image content frame having an intermediate number of refresh periods, the intermediate number of refresh periods being less than the first number of differential activations and more than the second number of differential activations.

[0015] Example 8 is the method according to Example 7, wherein: the first number of differential activations is four activations; the intermediate number of differential activations is three activations; and the second number of differential activations is two activations.

[0016] Example 9 is the method according to any one of Examples 1 to 8, wherein: the display device presents the first line of the intermediate image content frame by activating the first line of the pixel array for a first amount of time; and the display device presents the second line of the intermediate image content frame by activating the second line of the pixel array for a second amount of time, the second amount of time being different from the first amount of time.

[0017] Example 10 is the method according to any one of Examples 1 to 9, comprising: receiving an indication that the display device is to switch back from the second refresh rate to the first refresh rate; in response to receiving the indication that the display device is to switch back from the second refresh rate to the first refresh rate, programming additional intermediate image content frames into the pixel array, including scanning the additional intermediate image content frames line by line into the pixel array at the intermediate scan rate; activating the pixel array to present the additional intermediate image content frames scanned into the pixel array at the intermediate scan rate; when the display device is operating at the first refresh rate, programming additional first image content frames into the pixel array, including scanning the additional first image content frames line by line into the pixel array at the first scan rate; and activating the pixel array to present the additional first image content frames scanned into the pixel array at the first scan rate.

[0018] Example 11 is the method according to any one of Examples 1 to 10, wherein: when the display device is operating at an intermediate refresh rate, programming the intermediate image content frames into the pixel array, the intermediate refresh rate being between the first refresh rate and the second refresh rate.

[0019] Embodiment 12 is the method according to any one of Embodiments 1 to 11, wherein: before receiving the indication that the display device is to transition from the first refresh rate to the second refresh rate, the display device is programmed at the first refresh rate and presents a first series of at least one hundred image content frames, including programming and presenting the first image content frame; and after presenting the intermediate image content frame, the display device presents a second series of at least one hundred image content frames at the second refresh rate, including programming and presenting the second image content frame.

[0020] Embodiment 13 is the method according to Embodiment 12, wherein: the programming of the first series of at least one hundred image content frames includes scanning each image content frame of the first series of at least one hundred image content frames line by line into the pixel array at the first scan rate; and the programming of the second series of at least one hundred image content frames includes scanning each image content frame of the second series of at least one hundred image content frames line by line into the pixel array at the second scan rate.

[0021] Embodiment 14 is the method according to any one of Embodiments 12 to 13, wherein: the programming of the intermediate image content frame is to scan the only image content frame into the pixel array at the intermediate scan rate between the display device presenting the first image content frame and the display device presenting the second image content frame.

[0022] Embodiment 15 is the method according to any one of Embodiments 1 to 14, including: after the display device presents the first image content frame and before the display device presents the second image content frame: programming a second intermediate image content frame into the pixel array, including scanning the second intermediate image content frame line by line into the pixel array at a second intermediate scan rate, the second intermediate scan rate being between the first scan rate and the second scan rate; activating the pixel array to present the second intermediate image content frame scanned into the pixel array at the second intermediate scan rate; programming a third intermediate image content frame into the pixel array, including scanning the third intermediate image content frame line by line into the pixel array at a third intermediate scan rate, the third intermediate scan rate being between the first scan rate and the second scan rate; and activating the pixel array to present the third intermediate image content frame scanned into the pixel array at the third intermediate scan rate.

[0023] Embodiment 16 is the method according to Embodiment 15, wherein: the intermediate scan rate, the second intermediate scan rate, and the third intermediate scan rate represent a series of different scan frequencies between the first scan rate and the second scan rate.

[0024] Example 17 is the method as described in Example 16, wherein: the difference between the intermediate scanning rate and the second intermediate scanning rate is the same as the difference between the second intermediate scanning rate and the third intermediate scanning rate.

[0025] Example 18 is the method as described in any one of Examples 16 to 17, wherein: when the display device is operating at a first intermediate refresh rate between the first refresh rate and the second refresh rate, programming the intermediate image content frame into the pixel array; when the display device is operating at a second intermediate refresh rate between the first refresh rate and the second refresh rate, programming the second intermediate image content frame into the pixel array; and when the display device is operating at a third intermediate refresh rate between the first refresh rate and the second refresh rate, programming the third intermediate image content frame into the pixel array.

[0026] Example 19 is the method as described in any one of Examples 1 to 18, including: applying a first gamma value to the first image content frame, the first gamma value being the gamma value designated for the first refresh rate; applying an intermediate gamma value to the intermediate image content frame; and applying a second gamma value to the second image content frame, the second gamma value being the gamma value designated for the second refresh rate.

[0027] Embodiment 20 is a display system, including: a display device including a pixel array; and a circuit system configured to: when the display device is operating at a first refresh rate, program a first image content frame into the pixel array, including scanning the first image content frame line by line into the pixel array at a first scan rate, wherein the image content presented by the pixel array is refreshed at the first refresh rate; activate the pixel array to present the first image content frame scanned into the pixel array at the first scan rate; receive an indication that the display device is to transition from the first refresh rate to a second refresh rate, wherein the image content presented by the pixel array is refreshed at the second refresh rate; in response to receiving the indication that the display device is to transition from the first refresh rate to the second refresh rate, program an intermediate image content frame into the pixel array, including scanning the intermediate image content frame line by line into the pixel array at an intermediate scan rate, the intermediate scan rate being between the first scan rate and the second scan rate; activate the pixel array to present the intermediate image content frame scanned into the pixel array at the intermediate scan rate; after the display device has presented the intermediate image content frame and when the display device is operating at the second refresh rate, program a second image content frame into the pixel array, including scanning the second image content frame line by line into the pixel array at the second scan rate; and activate the pixel array to present the second image content frame scanned into the pixel array at the second scan rate.

[0028] Embodiment 21 is the display system as described in Embodiment 20, wherein the circuit system is configured to perform the method as described in any one of Embodiments 1 to 19.

[0029] Details of one or more implementations are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A diagram showing an example display system of an electronic device.

[0031] Figures 2A to 2B A diagram showing a pixel circuit of a display device and a corresponding timing diagram.

[0032] Figures 3A to 3B A diagram showing frames presented at two different refresh rates.

[0033] Figure 4A A diagram showing frames presented at a reduced scan rate.

[0034] Figures 4B to 4C A diagram showing the effect of a transition from one scan rate to another.

[0035] Figure 5A Shows a graph demonstrating the conversion between refresh rates of a presentation including an intermediate frame.

[0036] Figure 5B Shows an example characteristic table of a frame sequence.

[0037] Figures 6A to 6C Shows a graph demonstrating how a display device can achieve multiple differential pixel activations in each frame.

[0038] Figures 7A to 7C Shows a graph of the conversion between refresh rates and various ways of converting between different numbers of discrete pixel activations.

[0039] Figures 8A to 8D Shows a flowchart of a process for scanning image data into a pixel array at an intermediate scan rate during conversion between different refresh rates.

[0040] Figure 9 Is a block diagram of a computing device that can be used to implement the systems and methods described in this document, the computing device being a client or a server or multiple servers.

[0041] In the various figures, the same reference numerals indicate the same elements. Detailed Description

[0042] This document generally describes techniques for scanning image data into a pixel array at an intermediate scan rate during conversion between different refresh rates. A computing device can scan image data into a pixel array at different scan rates for different display refresh rates. To minimize or eliminate perceptible screen flicker to a user during the conversion from a first refresh rate and first scan rate to a second refresh rate and second scan rate, the computing device can present multiple frames of the image data during the conversion period. The scan rate of the frames presented during the conversion period can be gradually changed from the first scan rate to the second scan rate. The following discussion explains the operation of an example display device and how the display device can achieve an intermediate scan rate during conversion between refresh rates.

[0043] Figure 1 Shows a diagram of an example display system 100 of a computing device 190. The display system 100 can be an LED display system including a pixel array 112 that emits light. Each light-emitting pixel includes an LED (e.g., an OLED). The pixel array 112 can be located on a display panel 104 that includes various supporting circuitry systems, including a scan driver 108 and an emission driver 109.

[0044] The pixel array 112 is driven by multiple drivers, including a scan driver 108, an emission driver 109, and a data driver 110. The scan driver 108 and the emission driver 109 can be integrated (e.g., stacked) row line drivers.

[0045] The data driver 110 provides data signals (e.g., voltage data (VDATA)) to be received by data lines (e.g., D1 to D3), where the data signals can be stored by the capacitance of each respective data line. The scan driver 108 provides a SCAN signal to one of the selected scan lines in the scan lines (e.g., SCAN1) to shift the data signals stored in the data lines to the pixels in the selected scan line, thereby programming the pixels in the selected scan line with the image data specified by the data signals. The emission driver 109 provides an EM signal to one of the selected emission lines in the emission lines (e.g., E1) to activate the LEDs in the selected row to emit light at the intensity specified by the data signals.

[0046] Although Figure 1 the display system 100 is shown having the scan driver 108 and the emission driver 109 on one side of the display, the scan driver 108 and the emission driver 109 can be located on different sides of the display (e.g., left and right) to improve driving performance.

[0047] The pixel array 112 includes multiple light-emitting pixels, e.g., pixels P11 to P34. A pixel is a small element of the display, and the pixel includes an LED that can emit light at different intensities based on the image data supplied to the pixel. The color of the light emitted by each pixel can be defined by the type of LED included in each pixel and / or the color of the filter placed on each such LED.

[0048] Each pixel includes an LED and circuitry for receiving the image data value provided by the data signal, storing the received image data value, and driving the LED at an intensity based on the data value. The pixel circuitry can have the configuration shown in Figure 2A , but other pixel circuitry configurations can also be used. Each pixel within the pixel array 112 can be individually addressed to produce various intensities of the color produced by that pixel.

[0049] Each pixel maintains a generally stable brightness throughout the frame time, thereby displaying light at an intensity corresponding to the supplied image data. The frame time or frame period is the amount of time between the start of one frame and the start of the next frame. The frame time can be the reciprocal of the frame rate of the display system 100. For example, a frame rate of 60 frames per second (fps) corresponds to a frame time of one-sixtieth of a second or 0.0167 seconds.

[0050] The pixel array 112 extends in a plane and includes pixel rows that extend horizontally across the pixel array 112 and pixel columns that extend vertically across the pixel array 112. For example, the first row of the pixel array 112 includes pixels P11, P21, and P31, while the second row of the pixel array 112 includes pixels P12, P22, and P32. The first column of the pixel array 112 includes pixels P11, P12, P13, and P14, while the second column of the pixel array includes pixels P21, P22, P23, and P24.

[0051] For simplicity, Figure 1 only a few pixels are shown. In practice, there can be thousands or millions of pixels in the pixel array 112. Increasing the number of pixels in a pixel array of the same size results in a higher image resolution (e.g., a greater pixel density).

[0052] The display system 100 includes a display driver circuit 106 that provides signals with appropriate voltage, current, and timing to cause the pixel array 112 to show an image according to an image content frame received by the display driver circuit 106. The display driver circuit 106 can be separated from the display panel 104 (as Figure 1 shown), or can be part of the display panel 104.

[0053] The display driver circuit 106 can receive display control signals and image content frames from a separate circuit such as a system-on-chip (SoC) 105. The SoC 105 can be the main processor of the computing device 190 and can be the processor on which applications execute. The display driver circuit 106 can be, for example, a semiconductor integrated circuit or a state machine. The display driver circuit 106 can be a microcontroller and can incorporate RAM, flash memory, EEPROM, ROM, etc. The scan driver 108, the emission driver 109, and / or the data driver 110 can be integrated with the display driver circuit 106 or separated from the display driver circuit 106. When the display driver circuit 106 is implemented as an integrated circuit, it can be referred to as a "DDIC".

[0054] The display driver circuit 106 includes a logic circuitry 160 that can receive display control signals from the SoC 105 and can control the operation of the display driver circuit 106. The display driver circuit 106 can store one or more image content frames received from the SoC 105 in the GRAM 162. For example, the GRAM 162 can be used as a frame buffer for storing a single image content frame.

[0055] The display driver 110 may include a digital-to-analog (D / A) converter 164 that can convert the image data received from the GRAM 162 from digital form to analog form (e.g., to discrete analog voltage levels). The conversion process involves converting individual image data lines from the stored frame and may use a reference voltage received from a gamma block 164. In some examples, the gamma block 324 generates eight different reference voltage levels. The eight reference voltages represent intermediate levels between the gray value zero and two hundred and fifty-five.

[0056] The display driver 110 may include a source amplifier 168 that amplifies the signal output from the D / A converter 166 to transmit such a signal to the display panel 104 (e.g., to the multiplexer 113 of the display panel 104). Thus, the signal supplied by the data driver 110 to the columns of the pixel array 112 is based on the image content frame received by the display driver circuit 106 from the SoC 105 and stored in the GRAM 162.

[0057] The data driver 110 outputs data values to a set of multiplexers 114 (e.g., MUX1, MUX2, and MUX3) via source amplifier output signal lines SAN (e.g., a set of source amplifier signal lines SA1, SA2, and SA3). Each multiplexer in the set receives a data value from a corresponding source amplifier output signal line and routes the received data value among a greater number of data lines. For example, Figure 1 shows a single multiplexer 114 configured to receive a stream of data values from the data driver 110 via the source output signal line SA1 and distribute the stream of data values one at a time among the data signal lines D1 to D3. In practice, there may be multiple multiplexers, each fed data values by a corresponding source control signal line.

[0058] The timing controller 134 generates control signals, e.g., signals that control the display frame start time and the display frame stop time of each frame presented by the display panel 104, where a frame represents a single image in a series of images presented by the display panel 104. In examples where multiple emission cycles are used to present each frame presented by the display panel, the control signals generated by the timing controller 134 may control the display emission start time and the display emission stop time of each emission cycle. The control signals generated by the timing controller 134 may drive the scan driver 108, the emission driver 109, the display driver 110, and the multiplexer 114. Thus, the display driver circuit 106 controls the timing of the SCAN signal, the EM signal, and the data signal.

[0059] The clock signal generator 136 can generate a clock signal that defines the rate at which the various components of the display system 100 operate. For example, the timing controller 134 can receive the clock signal and provide a VSync signal to the respective drivers at time intervals that are multiples of the clock signal. The scan driver 108 and the emission driver 109 transition from one line to another at a rate defined by the clock signal (e.g., switch from one line to another with each cycle of the clock signal). The refresh rate of the display system 100 can be a multiple of the clock signal.

[0060] The scan driver 108 and the emission driver 109 supply SCAN signals and EM signals to the rows of the pixel array 112. For example, the scan driver 108 supplies scan signals to the rows of pixels via scan lines S1 to S4, and the emission driver 109 supplies EM signals to the rows of pixels via EM lines E1 to E4. Each pixel row in the pixel array 112 is addressed by a scan line and a corresponding emission line. For example, the first row in the pixel array 112 is addressed by scan line SCAN1 and emission line E1.

[0061] Each pixel in the pixel array 112 can be addressed by a horizontal scan line, a horizontal EM line, and a vertical data line. For example, pixel P11 can be addressed by data line D1, scan line S1, and EM line E1. Pixel P23 can be addressed by data line D2, scan line S3, and EM line E3.

[0062] For each frame, the scan lines are addressed sequentially. The scan direction determines the order in which the scan lines are addressed (e.g., the direction in which pixel rows receive data values and then emit light based on the intensity of the received data values). In the display system 100, the scan direction is from the top of the pixel array 112 to the bottom of the pixel array 112. For example, scan line S1 is addressed first, followed by scan line S2, then S3, and so on. In some implementations, all pixel rows are programmed with data values using the SCAN signal (one row at a time), and then the display device activates all pixel rows based on the intensity of the programmed data values. In some implementations, the display device can activate pixel rows while other pixel rows are still being programmed, such that there is a gap of one or more rows between the row currently receiving the SCAN signal and the pixel rows that have been activated and started emitting light.

[0063] The display system 100 also includes a power supply 150. The power supply 150 provides a first power supply voltage ELVDD and a second power supply voltage ELVSS, both of which are supplied to each pixel in the pixel array 112. In some examples, the power supply 150 can be integrated with the display driver circuit 106.

[0064] The power supply 150 or the display driver circuit 106 can include a DC-to-DC converter (at Figure 1(not shown in the figure). The DC - to - DC converter can boost a lower input voltage to a stable higher output voltage. For example, the input voltage of the DC - to - DC converter can be three volts, and the output voltage can be six volts. The control signals (e.g., scan signals, emission signals, and multiplexer signals) provided by the timing controller 134 to the display panel 104 can be at the higher voltage generated by the DC - to - DC converter. The logic circuitry 160 and other components of the display driver circuit 106 can operate at a lower voltage.

[0065] In some examples, each of the data lines D1 to D3 represents multiple data lines. For example, pixel P11 can include three sub - pixels (e.g., P11R is a red sub - pixel, P11G is a green sub - pixel, and P11B is a blue sub - pixel), and data line D1 can represent three corresponding data lines, each addressing a corresponding sub - pixel of pixel P11. In some examples, each of the data lines D1 to D3 represents data lines for sub - pixels of different colors (e.g., P11 represents a red sub - pixel, P21 represents a green sub - pixel, and P31 represents a blue sub - pixel).

[0066] Although Figure 1 shows that each row is addressed by a single scan line, each row can also be addressed by multiple scan lines (e.g., nSCAN and pSCAN). Although Figure 1 shows an example component of an LED display, the described technology can be applied to other flat - panel display technologies including pixel arrays. For example, the technology can be applied to liquid - crystal displays (LCDs) and plasma display panels (PDPs).

[0067] Figure 2A A diagram showing a pixel circuit of a display device, the pixel circuit including an LED and corresponding driver circuitry for the pixel circuit. Figure 2A A more detailed view of a single pixel from the Figure 1 pixel array shown in can be shown. Although this disclosure sometimes refers to the Figure 2A components shown in as "pixel circuits", this disclosure can also simply refer to these components as "pixels". Further, Figure 2A the pixels shown in can represent sub - pixels.

[0068] The pixel circuit can be an active - matrix OLED (AMOLED) pixel circuit. The pixel circuit receives an EM signal on the emission signal line, a SCAN signal on the scan signal line, and a data voltage (VDATA) signal on the data signal line. The pixel circuit 200 receives a first power supply voltage ELVDD on the first voltage supply line, a second power supply voltage ELVSS on the second voltage supply line, and an initial reference voltage VINIT on the initial voltage supply line.

[0069] The pixel circuit includes an organic light-emitting diode (OLED). The OLED includes a layer of an organic compound that emits light in response to a current IOLED. The organic layer is located between two electrodes (an anode and a cathode). The OLED is driven by a driving transistor T1 that receives a power supply voltage ELVDD and serves as a current source for driving the OLED to emit light.

[0070] The pixel further includes a storage capacitor CST and transistors T2 to T7. The operation of the pixel is defined by the states of control signals SCAN, EM, and VDATA. The amount / level of the OLED current (IOLED) is set by the voltage present at the gate terminal (referred to herein as the "G" node) of the driving transistor T1.

[0071] The driving transistor T1 has a threshold voltage VTH between the gate terminal and the source terminal of the driving transistor T1. If the voltage between the gate terminal and the source terminal is higher than the threshold voltage VTH, the driving transistor T1 creates a conduction path from the source terminal to the drain terminal. The amount of the current IOLED flowing through the conduction path passing through the driving transistor T1 corresponds to the amount by which the voltage between the gate terminal and the source terminal exceeds the threshold voltage VTH.

[0072] Figure 2B is shown being provided to Figure 2A a timing diagram of the control signals shown in and received by the pixel. These control signals repeatedly transition between an initialization phase, a programming phase, and an emission phase during the operation of the display system 100.

[0073] At the end of the emission phase, the EM signal (e.g., by changing from a low state to a high state) transitions to an off state. This transition turns off transistors T5 and T6, which interrupts the supply of current from ELVDD to the OLED, thus stopping the light emission by the OLED. Since the EM signal can be provided to an entire pixel line, this transition can turn off all the pixels in the pixel line.

[0074] During the initialization phase, the SCAN[n - 1] signal (e.g., by changing from a high state to a low state) transitions to an on state, which turns on transistor T4 for a period of time and initializes the G node to an initialization voltage VINIT. Since the SCAN[n - 1] signal can be provided to an entire pixel line, this initialization phase can erase the data values previously stored at each pixel in the pixel line. The SCAN[n - 1] signal can be the SCAN[n] signal provided to the previous row by the state machine of the scan driver 108.

[0075] During the programming phase, the SCAN[n] signal (e.g., by going low) transitions to an on state, which turns on transistors T2, T3, and T7 for a period of time. This causes the VDATA value at the data line to reach the G node through transistors T2, T1, and T3, thereby setting the G node to a value based on the value of the VDATA line (e.g., the voltage at VDATA minus the effect of the transistor threshold voltage). Since the SCAN signal can be provided to the entire pixel line, this programming phase can cause each pixel in the pixel line to move the data voltage value from the corresponding data line of each pixel to the G node of each corresponding pixel.

[0076] During the emission phase, the EM signal (e.g., by going low) transitions to an on state, which turns on transistors T5 and T6. Current flows from ELVDD through transistors T5, T1, and T6 to the anode of the OLED. Since the EM signal is provided to the entire pixel line, all pixels in this pixel line can be activated.

[0077] The current level supplied to the OLED in each pixel is determined by the voltage at the G node of that pixel (e.g., using the G node voltage level that has been programmed to the data line). The intensity or brightness of the light emitted by the OLED is directly related to the amount of current IOLED applied to the OLED, where a larger current corresponds to a larger light intensity compared to a lower current. The storage capacitor CST maintains the voltage at the G node such that the OLED emits light at a generally constant level during the emission phase. During the emission phase, the voltage at the G node can drop slightly. Thus, during the emission phase, the current IOLED applied to the OLED and the intensity of the light emitted by the OLED can drop slightly.

[0078] Figure 3A A diagram showing a frame sequence presented at a 120 Hz refresh rate is shown. Specifically, the diagram shows four frames 310a to 310b, where the frame times are separated from each other by vertical dashed lines. The vertical dashed lines indicate the start of each frame time (e.g., an instance of the VSync signal), where the amount of time between successive lines is defined by the current refresh rate of the display device. Figure 3A The diagram shows the display operation at a 120 Hz refresh rate, as shown by the notation "P(120 Hz)" along the horizontal time axis, indicating that each frame has a single "period at 120 Hz" of 0.00833 seconds.

[0079] Figure 3A The vertical dimension of the diagram represents the rows of the pixel array, from "Row 1" (e.g., the top row of the pixel array) to the last "Row N" (e.g., the bottom row of the pixel array).

[0080] The shaded area marked as "Initialization" represents the period during which pixels in each row are initialized (e.g., as a result of an activation signal on the SCAN[n - 1] line for a given pixel row). Each pixel row can be initialized individually such that only a single pixel row receives a valid signal on its SCAN[n - 1] line at a time.

[0081] In each cycle of the clock signal, the pixel row at which the SCAN[n - 1] line is activated can switch to the next pixel row, such that the start of each frame is different for each pixel row. Accordingly, the accompanying drawings use vertical lines to show the start / end of the frame from the perspective of the first row. The progression of activating the SCAN[n - 1] lines one after another down the pixel array is shown by the slanted nature of the "Initialization" area. The scan driver 108 ( Figure 1 ) is a component of the display device that activates the SCAN[n - 1] lines one at a time.

[0082] The rate at which the scan driver 108 cycles through the lines is defined by the clock signal (e.g., the clock signal generated by the clock signal generator 136 ( Figure 1 ). The clock signal can be received by the scan driver 108 and / or the timing controller 134 to cause the scan driver 108 to scan the pixel array 112 at a particular scan rate (e.g., a scan rate directly corresponding to the frequency of the clock signal or a multiple thereof). Figure 3A The figure shows the scan rate "f" (representing "frequency") accompanied by a slanted arrow and a square wave above the arrowhead.

[0083] The shaded area marked as "Programming" represents the period during which pixels in each row are programmed with image data (e.g., as a result of an activation signal on the SCAN line for a given pixel row). Each pixel row can be programmed individually such that only a single pixel row receives a valid signal on its SCAN line at a time.

[0084] In each cycle of the clock signal, the pixel row at which the SCAN line is activated can switch in the same manner as the "Initialization" operation. The activation of the SCAN lines also scans line by line at the scan rate "f". As Figure 2B shown, the "Programming" period (resulting from the activation of the SCAN[n] line) for each pixel line can follow the "Initialization" period (resulting from the activation of the SCAN[n - 1] line) for the same pixel line. When a pixel line is in the "Initialization" period and the "Programming" period (see Figure 2B ), that pixel line may not emit light.

[0085] The non-shaded region marked as "emission" represents the period during which the emission lines for a pixel row are activated, causing the pixels in that row to emit light at an intensity specified by the image data values programmed into the pixels in that row.

[0086] In some implementations, the "emission" period includes multiple differential activations of each pixel in the pixel row, such as pixel activations 320a and 320b. The differential pixel activations can be caused by the pixel lines performing "self-refresh" or otherwise briefly deactivating the LED emission. During such a refresh, each pixel can retain its programmed image data value, such that the LED emits light at the same intensity after reactivation. Each pixel line can start and end its corresponding activation period individually, line by line. Thus, activation periods 320a and 320b represent the activation periods for a single row in the pixel array. The activation periods for adjacent pixel rows can be offset by a single clock cycle (or a multiple thereof) in time.

[0087] Dividing the emission period into multiple differential pixel activations allows the display to dim in a way that can avoid perceptible flicker. For example, pulse width modulation techniques are used to provide multiple shorter "off" periods instead of providing a single longer "off" period (e.g., at the end of the emission period between the "emission" period and the "initialization" period, or by extending the "initialization" period). A single longer "off" period can generate perceptible flicker for the user, while dividing the same amount of "off" time into multiple differential "off" periods may not be perceptible to the user.

[0088] Figure 3B A diagram showing a sequence of frames presented at a 120 Hz refresh rate is shown. The operation of the display device represented by Figure 3B is similar to the operation of Figure 3A where the main difference is that the refresh rate in Figure 3B is 60 Hz instead of the 120 Hz refresh rate shown in Figure 3A , doubling the length of each frame. Additionally, the number of differential pixel activations per emission period doubles (four instead of two). In the operating state shown in Figures 3A to 3B , the length of each differential pixel activation can be the same for both 120 Hz and 60 Hz. Figure 3B The scan rates of the "initialization" period and the "emission" period in Figure 3A are the same as those in Figures 3A to 3B (both are "f"). The display device can switch between the operating modes shown in

[0089] Figure 4AA diagram showing a frame sequence presented at a 60 Hz refresh rate is shown. Figure 3B The display operation shown in Figure 3B is similar to the display operation of Figure 4A , except that the scan rate in Figure 3B is "f / 2", which is half of the scan rate frequency "f" shown in Figure 3B . Therefore, compared to the operation of Figure 3B , the display device operation shown in

[0090] takes longer to initialize the entire image content frame and program it into the pixel array. In other words, it may take twice as long to scan each frame. Figure 1 Operating at a reduced scan rate can reduce the level of energy consumed by the display device. For example, a reduced scan rate can be achieved by reducing the frequency generated by the clock signal generator 136 (

[0091] ), which can slow down the operation of multiple components (such as the timing controller 134, the scan driver 108, the emission driver 109, and the display driver 110) that receive the clock signal. The difficulty in achieving a relatively low scan rate at a lower refresh rate (e.g., 60 Hz) is that the amount of time it takes for the display device to scan the entire pixel array may be greater than the amount of time it takes to scan the entire pixel array at a higher refresh rate (e.g., 120 Hz). Thus, if the scan rate remains the same among all different refresh rates, the frame time at the highest refresh rate achieved by the display device is a constraint on how much the scan rate can be reduced.

[0092] Figure 4B A diagram showing that as the display device transitions from a low refresh rate to a higher refresh rate, the display device transitions from a low scan rate to a higher scan rate is shown. The first frame 410a is achieved using a first refresh rate of 60 Hz and a first scan rate of "f". The second frame 410b is achieved using a second refresh rate of 120 Hz and a second scan rate of "2f".

[0093] In some implementations, a change in the scan rate can result in an undesired user-perceivable flicker, e.g., due to the change in frequency being greater than a threshold change in frequency. The user-perceivable flicker may be caused by the different amounts of time that the rows of the pixel array emit light during the transition. The different amounts of time are shown by the converging arrows in Figure 4B . For example, the pixels in row 1 are active and emit light for a greater amount of time than the pixels in row N are active and emit light.

[0094] Figure 4C A diagram showing the transition between scan rates and the effect of the transition on achieving multiple differential pixel activations per emission period is shown. For example,Figure 4C illustrates how the convergence of the scans of frames 430a and 430b interferes with achieving the same number of differential pixel activations for each pixel row. For example, row 1 is activated for a length sufficient to achieve four differential pixel activations, while row N is activated for a length sufficient to achieve only two differential pixel activations. The intermediate rows are activated for a length sufficient to achieve only three differential pixel activations. In Figure 4C the operating mode shown, to minimize user-perceivable flicker, different pixel lines can achieve different numbers of differential pixel activations, and those pixel activations can have different lengths from line to line.

[0095] Figure 5A shows a graph demonstrating the transition between refresh rates, where the transition includes intermediate frames. For example, Figure 5A shows: (1) a first frame 510a operating at a first refresh rate and a first scan rate (e.g., 60 Hz and "f"); (2) a second frame 510c operating at a second refresh rate and a second scan rate (e.g., 120 Hz and "2f"); and (3) an intermediate frame 510b operating at an intermediate refresh rate and an intermediate scan rate (e.g., 90 Hz and "1.5f").

[0096] Figure 5A The "emission" time periods in

[0097] Figure 5A are all marked. The time period marked as "steady-state emission 60 Hz" represents the last emission time period of the steady-state presentation of multiple frames operating at a 60 Hz refresh rate. Conversely, the time period marked as "steady-state emission 120 Hz" represents the first emission time period of the steady-state presentation of multiple frames operating at a 120 Hz refresh rate.

[0097] Figure 5A The transition shown in Figure 5A includes a single "intermediate scan #1", which represents a single set of "initialization" scans and "emission" scans operating at an intermediate scan rate of "1.5f", which is between the scan rates "f" and "2f". Figure 5A Also shown is an intermediate rate of 90 Hz for the refresh rate of the intermediate frame, which is between the refresh rates of 60 Hz and 120 Hz. In some implementations, the refresh rate of the intermediate frame is the higher of the two main refresh rates, such that frame 510b should have a refresh rate of 60 Hz. Figure 7C (discussed more later) shows the operation of a display device in which there is at least one intermediate frame but no intermediate refresh rate.

[0098] The benefit of using an intermediate scan rate to transition between scan rates (as shown in Figure 5A ) is that the magnitude of the change in the scan rate between two adjacent frames can be relatively small, such that the user may not perceive the change in the scan rate. For example, Figure 5AThe convergence between the arrows shown in is not as significant as Figure 4B the convergence shown in.

[0099] Although Figure 5A shows a conversion from one refresh rate to another using a single intermediate scan, the display device may implement multiple such intermediate scans that sequentially change from a first scan rate to a second scan rate. The number of intermediate frames may depend on the amount of difference between the first scan rate and the second scan rate, and the amount by which the scan rate can be changed per frame without being perceptible to the user.

[0100] Figure 5B shows an example characteristic table of a frame sequence presented by a display device. The top row of the table identifies eleven different frames with unique frame numbers, and the second row identifies the type of each frame. Frame #1 is listed as a normal speed (NS) type of frame, which has a scan rate of "f" and a frame length of 1 / 60 second. Each of the hundreds of frames before Frame #1 may have the same characteristics. Frame #11 is a high speed (HS) type of frame, which has a scan rate of "2f" and a frame length of 1 / 120 second. Each of the hundreds of frames after Frame #11 may have the same characteristics.

[0101] Frames #2 to #10 are each intermediate type of frames. Since each of these nine frames has different characteristics, they are respectively identified as "I-1", "I-2", etc., up to "I-9". As shown by the "scan rate" row, the scan rate changes gradually frame by frame by increasing 0.1 "f" per frame. The change in the scan rate can be achieved by modifying the oscillator frequency (e.g., the frequency generated by Figure 1 the clock signal generator 136 shown in). Figure 5B shows that the change is linear (0.1 "f" per frame), but the change can also be proportional (e.g., increasing by a percentage per frame). In some implementations, the frame length changes gradually frame by frame by increasing 6 Hz per frame. Similar to the change in the scan rate, the change in the frame length can be proportional.

[0102] The "gamma value" row in the table indicates how each frame can use differential gamma values (e.g., information for calibrating the image content to the physical and operating characteristics of the display device). In some examples, all intermediate frames use a single gamma value (e.g., all use gamma value "B"). In some examples, half of the intermediate frames use the gamma value of the NS frame type (e.g., frames 2 to 6 use gamma value "A"), and half of the intermediate frames use the gamma value of the HS frame type (e.g., frames 7 to 10 use gamma value K). Other conversion methods from gamma value "A" to gamma value "B" can be used (e.g., two intermediate gamma values, three intermediate gamma values, etc.).

[0103] Figures 6A to 6C A diagram showing how a display device can implement multiple differential pixel activations in each frame for different types of frames.

[0104] Figure 6A The diagram shows a display device during steady-state operation (e.g., at a constant 60 Hz or 120 Hz refresh rate). The vertical dashed lines represent different scans of "initialization" and "programming", such as Figure 3B two adjacent "initialization" scans and "programming" scan pairs in Figure 3B Although the scan operation is shown with slanted regions, Figure 6A this operation is represented by vertical dashed "scan" lines to show how each pixel row emits light for the same length of time in each frame.

[0105] Figure 6B The diagram shows a display device during intermediate operation, as shown by the converging Scan N line and Scan N+1 line. The convergence of these Scan lines corresponds to Figure 5A the convergence of the "f" scan line and the "1.5f" scan line in

[0106] Figure 6C resulting in row 1 having a shorter overall emission period than row 1 (although the user may not perceive this difference). The difference in emission length is resolved by changing only the last activation performed by each pixel row. The benefit of this method is that any previous activations in the same frame can be performed at the same / continuous scan rate (e.g., using a short "off" signal during the emission period to scan the "emission" lines). When the next frame starts (e.g., when the next VSync signal is issued), the transition to a new clock rate can begin, where the timing of the next frame is defined by the refresh rate. Figure 6B Figure 1 Similar to Figure 6C the first row pixel activation in Figure 6C the diagram shows a display device during intermediate operation, except that all differential activations in each row vary uniformly to fill the entire emission period. For example,

[0107] Figures 7A to 7C A diagram showing the transition between refresh rates and various ways of transitioning between different numbers of discrete pixel activations. For example, Figures 7A to 7CAll show the following conversion: from (1) a display operation with a scan rate of "f" and four differentially activated at a 60 Hz refresh rate to (2) a display operation with a scan rate of "2f" and two differentially activated at a 120 Hz refresh rate.

[0108] Figures 7A to 7C The first difference among the operations is how to perform the conversion from four differentially activated to two differentially activated. Figure 7A Shows that the conversion is gradual: (1) at 70 Hz, four differentially activated are retained, but the total emission time amount is shortened (e.g., by uniformly shortening all activation periods, or by only shortening the last activation), and (2) then at 60 Hz, it drops to three activations. This process is repeated for each frame, thus stretching each activation and / or discarding a certain activation to fill each emission period.

[0109] Figure 7B Shows that the change from four activations per frame to two activations per frame is achieved in one go using a first intermediate frame (e.g., a 70 Hz frame). All intermediate frames have two pixel activations, which is the number of activations in the 120 Hz refresh rate operation mode. The display device can set the size of each group of two activations to fill their corresponding emission time periods, such that the activations for different intermediate frames can have different lengths. It can be done uniformly (e.g., as shown in Figure 6C ), or by setting the size of a single activation (e.g., as shown in Figure 6B ).

[0110] Except Figure 7C shows that the change occurs at the end of the conversion rather than at the beginning, Figure 7C it also shows that the change from four activations per frame can be achieved in one go.

[0111] Although Figure 7A and Figure 7B show that the refresh period changes gradually with each intermediate frame during the conversion from 60 Hz to 120 Hz, but Figure 7C shows that the change in the refresh rate can be achieved in one go. For example, 7C shows that the refresh rate remains at 60 Hz while the scan rate changes gradually. Then, at the end of the conversion, the refresh rate changes to 120 Hz.

[0112] As Figure 7C shown, the benefit of operating the display is that the SoC can be able to easily provide frames that are properly timed for two discrete refresh rates (e.g., 60 Hz and 120 Hz). The SoC may have to perform additional processing (e.g., frame interpolation) in order to perform a multi-step conversion between refresh rates (such as Figures 7A to 7BFrames that are appropriately timed for display are generated during the conversion shown in

[0113] Although Figures 4A to 7C the conversion from a lower refresh rate to a higher refresh rate is shown, the conversion from a higher refresh rate to a lower refresh rate may involve the same operations, just in reverse order. For example, the conversion from a higher refresh rate to a lower refresh rate can be performed by stepping through the frames referenced by the table of Figure 5B in order from right to left.

[0114] Figures 8A to 8D FIG. shows a flow chart of a process for scanning image data into a pixel array at an intermediate scan rate during a conversion between different refresh rates. This process can be performed by the display system 100 ( Figure 1 ). and its components.

[0115] At block 810, the display system receives a first image content frame. For example, the display driver circuit 106 receives the image content frame from the SoC 105 and stores the image content frame in the GRAM 162. The frame is also received line by line by the display panel 104.

[0116] At block 812, the pixel array 112 is initialized. For example, the scan driver can successively activate the SCAN[n - 1] lines of each pixel row one after another ( Figure 1 not shown in Figure 2B ), to initialize (e.g., erase) the image data values stored by each pixel in the array.

[0117] At block 814, the first image content frame is programmed into the pixel array by scanning the first image content frame line by line into the pixel array at a first scan rate. For example, the display driver circuit 106 can send the image data values for the first row of the current image content frame to the data lines D1 to D3, and the display driver circuit 106 can then send a signal to the scan driver 108 to cause the scan driver 108 to activate the first scan line, e.g., the SCAN1 line. The scan line is activated by supplying an "on" signal to the scan line, causing the pixels P11, P21, and P31 to perform an operation to transfer the image data values stored on the data lines D1 to D3 to the pixels P11, P21, and P31. This process can be repeated for each successive row of the image content frame (e.g., by activating SCAN2, then SCAN3, and then SCAN4).

[0118] The rate of the cycle of the display device from activating one SCAN[n] line to the next SCAN[n] line—and also from one SCAN[n-1] line to the next SCAN[n-1] line—is defined by the scan rate of the display panel 104. The scan rate of the display panel can correspond to the frequency of the clock signal generated by the clock signal generator 136 or a multiple of the frequency of the clock signal (e.g., activating the next SCAN[n] line every two clock cycles).

[0119] At block 818, the pixel array is activated to present a first image content frame scanned into the pixel array at a first scan rate. For example, the display driver circuit 106 can send a signal to the emission driver 109 to cause the emission driver 109 to sequentially activate each emission line one at a time. For example, the emission driver 109 can activate line E1, then line E2, then line E3, and then line E4. Activating the lines causes the pixels in the corresponding rows to activate and emit light at an intensity specified by the data value programmed into each pixel in that row.

[0120] At block 819, the display panel 104 can present a first number of differentially activated frames over the emission period for a single frame. For example, the emission driver 109 can scan short "off" periods one or more times across emission lines E1 to E4 during one frame. The length of one or more short "off" periods can affect the overall intensity of the display and can be used by the SoC 105 to implement screen-wide dimming.

[0121] In some implementations, the operations of blocks 810 to 819 can occur when the display device is operating at a 60 Hz refresh rate, and the number of differentially activated frames per emission period can be four (as Figures 7A to 7C shown). The display device can operate at different first refresh rates (e.g., any refresh rate between 55 Hz and 95 Hz). In some implementations, the first refresh rate is 82.5 Hz (and the second refresh rate to be discussed below is 165 Hz).

[0122] At block 820, the computing device determines whether to transition to a second refresh rate. During steady-state operation, the result of this determination is "no", and the display driver circuit 106 will continue to repeat the operations of the blocks in Figure 8A for each frame supplied to the display driver circuit 106 by the SoC 105.

[0123] When the type of visual content being displayed by the computing device is about to change, the computing device can determine to transition to a second refresh rate ( Figure 8Ain the "Yes" branch). For example, a computing device in which the display system 100 is installed may receive a user input to start a video game. In response, the SoC 105 may send a signal to the display driver circuit 106, thereby instructing that the operation of the display driver circuit 106 will switch to a different refresh rate (e.g., from 60 Hz to 120 Hz), and the SoC 105 will start supplying image content frames at twice the rate (e.g., 120 frames per second instead of 60 frames per second). In response to such a "Yes" determination, the operations of Figure 8B the flowchart are performed.

[0124] At block 830, the computing device identifies the process for the intermediate image content frames. For example, the SoC 105 may identify stored instructions that direct the computing device to transition from 60 Hz to 120 Hz using nine intermediate frames, as Figure 5B shown. Additionally or alternatively, the stored instructions may be implemented by the logic circuitry 160.

[0125] At block 832, the computing device identifies the scan rate sequence for the process for the intermediate frames. For example, the SoC 105 or the logic circuitry 160 may include instructions that identify Figure 5B the nine intermediate scan rates shown.

[0126] At block 834, the computing device identifies the refresh rate sequence for the process for the intermediate frames. For example, the SoC 105 or the logic circuitry 160 may include instructions that identify Figure 5B the nine intermediate frame durations (or their corresponding refresh rates) shown.

[0127] At block 836, the computing device identifies one or more gamma values for the process for the intermediate frames. For example, the SoC 105 or the logic circuitry 160 may include instructions that identify Figure 5B the nine intermediate gamma values shown, in which there are one or more transitions between the gamma values during the transition period.

[0128] At block 840, the display system receives the intermediate image content frames. For example, the display driver circuit 106 receives the image content frames from the SoC 105 and stores the image content frames in the GRAM 162. The received and stored frames may be the next frame after the latest instance of the first frame of the cyclic operation relayed from the frames in Figure 8A .

[0129] At block 842, the pixel array 112 is initialized. For example, the scan driver may successively activate each pixel row's SCAN[n - 1] line one by one ( Figure 1(not shown in the figure) to initialize the erasure / initialize the image data values stored at each pixel in the array.

[0130] At block 844, the intermediate image content frame is programmed into the pixel array 112 by scanning the intermediate image content frame line by line at an intermediate scan rate into the pixel array. The operations involved in scanning the intermediate image content frame into the pixel array 112 can be the same as the operations described with respect to the first refresh rate, except that the scan rate can be an intermediate scan rate that is greater than the above-described first scan rate but less than the second scan rate to which the display device is transitioning.

[0131] At block 846, the display device can operate at an intermediate refresh rate for the intermediate frame. For example, the length of time elapsed between the start VSync signal of the intermediate frame and the end VSync signal of the intermediate frame can be a length of time corresponding to a frequency between the first refresh rate and the second refresh rate (e.g., even if the display device may only output a single intermediate frame during that length of time).

[0132] At block 848, the pixel array is activated to present the intermediate image content frame scanned into the pixel array at the intermediate scan rate. For example, the display driver circuit 106 can send a signal to the emission driver 109 to cause the emission driver 109 to successively activate each emission line one by one.

[0133] At block 849, the display panel 104 can present an intermediate frame with an intermediate number of differentially activated pixels over the emission period for a single frame. For example, the emission driver 109 can activate each pixel row three times during the intermediate frame.

[0134] At block 850, the computing device determines whether to transition to another intermediate frame. In an example where the transition from the first refresh rate to the second refresh rate includes a plurality of intermediate frames (e.g., as shown in Figure 5B ), the result of this determination is "yes", and the display driver circuit 106 can continue to repeat the operations of blocks 840 to 849 for each intermediate frame (e.g., potentially using unique operating characteristics for each frame, as shown in Figure 5B ).

[0135] If there are no additional intermediate frames (e.g., because the current intermediate frame is the last intermediate frame of the transition), the computing device can transition to the Figure 8D operation. (The "No → to the first refresh rate" branch in Figure 8C is for the intermediate frame operation when transitioning back from the second refresh rate to the first refresh rate, as shown in Figure 8D ).

[0136] At block 860, the display system receives a second image content frame. For example, the display driver circuit 106 receives the image content frame from the SoC 105 and stores the image content frame in the GRAM 162. The second frame is also received line by line by the display panel 104.

[0137] At block 862, the pixel array 112 is initialized. For example, the scan driver can successively activate the SCAN[n - 1] lines of each pixel row one by one to initialize the image data values stored by each pixel in the array.

[0138] At block 864, the second image content frame is programmed into the pixel array by scanning the second image content frame line by line into the pixel array at a second scan rate. The second scan rate can be greater than the first scan rate and all intermediate scan rates and can be a multiple of the first scan rate.

[0139] At block 866, the display device can operate at a second refresh rate. The second refresh rate can be greater than the first refresh rate and can be a multiple of the first refresh rate (e.g., 120 Hz).

[0140] At block 868, the pixel array is activated to present the second image content frame scanned into the pixel array 112 at the second scan rate.

[0141] At block 869, the display panel 104 can present a second frame with a second number of differential activations over the emission period for a single frame. For example, the second frame can present two differential activations.

[0142] At block 870, the computing device determines whether to switch to the first refresh rate. During steady - state operation, the result of this determination is "no", and the display driver circuit 106 will continue to repeat the operations of the blocks Figure 8C for each frame supplied by the SoC 105 to the display driver circuit 106.

[0143] When the type of visual content being displayed by the computing device is about to change, the computing device can determine to switch to the first refresh rate ( Figure 8B the "yes" branch in). For example, the computing device can receive a user input to end a video game and convert the computing device user interface to a static image of the home screen icon. In response, the SoC 105 can send a signal to the display driver circuit 106, thereby indicating that the operation of the display driver circuit 106 will switch to a different refresh rate (e.g., from 120 Hz to 60 Hz), and the SoC 105 will start supplying image content frames at half the rate (e.g., 60 frames per second instead of 120 frames per second). In response to such a "yes" determination, the operations of the Figure 8C flowchart are executed (by leading toFigure 8A branches away from Figure 8C )

[0144] Figure 9 FIG. 900, 950 are block diagrams of computing devices that may be used to implement the systems and methods described in this document, the computing device being a client or a server or multiple servers. Computing device 900 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Computing device 950 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only intended as examples and are not intended to limit the implementations described and / or claimed in this document.

[0145] Computing device 900 includes a processor 902, a memory 904, a storage device 906, a high-speed controller 908 connected to the memory 904 and a high-speed expansion port 910, and a low-speed controller 912 connected to a low-speed expansion port 914 and the storage device 906. Each of the components 902, 904, 906, 908, 910, and 912 is interconnected using various buses and may be mounted on a common motherboard or otherwise as appropriate. The processor 902 may process instructions for execution within the computing device 900, including instructions stored in the memory 904 or on the storage device 906, to display graphical information of a GUI on an external input / output device such as a display 916 coupled to the high-speed controller 908. In other implementations, multiple processors and / or multiple buses and multiple memories and multiple types of memory may be used as appropriate. Additionally, multiple computing devices 900 may be connected, where each device provides a portion of the necessary operations (e.g., as a server farm, a group of blade servers, or a multi-processor system).

[0146] The memory 904 stores information within the computing device 900. In one implementation, the memory 904 is one or more volatile memory units. In another implementation, the memory 904 is one or more non-volatile memory units. The memory 904 may also be another form of computer-readable medium, such as a magnetic disk or an optical disk.

[0147] The storage device 906 can provide large-capacity storage for the computing device 900. In one implementation, the storage device 906 can be or include a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a magnetic tape device, a flash memory, or other similar solid-state memory devices, or an array of devices, including devices in a storage area network or other configurations. A computer program product can be tangibly embodied in an information carrier. The computer program product can also include instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer or machine-readable medium, such as the memory 904, the storage device 906, or the memory on the processor 902.

[0148] The high-speed controller 908 manages the bandwidth-intensive operations of the computing device 900, while the low-speed controller 912 manages the lower bandwidth-intensive operations. Such a functional assignment is merely an example. In one implementation, the high-speed controller 908 is coupled to the memory 904, the display 916 (e.g., via a graphics processor or accelerator), and a high-speed expansion port 910 that can accept various expansion cards (not shown). In an implementation, the low-speed controller 912 is coupled to the storage device 906 and a low-speed expansion port 914. The low-speed expansion port, which can include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), can be coupled to one or more input / output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or a router, for example, via a network adapter.

[0149] As shown in the accompanying drawings, the computing device 900 can be implemented in many different forms. For example, it can be implemented as a standard server 920, or implemented multiple times in a group of such servers. It can also be implemented as part of a rack server system 924. Additionally, it can be implemented in a personal computer such as a laptop computer 922. Alternatively, components from the computing device 900 can be combined with other components in a mobile device (not shown) such as the device 950. Each of such devices can include one or more of the computing devices 900, 950, and the entire system can be composed of multiple computing devices 900, 950 that communicate with each other.

[0150] The computing device 950 includes a processor 952, a memory 964, an input / output device such as a display 954, a communication interface 966, and a transceiver 968, and other components. The device 950 can also be provided with a storage device such as a microdrive or other device to provide additional storage. Each of the components 950, 952, 964, 954, 966, and 968 is interconnected using various buses, and several components can be mounted on a common motherboard or otherwise mounted as appropriate.

[0151] The processor 952 can execute instructions within the computing device 950, including instructions stored in the memory 964. The processor can be implemented as a chipset including separate multiple analog and digital processors on a chip. Additionally, the processor can be implemented using any of a variety of architectures. For example, the processor can be a CISC (Complex Instruction Set Computer) processor, a RISC (Reduced Instruction Set Computer) processor, or a MISC (Minimal Instruction Set Computer) processor. The processor can provide, for example, coordination of other components of the device 950, such as control of the user interface, applications run by the device 950, and wireless communication performed by the device 950.

[0152] The processor 952 can communicate with the user through a control interface 958 and a display interface 956 coupled to a display 954. The display 954 can be, for example, a TFT (Thin Film Transistor Liquid Crystal Display) display, an OLED (Organic Light Emitting Diode) display, or other suitable display technology. The display interface 956 can include appropriate circuitry for driving the display 954 to present graphics and other information to the user. The control interface 958 can receive commands from the user and convert them for submission to the processor 952. Additionally, an external interface 962 can be provided to communicate with the processor 952 to enable the device 950 to perform near area communication with other devices. The external interface 962 can provide, for example, wired communication in some implementations, or wireless communication in other implementations, and can also use multiple interfaces.

[0153] The memory 964 stores information within the computing device 950. The memory 964 can be implemented as one or more computer-readable media, one or more volatile memory units, or one or more non-volatile memory units, or a combination thereof. An extended memory 974 can also be provided, and the extended memory is connected to the device 950 through an extended interface 972, which can include, for example, a SIMM (Single In-line Memory Module) card interface. Such an extended memory 974 can provide additional storage space for the device 950, or can also store applications or other information of the device 950. Specifically, the extended memory 974 can include instructions for executing or supplementing the above processes, and can also include security information. Thus, for example, the extended memory 974 can be provided as a security module of the device 950 and can be programmed with instructions that allow for the secure use of the device 950. Additionally, security applications and additional information can also be provided via the SIMM card, such as placing identification information on the SIMM card in an unbreakable manner.

[0154] The memory may include, for example, flash memory and / or NVRAM memory, as discussed below. In one implementation, the computer program product is tangibly embodied in an information carrier. The computer program product contains instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer or machine-readable medium, such as the memory 964, the extended memory 974, or the memory on the processor 952, which can be received, for example, via the transceiver 968 or the external interface 962.

[0155] The device 950 can communicate wirelessly via the communication interface 966, which may include digital signal processing circuitry when necessary. The communication interface 966 can provide communication under various modes or protocols, such as GSM voice calls, SMS, EMS, or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000, or GPRS, etc. Such communication can occur, for example, via the radio frequency transceiver 968. Additionally, short-range communication can occur, such as using Bluetooth, WiFi, or other such transceivers (not shown). Additionally, the GPS (Global Positioning System) receiver module 970 can provide additional wireless data related to navigation and positioning to the device 950, which can be appropriately used by applications running on the device 950.

[0156] The device 950 can also use the audio codec 960 for audible communication, which can receive oral information from the user and convert the information into usable digital information. The audio codec 960 can also generate audible sounds for the user, such as through a speaker in the earpiece of the device 950, for example. Such sounds can include sounds from a voice telephone call, can include recorded sounds (e.g., voice messages, music files, etc.), and can also include sounds generated by applications operating on the device 950.

[0157] As shown in the drawings, the computing device 950 can be implemented in a variety of different forms. For example, it can be implemented as a cellular phone 980. It can also be implemented as part of a smart phone 982, a personal digital assistant, or other similar mobile devices.

[0158] Additionally, the computing device 900 or 950 can include a Universal Serial Bus (USB) flash drive. The USB flash drive can store the operating system and other applications. The USB flash drive can include input / output components, such as a wireless transmitter or a USB connector that can be inserted into a USB port of another computing device.

[0159] The various implementations of the systems and techniques described herein can be implemented in digital electronic circuitry, integrated circuit systems, specially designed ASICs (Application Specific Integrated Circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementations in one or more computer programs executable and / or interpretable on a programmable system including at least one programmable processor which may be special purpose or general purpose and coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0160] These computer programs (also referred to as programs, software, software applications, or code) include machine instructions for a programmable processor and can be implemented in high-level procedural and / or object-oriented programming languages and / or in assembly / machine language. As used herein, the term "machine-readable medium", "computer-readable medium" refers to any computer program product, apparatus, and / or device (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0161] For providing interaction with a user, the systems and techniques described herein can be implemented on a computer having a display device (e.g., a CRT (Cathode Ray Tube) or LCD (Liquid Crystal Display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0162] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or includes middleware components (e.g., an application server), or includes frontend components (e.g., a client computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), peer-to-peer networks (having ad-hoc or static members), grid computing infrastructures, and the Internet.

[0163] A computing system can include clients and servers. The clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0164] Although some implementations have been described in detail above, other modifications are possible. In addition, other mechanisms can be used for performing the systems and methods described in this document. Additionally, the logical flows depicted in the figures do not require the particular order shown, or sequential order, to achieve the desired result. Other steps can be provided, or steps can be deleted from the described flows, and other components can be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

Claims

1. A method of operating a display device including a pixel array, the method comprising: When the display device is operating at a first refresh rate, programming a first image content frame into the pixel array, including scanning the first image content frame line by line into the pixel array at a first scan rate, wherein the image content presented by the pixel array is refreshed at the first refresh rate; Activating the pixel array to present the first image content frame scanned into the pixel array at the first scan rate; Receiving an indication that the display device is to transition from the first refresh rate to a second refresh rate, wherein the image content presented by the pixel array is refreshed at the second refresh rate; In response to receiving the indication that the display device is to transition from the first refresh rate to the second refresh rate, programming an intermediate image content frame into the pixel array, including scanning the intermediate image content frame line by line into the pixel array at an intermediate scan rate that is between the first scan rate and the second scan rate; Activating the pixel array to present the intermediate image content frame scanned into the pixel array at the intermediate scan rate; After the display device has presented the intermediate image content frame and while the display device is operating at the second refresh rate, programming a second image content frame into the pixel array, including scanning the second image content frame line by line into the pixel array at the second scan rate; And Activating the pixel array to present the second image content frame scanned into the pixel array at the second scan rate.

2. The method according to claim 1, wherein: The first frame, the intermediate frame, and the second frame are frames in a frame sequence presented by the display device.

3. The method according to any one of claims 1 to 2, wherein: Scanning the first image content frame line by line into the pixel array at the first scan rate includes: (i) Scanning the first line of the first image content frame into the first line of the pixel array at a first time; and (ii) Scanning the second line of the first image content frame into the second line of the pixel array at a second time; and The difference between the first time and the second time is defined by the first scan rate.

4. The method according to any one of claims 1 to 3, wherein: The first refresh rate is lower than the second refresh rate; The first scan rate is lower than the intermediate scan rate; and The second scan rate is higher than the intermediate scan rate.

5. The method according to claim 4, wherein: The first refresh rate is a frequency between 60 Hz and 100 Hz; and The second refresh rate is twice the first refresh rate.

6. The method according to any one of claims 4 to 5, wherein: The display device presents the first image content frame having a first number of differential activations; and The display device presents the second image content frame having a second number of differential activations, the second number of differential activations being less than the first number of differential activations.

7. The method according to claim 6, wherein: the display device presents the intermediate image content frame having an intermediate number of refresh periods, the intermediate number of refresh periods being less than the first number of differential activations and more than the second number of differential activations.

8. The method according to claim 7, wherein: the first number of differential activations is four activations; the intermediate number of differential activations is three activations; and the second number of differential activations is two activations.

9. The method according to any one of claims 1 to 8, wherein: the display device presents a first line of the intermediate image content frame by activating a first line of the pixel array for a first amount of time; and the display device presents a second line of the intermediate image content frame by activating a second line of the pixel array for a second amount of time, the second amount of time being different from the first amount of time.

10. The method according to any one of claims 1 to 9, comprising: receiving an indication that the display device is to switch back from the second refresh rate to the first refresh rate; in response to receiving the indication that the display device is to switch back from the second refresh rate to the first refresh rate, programming additional intermediate image content frames into the pixel array, including scanning the additional intermediate image content frames line by line into the pixel array at the intermediate scan rate; activating the pixel array to present the additional intermediate image content frames scanned into the pixel array at the intermediate scan rate; when the display device is operating at the first refresh rate, programming additional first image content frames into the pixel array, including scanning the additional first image content frames line by line into the pixel array at the first scan rate; and activating the pixel array to present the additional first image content frames scanned into the pixel array at the first scan rate.

11. The method according to any one of claims 1 to 10, wherein: when the display device is operating at an intermediate refresh rate, the programming of the intermediate image content frames into the pixel array is performed, the intermediate refresh rate being between the first refresh rate and the second refresh rate.

12. The method according to any one of claims 1 to 11, wherein: before receiving the indication that the display device is to switch from the first refresh rate to the second refresh rate, the display device programs and presents a first series of at least one hundred image content frames at the first refresh rate, including programming and presenting the first image content frames; and after presenting the intermediate image content frames, the display device presents a second series of at least one hundred image content frames at the second refresh rate, including programming and presenting the second image content frames.

13. The method according to claim 12, wherein: the programming of the first series of at least one hundred image content frames includes scanning each of the first series of at least one hundred image content frames line by line into the pixel array at the first scan rate; and Programming the at least one hundred image content frames of the second series includes scanning each of the at least one hundred image content frames of the second series line by line into the pixel array at the second scan rate.

14. The method according to any one of claims 12 to 13, wherein: Programming the intermediate image content frame is to scan the only image content frame into the pixel array at the intermediate scan rate between when the display device presents the first image content frame and when the display device presents the second image content frame.

15. The method according to any one of claims 1 to 14, including after the display device presents the first image content frame and before the display device presents the second image content frame: Programming a second intermediate image content frame into the pixel array, including scanning the second intermediate image content frame line by line into the pixel array at a second intermediate scan rate between the first scan rate and the second scan rate; Activating the pixel array to present the second intermediate image content frame scanned into the pixel array at the second intermediate scan rate; Programming a third intermediate image content frame into the pixel array, including scanning the third intermediate image content frame line by line into the pixel array at a third intermediate scan rate between the first scan rate and the second scan rate; and Activating the pixel array to present the third intermediate image content frame scanned into the pixel array at the third intermediate scan rate.

16. The method according to claim 15, wherein: The intermediate scan rate, the second intermediate scan rate, and the third intermediate scan rate represent a series of different scan frequencies between the first scan rate and the second scan rate.

17. The method according to claim 16, wherein: The difference between the intermediate scan rate and the second intermediate scan rate is the same as the difference between the second intermediate scan rate and the third intermediate scan rate.

18. The method according to any one of claims 16 to 17, wherein: When the display device is operating at a first intermediate refresh rate, programming the intermediate image content frame into the pixel array, the first intermediate refresh rate being between the first refresh rate and the second refresh rate; When the display device is operating at a second intermediate refresh rate, programming the second intermediate image content frame into the pixel array, the second intermediate refresh rate being between the first refresh rate and the second refresh rate; and When the display device is operating at a third intermediate refresh rate, programming the third intermediate image content frame into the pixel array, the third intermediate refresh rate being between the first refresh rate and the second refresh rate.

19. The method according to any one of claims 1 to 18, including: Applying a first gamma value to the first image content frame, the first gamma value being the gamma value designated for the first refresh rate; Applying an intermediate gamma value to the intermediate image content frame; and applying a second gamma value to the second image content frame, the second gamma value being a gamma value designated for the second refresh rate.

20. A display system, comprising: a display device including a pixel array; and a circuit system configured to: when the display device is operating at a first refresh rate, program a first image content frame into the pixel array, including scanning the first image content frame line by line into the pixel array at a first scan rate, wherein the image content presented by the pixel array is refreshed at the first refresh rate; activate the pixel array to present the first image content frame scanned into the pixel array at the first scan rate; receive an indication that the display device is to transition from the first refresh rate to a second refresh rate, wherein the image content presented by the pixel array is refreshed at the second refresh rate; in response to receiving the indication that the display device is to transition from the first refresh rate to the second refresh rate, program an intermediate image content frame into the pixel array, including scanning the intermediate image content frame line by line into the pixel array at an intermediate scan rate that is between the first scan rate and a second scan rate; activate the pixel array to present the intermediate image content frame scanned into the pixel array at the intermediate scan rate; after the display device has presented the intermediate image content frame and when the display device is operating at the second refresh rate, program a second image content frame into the pixel array, including scanning the second image content frame line by line into the pixel array at the second scan rate; and activate the pixel array to present the second image content frame scanned into the pixel array at the second scan rate.

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