Display substrate and display device

Abstract

A display substrate and a display device, the display substrate including a plurality of light emission control signal lines (EM1, EM2, EM3), a plurality of power supply lines (VDD), and a plurality of sub-pixels, the sub-pixels including a sub-pixel driving circuit and a light emitting element; the sub-pixel driving circuit comprises a driving transistor (T3), a power supply control transistor (T5) and a light-emitting control transistor (T6); a first pole of the power supply control transistor (T5) is coupled with a corresponding power line (VDD), and a second pole of the power supply control transistor (T5) is coupled with a first pole of the driving transistor (T3); a first pole of the light-emitting control transistor (T6) is coupled with a second pole of the driving transistor (T3), and a second pole of the light-emitting control transistor (T6) is coupled with the light-emitting element; in the same sub-pixel driving circuit, a grid electrode of a power supply control transistor (T5) and a grid electrode of a light-emitting control transistor (T6) are coupled with different light-emitting control signal lines (EM1, EM2 and EM3); the light emission control signal lines (EM1, EM2, EM3) include at least two light emission control portions (EM11, EM12) arranged in a first direction, two adjacent light emission control portions (EM11, EM12) are coupled, and the two adjacent light emission control portions (EM11, EM12) are arranged in different layers.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and the display quality requirements of display products are also becoming increasingly higher. Currently, commonly used display products include active-matrix organic light-emitting diode (AMOLED) display products and liquid crystal display (LCD) products.

[0003] AMOLED display products typically include sub-pixel driver circuits and light-emitting elements. The sub-pixel driver circuits are used to drive the light-emitting elements to emit light, thereby achieving the display function of the display product. The structure and driving method of the sub-pixel driver circuits can both affect the display quality of the display product.

[0004] Summary of the Invention

[0005] An object of the present disclosure is to provide a display substrate and a display device.

[0006] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0007] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of light-emitting control signal lines, a plurality of power supply lines, and a plurality of sub-pixels, all disposed on the base substrate, the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element;

[0008] The sub-pixel driving circuit includes a driving transistor, a power control transistor, and a light emitting control transistor; a first electrode of the power control transistor is coupled to a corresponding power line, and a second electrode of the power control transistor is coupled to a first electrode of the driving transistor; a first electrode of the light emitting control transistor is coupled to a second electrode of the driving transistor, and a second electrode of the light emitting control transistor is coupled to the light emitting element;

[0009] In the same sub-pixel driving circuit, the gate of the power control transistor and the gate of the light-emitting control transistor are coupled to different light-emitting control signal lines; the light-emitting control signal line includes at least two light-emitting control parts arranged along a first direction, two adjacent light-emitting control parts are coupled, and the two adjacent light-emitting control parts are arranged in different layers.

[0010] Optionally, the plurality of light-emitting control signal lines include a plurality of first light-emitting control signal lines and a plurality of second light-emitting control signal lines;

[0011] In the same sub-pixel driving circuit, the gate of the power control transistor is coupled to the corresponding first light-emitting control signal line, and the gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line. At least part of the first light-emitting control signal line and at least part of the second light-emitting control signal line are located within the layout area of ​​the same sub-pixel driving circuit.

[0012] Optionally, at least a portion of the orthographic projection of the first light-emitting control signal line on the substrate is located between the orthographic projection of the gate of the power control transistor to which it is coupled on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate.

[0013] Optionally, the display substrate further includes a plurality of data lines and a plurality of second scan lines; the sub-pixel driving circuit further includes a data writing transistor, wherein a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0014] In a layout area of ​​the same sub-pixel driving circuit, the first light emitting control signal line, the second light emitting control signal line and the second scanning line are sequentially arranged along a second direction, and the second direction intersects the first direction.

[0015] Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor and the second electrode of the power control transistor are coupled to form a second node portion; the first electrode of the light emission control transistor and the second electrode of the driving transistor are coupled to form a third node portion;

[0016] The orthographic projection of the first light-emitting control signal line on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate; and / or, the orthographic projection of the first light-emitting control signal line on the base substrate at least partially overlaps with the orthographic projection of the third node portion on the base substrate; and / or, the orthographic projection of the second light-emitting control signal line on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate.

[0017] Optionally, the first light-emitting control signal line includes a plurality of first light-emitting control parts and a plurality of second light-emitting control parts, the first light-emitting control parts and the second light-emitting control parts are alternately arranged along a first direction, and adjacent first light-emitting control parts and second light-emitting control parts are coupled; the first light-emitting control part and the gate of the power control transistor are arranged in a different layer, and the second light-emitting control part and the gate of the power control transistor are arranged in the same layer, and the orthographic projection of the first light-emitting control part on the substrate at least partially overlaps with the orthographic projection of the second node portion on the substrate; and / or,

[0018] The orthographic projection of the first light emitting control portion on the base substrate at least partially overlaps with the orthographic projection of the third node portion on the base substrate; and / or,

[0019] The second light-emitting control signal line includes multiple third light-emitting control parts and multiple fourth light-emitting control parts, the third light-emitting control parts and the fourth light-emitting control parts are alternately arranged along the first direction, and the adjacent third light-emitting control parts are coupled; the third light-emitting control part and the gate of the power control transistor are arranged in a different layer, and the fourth light-emitting control part and the gate of the power control transistor are arranged in the same layer, and the orthographic projection of the third light-emitting control part on the substrate at least partially overlaps with the orthographic projection of the second node part on the substrate.

[0020] Optionally, the display substrate includes a first gate metal layer and a first source / drain metal layer stacked in sequence in a direction away from the base substrate;

[0021] The first light emitting control part and the third light emitting control part are provided in the same layer and material as the first source / drain metal layer; the second light emitting control part and the fourth light emitting control part are provided in the same layer and material as the first gate metal layer.

[0022] Optionally, the display substrate further includes a plurality of first scan lines; the sub-pixel driving circuit further includes a compensation transistor, wherein a gate of the compensation transistor is coupled to the corresponding first scan line, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor;

[0023] The compensation transistor includes a compensation active layer, wherein the compensation active layer includes two channel portions and conductor portions respectively coupled to the two channel portions;

[0024] The sub-pixel driving circuit also includes a shielding portion and a first conductive connecting portion; the orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the conductor portion on the base substrate; the first conductive connecting portion is coupled to the shielding portion and the power line respectively.

[0025] Optionally, the sub-pixel driving circuit also includes a storage capacitor, the first plate of the storage capacitor is coupled to the gate of the driving transistor; the first conductive connection portion is also coupled to the second plate of the storage capacitor and / or the first electrode of the power control transistor.

[0026] Optionally, the plurality of light-emitting control signal lines include a plurality of third light-emitting control signal lines;

[0027] In the same sub-pixel driving circuit, the gate of the light-emitting control transistor is coupled to the corresponding third light-emitting control signal line, at least part of the third light-emitting control signal line is located within the layout area of ​​the same sub-pixel driving circuit, and the gate of the power control transistor is coupled to the third light-emitting control signal line coupled to the gate of the light-emitting control transistor in the previous sub-pixel driving circuit adjacent along the second direction.

[0028] Optionally, the sub-pixel driving circuit also includes a second conductive connection portion, a first end of the second conductive connection portion is coupled to the gate of the power control transistor in the current sub-pixel driving circuit, and a second end of the second conductive connection portion is coupled to a third light-emitting control signal line coupled to the previous sub-pixel driving circuit adjacent to the current sub-pixel driving circuit along the second direction.

[0029] Optionally, the display substrate further includes a plurality of data lines and a plurality of second scan lines; the sub-pixel driving circuit further includes a data writing transistor, wherein a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0030] The second electrode of the data writing transistor, the first electrode of the driving transistor and the second electrode of the power control transistor are coupled to form a second node portion together; the orthographic projection of the third light-emitting control signal line on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate.

[0031] Optionally, the third light-emitting control signal line includes a plurality of fifth light-emitting control parts and a plurality of sixth light-emitting control parts, the fifth light-emitting control parts and the sixth light-emitting control parts are alternately arranged along the first direction, and the adjacent fifth light-emitting control parts and the sixth light-emitting control parts are coupled; the fifth light-emitting control part and the gate of the power control transistor are arranged in a different layer, and the sixth light-emitting control part and the gate of the power control transistor are arranged in the same layer, and the orthographic projection of the fifth light-emitting control part on the substrate at least partially overlaps with the orthographic projection of the second node portion on the substrate.

[0032] Optionally, the display substrate includes a first gate metal layer and a first source / drain metal layer stacked in sequence in a direction away from the base substrate;

[0033] The fifth light emitting control part is provided in the same layer and made of the same material as the first source-drain metal layer; and / or the second conductive connection part is provided in the same layer and made of the same material as the first source-drain metal layer.

[0034] Optionally, the display substrate further includes a plurality of first initialization signal lines and a plurality of first scan lines; the sub-pixel driving circuit further includes a compensation transistor, wherein a gate of the compensation transistor is coupled to the corresponding first scan line, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor;

[0035] The compensation transistor includes a compensation active layer, wherein the compensation active layer includes two channel portions and conductor portions respectively coupled to the two channel portions;

[0036] The sub-pixel driving circuit further includes a shielding portion coupled to the corresponding first initialization signal line; an orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the conductor portion on the base substrate.

[0037] Optionally, the sub-pixel driving circuit also includes a first conductive connection portion and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor; the first conductive connection portion is respectively coupled to the power line, the second plate of the storage capacitor, and the first electrode of the power control transistor.

[0038] Optionally, the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power line;

[0039] An orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the second node portion on the base substrate.

[0040] Optionally, an orthographic projection of the second electrode on the base substrate at least partially overlaps with an orthographic projection of a third node portion in the sub-pixel driving circuit on the base substrate.

[0041] Optionally, the first electrode plate includes a first electrode plate main portion and a first electrode plate protrusion; the second electrode plate includes a second electrode plate main portion and a second electrode plate protrusion;

[0042] The orthographic projection of the first electrode main body on the substrate at least partially overlaps with the orthographic projection of the second electrode main body on the substrate; the orthographic projection of the first electrode protrusion on the substrate at least partially overlaps with the orthographic projection of the second electrode protrusion on the substrate;

[0043] The orthographic projection of the second electrode protrusion on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate; and / or the orthographic projection of the second electrode protrusion on the base substrate at least partially overlaps with the orthographic projection of the third node portion on the base substrate.

[0044] Optionally, the display substrate includes a display area and a peripheral area located around the display area;

[0045] The display substrate further includes a plurality of first shift register units all located in the peripheral area;

[0046] In the same sub-pixel driving circuit, the second light-emitting control signal line coupled to the gate of the light-emitting control transistor is coupled to the corresponding first shift register unit, and the first light-emitting control signal line coupled to the gate of the power control transistor is coupled to the first shift register unit coupled to the gate of the light-emitting control transistor in the sub-pixel driving circuit adjacent along the second direction.

[0047] Optionally, the display substrate includes a display area and a peripheral area located around the display area;

[0048] The display substrate further includes a plurality of first shift register units and a plurality of second shift register units, all of which are located in the peripheral area, and the display area is located between the first shift register units and the second shift register units;

[0049] The first shift register unit is coupled to the corresponding first light emitting control signal line, and the second shift register unit is coupled to the corresponding second light emitting control signal line.

[0050] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0052] FIG1 is a schematic diagram of a first circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0053] FIG2 is a first timing diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0054] FIG3 is a second timing diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0055] FIG4 is a schematic diagram showing a display substrate provided with shift register units on both sides according to an embodiment of the present disclosure;

[0056] FIG5 is a schematic diagram of a second circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0057] FIG6 is a schematic diagram of a third circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0058] FIG7 is a schematic diagram of a fourth circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0059] FIG8 is a schematic diagram of a fifth circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0060] FIG9 is a schematic diagram of a sixth circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0061] FIG10 is a schematic cross-sectional view of a film layer provided in an embodiment of the present disclosure;

[0062] FIG11 is a schematic diagram of a first layout of an active layer provided in an embodiment of the present disclosure;

[0063] FIG12 is a schematic diagram of a first layout of a first gate metal layer provided in an embodiment of the present disclosure;

[0064] FIG13 is a schematic diagram of a first layout of an active layer and a first gate metal layer provided in an embodiment of the present disclosure;

[0065] FIG14 is a schematic diagram of a first layout of a second gate metal layer provided in an embodiment of the present disclosure;

[0066] FIG15 is a schematic diagram of a first layout with a second gate metal layer added on the basis of FIG13;

[0067] FIG16 is a schematic diagram of a first layout of a first source / drain metal layer provided in an embodiment of the present disclosure;

[0068] FIG17 is a schematic diagram of a first layout of vias included in an interlayer insulating layer provided by an embodiment of the present disclosure;

[0069] FIG18 is a schematic diagram of a first layout with a first source / drain metal layer added on the basis of FIG15 ;

[0070] FIG19 is a schematic diagram of a first layout of a second source / drain metal layer provided in an embodiment of the present disclosure;

[0071] FIG20 is a schematic diagram of a first layout of vias included in a first planar layer provided by an embodiment of the present disclosure;

[0072] FIG21 is a schematic diagram of a first layout with a second source / drain metal layer added on the basis of FIG18 ;

[0073] FIG22 is a schematic diagram of a first layout of a first gate metal layer, a second gate metal layer, and a first source / drain metal layer provided in an embodiment of the present disclosure;

[0074] FIG23 is a schematic diagram of a first layout of a first source-drain metal layer and a second source-drain metal layer provided in an embodiment of the present disclosure;

[0075] FIG24 is a schematic diagram of a second layout of an active layer provided in an embodiment of the present disclosure;

[0076] FIG25 is a schematic diagram of a second layout of the first gate metal layer provided in an embodiment of the present disclosure;

[0077] FIG26 is a schematic diagram of a second layout of the active layer and the first gate metal layer provided in an embodiment of the present disclosure;

[0078] FIG27 is a schematic diagram of a second layout of a second gate metal layer provided in an embodiment of the present disclosure;

[0079] FIG28 is a schematic diagram of a second layout with a second gate metal layer added based on FIG26 ;

[0080] FIG29 is a schematic diagram of a second layout of the first source / drain metal layer provided in an embodiment of the present disclosure;

[0081] FIG30 is a schematic diagram of a second layout of vias included in the interlayer insulating layer provided by an embodiment of the present disclosure;

[0082] FIG31 is a schematic diagram of a second layout with a first source / drain metal layer added on the basis of FIG28 ;

[0083] FIG32 is a schematic diagram of a second layout of a second source / drain metal layer provided in an embodiment of the present disclosure;

[0084] FIG33 is a schematic diagram of a second layout of the first gate metal layer, the second gate metal layer, and the first source / drain metal layer provided in an embodiment of the present disclosure;

[0085] FIG34 is a schematic diagram of a second layout of the first source-drain metal layer and the second source-drain metal layer provided in an embodiment of the present disclosure;

[0086] FIG35 is a second schematic diagram of the layout from the active layer to the second source-drain metal layer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0088] The specific structures of sub-pixel driving circuits used in display products vary greatly, and both the structure and driving method of the sub-pixel driving circuits can affect the display quality of the display products. This disclosure provides a display substrate that is compatible with sub-pixel driving circuits of various structures, effectively improving the display quality of display products.

[0089] Referring to FIG. 1 , FIG. 18 and FIG. 31 , an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of light-emitting control signal lines (e.g., a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, and a third light-emitting control signal line EM3), a plurality of power supply lines VDD, and a plurality of sub-pixels, each of which includes a sub-pixel driving circuit and a light-emitting element, all disposed on the base substrate;

[0090] The sub-pixel driving circuit includes a driving transistor T3, a power control transistor T5, and a light control transistor T6; a first electrode of the power control transistor T5 is coupled to a corresponding power line VDD, and a second electrode of the power control transistor T5 is coupled to a first electrode of the driving transistor T3; a first electrode of the light control transistor T6 is coupled to a second electrode of the driving transistor T3, and a second electrode of the light control transistor T6 is coupled to the light emitting element;

[0091] In the same sub-pixel driving circuit, the gate of the power control transistor T5 and the gate of the light-emitting control transistor T6 are coupled to different light-emitting control signal lines; the light-emitting control signal line includes at least two light-emitting control parts arranged along a first direction, two adjacent light-emitting control parts are coupled, and the two adjacent light-emitting control parts are arranged in different layers.

[0092] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0093] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0094] Exemplarily, the plurality of light-emission control signal lines are arranged along the second direction, the light-emission control signal lines include at least a portion extending along the first direction, and the light-emission control signal lines are used to transmit light-emission control signals. The plurality of power supply lines VDD are arranged along the first direction, the power supply lines VDD include at least a portion extending along the second direction. The plurality of power supply lines VDD correspond one-to-one with the plurality of columns of sub-pixel driver circuits, and the power supply lines VDD are respectively coupled to each sub-pixel driver circuit in a corresponding column of sub-pixel driver circuits, and the power supply lines VDD are used to transmit power signals.

[0095] Exemplarily, in the same sub-pixel driving circuit, the gate of the power control transistor T5 and the gate of the light emitting control transistor T6 are coupled to different light emitting control signal lines, and the gate of the power control transistor T5 and the gate of the light emitting control transistor T6 receive light emitting control signals provided by different light emitting control signal lines.

[0096] Exemplarily, the light-emission control signal line includes a plurality of light-emission control sections arranged sequentially along a first direction, with two adjacent light-emission control sections disposed in different layers and coupled to each other via vias. This arrangement allows some of the plurality of light-emission control sections to form an integrated structure with the gates of the transistors to which they are coupled, ensuring connection performance while reducing connection difficulty. Another portion of the light-emission control sections is disposed in a different layer from the gates of the transistors, thereby avoiding the formation of an additional abnormal transistor structure between the other portion of the light-emission control sections and the overlapping active layer, thereby ensuring operational stability of the sub-pixel drive circuit.

[0097] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, by coupling the gate of the power control transistor T5 and the gate of the light control transistor T6 in the same sub-pixel driving circuit to different light control signal lines, the power control transistor T5 and the light control transistor T6 in the same sub-pixel driving circuit can be independently controlled by different light control signal lines. In this way, the power control transistor T5 and the light control transistor T6 in the same sub-pixel driving circuit can be controlled to have the same or different conduction periods, depending on actual needs. In the display substrate provided by the embodiment of the present disclosure, when the power control transistor T5 in the same sub-pixel driving circuit is controlled to turn on before the light control transistor T6, the power signal transmitted by the power line VDD can be preferentially written to the first electrode of the driving transistor T3, which is conducive to improving the smear phenomenon.

[0098] In the display substrate provided by the embodiment of the present disclosure, the sub-pixel driving circuit is compatible with a variety of circuit structures including the power control transistor T5 and the light emission control transistor T6, such as: a 6T1C circuit structure (i.e., 6 transistors and 1 capacitor), a 7T1C circuit structure (i.e., 7 transistors and 1 capacitor), an 8T1C circuit structure (i.e., 8 transistors and 1 capacitor), a 9T1C circuit structure (i.e., 9 transistors and 1 capacitor), etc., but not limited thereto. In the display substrate provided by the embodiment of the present disclosure, by reasonably controlling the conduction time of the power control transistor T5 and the light emission control transistor T6 in the same sub-pixel driving circuit, the display quality of the display product can be effectively improved.

[0099] As shown in FIG. 11 to FIG. 23 , in some embodiments, the plurality of light emitting control signal lines include a plurality of first light emitting control signal lines EM1 and a plurality of second light emitting control signal lines EM2 ;

[0100] In the same sub-pixel driving circuit, the gate of the power control transistor T5 is coupled to the corresponding first light-emitting control signal line EM1, and the gate of the light-emitting control transistor T6 is coupled to the corresponding second light-emitting control signal line EM2. At least a portion of the first light-emitting control signal line EM1 and at least a portion of the second light-emitting control signal line EM2 are located in the layout area Q1 of the same sub-pixel driving circuit.

[0101] Exemplarily, the first emission control signal lines EM1 and the second emission control signal lines EM2 are alternately arranged along the second direction. The first emission control signal lines EM1 include at least a portion extending along the first direction. The second emission control signal lines EM2 include at least a portion extending along the first direction.

[0102] Illustratively, the plurality of first light-emitting control signal lines EM1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first light-emitting control signal lines EM1 are respectively coupled to the gates of the power control transistors T5 in the corresponding row of sub-pixel driving circuits. The plurality of second light-emitting control signal lines EM2 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second light-emitting control signal lines EM2 are respectively coupled to the gates of the light-emitting control transistors T6 in the corresponding row of sub-pixel driving circuits.

[0103] For example, the timings of the light emitting control signals transmitted by the first light emitting control signal line EM1 and the second light emitting control signal line EM2 coupled to the same sub-pixel driving circuit may be the same or different.

[0104] The above arrangement ensures that each row of sub-pixel driving circuits corresponds to a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2, and both the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are located within the layout area where the sub-pixel driving circuits in that row are located. This layout not only enables independent control of the power control transistor T5 and the light-emitting control transistor T6 in the same sub-pixel driving circuit, but also ensures that the power control transistor T5 is closer to the first light-emitting control signal line EM1 to which it is coupled, and that the light-emitting control transistor T6 is closer to the second light-emitting control signal line EM2 to which it is coupled, thereby reducing the layout difficulty of the display substrate.

[0105] As shown in FIG1 , in some embodiments, the display substrate includes a power line VDD, a data line DA, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line Rst, a first scan line GA1, a second scan line GA2, a first emission control signal line EM1, and a second emission control signal line EM2. The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, an emission control transistor T6, and a storage capacitor Cst.

[0106] The gate of the first reset transistor T1 is coupled to the corresponding reset signal line Rst, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g (i.e., the first node portion N1) of the driving transistor T3.

[0107] The gate of the compensation transistor T2 is coupled to the corresponding first scan line GA1 , the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3 , and the second electrode of the compensation transistor T2 is coupled to the gate T3 - g of the driving transistor T3 .

[0108] The gate of the data writing transistor T4 is coupled to the corresponding second scan line GA2 , the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 .

[0109] The gate of the power control transistor T5 is coupled to the corresponding first light emitting control signal line EM1, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0110] The gate of the light-emitting control transistor T6 is coupled to the corresponding second light-emitting control signal line EM2. The first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3. The second electrode of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element (i.e., the fourth node N4). The cathode of the light-emitting element receives the negative power supply signal VSS.

[0111] As shown in Figure 2, the working timing of the sub-pixel driving circuit is illustrated. In the figure, GA1 represents the signal transmitted by the first scan line GA1 connected to the sub-pixel driving circuit of this row, and GA1' represents the signal transmitted by the first scan line GA1 connected to the sub-pixel driving circuit of the previous row adjacent to this row. It can be seen from the figure that in the data writing stage, the second scan signal transmitted by the second scan line GA2 is at an effective level (such as a low level) to control the writing of the data signal. After the data writing stage is completed, the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 is first at an effective level (such as a low level) to write the power signal, and then the second light-emitting control signal transmitted by the second light-emitting control signal line EM2 is at an effective level (such as a low level) to control the light-emitting element to emit light, that is, enter the light-emitting stage.

[0112] Exemplarily, the compensation transistor T2 and the first reset transistor T1 may be driven by a shift register unit used to drive a light-emission control signal line, or a separate shift register unit specifically used to drive the compensation transistor T2 and the first reset transistor T1 may be provided. For example, when a separate shift register unit specifically used to drive the compensation transistor T2 and the first reset transistor T1 is used, in the n-th row sub-pixel driving circuit, the gate of the compensation transistor T2 is coupled to the corresponding shift register unit in the n-th row, and the first reset transistor T1 is coupled to the shift register unit in the (n-7)th row, but the present invention is not limited thereto.

[0113] As shown in Figures 12, 15 and 18, in some embodiments, at least a portion of the orthographic projection of the first light-emitting control signal line EM1 on the substrate is located between the orthographic projection of the gate T5-g of the power control transistor T5 coupled thereto on the substrate and the orthographic projection of the second light-emitting control signal line EM2 on the substrate.

[0114] As shown in Figures 11, 12 and 13, it should be noted that the orthographic projection of the gate T5-g of the power control transistor T5 on the substrate at least partially overlaps with the orthographic projection of the power control active layer 25 on the substrate, and the portion of the power control active layer 25 located in the overlapping area serves as the channel of the power control transistor T5.

[0115] Exemplarily, at least part of the orthographic projection of the first light emitting control signal line EM1 on the base substrate is located between the orthographic projection of the gate T3 - g of the driving transistor T3 on the base substrate and the orthographic projection of the second light emitting control signal line EM2 on the base substrate.

[0116] The above configuration enables the power control transistor T5 and the driving transistor T3 to be located on the same side of the first light emitting control signal line EM1, which is more conducive to achieving coupling between the power control transistor T5 and the driving transistor T3 and reducing the layout difficulty of the display substrate.

[0117] As shown in FIG18 , in some embodiments, the display substrate further includes a plurality of data lines DA and a plurality of second scan lines GA2; the sub-pixel driving circuit further includes a data writing transistor T4, wherein a gate of the data writing transistor T4 is coupled to the corresponding second scan line GA2, a first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3;

[0118] In the layout area of ​​the same sub-pixel driving circuit, the first light emitting control signal line EM1, the second light emitting control signal line EM2 and the second scanning line GA2 are sequentially arranged along a second direction, and the second direction intersects the first direction.

[0119] Exemplarily, the plurality of data lines DA are arranged along the first direction, and the data lines DA include at least a portion extending along the second direction. The plurality of data lines DA correspond one-to-one to the plurality of columns of sub-pixel driving circuits. Each data line DA is coupled to the first electrode of each data writing transistor T4 in the corresponding column of sub-pixel driving circuits.

[0120] Exemplarily, the plurality of second scan lines GA2 are arranged along the second direction, and the second scan lines GA2 include at least a portion extending along the first direction. The plurality of second scan lines GA2 correspond one-to-one to multiple rows of sub-pixel driver circuits. Each second scan line GA2 is coupled to the gate of each data write transistor T4 in a corresponding row of sub-pixel driver circuits.

[0121] In the display substrate provided by the above embodiment, by being arranged in the layout area of ​​the same sub-pixel driving circuit, the orthographic projection of the first light-emitting control signal line EM1 on the base substrate, the orthographic projection of the second light-emitting control signal line EM2 on the base substrate, and the orthographic projection of the second scanning line GA2 on the base substrate are arranged in sequence, which reasonably utilizes the limited layout space and reduces the difficulty of partial layout of the display substrate within the limited layout space.

[0122] As shown in FIG13 , FIG15 and FIG18 , in some embodiments, the second electrode of the data writing transistor T4, the first electrode of the driving transistor T3 and the second electrode of the power control transistor T5 are coupled to form a second node portion N2; the first electrode of the light emission control transistor T6 and the second electrode of the driving transistor T3 are coupled to form a third node portion N3.

[0123] The orthographic projection of the first light-emitting control signal line EM1 on the substrate at least partially overlaps with the orthographic projection of the second node portion N2 on the substrate; and / or, the orthographic projection of the first light-emitting control signal line EM1 on the substrate at least partially overlaps with the orthographic projection of the third node portion N3 on the substrate; and / or, the orthographic projection of the second light-emitting control signal line EM2 on the substrate at least partially overlaps with the orthographic projection of the second node portion on the substrate.

[0124] As shown in Figures 11 and 13, exemplarily, the second electrode of the data writing transistor T4, the first electrode of the driving transistor T3 and the second electrode of the power control transistor T5 are all arranged in the same layer and material as the active layer in the display substrate, and the second electrode of the data writing transistor T4, the first electrode of the driving transistor T3 and the second electrode of the power control transistor T5 form an integrated structure, together forming a second node portion N2.

[0125] Exemplarily, the first electrode of the light-emitting control transistor T6 and the second electrode of the driving transistor T3 are both provided in the same layer and the same material as the active layer in the display substrate, and the first electrode of the light-emitting control transistor T6 and the second electrode of the driving transistor T3 form an integrated structure, and together form a third node portion N3.

[0126] Exemplarily, an orthographic projection of the second light emitting control signal line EM2 on the base substrate does not overlap with an orthographic projection of the third node portion N3 on the base substrate.

[0127] Exemplarily, the first light-emitting control signal line EM1 includes a plurality of first light-emitting control parts EM11 and a plurality of second light-emitting control parts EM12, the first light-emitting control parts EM11 and the second light-emitting control parts EM12 are alternately arranged along a first direction, and adjacent first light-emitting control parts EM11 and second light-emitting control parts EM12 are coupled; the first light-emitting control part EM11 and the gate of the power control transistor T5 are arranged in a different layer, and the second light-emitting control part EM12 and the gate of the power control transistor T5 are arranged in the same layer, and the orthographic projection of the first light-emitting control part EM11 on the substrate at least partially overlaps with the orthographic projection of the second node portion on the substrate.

[0128] Exemplarily, an orthographic projection of the first light emitting control portion EM11 on the base substrate at least partially overlaps with an orthographic projection of the third node portion N3 on the base substrate.

[0129] Exemplarily, the second light-emitting control signal line EM2 includes a plurality of third light-emitting control parts EM21 and a plurality of fourth light-emitting control parts EM22, the third light-emitting control parts EM21 and the fourth light-emitting control parts EM22 are alternately arranged along a first direction, and the adjacent third light-emitting control parts EM21 and the fourth light-emitting control parts EM22 are coupled; the third light-emitting control parts EM21 and the gate of the power control transistor T5 are arranged in a different layer, the fourth light-emitting control parts EM22 and the gate of the power control transistor T5 are arranged in the same layer, and the orthographic projection of the third light-emitting control part EM21 on the substrate at least partially overlaps with the orthographic projection of the second node portion on the substrate.

[0130] This arrangement effectively utilizes limited layout space, reducing the difficulty of partially arranging the display substrate within this limited layout space. Furthermore, this arrangement avoids the formation of additional transistor structures between the first and second emission control signal lines EM1 and EM2 and the second and third node portions, thereby ensuring operational stability of the sub-pixel driver circuit.

[0131] In some embodiments, the display substrate includes a first gate metal layer and a first source / drain metal layer stacked in sequence in a direction away from the base substrate;

[0132] As shown in Figures 12 and 16, the first light emitting control part EM11 and the third light emitting control part EM21 are arranged in the same layer and material as the first source and drain metal layer; the second light emitting control part EM12 and the fourth light emitting control part EM22 are arranged in the same layer and material as the first gate metal layer.

[0133] As shown in FIG10 , the display substrate exemplarily includes a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include a passivation layer PVX, but is not limited thereto.

[0134] In the display substrate provided by the above embodiment, by arranging the first light-emitting control part EM11 and the third light-emitting control part EM21 to be in the same layer and material as the first source-drain metal layer, the first light-emitting control part EM11 and the third light-emitting control part EM21 can be formed simultaneously with the first source-drain metal layer in the same patterning process, thereby avoiding the addition of additional patterning processes and simplifying the manufacturing process flow of the display substrate.

[0135] In the display substrate provided by the above embodiment, by setting the second light-emitting control part EM12 and the fourth light-emitting control part EM22 to the same layer and the same material as the first gate metal layer, the second light-emitting control part EM12 and the fourth light-emitting control part EM22 can be formed simultaneously with the first gate metal layer in the same composition process, avoiding the addition of additional composition processes and simplifying the manufacturing process flow of the display substrate.

[0136] As shown in Figures 11, 13, 15, 16, and 18 to 23, in some embodiments, the display substrate further includes a plurality of first scan lines GA1; the sub-pixel driving circuit further includes a compensation transistor T2, wherein a gate of the compensation transistor T2 is coupled to the corresponding first scan line GA1, a first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and a second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3;

[0137] The compensation transistor T2 includes a compensation active layer 22 , wherein the compensation active layer 22 includes two channel portions 221 and a conductor portion 222 respectively coupled to the two channel portions 221 ;

[0138] The sub-pixel driving circuit further includes a shielding portion 30 and a first conductive connecting portion 41; the orthographic projection of the shielding portion 30 on the base substrate at least partially overlaps with the orthographic projection of the conductor portion 222 on the base substrate; the first conductive connecting portion 41 is coupled to the shielding portion 30 and the power line VDD, respectively.

[0139] Exemplarily, the plurality of first scan lines GA1 are arranged along the second direction, and the first scan lines GA1 include at least a portion extending along the first direction. The plurality of first scan lines GA1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first scan lines GA1 are respectively coupled to the gates of the compensation transistors T2 in the corresponding row of sub-pixel driving circuits.

[0140] Exemplarily, the compensation transistor T2 comprises a dual-gate transistor. The compensation transistor T2 includes a compensation active layer 22, which comprises two channel portions and a conductor portion coupled to the two channel portions. The compensation active layer 22 is also used to form a first electrode and a second electrode of the compensation transistor T2. The orthographic projection of the channel portion on the substrate overlaps with the orthographic projection of the gate of the compensation transistor T2 on the substrate, while the orthographic projection of the conductor portion on the substrate does not overlap with the orthographic projection of the gate of the compensation transistor T2 on the substrate.

[0141] Exemplarily, the shielding portion 30 is provided in the same layer and material as the second gate metal layer, and the first conductive connecting portion is provided in the same layer and material as the first source / drain metal layer.

[0142] In the display substrate provided in the above embodiment, by setting the first conductive connection portion to be coupled to the shielding portion 30 and the power line VDD respectively, the shielding portion 30 has the same stable potential as the power signal, and the orthographic projection of the shielding portion 30 on the base substrate is set to at least partially overlap with the orthographic projection of the conductor portion on the base substrate, which can effectively shield the conductor portion from external interference, ensure the characteristics of the compensation transistor T2, and thus well ensure the operating stability of the display substrate.

[0143] As shown in Figures 11, 13, 15, 16, and 18 to 23, in some embodiments, the sub-pixel driving circuit also includes a storage capacitor Cst, and the first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor T3; the first conductive connection portion 41 is also coupled to the second plate Cst2 of the storage capacitor Cst and / or the first electrode of the power control transistor T5.

[0144] Exemplarily, the first plate Cst1 of the storage capacitor Cst is reused as the gate T3-g of the driving transistor T3. The second plate Cst2 of the storage capacitor Cst is provided in the same layer and material as the second gate metal layer.

[0145] The above-mentioned arrangement of the first conductive connecting portion 41, which is respectively coupled to the second plate Cst2 of the storage capacitor Cst, the first electrode of the power control transistor T5, the shielding portion 30 and the power line VDD, effectively reduces the complexity of the sub-pixel driving circuit, reduces the layout space occupied by the sub-pixel driving circuit, and reduces the layout difficulty of the display substrate.

[0146] As shown in FIG. 24 to FIG. 35 , in some embodiments, the plurality of light emitting control signal lines include a plurality of third light emitting control signal lines EM3 ​​;

[0147] In the same sub-pixel driving circuit, the gate of the light-emitting control transistor T6 is coupled to the corresponding third light-emitting control signal line EM3, and at least a portion of the third light-emitting control signal line EM3 is located within the layout area Q1 of the same sub-pixel driving circuit. The gate of the power control transistor T5 is coupled to the third light-emitting control signal line EM3 coupled to the gate of the light-emitting control transistor T6 in the previous sub-pixel driving circuit adjacent along the second direction.

[0148] Exemplarily, the plurality of third emission control signal lines EM3 ​​are arranged along the second direction, and the third emission control signal lines EM3 ​​include at least a portion extending along the first direction. The plurality of third emission control signal lines EM3 ​​correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the third emission control signal lines EM3 ​​are respectively coupled to the gates of the emission control transistors T6 in the corresponding row of sub-pixel driving circuits.

[0149] Exemplarily, at least a portion of the third light emitting control signal line EM3 is located within a layout area where a corresponding row of sub-pixel driving circuits are located.

[0150] Exemplarily, the gate of the power control transistor T5 in the current sub-pixel driving circuit is coupled to the third light emitting control signal line EM3 coupled to the gate of the light emitting control transistor T6 in the previous sub-pixel driving circuit adjacent along the second direction.

[0151] In the display substrate provided by the above embodiment, only one third emission control signal line EM3 is arranged within the layout area where each row of sub-pixel driver circuits resides, reducing the layout complexity within the sub-pixel driver circuit layout area. Furthermore, the above arrangement enables the emission control transistor T6 and the power control transistor T5 in the same sub-pixel driver circuit to be controlled by different third emission control signal lines EM3, thereby achieving independent control of the power control transistor T5 and the emission control transistor T6 in the same sub-pixel driver circuit.

[0152] As shown in Figures 28, 29, 31 and 33, in some embodiments, the sub-pixel driving circuit also includes a second conductive connection portion 42, a first end of the second conductive connection portion 42 is coupled to the gate of the power control transistor T5 in the current sub-pixel driving circuit, and a second end of the second conductive connection portion 42 is coupled to the third light-emitting control signal line EM3 coupled to the previous sub-pixel driving circuit adjacent to the current sub-pixel driving circuit along the second direction.

[0153] Exemplarily, the second conductive connection portion 42 includes at least a portion extending along the second direction.

[0154] Exemplarily, the second conductive connection portion 42 and the data line DA are provided in different layers. The orthographic projection of the second conductive connection portion 42 on the base substrate at least partially overlaps with the orthographic projection of the data line DA on the base substrate.

[0155] In the display substrate provided by the above embodiment, by setting the second conductive connection portion 42, the gate of the power control transistor T5 in the current sub-pixel driving circuit is coupled to the third light-emitting control signal line EM3 coupled to the gate of the light-emitting control transistor T6 in the previous sub-pixel driving circuit adjacent along the second direction. By setting the orthographic projection of the second conductive connection portion 42 on the base substrate to at least partially overlap with the orthographic projection of the data line DA on the base substrate, the additional layout space occupied by the second conductive connection portion 42 can be reduced, which is conducive to reducing the layout difficulty of the display substrate.

[0156] As shown in FIG24 to FIG34 , in some embodiments, the display substrate further includes a plurality of data lines DA and a plurality of second scan lines GA2; the sub-pixel driving circuit further includes a data writing transistor T4, wherein a gate of the data writing transistor T4 is coupled to the corresponding second scan line GA2, a first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3;

[0157] The second electrode of the data writing transistor T4, the first electrode of the driving transistor T3 and the second electrode of the power control transistor T5 are coupled to jointly form a second node portion N2; the orthographic projection of the third light-emitting control signal line EM3 on the substrate at least partially overlaps with the orthographic projection of the second node portion N2 on the substrate.

[0158] Exemplarily, the third light-emitting control signal line EM3 includes a plurality of fifth light-emitting control parts EM31 and a plurality of sixth light-emitting control parts EM32, the fifth light-emitting control parts EM31 and the sixth light-emitting control parts EM32 are alternately arranged along the first direction, and the adjacent fifth light-emitting control parts EM31 and the sixth light-emitting control parts EM32 are coupled; the fifth light-emitting control part EM31 and the gate of the power control transistor T5 are arranged on a different layer, the sixth light-emitting control part EM32 and the gate of the power control transistor T5 are arranged on the same layer, and the orthographic projection of the fifth light-emitting control part EM31 on the substrate at least partially overlaps with the orthographic projection of the second node part N2 on the substrate.

[0159] The above arrangement rationally utilizes limited layout space, reducing the difficulty of partial layout of the display substrate within the limited layout space. Furthermore, the above arrangement avoids the formation of additional transistor structures between the third light-emitting control signal line EM3 and the second and third node portions N2 and N3, thereby ensuring the stability of the sub-pixel driving circuit.

[0160] As shown in FIG33 , in some embodiments, the display substrate includes a first gate metal layer and a first source / drain metal layer stacked in sequence in a direction away from the base substrate;

[0161] The fifth light emitting control portion EM31 is provided in the same layer and made of the same material as the first source / drain metal layer; and / or the second conductive connection portion is provided in the same layer and made of the same material as the first source / drain metal layer.

[0162] In the display substrate provided by the above embodiment, by setting the fifth light-emitting control part EM31 to the same layer and material as the first source-drain metal layer, the fifth light-emitting control part EM31 can be formed simultaneously with the first source-drain metal layer in the same patterning process, avoiding the addition of additional patterning processes and simplifying the manufacturing process flow of the display substrate.

[0163] In the display substrate provided by the above embodiment, by setting the second conductive connection part and the first source-drain metal layer in the same layer and material, the second conductive connection part can be formed simultaneously with the first source-drain metal layer in the same composition process, avoiding the addition of additional composition processes and simplifying the manufacturing process flow of the display substrate.

[0164] As shown in FIG24 , FIG31 and FIG33 , in some embodiments, the display substrate further includes a plurality of first initialization signal lines Vinit1 and a plurality of first scan lines GA1; the sub-pixel driving circuit further includes a compensation transistor T2, wherein a gate of the compensation transistor T2 is coupled to the corresponding first scan line GA1, a first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and a second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3;

[0165] The compensation transistor T2 includes a compensation active layer 22 , wherein the compensation active layer 22 includes two channel portions 221 and a conductor portion 222 respectively coupled to the two channel portions 221 ;

[0166] The sub-pixel driving circuit further includes a shielding portion 30 coupled to the corresponding first initialization signal line Vinit1; an orthographic projection of the shielding portion 30 on the base substrate at least partially overlaps with an orthographic projection of the conductor portion on the base substrate.

[0167] Exemplarily, the plurality of first initialization signal lines Vinit1 are arranged along the second direction, and the first initialization signal line Vinit1 includes at least a portion extending along the first direction. The plurality of first initialization signal lines Vinit1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first initialization signal line Vinit1 is respectively coupled to the first electrode of each first reset transistor T1 in a corresponding row of sub-pixel driving circuits.

[0168] Exemplarily, the first reset transistor T1 comprises a dual-gate transistor, including a first reset active layer comprising two channel portions and a conductor portion coupled to the two channel portions. The orthographic projection of the second initialization signal line Vinit2 in the display substrate on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate. This configuration can better protect the first reset transistor T1 from external interference, thereby ensuring the characteristics of the first reset transistor T1.

[0169] Exemplarily, as shown in Figures 22 and 33, the display substrate also includes a compensation initialization signal line Vinit2', and the compensation initialization signal line Vinit2' includes at least a portion extending along the second direction. The compensation initialization signal line Vinit2' is coupled to at least a portion of the second initialization signal line Vinit2, and can form a grid structure with at least a portion of the second initialization signal line Vinit2, which is beneficial to improving the uniformity of the second initialization signal line Vinit2 and reducing the loading of the second initialization signal line Vinit2.

[0170] Exemplarily, the shielding portion 30 and the corresponding first initialization signal line Vinit1 form an integrated structure.

[0171] In the display substrate provided by the above embodiment, the shielding portion 30 is coupled to the corresponding first initialization signal line Vinit1, so that the shielding portion 30 has the same stable potential as the first initialization signal, and the orthographic projection of the shielding portion 30 on the base substrate is set to at least partially overlap with the orthographic projection of the conductor portion on the base substrate, which can effectively shield the external interference to the conductor portion, ensure the characteristics of the compensation transistor T2, and thus well ensure the working stability of the display substrate.

[0172] As shown in Figures 28 to 34, in some embodiments, the sub-pixel driving circuit also includes a first conductive connection portion 41 and a storage capacitor Cst; the first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor T3; the first conductive connection portion 41 is respectively coupled to the power line VDD, the second plate Cst2 of the storage capacitor Cst, and the first electrode of the power control transistor T5.

[0173] The above-mentioned arrangement of the first conductive connection portion 41 is respectively coupled to the second plate Cst2 of the storage capacitor Cst, the first electrode of the power control transistor T5 and the power line VDD, thereby effectively reducing the complexity of the sub-pixel driving circuit, reducing the layout space occupied by the sub-pixel driving circuit, and reducing the layout difficulty of the display substrate.

[0174] As shown in Figures 12 to 18 and Figures 28 to 34, in some embodiments, the sub-pixel driving circuit further includes a storage capacitor Cst, a first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor T3, and a second plate Cst2 of the storage capacitor Cst is coupled to the power line VDD; the orthographic projection of the second plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the second node portion N2 on the substrate.

[0175] Since the second plate Cst2 of the storage capacitor Cst has the same stable potential as the power signal, the above configuration enables the second plate Cst2 to shield the interference of peripheral signals on the second node portion N2, thereby ensuring the stability of the second node portion N2.

[0176] As shown in Figures 12 to 18 and Figures 28 to 34, in some embodiments, the orthographic projection of the second electrode Cst2 on the base substrate at least partially overlaps with the orthographic projection of the third node portion N3 in the sub-pixel driving circuit on the base substrate.

[0177] Since the second plate Cst2 of the storage capacitor Cst has the same stable potential as the power signal, the above configuration enables the second plate Cst2 to shield the interference of peripheral signals on the third node portion N3, thereby ensuring the stability of the third node portion N3.

[0178] As shown in FIG12 to FIG18 and FIG28 to FIG34, in some embodiments, the first electrode plate Cst1 includes a first electrode plate body portion Cst11 and a first electrode plate protrusion portion Cst12; the second electrode plate Cst2 includes a second electrode plate body portion Cst21 and a second electrode plate protrusion portion Cst22;

[0179] The orthographic projection of the first electrode main portion Cst11 on the base substrate at least partially overlaps with the orthographic projection of the second electrode main portion Cst21 on the base substrate; the orthographic projection of the first electrode protrusion Cst12 on the base substrate at least partially overlaps with the orthographic projection of the second electrode protrusion Cst22 on the base substrate;

[0180] The orthographic projection of the second electrode protrusion Cst22 on the base substrate at least partially overlaps with the orthographic projection of the second node portion N2 on the base substrate; and / or the orthographic projection of the second electrode protrusion Cst22 on the base substrate at least partially overlaps with the orthographic projection of the third node portion N3 on the base substrate.

[0181] The above-mentioned setting that the orthographic projection of the first electrode protrusion Cst12 on the base substrate and the orthographic projection of the second electrode protrusion Cst22 on the base substrate at least partially overlap increases the capacitance value of the storage capacitor Cst, which is beneficial to improving the driving performance of the sub-pixel driving circuit.

[0182] The above configuration can effectively shield the interference of peripheral signals on the second node portion N2 and the third node portion N3, thereby ensuring the stability of the third node portion N3.

[0183] In some embodiments, the display substrate includes a display area and a peripheral area located around the display area;

[0184] The display substrate further includes a plurality of first shift register units all located in the peripheral area;

[0185] In the same sub-pixel driving circuit, the second light-emitting control signal line EM2 coupled to the gate of the light-emitting control transistor T6 is coupled to the corresponding first shift register unit, and the first light-emitting control signal line EM1 coupled to the gate of the power control transistor T5 is coupled to the first shift register unit coupled to the gate of the light-emitting control transistor T6 in the sub-pixel driving circuit adjacent along the second direction.

[0186] Exemplarily, the peripheral area surrounds the display area, but is not limited thereto.

[0187] Exemplarily, the plurality of first shift register units are disposed only in a peripheral area on the left or right side of the display substrate, but the present invention is not limited thereto.

[0188] Exemplarily, the second light-emitting control signal line EM2 coupled to the gate of the light-emitting control transistor T6 is coupled to the corresponding first shift register unit in the peripheral area. The first light-emitting control signal line EM1 coupled to the gate of the power control transistor T5 is coupled to the first shift register unit coupled to the gate of the light-emitting control transistor T6 in the adjacent sub-pixel driving circuit along the second direction in the peripheral area.

[0189] In the display substrate provided in the above embodiment, the display substrate is provided to include a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2, the second light-emitting control signal line EM2 is coupled to the first shift register unit corresponding to the sub-pixel driving circuit of the current row coupled thereto, and the first light-emitting control signal line EM1 is coupled to the first shift register unit corresponding to the sub-pixel driving circuit of the previous row adjacent to the sub-pixel driving circuit of the current row coupled thereto along the second direction.

[0190] In the display substrate provided in the above embodiment, the display substrate may include a first compensation shift register unit, so that the first light emitting control signal line EM1 coupled to the first row of sub-pixel driving circuits may be coupled to the first compensation shift register unit.

[0191] In some embodiments, the display substrate includes a display area and a peripheral area located around the display area;

[0192] The display substrate further includes a plurality of first shift register units and a plurality of second shift register units, all of which are located in the peripheral area, and the display area is located between the first shift register units and the second shift register units;

[0193] The first shift register unit is coupled to the corresponding first light emitting control signal line EM1 , and the second shift register unit is coupled to the corresponding second light emitting control signal line EM2 .

[0194] Exemplarily, the plurality of first shift register units are located in a peripheral area on the left side of the display substrate, and the plurality of second shift register units are located in a peripheral area on the right side of the display substrate, but the present invention is not limited thereto.

[0195] Exemplarily, the plurality of first shift register units correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the plurality of second shift register units correspond one-to-one to the plurality of rows of sub-pixel driving circuits.

[0196] Exemplarily, the first shift register unit is controlled by a first clock signal line CK1 and a second clock signal line CK2, and the second shift register unit is controlled by a third clock signal line CK3 and a fourth clock signal line CK4.

[0197] It should be noted that FIG4 illustrates the first row of sub-pixel driving circuits Row_1 to the 3000th row of sub-pixel driving circuits Row_3000 in the display substrate. It also illustrates a plurality of first shift register units (i.e., EL1 to EL3000) located on the left side of the display area. It also illustrates a plurality of second shift register units (i.e., ER1 to EL3000) located on the right side of the display area.

[0198] In the display substrate provided in the above embodiment, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are each driven unilaterally and independently controlled by two groups of shift register units (i.e., a plurality of first shift register units as one group, and a plurality of second shift register units as another group). This approach better utilizes the layout space in the peripheral area of ​​the display substrate and better implements the drive of the light-emitting control signal lines. More specifically, as shown in Figure 3, the first light-emitting control signal line EM1 is driven by the first shift register unit to which it is coupled, and the second light-emitting control signal line EM2 is driven by the second shift register unit to which it is coupled. The figure illustrates the timing of the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 and the timing of the second light-emitting control signal transmitted by the second light-emitting control signal line EM2.

[0199] In some embodiments, the first light-emitting control signal line is formed as an integral structure; and / or the second light-emitting control signal line is formed as an integral structure.

[0200] Exemplarily, the first light-emitting control signal line and / or the second light-emitting control signal line are made of a single film layer. For example, the first light-emitting control signal line and / or the second light-emitting control signal line are provided in the same layer and material as the first gate metal layer, but the present invention is not limited thereto.

[0201] In the above-mentioned arrangement, the first light-emitting control signal line and / or the second light-emitting control signal line do not require a conversion film layer in the display area, thereby avoiding the production of vias for the conversion film layer in the display area, thereby reducing the difficulty of layout of the display substrate in a limited space, and is conducive to improving the resolution of the display substrate.

[0202] As shown in FIG5 and FIG6 , in some embodiments, the first light emitting control signal line is provided in the same layer and made of the same material as the first gate metal layer included in the display substrate;

[0203] The first light emitting control signal line EM1 and the third node portion N3 form a first transmission transistor T9, the first light emitting control signal line EM1 is multiplexed as a gate of the first transmission transistor T9, a first electrode of the first transmission transistor T9 is coupled to the second electrode of the driving transistor T3, and a second electrode of the first transmission transistor T9 is coupled to the first electrode of the light emitting control transistor T6; and / or,

[0204] The first light-emitting control signal line EM1 and the second node portion N2 form a second transmission transistor T8, and the first light-emitting control signal line EM1 is multiplexed as the gate of the second transmission transistor T8. The first electrode of the second transmission transistor T8 is coupled to the second electrode of the power control transistor T5, and the second electrode of the second transmission transistor T8 is coupled to the first electrode of the driving transistor T3 and the second electrode of the data writing transistor T4 respectively.

[0205] In the display substrate provided in the above embodiment, the first emission control signal line EM1 is provided in the same layer and material as the first gate metal layer, eliminating the need for a conversion film layer within the display area. This avoids the need for fabricating vias for the conversion film layer within the display area, thereby reducing the layout difficulty of the display substrate within a limited space and facilitating improved resolution of the display substrate. In the display substrate provided in the above embodiment, the first emission control signal line EM1 is provided in the same layer and material as the first gate metal layer, thereby forming an additional first transfer transistor T9 between the first emission control signal line EM1 and the third node portion N3, and / or forming an additional first transfer transistor T9 between the first emission control signal line EM1 and the second node portion N2. This additional transistor does not affect the normal driving of the sub-pixel driver circuit.

[0206] As shown in FIG7 and FIG8 , in some embodiments, the second light emitting control signal line EM2 is provided in the same layer and the same material as the first gate metal layer included in the display substrate;

[0207] The second light-emitting control signal line EM2 and the second node portion N2 form a third transmission transistor T10, the second light-emitting control signal line EM2 is multiplexed as a gate of the third transmission transistor T10, a first electrode of the third transmission transistor T10 is coupled to the second electrode of the power control transistor T5, and a second electrode of the third transmission transistor T10 is coupled to the first electrode of the driving transistor T3 and the second electrode of the data writing transistor T4 respectively; and / or,

[0208] The second light-emitting control signal line EM2 and the third node portion N3 form a fourth transmission transistor T11, and the second light-emitting control signal line EM2 is multiplexed as the gate of the fourth transmission transistor T11. The first electrode of the fourth transmission transistor T11 is coupled to the second electrode of the driving transistor T3, and the second electrode of the fourth transmission transistor T11 is coupled to the first electrode of the light-emitting control transistor T6.

[0209] As shown in FIG9 , in some embodiments, the first light emitting control signal line EM1 and the second light emitting control signal line EM2 are both provided in the same layer and the same material as the first gate metal layer;

[0210] The second light-emitting control signal line EM2 and the second node portion N2 form a third transmission transistor T10, the second light-emitting control signal line EM2 is multiplexed as a gate of the third transmission transistor T10, a first electrode of the third transmission transistor T10 is coupled to the second electrode of the power control transistor T5, and a second electrode of the third transmission transistor T10 is coupled to the first electrode of the driving transistor T3 and the second electrode of the data writing transistor T4 respectively; and / or,

[0211] The first light-emitting control signal line EM1 and the third node portion N3 form a first transmission transistor T9, and the first light-emitting control signal line EM1 is multiplexed as the gate of the first transmission transistor T9. The first electrode of the first transmission transistor T9 is coupled to the second electrode of the driving transistor T3, and the second electrode of the first transmission transistor T9 is coupled to the first electrode of the light-emitting control transistor T6.

[0212] As shown in Figures 11 and 24, the figures illustrate the first reset active layer 21 included in the first reset transistor T1, the compensation active layer 22 included in the compensation transistor T2, the driving active layer 23 included in the driving transistor T3, the data writing active layer 24 included in the data writing transistor T4, the power control active layer 25 included in the power control transistor T5, the light emitting control active layer 26 included in the light emitting control transistor T6, and the second reset active layer 27 included in the second reset transistor T7.

[0213] As shown in Figures 16 to 20, the first conductive connection part 41 is coupled to the second plate Cst2 of the storage capacitor Cst through the sixth via Via6 and the eighth via Via8, the first conductive connection part 41 is coupled to the shielding part 30 through the second via Via2, the first conductive connection part 41 is coupled to the first electrode of the power control transistor T5 through the ninth via Via9, and the first conductive connection part 41 is coupled to the power line VDD through the eighteenth via Via18.

[0214] As shown in FIG. 16 to FIG. 20 , the third conductive connection portion 43 is coupled to the first initialization signal line Vinit1 through the fourth via Via4 , and the third conductive connection portion 43 is coupled to the first electrode of the first reset transistor T1 through the fifth via Via5 .

[0215] As shown in Figures 16 to 20, the fifth conductive connection portion 45 is coupled to the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2 through the third via Via3, and the fifth conductive connection portion 45 is coupled to the gate T3-g of the driving transistor T3 through the seventh via Via7.

[0216] As shown in Figures 16 to 20, the sixth conductive connection part 46 is coupled to the second electrode of the light-emitting control transistor T6 and the second electrode of the second reset transistor T7 through the twelfth via Via12, the sixth conductive connection part 46 is coupled to the ninth conductive connection part 49 through the nineteenth via Via19, and the ninth conductive connection part 49 is coupled to the anode of the light-emitting element.

[0217] As shown in FIG. 16 to FIG. 20 , the seventh conductive connection portion 47 is coupled to the first electrode of the second reset transistor T7 through the thirteenth via hole Via13 , and the seventh conductive connection portion 47 is coupled to the second initialization signal line Vinit2 through the fourteenth via hole Via14 .

[0218] As shown in FIG. 16 to FIG. 20 , the eighth conductive connection portion 48 is coupled to the first electrode of the data writing transistor T4 through the seventeenth via hole Via17 , and the eighth conductive connection portion 48 is coupled to the data line DA through the twentieth via hole Via20 .

[0219] As shown in FIG. 16 to FIG. 20 , the first light emission control part EM11 is coupled to the second light emission control part EM12 on one side through the tenth via hole Via10 , and is also coupled to the second light emission control part EM12 on the other side through the eleventh via hole Via11 .

[0220] As shown in FIG. 16 to FIG. 20 , the third light emitting control part EM21 is coupled to the fourth light emitting control part EM22 on one side through the fifteenth via hole Via15 , and is also coupled to the fourth light emitting control part EM22 on the other side through the sixteenth via hole Via16 .

[0221] As shown in Figures 29 to 34, the second conductive connection part 42 is coupled to the gate of the power control transistor T5 through the twenty-second via Via22, and the second conductive connection part 42 is coupled to the sixth light-emitting control part EM32 through the twenty-fourth via Via24. The second conductive connection part 42 and the fifth light-emitting control part EM31 form an integrated structure.

[0222] As shown in FIG. 29 to FIG. 34 , the fifth light emitting control part EM31 is coupled to the sixth light emitting control part EM32 through the twenty-third via hole Via23 .

[0223] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0224] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0225] In the display substrate provided by the above embodiment, by coupling the gate of the power control transistor and the gate of the emission control transistor in the same sub-pixel driving circuit to different emission control signal lines, the power control transistor and the emission control transistor in the same sub-pixel driving circuit can be independently controlled by different emission control signal lines. This allows the power control transistor and the emission control transistor in the same sub-pixel driving circuit to be controlled to have identical or different conduction periods, depending on actual needs. In the display substrate provided by the above embodiment, when the power control transistor in the same sub-pixel driving circuit is controlled to turn on before the emission control transistor, the power signal transmitted by the power line can be preferentially written to the first electrode of the driving transistor, which is beneficial for improving the smear phenomenon. In the display substrate provided by the above embodiment, the sub-pixel driving circuit is compatible with various circuit structures including the power control transistor and the emission control transistor. In the display substrate provided by the above embodiment, by rationally controlling the conduction time of the power control transistor and the emission control transistor in the same sub-pixel driving circuit, the display quality of the display product can be effectively improved.

[0226] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the display substrate provided by the above-mentioned embodiment, which will not be described in detail here.

[0227] It should be noted that the layout area occupied by each sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0228] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0229] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0230] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0231] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0232] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0233] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0234] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0235] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate, and a plurality of light-emitting control signal lines, a plurality of power supply lines and a plurality of sub-pixels all disposed on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element; The sub-pixel driving circuit includes a driving transistor, a power control transistor and a light emitting control transistor; a first electrode of the power control transistor is coupled to a corresponding power line, and a second electrode of the power control transistor is coupled to a first electrode of the driving transistor; a first electrode of the light emitting control transistor is coupled to a second electrode of the driving transistor, and a second electrode of the light emitting control transistor is coupled to the light emitting element; In the same sub-pixel driving circuit, the gate of the power control transistor and the gate of the light emission control transistor are coupled to different light emission control signal lines; The light emitting control signal line includes at least two light emitting control parts arranged along a first direction, two adjacent light emitting control parts are coupled, and two adjacent light emitting control parts are arranged in different layers.

2. The display substrate according to claim 1, wherein: The plurality of light-emitting control signal lines include a plurality of first light-emitting control signal lines and a plurality of second light-emitting control signal lines; In the same sub-pixel driving circuit, the gate of the power control transistor is coupled to the corresponding first light-emitting control signal line, the gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line, and at least part of the first light-emitting control signal line and at least part of the second light-emitting control signal line are located within the layout area of ​​the same sub-pixel driving circuit.

3. The display substrate according to claim 2, wherein: At least a portion of the orthographic projection of the first light emitting control signal line on the base substrate is located between the orthographic projection of the gate of the power control transistor coupled thereto on the base substrate and the orthographic projection of the second light emitting control signal line on the base substrate.

4. The display substrate according to claim 3, wherein: The display substrate further includes a plurality of data lines and a plurality of second scan lines; the sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; In a layout area of ​​a same sub-pixel driving circuit, the first light emitting control signal line, the second light emitting control signal line and the second scanning line are arranged in sequence along a second direction, and the second direction intersects with the first direction.

5. The display substrate according to claim 4, wherein: The second electrode of the data writing transistor, the first electrode of the driving transistor and the second electrode of the power control transistor are coupled to form a second node portion; The first electrode of the light emitting control transistor is coupled to the second electrode of the driving transistor to form a third node portion together; The orthographic projection of the first light-emitting control signal line on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate; And / or, the orthographic projection of the first light-emitting control signal line on the base substrate at least partially overlaps with the orthographic projection of the third node portion on the base substrate; And / or, an orthographic projection of the second light emitting control signal line on the base substrate at least partially overlaps with an orthographic projection of the second node portion on the base substrate.

6. The display substrate according to claim 5, wherein: The first light-emitting control signal line includes a plurality of first light-emitting control parts and a plurality of second light-emitting control parts, the first light-emitting control parts and the second light-emitting control parts are alternately arranged along a first direction, and the adjacent first light-emitting control parts and the second light-emitting control parts are coupled; the first light-emitting control parts and the gate of the power control transistor are arranged in different layers, and the second light-emitting control parts and the gate of the power control transistor are arranged in the same layer; The orthographic projection of the first light emitting control portion on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate; and / or, The orthographic projection of the first light emitting control part on the base substrate at least partially overlaps with the orthographic projection of the third node portion on the base substrate; and / or, The second light-emitting control signal line includes a plurality of third light-emitting control parts and a plurality of fourth light-emitting control parts, the third light-emitting control parts and the fourth light-emitting control parts are alternately arranged along a first direction, and adjacent third light-emitting control parts are coupled; the third light-emitting control parts and the gate of the power control transistor are arranged in a different layer, the fourth light-emitting control parts and the gate of the power control transistor are arranged in the same layer, and the orthographic projection of the third light-emitting control parts on the substrate at least partially overlaps with the orthographic projection of the second node part on the substrate.

7. The display substrate according to claim 6, wherein: The display substrate comprises a first gate metal layer and a first source-drain metal layer which are sequentially stacked in a direction away from the base substrate; The first light emitting control part and the third light emitting control part are provided in the same layer and with the same material as the first source-drain metal layer; the second light emitting control part and the fourth light emitting control part are provided in the same layer and with the same material as the first gate metal layer.

8. The display substrate according to claim 2, wherein: The display substrate further includes a plurality of first scan lines; the sub-pixel driving circuit further includes a compensation transistor, a gate of the compensation transistor is coupled to the corresponding first scan line, a first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; The compensation transistor includes a compensation active layer, wherein the compensation active layer includes two channel portions and conductor portions respectively coupled to the two channel portions; The sub-pixel driving circuit also includes a shielding portion and a first conductive connection portion; the orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate; the first conductive connection portion is coupled to the shielding portion and the power line, respectively.

9. The display substrate according to claim 8, wherein: The sub-pixel driving circuit also includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor; the first conductive connection portion is also coupled to the second plate of the storage capacitor and / or the first electrode of the power control transistor.

10. The display substrate according to claim 1, wherein: The plurality of light-emitting control signal lines include a plurality of third light-emitting control signal lines; In the same sub-pixel driving circuit, the gate of the light-emitting control transistor is coupled to the corresponding third light-emitting control signal line, at least part of the third light-emitting control signal line is located within the layout area of ​​the same sub-pixel driving circuit, and the gate of the power control transistor is coupled to the third light-emitting control signal line coupled to the gate of the light-emitting control transistor in the previous sub-pixel driving circuit adjacent along the second direction.

11. The display substrate according to claim 10, wherein: The sub-pixel driving circuit also includes a second conductive connection portion, a first end of the second conductive connection portion is coupled to the gate of the power control transistor in the current sub-pixel driving circuit, and a second end of the second conductive connection portion is coupled to a third light-emitting control signal line coupled to the previous sub-pixel driving circuit adjacent to the current sub-pixel driving circuit along the second direction.

12. The display substrate according to claim 11, wherein: The display substrate further includes a plurality of data lines and a plurality of second scan lines; the sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; The second electrode of the data writing transistor, the first electrode of the driving transistor and the second electrode of the power control transistor are coupled to form a second node portion; An orthographic projection of the third light emitting control signal line on the base substrate at least partially overlaps with an orthographic projection of the second node portion on the base substrate.

13. The display substrate according to claim 12, wherein: The third light-emitting control signal line includes a plurality of fifth light-emitting control parts and a plurality of sixth light-emitting control parts, the fifth light-emitting control parts and the sixth light-emitting control parts are alternately arranged along a first direction, and the adjacent fifth light-emitting control parts are coupled; the fifth light-emitting control part and the gate of the power control transistor are arranged in a different layer, the sixth light-emitting control part and the gate of the power control transistor are arranged in the same layer, and the orthographic projection of the fifth light-emitting control part on the substrate at least partially overlaps with the orthographic projection of the second node portion on the substrate.

14. The display substrate according to claim 13, wherein: The display substrate comprises a first gate metal layer and a first source-drain metal layer which are sequentially stacked in a direction away from the base substrate; The fifth light emitting control part is provided in the same layer and the same material as the first source-drain metal layer; and / or the second conductive connection part is provided in the same layer and the same material as the first source-drain metal layer.

15. The display substrate according to claim 10, wherein: The display substrate further includes a plurality of first initialization signal lines and a plurality of first scan lines; the sub-pixel driving circuit further includes a compensation transistor, a gate of the compensation transistor is coupled to the corresponding first scan line, a first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; The compensation transistor includes a compensation active layer, wherein the compensation active layer includes two channel portions and conductor portions respectively coupled to the two channel portions; The sub-pixel driving circuit further includes a shielding portion coupled to the corresponding first initialization signal line; an orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the conductor portion on the base substrate.

16. The display substrate according to claim 10, wherein: The sub-pixel driving circuit also includes a first conductive connection portion and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor; the first conductive connection portion is respectively coupled to the power line, the second plate of the storage capacitor, and the first electrode of the power control transistor.

17. The display substrate according to claim 5 or 12, wherein: The sub-pixel driving circuit further comprises a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power line; An orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the second node portion on the base substrate.

18. The display substrate according to claim 17, wherein: The orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the third node portion in the sub-pixel driving circuit on the base substrate.

19. The display substrate according to claim 18, wherein: The first electrode plate includes a first electrode plate body and a first electrode plate protrusion; the second electrode plate includes a second electrode plate body and a second electrode plate protrusion; The orthographic projection of the first electrode plate main body on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate main body on the base substrate; The orthographic projection of the first electrode plate protrusion on the substrate substrate at least partially overlaps with the orthographic projection of the second electrode plate protrusion on the substrate substrate; The orthographic projection of the second electrode protrusion on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate; And / or, the orthographic projection of the second electrode plate protrusion on the base substrate at least partially overlaps with the orthographic projection of the third node portion on the base substrate.

20. The display substrate according to claim 2, wherein: The display substrate comprises a display area and a peripheral area located around the display area; The display substrate further includes a plurality of first shift register units all located in the peripheral area; In the same sub-pixel driving circuit, the second light-emitting control signal line coupled to the gate of the light-emitting control transistor is coupled to the corresponding first shift register unit, and the first light-emitting control signal line coupled to the gate of the power control transistor is coupled to the first shift register unit coupled to the gate of the light-emitting control transistor in the sub-pixel driving circuit adjacent along the second direction.

21. The display substrate according to claim 2, wherein: The display substrate comprises a display area and a peripheral area located around the display area; The display substrate further comprises a plurality of first shift register units and a plurality of second shift register units, all of which are located in the peripheral area, and the display area is located between the first shift register units and the second shift register units; The first shift register unit is coupled to the corresponding first light emitting control signal line, and the second shift register unit is coupled to the corresponding second light emitting control signal line.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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