Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: a first insulating layer; the second insulating layer is arranged on the first insulating layer; the third insulating layer is arranged on the second insulating layer; the fourth insulating layer is embedded in the third insulating layer; the first insulating layer is arranged on the first insulating layer, the second insulating layer is arranged on the second insulating layer, the third insulating layer is arranged on the fourth insulating layer, the fifth insulating layer is arranged on the third insulating layer, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are made of different materials, and the second insulating layer and the fifth insulating layer are made of the same material. And the thickness in the vertical direction between the upper surface of the fourth insulating layer and the upper surface of the third insulating layer is smaller than the thickness in the vertical direction of the second insulating layer.

Description

Technical Field

[0001] The embodiments relate to a circuit board, and more particularly, to a circuit board having improved mechanical reliability and electrical reliability and a semiconductor package including the circuit board. Background Art

[0002] As the performance of electrical / electronic products improves, technologies for mounting a larger number of semiconductor devices on a circuit board of a semiconductor package with a limited size are being proposed and studied. However, since a general semiconductor package is based on mounting a single semiconductor device, there are limitations in obtaining desired performance.

[0003] Therefore, recently, a semiconductor package using multiple circuit boards to mount multiple semiconductor devices has been provided. This semiconductor package has a structure in which multiple semiconductor devices are connected to each other on the circuit board in a horizontal direction and / or a vertical direction. Therefore, the semiconductor package has the advantages of effectively using the mounting area of the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Due to these advantages, the semiconductor package as described above is widely applied to mobile devices and the like.

[0005] Moreover, as the number and / or size of each semiconductor device increase according to the trend of high integration, or as the functional parts of the semiconductor devices are divided, semiconductor packages applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding the concept to semiconductor chiplets.

[0006] Therefore, the mutual communication between semiconductor devices and / or semiconductor chiplets is becoming important, and thus, there is a trend to provide an interposer between the circuit board of the semiconductor package and the semiconductor devices.

[0007] The interposer can be used as a redistribution layer that gradually increases the width or depth of the circuit pattern from the semiconductor device to the circuit pattern of the semiconductor package in order to facilitate the mutual communication between the semiconductor devices and / or semiconductor chiplets, or interconnect the semiconductor devices and the semiconductor package circuit board, thereby smoothly transmitting electrical signals between the semiconductor device and the semiconductor package circuit board having a circuit pattern relatively larger than the circuit pattern of the semiconductor device.

[0008] The interposer layer may have an area larger than the total area of a plurality of semiconductor devices and / or chiplets, so as to integrally mount the plurality of semiconductor devices and / or chiplets, or may be provided only in a portion for interconnecting between the semiconductor devices and / or chiplets. That is, the area of the interposer layer may increase as the number of semiconductor devices and / or chiplets increases, or the area of the interposer layer may not increase. However, as the number of semiconductor devices and / or chiplets increases, the area of the circuit board of the semiconductor package tends to increase. Therefore, as the area of the semiconductor package increases, the semiconductor package has a problem of more significant warping.

[0009] Meanwhile, the package circuit board and / or the interposer layer applied to the semiconductor package are provided with connection members connected to the semiconductor devices and / or chiplets. The connection members are used to horizontally connect the plurality of semiconductor devices and / or chiplets. Therefore, the connection members can be embedded in the package circuit board and / or the interposer layer. At this time, the connection members can be inorganic bridges or organic bridges.

[0010] Moreover, the inorganic and / or organic materials constituting the connection members may include insulating materials different from the insulating layers provided in the package circuit board and / or the interposer layer. Therefore, the thermal expansion coefficients of the package circuit board and / or the interposer layer and the connection members can be different from each other. As a result, when thermal stress is applied to the semiconductor package, the stress may concentrate on the connection members embedded in the package circuit board and / or the interposer layer. As a result, there is a problem of cracks appearing in the regions where the connection members are embedded in the semiconductor package. Summary of the Invention

[0011] Technical Problem

[0012] Embodiments provide a circuit board having a novel structure and a semiconductor package including the circuit board.

[0013] Moreover, embodiments provide a circuit board having improved warping characteristics and a semiconductor package including the circuit board.

[0014] Moreover, embodiments provide a circuit board having improved electrical reliability and mechanical reliability of connection members, and a semiconductor package including the circuit board.

[0015] The technical problems to be solved by the proposed embodiments are not limited to the above technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the embodiments described below belong.

[0016] Technical Solution

[0017] The circuit board according to the embodiment includes: a first insulating layer; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a fourth insulating layer embedded in the third insulating layer; and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are made of different materials, wherein the second insulating layer and the fifth insulating layer are made of the same material, and wherein the thickness in the vertical direction between the upper surface of the fourth insulating layer and the upper surface of the third insulating layer is less than the thickness of the second insulating layer in the vertical direction.

[0018] Moreover, the thickness in the vertical direction between the lower surface of the fourth insulating layer and the lower surface of the third insulating layer is less than the thickness of the second insulating layer in the vertical direction.

[0019] Moreover, the second insulating layer includes a first resin layer and a first reinforcing member disposed within the first resin layer.

[0020] Moreover, the fourth insulating layer includes a second resin layer and a second reinforcing member disposed within the second resin layer, and the number of layers or the thickness of the first reinforcing member is different from the number of layers or the thickness of the second reinforcing member.

[0021] Moreover, the first reinforcing member and the second reinforcing member include glass fibers or reinforcing fibers different from the filler.

[0022] Moreover, the number of layers of the first reinforcing member is less than the number of layers of the second reinforcing member.

[0023] Moreover, the thickness of a single layer of the first reinforcing member is less than the thickness of a single layer of the second reinforcing member.

[0024] Moreover, the third insulating layer does not have a reinforcing member.

[0025] Moreover, the circuit board further includes: a first electrode portion that penetrates at least some regions of the second insulating layer; a second electrode portion that penetrates at least some regions of the third insulating layer; and a third electrode portion that penetrates the fourth insulating layer.

[0026] Moreover, the first electrode portion includes a first pad portion and a first through portion, and the first through portion has an inclined surface, and the width of the inclined surface gradually decreases from the lower surface of the second insulating layer toward the upper surface of the second insulating layer.

[0027] Moreover, the second electrode portion includes a second pad portion and a second through portion. The second through portion has an inclined surface, and the width of the inclined surface gradually decreases from the lower surface of the third insulating layer toward the lower surface of the fourth insulating layer. The inclined surface of the first through portion is different from the inclined surface of the second through portion.

[0028] Moreover, the third electrode portion includes a third pad portion and a third through portion. The third through portion includes: a first inclined surface adjacent to the upper surface of the fourth insulating layer, and the width of the first inclined surface gradually decreases toward the lower surface of the fourth insulating layer; and a second inclined surface adjacent to the lower surface of the fourth insulating layer, and the width of the second inclined surface gradually decreases toward the upper surface of the fourth insulating layer.

[0029] Moreover, the thickness of the first through portion in the vertical direction is greater than the thickness of the second through portion in the vertical direction and less than the thickness of the third through portion in the vertical direction. The thickness of the second through portion in the vertical direction is less than the thickness of each of the first through portion and the third through portion in the vertical direction, and the thickness of the third through portion is greater than the thickness of each of the first through portion and the second through portion in the vertical direction.

[0030] Moreover, each of the first through portion and the third through portion has a recess that horizontally overlaps with the reinforcing member, and the second through portion does not have a recess that horizontally overlaps with the reinforcing member.

[0031] Moreover, the number of recesses provided in the first through portion or the thickness of a single recess of the first through portion in the vertical direction is less than the number of recesses provided in the third through portion or the thickness of a single recess of the third through portion in the vertical direction.

[0032] Moreover, the fourth insulating layer has a through hole penetrating the upper surface and the lower surface of the fourth insulating layer, and the circuit board further includes: a first dummy electrode provided on the upper surface of the fourth insulating layer adjacent to the through hole; and a second dummy electrode provided on the lower surface of the fourth insulating layer adjacent to the through hole.

[0033] Moreover, at least one of the side surface of the first dummy electrode and the side surface of the second dummy electrode is provided in the same plane as the side wall of the through hole of the fourth insulating layer.

[0034] Moreover, the side surface of the first dummy electrode, the side surface of the second dummy electrode, and the side surface of the through hole of the fourth insulating layer are provided in the same plane.

[0035] Moreover, the side surfaces of the first dummy electrode and the second dummy electrode are not aligned with each other in the vertical direction.

[0036] In addition, the upper width and the lower width of the through hole are different from each other.

[0037] Moreover, the semiconductor package includes a connection member disposed in the through hole.

[0038] Moreover, the connection member is any one of a semiconductor active device, a semiconductor passive device, an inorganic bridge, and an organic bridge.

[0039] Moreover, there is a step difference between the upper surface of the first dummy electrode and the upper surface of the terminal of the connection member.

[0040] Moreover, the upper surface of the terminal of the connection member is higher than the upper surface of the first dummy electrode, and the vertical distance of the step difference is 8 μm or less.

[0041] Advantageous Effects

[0042] The semiconductor package of the embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer embedded in the third insulating layer, and a fifth insulating layer disposed on the third insulating layer. Among them, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are formed of different materials, the second insulating layer and the fifth insulating layer are formed of the same material, and the thickness in the vertical direction between the upper surface of the fourth insulating layer and the upper surface of the third insulating layer can be less than the thickness in the vertical direction of the second insulating layer. Thus, the embodiment can reduce the thickness of the semiconductor package, and at the same time prevent the semiconductor package from bending in a specific direction by using the third insulating layer.

[0043] Specifically, the third insulating layer may have a relatively low Young's modulus, thereby suppressing the occurrence of warping acting on the semiconductor package, and further preventing the semiconductor package from bending significantly in a specific direction while absorbing the impact applied to the semiconductor package. Thus, the embodiment can solve the problem of deterioration of operating characteristics due to significant bending of the semiconductor package in a specific direction, and can further solve the problem of damage to the connection member disposed in the third insulating layer due to impact. Moreover, the embodiment can use the third insulating layer to arrange the electrode portion connected to the connection member, thereby improving the alignment between the electrode portion and the connection member.

[0044] Moreover, the fourth insulating layer may include a through hole, and a connection member may be disposed in the through hole. Moreover, a first dummy electrode may be disposed on the upper surface of the fourth insulating layer, and a second dummy electrode may be disposed on the lower surface of the fourth insulating layer. At least one side surface of the first dummy electrode and the second dummy electrode may be located in the same plane as the side wall of the through hole. The first dummy electrode and the second dummy electrode may be electrodes for forming a through hole by a laser process. Moreover, embodiments may use the first dummy electrode and the second dummy electrode to make the upper width and the lower width of the through hole substantially the same, thereby reducing the area of the dead zone increased by the difference between the upper and lower widths. Accordingly, embodiments may reduce the thickness of the semiconductor package.

[0045] Moreover, embodiments may change the shape of the through hole by misaligning the first dummy electrode and the second dummy electrode in the vertical direction. Thereby, embodiments may freely change the shape of the through hole according to the shape of the connection member, thereby improving the design freedom.

[0046] Moreover, embodiments may have a step between the upper surface of the terminal of the connection member and the upper surface of the first dummy electrode, and the step is controlled to be kept below a specific level. Thereby, embodiments may increase the connection alignment between the electrode portion and the terminal, and further minimize the voids generated during the process of filling the through hole with an insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0048] Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0049] Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0050] Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0051] Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0052] Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment.

[0053] Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0054] Figure 2 is a cross-sectional view showing a circuit board according to a first embodiment.

[0055] Figure 3 is a cross-sectional view of a first electrode portion showing Figure 2 .

[0056] Figure 4 is a cross-sectional view of a second electrode portion showing Figure 2 .

[0057] Figure 5 is a cross-sectional view of a third electrode portion showing Figure 2 .

[0058] Figure 6 is a plan view of a dummy electrode of a third electrode portion according to an embodiment.

[0059] Figure 7 is a cross-sectional view of a dummy electrode and a via hole according to a first embodiment.

[0060] Figure 8 is a cross-sectional view of a dummy electrode and a via hole according to a second embodiment.

[0061] Figure 9 is a cross-sectional view of a dummy electrode and a via hole according to a third embodiment.

[0062] Figure 10 is a cross-sectional view of a dummy electrode and a position of a terminal of a connection member according to a first embodiment.

[0063] Figure 11 is a cross-sectional view of a dummy electrode and a position of a terminal of a connection member according to a second embodiment.

[0064] Figure 12 is a cross-sectional view of a circuit board according to a second embodiment. DETAILED DESCRIPTION

[0065] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which the same reference numerals are used to denote the same or similar elements, and redundant descriptions thereof will be omitted. In the following description, the suffixes "module" and "portion" of components are given or mixed only for the ease of preparation of the description and have no meaning or function to distinguish from each other. Further, in the following description of the embodiments of the present invention, when it is determined that the gist of the embodiments disclosed herein may be blurred, the detailed description of the related art will be omitted. In addition, the accompanying drawings are included to provide a further understanding of the present invention, and the drawings are incorporated into the present specification and constitute a part of the present specification, and it should be understood that the present invention is intended to cover all modifications, equivalents, or alternatives falling within the spirit and scope of the present invention.

[0066] Terms such as first, second, etc. including ordinal numbers may be used to describe various components, but the elements are not limited to these terms. These terms are only used to distinguish one component from another.

[0067] When a component is referred to as being “connected” or “in contact” with another component, it can be directly connected or joined to the other component, but it should be understood that other components can be present therebetween. When a component is referred to as being “directly connected” or “directly in contact” with another component, it should be understood that no other components can be present therebetween.

[0068] Unless the context clearly indicates otherwise, the singular form includes the plural form.

[0069] In this application, terms such as “including” or “having” are used to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification. However, it should be understood that these terms do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0070] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0071] - Electronic device -

[0072] Before describing the embodiments, an electronic device to which the embodiments are applied, a semiconductor package, will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0073] The semiconductor devices can include active devices and / or passive devices. The active devices can be semiconductor chips in the form of integrated circuits (ICs), where hundreds to millions of devices are integrated in one semiconductor device. The semiconductor devices can be logic chips, memory chips, etc. The logic chips can be central processing units (CPUs), graphics processing units (GPUs), etc. For example, the logic chip can be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or can be an analog-to-digital converter, an application-specific IC (ASIC), or can be a chipset including a specific combination of those listed above.

[0074] The memory chips can be stacked memories such as HBM. The memory chips can also include memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), flash memories, etc.

[0075] On the other hand, the product group of the semiconductor package of the application embodiment can be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package on Package), and SIP (System in Package), but is not limited thereto.

[0076] Moreover, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the embodiment is not limited thereto, and can be any other electronic device that processes data in addition to these.

[0077] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment can have various package structures including the circuit board to be described later.

[0078] Moreover, in one embodiment, the circuit board can be the first circuit board described below.

[0079] Moreover, in another embodiment, the circuit board can be the second circuit board described below.

[0080] Figure 1a is a cross-sectional view showing a semiconductor package according to the first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to the second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to the third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to the fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to the fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to the sixth embodiment, and Figure 1gIt is a cross-sectional view showing a semiconductor package according to the seventh embodiment.

[0081] Reference Figure 1a , the semiconductor package according to the first embodiment may include a first circuit board 1100, a second circuit board 1200, and a semiconductor device 1300.

[0082] The first circuit board 1100 may represent a package substrate.

[0083] For example, the first circuit board 1100 may provide a space for at least one external circuit board to be coupled thereto. The external circuit board may refer to the second circuit board 1200 coupled to the first circuit board 1100. In addition, the external circuit board may refer to a main board in an electronic device included in the lower part coupled to the first circuit board 1100.

[0084] In addition, although not shown in the figure, the first circuit board 1100 may provide a space in which at least one semiconductor device is installed.

[0085] The first circuit board 1100 may include at least one insulating layer and an electrode portion provided on the at least one insulating layer.

[0086] The second circuit board 1200 may be disposed on the first circuit board 1100.

[0087] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is installed. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are installed. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320 to the first circuit board 1100 while electrically connecting the first semiconductor device 1310 and the second semiconductor device 1320. That is, the second circuit board 1200 may perform a horizontal connection function between multiple semiconductor devices and a vertical connection function between the semiconductor device and the package substrate.

[0088] Figure 1a It is shown that the first semiconductor device 1310 and the second semiconductor device 1320 are disposed on the second circuit board 1200, but it is not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor devices may be disposed.

[0089] The second circuit board 1200 may be disposed between at least one semiconductor device 1300 and the first circuit board 1100.

[0090] In an embodiment, the second circuit board 1200 may be an active interposer used as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the semiconductor package of the embodiment may have a structure vertically stacked on the first circuit board 1100 and may have the functions of a plurality of logic chips. Having the functions of a logic chip may mean that it may have the functions of active devices and passive devices. In the case of active devices, different from passive devices, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may have the functions of active devices. Moreover, the active interposer may execute the functions of the corresponding logic chip while performing the signal transmission function between the second logic chip disposed thereon and the first circuit board 1100.

[0091] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may be used as a signal relay between the semiconductor device 1300 and the first circuit board 1100 and may have the functions of passive devices such as resistors, capacitors, or inductors. For example, due to 5G, the Internet of Things (IOT), improved image quality, and increased communication speed, the number of terminals of the semiconductor device 1300 has gradually increased. That is, the number of terminals provided in the semiconductor device 1300 increases, thereby reducing the width of the terminals or the pitch between a plurality of terminals. In this case, the first circuit board 1100 may be a main board connected to an electronic device. There is a problem that in order for the electrodes provided on the first circuit board 1100 to have widths and pitches respectively connected to the semiconductor device 1300 and the main board, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complicated. Therefore, in the first embodiment, the second circuit board 1200 may be disposed on the first circuit board 1100 and the semiconductor device 1300. Moreover, the second circuit board 1200 may include electrodes having fine widths and pitches corresponding to the terminals of the semiconductor device 1300.

[0092] The semiconductor device 1300 may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), etc., or may be a chipset including a specific combination of those listed above. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0093] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0094] For example, a semiconductor package may include a first connection portion 1410 disposed between a first circuit board 1100 and a second circuit board 1200. The first connection portion 1410 may electrically connect the second circuit board 1200 to the first circuit board 1100 while coupling them.

[0095] For example, a semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and a semiconductor device 1300. The second connection portion 1420 may electrically connect the semiconductor device 1300 to the second circuit board 1200 while coupling them.

[0096] The semiconductor package may include a third connection portion 1430 disposed on a lower surface of the first circuit board 1100. The third connection portion 1430 may electrically connect the first circuit board 1100 to a main board while coupling them.

[0097] At this time, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 may be electrically connected between multiple components by using at least one of wire bonding, solder bonding, and direct intermetallic bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 have the function of electrically connecting multiple components, when direct intermetallic bonding is used, the connection portion of the semiconductor package may be understood as an electrical connection portion rather than solder or a wire.

[0098] The wire bonding method may refer to electrically connecting multiple components using a wire such as gold (Au). In addition, the solder bonding method may use a material containing at least one of Sn, Ag, and Cu to electrically connect multiple components. Moreover, the direct intermetallic bonding method may refer to recrystallization by applying heat and pressure between multiple components in the absence of solder, wire, conductive adhesive, etc. Moreover, direct bonding occurs between multiple components. Moreover, the direct intermetallic bonding method may refer to the bonding method through the second connection portion 1420. In this case, the second connection portion 1420 may represent a metal layer formed between multiple components by recrystallization.

[0099] Specifically, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 may couple multiple components to each other by a thermal compression (TC) bonding method. Thermal compression bonding may refer to a method of directly coupling multiple components by applying heat and pressure to the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430.

[0100] At this time, at least one of the first circuit board 1100 and the second circuit board 1200 may be provided with protrusions protruding outward from the insulating layer away from the corresponding board, and a first connection part 1410, a second connection part 1420, and a third connection part 1430 are provided on the protrusions. The protrusions may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0101] The protrusions may be referred to as bumps. The protrusions may also be referred to as posts. The protrusions may also be referred to as pillars. Preferably, the protrusions may refer to the electrodes among the electrodes of the second circuit board 1200 on which the second connection part 1420 for coupling to the semiconductor device 1300 is provided. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the plurality of second connection parts 1420 respectively connected to the plurality of terminals of the semiconductor device 1300 through a conductive adhesive such as solder. Therefore, in an embodiment, thermal compression bonding may be performed to reduce the volume of the second connection part 1420. Moreover, in order to ensure prevention of diffusion and alignment to prevent the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusions from diffusing into the interposer and / or the circuit board, the electrodes of the second circuit board 1200 on which the second connection part 1420 is provided may include protrusions.

[0102] Meanwhile, referring to Figure 1b , the semiconductor package of the second embodiment may be different from the semiconductor package of the first embodiment in that the connection member 1210 is provided on the second circuit board 1200. The connection member 1210 may be referred to as a bridge circuit board. For example, the connection member 1210 may include a redistribution layer. The connection member 1210 may perform a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area of the semiconductor device is usually too large, the connection member 1210 may include a redistribution layer. Since there are large differences between the semiconductor package and the semiconductor device in terms of the width or pitch of the circuit pattern, etc., a circuit pattern is required for the buffering effect of electrical connection. The buffering effect may mean having a size between the width or pitch of the circuit pattern of the semiconductor package and the width or pitch of the circuit pattern of the semiconductor device, and the redistribution layer may include a function of performing the buffering effect.

[0103] In an embodiment, the connection member 1210 may be an inorganic bridge. For example, the inorganic bridge may be a silicon bridge. That is, the connection member 1210 may include a silicon circuit board and a redistribution layer provided on the silicon circuit board.

[0104] In another embodiment, the connection member 1210 may be an organic bridge. For example, the connection member 1210 may include an organic material. For example, the connection member 1210 may include an organic circuit board including an organic material instead of a silicon circuit board.

[0105] The connection member 1210 may be embedded in the second circuit board 1200, but is not limited thereto. For example, the connection member 1210 may be disposed on the second circuit board 1200 to have a protruding structure.

[0106] In addition, the second circuit board 1200 may include a cavity, and the connection member 1210 may be disposed in the cavity of the second circuit board 1200.

[0107] The connection member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200.

[0108] Reference Figure 1c , the semiconductor package according to the third embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, compared with the semiconductor package of the second embodiment, the semiconductor package of the third embodiment may have a structure in which the first circuit board 1100 is removed therein.

[0109] That is, the second circuit board 1200 of the third embodiment may be used as a package substrate while performing an interposer function.

[0110] The first connection portion 1410 disposed on the lower surface of the second circuit board 1200 may couple the second circuit board 1200 to the main board of the electronic device.

[0111] Reference Figure 1d , the semiconductor package according to the fourth embodiment may include a first circuit board 1100 and a semiconductor device 1300.

[0112] In this case, compared with the semiconductor package of the second embodiment, the semiconductor package of the fourth embodiment may have a structure in which the second circuit board 1200 is omitted.

[0113] That is, the first circuit board 1100 of the fourth embodiment may be used as a package circuit board while also performing the function of connecting the semiconductor device 1300 and the main board. To this end, the first circuit board 1100 may include a connection member 1110 for connecting a plurality of semiconductor devices. The connection member 1110 may be an inorganic bridge or an organic material bridge connecting a plurality of semiconductor devices.

[0114] Reference Figure 1e , compared with the semiconductor package of the fourth embodiment, the semiconductor package of the fifth embodiment may further include a third semiconductor device 1330.

[0115] To this end, the fourth connection part 1440 may be disposed on the lower surface of the first circuit board 1100.

[0116] Moreover, the third semiconductor device 1330 may be disposed on the fourth connection part 1440. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are respectively mounted on the upper side and the lower side.

[0117] In this case, the third semiconductor device 1330 may have a structure disposed on the lower surface of the second circuit board 1200 in the semiconductor package of Figure 1c which.

[0118] Referring to Figure 1f , the semiconductor package according to the sixth embodiment may include a first circuit board 1100. The first semiconductor device 1310 may be disposed on the first circuit board 1100. To this end, the first connection part 1410 may be disposed between the first circuit board 1100 and the first semiconductor device 1310.

[0119] Moreover, the first circuit board 1100 may include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump, or alternatively, may also be referred to as a post. The conductive coupling part 1450 may be disposed to have a protruding structure on the electrode disposed on the uppermost side of the first circuit board 1100.

[0120] The second semiconductor device 1320 may be disposed on the conductive coupling part 1450. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling part 1450. Moreover, the second connection part 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

[0121] Therefore, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection part 1420.

[0122] That is, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling part 1450, and may also be connected to the first semiconductor device 1310 through the second connection part 1420.

[0123] In this case, the second semiconductor device 1320 may receive a power signal and / or electric power through the conductive coupling part 1450. In addition, the second semiconductor device 1320 may send a communication signal to the first semiconductor device 1310 and receive a communication signal from the first semiconductor device 1310 through the second connection part 1420.

[0124] The semiconductor package according to the sixth embodiment can provide a power signal and / or electric power to the second semiconductor device 1320 through the conductive coupling portion 1450, so as to provide sufficient power to drive the second semiconductor device 1320 or achieve smooth control of power operations.

[0125] Therefore, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power supplied to the second semiconductor device 1320. In addition, in the embodiment, at least one of the power signal, electric power, and communication signal of the second semiconductor device 1320 can be provided through different paths via the conductive coupling portion 1450 and the second connection portion 1420. Thus, the embodiment can solve the problem that the communication signal is lost due to the power signal. For example, the embodiment can minimize the mutual interference between the power signal and the communication signal.

[0126] Meanwhile, the second semiconductor device 1320 in the sixth embodiment can have a POP (Package On Package) structure in which a plurality of package circuit boards are stacked and can be disposed on the first circuit board 1100. For example, the second semiconductor device 1320 can be a memory package including memory chips. Moreover, the memory package can be coupled to the conductive coupling portion 1450. In this case, the memory package can be not connected to the first semiconductor device 1310.

[0127] Meanwhile, the semiconductor package in the sixth embodiment can include a molding member 1460. The molding member 1460 can be disposed between the first circuit board 1100 and the second semiconductor device 1320. For example, the molding member 1460 can mold the first connection portion 1410, the second connection portion 1420, the first semiconductor device 1310, and the conductive coupling portion 1450.

[0128] Reference Figure 1g , the semiconductor package according to the seventh embodiment can include a first circuit board 1100, a first connection portion 1410, a second connection portion 1420, a semiconductor device 1300, and a third connection portion 1430.

[0129] In this case, the difference between the semiconductor package of the seventh embodiment and the semiconductor package of the fourth embodiment can be that the first circuit board 1100 includes a plurality of circuit board layers, and the connection member 1110 is omitted.

[0130] The first circuit board 1100 can include a plurality of circuit board layers. For example, the first circuit board 1100 can include a first circuit board layer 1100A corresponding to a package substrate and a second circuit board layer 1100B corresponding to a connection member.

[0131] In other words, the semiconductor package of the seventh embodiment may include a first circuit board layer 1100A and a second circuit board layer 1100B, where Figure 1a the first circuit board (package circuit board, 1100) and the second circuit board (interposer, 1200) disclosed in are integrally formed. The material of the insulating layer of the second circuit board layer 1100B may be different from the material of the insulating layer of the first circuit board layer 1100A. For example, the material of the insulating layer of the second circuit board layer 1100B may include a photocurable material. For example, the second circuit board layer 1100B may be a photo imageable dielectric (PID). Moreover, since the second circuit board layer 1100B includes a photocurable material, the electrodes can be miniaturized. Therefore, in the seventh embodiment, the second circuit board layer 1100B can be formed by sequentially stacking an insulating layer of a photocurable material on the first circuit board layer 1100A and forming miniaturized electrodes on the insulating layer of the photocurable material. Therefore, the second circuit board layer 1100B may include a redistribution layer function having microelectrodes and may include a function of horizontally connecting a plurality of semiconductor devices 1310 and 1320.

[0132] Before describing the circuit boards of the embodiments, the circuit boards described below may represent any one of the circuit boards included in the previous semiconductor packages. For example, the circuit boards described below may represent any one of the first circuit board 1100 and the second circuit board 1200 included in the semiconductor packages of the first to seventh embodiments.

[0133] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment, Figure 3 is showing Figure 2 a cross-sectional view of the first electrode portion of, Figure 4 is showing Figure 2 a cross-sectional view of the second electrode portion of, Figure 5 is showing Figure 2 a cross-sectional view of the third electrode portion of, Figure 6 is a plan view showing a dummy electrode of the third electrode portion according to an embodiment, Figure 7 is a cross-sectional view showing a dummy electrode and a via hole according to the first embodiment, Figure 8 is a cross-sectional view showing a dummy electrode and a via hole according to the second embodiment, Figure 9 is a cross-sectional view showing a dummy electrode and a via hole according to the third embodiment, Figure 10 is a cross-sectional view showing the positions of a dummy electrode and terminals of a connection member according to the first embodiment, Figure 11 is a cross-sectional view showing the positions of a dummy electrode and terminals of a connection member according to the second embodiment, and Figure 12 is a cross-sectional view showing a circuit board according to the second embodiment.

[0134] Hereinafter, reference will be made to Figures 2 to 12 specifically describe the semiconductor package according to the embodiments.

[0135] Reference Figure 2 , the semiconductor package may include a circuit board and a connection member 200 embedded in the circuit board.

[0136] In one embodiment, the connection member 200 may function to horizontally connect a plurality of semiconductor devices disposed on the circuit board. For example, the connection member 200 may include a high-density electrode pattern to connect a plurality of semiconductor devices. To this end, in one embodiment, the connection member 200 may be an inorganic bridge. The inorganic bridge may include a silicon bridge. Moreover, in another embodiment, the connection member 200 may be an organic bridge. The organic bridge may include at least one organic insulating layer and an electrode pattern disposed on the organic insulating layer.

[0137] In another embodiment, the connection member 200 may represent a semiconductor device. For example, in another embodiment, the connection member 200 may represent a semiconductor device embedded in the circuit board. The semiconductor device may include an active device and / or a passive device. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated in one semiconductor device. The semiconductor device may be an application processor (AP) device including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), etc., or may be a chipset including a specific combination of those listed above. Moreover, the connection member 200 may be an integrated passive device (IPD). Moreover, the connection member 200 may be a multi-layer ceramic capacitor (MLCC, multi-layer ceramic condenser, multi-layer ceramic capacitor, Multi-Layer Ceramic Condenser, Multi-Layer Ceramic Capacitor) or a silicon-based capacitor.

[0138] The connection member 200 may be embedded in the circuit board and may be electrically connected to an electrode portion included in the circuit board. For example, the connection member 200 may include terminals, and the terminals may be electrically connected to the electrode portion of the circuit board. The terminals may refer to electrode patterns provided in the organic bridge and / or the inorganic bridge, and may refer to electrode patterns provided in the semiconductor device.

[0139] The circuit board may provide a space for accommodating and embedding the connection member 200. The circuit board may provide a space in which at least one semiconductor device is mounted.

[0140] The circuit board may include an insulating layer and an electrode portion. The insulating layer may be provided in multiple layers. Moreover, the electrode portion may be provided in each of the multiple layers of the insulating layer. For example, the electrode portion may be provided as at least a part of a region penetrating through the multiple layers of the insulating layer.

[0141] The insulating layer may include a first insulating layer 111.

[0142] The first insulating layer 111 may refer to the insulating layer positioned at the lowermost side among the insulating layers provided in the circuit board. The first insulating layer 111 may have a function of protecting the circuit board. Thus, the first insulating layer 111 may be referred to as a solder resist layer or a protective layer.

[0143] The first insulating layer 111 may be a solder resist layer including an organic polymer material. For example, the first insulating layer 111 may include an epoxy acrylate series resin. Specifically, the first insulating layer 111 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first insulating layer 111 may be provided with any one of a photoresist layer, a cover-lay, and a polymer material.

[0144] For example, when a semiconductor device and / or an external circuit board is joined to the electrode portion of the embodiment using a conductive adhesive such as solder, the wettability between the solder and the first insulating layer 111 is poor, and thus, the electrical reliability problem occurring when multiple adjacent solders come into contact with each other can be solved.

[0145] The first insulating layer 111 may not include a reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or a glass fiber.

[0146] The reinforcing member may be distinguished from the filler. For example, the reinforcing member may represent a glass fiber material extending in the horizontal direction within the insulating layer, and may have a different meaning from the inorganic filler spaced apart from each other. That is, the reinforcing member may have a different length or width in the horizontal direction from the filler. For example, the glass fiber may extend to have a width greater than the width of the insulating layer. Here, the meaning of having a width greater than the width of the insulating layer may mean that the glass fiber may be provided in a shape bent in the horizontal direction. The filler is different from the reinforcing member, and may refer to an inorganic filler, for example.

[0147] The thickness of the first insulating layer 111 in the vertical direction can be in the range of 6 μm to 20 μm. Preferably, the first insulating layer 111 can have a thickness in the vertical direction of 8 μm to 18 μm. The first insulating layer 111 can have a thickness in the vertical direction of 10 μm to 16 μm. The thickness of the first insulating layer 111 in the vertical direction can refer to the vertical distance from the lower surface of the electrode portion closest to the first insulating layer 111 to the lower surface of the first insulating layer 111. For example, the thickness of the first insulating layer 111 in the vertical direction can refer to the vertical distance from the lower surface of the first electrode portion 120 in contact with the first insulating layer 111 to the lower surface of the first insulating layer 111.

[0148] If the thickness of the first insulating layer 111 in the vertical direction exceeds 20 μm, it may be difficult to thin the semiconductor package due to an increase in the thickness of the semiconductor package or an increase in the stress applied to the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. Moreover, if the thickness of the first insulating layer 111 is less than 6 μm, it may be difficult to stably protect the circuit board and / or the electrode portion, thereby reducing the electrical reliability or physical reliability.

[0149] The circuit board can include a second insulating layer 112 disposed on the first insulating layer 111.

[0150] The second insulating layer 112 can include an insulating material different from that of the first insulating layer 111. The second insulating layer 112 can have rigidity. For example, the second insulating layer 112 can include a reinforcing member. The second insulating layer 112 can include reinforcing fibers and / or glass fibers. For example, the second insulating layer 112 can be a prepreg including a reinforcing member, but is not limited thereto.

[0151] The second insulating layer 112 can be provided on the first insulating layer 111 in at least one layer. When the second insulating layer 112 is provided in multiple layers, the interface between the multiple layers of the second insulating layer 112 may not be distinguishable. In this case, the interface between the multiple layers of the second insulating layer 112 can be distinguished by the first electrode portion 120 passing through the second insulating layer 112. For example, the first electrode portion 120 can include a pad portion 121 and a through portion 122. Moreover, the pad portion 121 and the through portion 122 can have different widths in the horizontal direction and / or different slopes in the vertical direction. Moreover, when the second insulating layer 112 is provided with multiple layers of the same insulating material, the interface of each layer can be distinguished based on the difference in the width or slope of the pad portion 121 and the through portion 122 of the first electrode portion 120.

[0152] The thickness of a single layer of the second insulating layer 112 in the vertical direction may satisfy the range of 15 μm to 35 μm. The thickness of a single layer of the second insulating layer 112 in the vertical direction may satisfy the range of 17 μm to 33 μm. The thickness of a single layer of the second insulating layer 112 in the vertical direction may satisfy the range of 20 μm to 30 μm. If the thickness of a single layer of the second insulating layer 112 in the vertical direction is less than 15 μm, the reinforcing fibers provided in the second insulating layer 112 may be exposed from the second insulating layer 112, and electrical reliability problems may occur due to the contact between the exposed reinforcing fibers and the electrode portion. If the thickness of a single layer of the second insulating layer 112 in the vertical direction is less than 15 μm, the rigidity of the semiconductor package is reduced, and as a result, a problem may occur in that the semiconductor package is greatly bent in a specific direction. If the thickness of a single layer of the second insulating layer 112 in the vertical direction exceeds 35 μm, it may be difficult to thin the semiconductor package due to the increase in the thickness of the semiconductor package, or the stress applied to the insulating layer adjacent to the second insulating layer 112 may increase.

[0153] Preferably, the thickness of a single layer of the second insulating layer 112 in the vertical direction may be greater than the thickness of the first insulating layer 111 in the vertical direction. Thereby, the second insulating layer 112 can prevent stress from being applied to the lower side of the first insulating layer 111, thereby improving the overall mechanical reliability of the semiconductor package.

[0154] Meanwhile, Figure 2 the second insulating layer 112 in is shown as being provided in two layers, but is not limited thereto. The second insulating layer 112 may be provided in one layer, or may be provided in three or more layers.

[0155] The circuit board may include a third insulating layer 113 provided on the second insulating layer 112. The third insulating layer 113 may include an insulating material different from the insulating materials of the first insulating layer 111 and the second insulating layer 112.

[0156] The third insulating layer 113 may not include a reinforcing member. For example, the third insulating layer 113 may not include glass fibers and / or reinforcing fibers. The third insulating layer 113 may include an organic material that does not contain a reinforcing member, and the organic material can achieve a thin and light circuit board, excellent processability, and miniaturization of electrode components. For example, the third insulating layer 113 may use ABF (Ajinomoto Build-up Film), which is a product released by Ajinomoto Co., Ltd. However, the embodiments are not limited thereto, and the third insulating layer 113 may include RCC (Resin Coated Copper) or PID (Photo Imageable Dielectric resin) that do not contain a reinforcing member.

[0157] The third insulating layer 113 can prevent the semiconductor package from bending significantly in a specific direction. For example, the Young's Modulus of the third insulating layer 113 can be less than that of the second insulating layer 112, thereby preventing the semiconductor package from bending. The Young's Modulus of the second insulating layer 112 can be 32 GPa / R.T, and the Young's Modulus of the third insulating layer 113 can be 5.0 GPa / R.T.

[0158] The third insulating layer 113 can be provided in multiple layers. For example, the third insulating layer 113 can be provided with multiple layers, and the fourth insulating layer 114 is interposed therebetween. At this time, the fourth insulating layer 114 is provided between the multiple layers of the third insulating layer 113, and therefore, the interfaces of the multiple layers of the third insulating layer 113 can be distinguished by the fourth insulating layer 114.

[0159] The third insulating layer 113 may include a first region provided below the fourth insulating layer 114, a second region provided on the fourth insulating layer 114, and a third region provided in the through hole TH of the fourth insulating layer 114.

[0160] The thickness of each of the first region and the second region of the third insulating layer 113 in the vertical direction can be less than the thickness of a single layer of the second insulating layer 112 in the vertical direction and greater than the thickness of the first insulating layer 111 in the vertical direction. For example, the thickness in the vertical direction from the upper surface of the third insulating layer 113 to the upper surface of the fourth insulating layer 114 can be less than the thickness of a single layer of the second insulating layer 112 in the vertical direction. For example, the thickness in the vertical direction from the lower surface of the third insulating layer 113 to the lower surface of the fourth insulating layer 114 can be less than the thickness of a single layer of the second insulating layer 112 in the vertical direction. That is, the embodiments can control the thickness of the third insulating layer 113 within the range described below, thereby achieving the best reliability of the semiconductor package.

[0161] For example, the thickness of the third insulating layer 113 in the vertical direction may satisfy the range of 10 μm to 30 μm. Preferably, the thickness of the third insulating layer 113 in the vertical direction may satisfy the range of 12 μm to 28 μm. More preferably, the thickness of the third insulating layer 113 in the vertical direction may satisfy the range of 15 μm to 25 μm.

[0162] If the thickness of the third insulating layer 113 in the vertical direction is less than 10 μm, the bending prevention effect of the semiconductor package presented by the third insulating layer 113 may be insufficient. For example, the third insulating layer 113 is disposed between the fourth insulating layer 114 and the second insulating layer 112, and may have a function of absorbing the impact applied to the semiconductor package while preventing the semiconductor package from significantly bending in a specific direction. Moreover, the third insulating layer 113 is disposed to cover the connection member 200, thereby preventing the impact from being applied to the connection member 200. At this time, if the thickness of the third insulating layer 113 in the vertical direction is less than 10 μm, the impact absorption effect may be insufficient, and thus, the semiconductor package may significantly bend in a specific direction, resulting in a problem of deteriorated operating characteristics or a problem of cracks occurring in the connection member 200. Moreover, if the thickness of the third insulating layer 113 in the vertical direction exceeds 30 μm, it may be difficult to make the semiconductor package thinner due to the increased thickness of the semiconductor package, or the stress applied to the insulating layer adjacent to the third insulating layer 113 may increase.

[0163] The circuit board may include a fourth insulating layer 114 embedded in the third insulating layer 113. For example, the third insulating layer 113 may be disposed above and below the fourth insulating layer 114, and thereby, the fourth insulating layer 114 may have a structure embedded in the third insulating layer 113.

[0164] The fourth insulating layer 114 may include an insulating material different from the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. In this case, the meaning of including different insulating materials may mean that the types of insulating materials provided therein are different, or the width and / or thickness of the insulating materials are different.

[0165] The fourth insulating layer 114 may include a reinforcing member. For example, the fourth insulating layer 114 may include reinforcing fibers or glass fibers. At this time, the reinforcing member of the fourth insulating layer 114 may be the same type of reinforcing fiber or glass fiber as the reinforcing member of the second insulating layer 112.

[0166] However, the number of layers of the reinforcing member provided in the fourth insulating layer 114 and / or the thickness of the reinforcing member provided in the fourth insulating layer 114 may be different from the number of layers of the reinforcing member provided in the second insulating layer 112 and / or the thickness of the reinforcing member provided in the second insulating layer 112.

[0167] Preferably, the number of layers of the reinforcing member provided in the fourth insulating layer 114 may be greater than the number of layers of the reinforcing member provided in the second insulating layer 112. For example, the reinforcing member provided in the second insulating layer 112 may have a structure laminated into one or two layers. Moreover, the reinforcing member provided in the fourth insulating layer 114 may have a structure laminated into 3 to 5 layers. Moreover, the thickness of the reinforcing member provided in the fourth insulating layer 114 in the vertical direction may be greater than the thickness of the reinforcing member provided in the second insulating layer 112 in the vertical direction. This indicates that the fourth insulating layer 114 is an insulating layer positioned at the center of the laminated structure of the plurality of insulating layers of the semiconductor package, and thus can be used as the core layer of the semiconductor package. Moreover, the fourth insulating layer 114 must have a certain level or higher stiffness so that the overall stiffness of the semiconductor package can be increased. Therefore, in the manufacturing process of the semiconductor package, the process of laminating the insulating layer and the process of forming the electrode portion can be stably performed on the upper and lower portions of the fourth insulating layer 114, respectively.

[0168] The thickness of the fourth insulating layer 114 may be greater than the thickness of each single layer of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 in the vertical direction.

[0169] For example, the thickness of the fourth insulating layer 114 in the vertical direction may satisfy the range of 50 μm to 110 μm. Preferably, the thickness of the fourth insulating layer 114 in the vertical direction may satisfy the range of 60 μm to 100 μm. More preferably, the thickness of the fourth insulating layer 114 in the vertical direction may satisfy the range of 70 μm to 90 μm. If the thickness of the fourth insulating layer 114 in the vertical direction is less than 50 μm, the fourth insulating layer 114 may be insufficient to function as a core, and thus, the rigidity of the semiconductor package may be reduced, which may cause problems in the manufacturing process. For example, if the fourth insulating layer 114 cannot be used as a sufficient core layer, warping of the semiconductor package may occur, and problems may occur in that the electrode portion is not formed at the correct positions on the upper and lower portions of the fourth insulating layer 114. Moreover, if the thickness of the fourth insulating layer 114 in the vertical direction exceeds 110 μm, it may be difficult to make the semiconductor package thinner due to an increase in the thickness of the semiconductor package.

[0170] Meanwhile, the fourth insulating layer 114 may include a through hole TH. The through hole TH may be referred to as a receiving portion for receiving the connection member 200 therein. The width of the through hole TH in the horizontal direction may be greater than the width of the connection member 200 in the horizontal direction. For example, the inner wall of the through hole TH of the fourth insulating layer 114 may be spaced apart from the side surface of the connection member 200 by a certain distance. Thus, the fourth insulating layer 114 may not be in contact with the connection member 200. The connection member 200 may be disposed in the through hole TH of the fourth insulating layer 114, and the third insulating layer 113 may be disposed around the connection member.

[0171] The circuit board may include a fifth insulating layer 115 disposed on the third insulating layer 113. The fifth insulating layer 115 may include the same insulating material as the second insulating layer 112. For example, the second insulating layer 112 and the fifth insulating layer 115 may be layers including the same insulating material, and the second insulating layer 112 and the fifth insulating layer 115 may be respectively disposed on their upper and lower portions, with the third insulating layer 113 therebetween. The characteristics of the fifth insulating layer 115 may correspond to the characteristics of the second insulating layer 112, and thus a detailed description thereof will be omitted.

[0172] The circuit board may include a sixth insulating layer 116 disposed on the fifth insulating layer 115. The sixth insulating layer 116 may include the same insulating material as the first insulating layer 111. The characteristics of the sixth insulating layer 116 may correspond to the characteristics of the first insulating layer 111, and thus a detailed description thereof will be omitted.

[0173] As described above, the insulating layers of the circuit board according to the embodiment may be provided with a plurality of layers including a variety of different insulating materials. That is, the fourth insulating layer 114 may be disposed at the center of the circuit board, and the third insulating layer 113, the second insulating layer 112, and the first insulating layer 111 may be sequentially disposed below the fourth insulating layer 114, and the third insulating layer 113, the fifth insulating layer 115, and the sixth insulating layer 116 may be sequentially disposed on the fourth insulating layer 114. That is, the circuit board may be symmetrically provided with the same insulating material on the upper and lower portions of the circuit board based on the fourth insulating layer 114. Based on this, the embodiment may prevent the circuit board from being bent due to the laminated structure of the insulating layers having an upper symmetric structure and a lower symmetric structure.

[0174] Meanwhile, the circuit board includes an electrode portion. The electrode portion may be disposed to penetrate at least some regions of each of the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115.

[0175] For example, the electrode portion may include a first electrode portion 120 that penetrates at least some regions of the second insulating layer 112, a second electrode portion 130 that penetrates at least some regions of the third insulating layer 113, a third electrode portion 140 that penetrates at least some regions of the fourth insulating layer 114, and a fourth electrode portion 160 that penetrates at least some regions of the fifth insulating layer 115.

[0176] Each of the first electrode portion 120, the second electrode portion 130, the third electrode portion 140, and the fourth electrode portion 160 may include a pad portion and a via portion. The pad portion may represent an electrode that transmits a signal in the horizontal direction in each insulating layer, or an electrode connected to the via portion. The via portion may penetrate at least some regions of each insulating layer. Therefore, the via portion connects a plurality of pad portions provided on different layers in the vertical direction. The via portion may be referred to as a via electrode.

[0177] Specifically, referring to Figure 3 , the first electrode portion 120 may include a first pad portion 121 and a first via portion 122.

[0178] The first pad portion 121 of the first electrode portion 120 may be provided on the lower surface of the second insulating layer 112. At least a part of the lower surface of the first pad portion 121 of the first electrode portion 120 may be covered by the first insulating layer 111. Moreover, the first insulating layer 111 may have at least one opening, and at least a part of the first pad portion 121 of the first insulating layer 111 may vertically overlap the opening.

[0179] The first electrode portion 120 may include a first via portion 122 that penetrates at least some regions of the second insulating layer 112 and is connected to the first pad portion 121.

[0180] The first via portion 122 of the first electrode portion 120 may have an inclined surface. For example, the first via portion 122 of the first electrode portion 120 may have an inclined surface whose width gradually decreases from the lower surface of the second insulating layer 112 toward the upper surface of the second insulating layer 112. For example, the inner angle of the side surface of the first via portion 122 with respect to the lower surface of the first via portion 122 may be an acute angle. The vertical cross-sectional shape of the first via portion 122 of the first electrode portion 120 may be a trapezoidal shape. The upper surface of the first via portion 122 of the first electrode portion 120 may have a horizontal width smaller than that of the lower surface of the first via portion 122.

[0181] The outer wall 112S of the first via portion 122 of the first electrode portion 120 may include an uneven portion. Preferably, the outer wall 112S of the first via portion 122 of the first electrode portion 120 may be in contact with the second insulating layer 112. The second insulating layer 112 may include a resin layer 112a and reinforcing fibers 112b.

[0182] The outer wall 112S of the first through-hole portion 122 may include a portion in contact with the resin layer 112a and a portion in contact with the reinforcing fiber 112b. Moreover, the portion of the outer wall 112S of the first through-hole portion 122 in contact with the reinforcing fiber 112b may embed at least a part of the reinforcing fiber 112b.

[0183] Therefore, the outer wall 112S of the first through-hole portion 122 may include a recess 122CP, and the reinforcing fiber 112b of the second insulating layer 112 is disposed in the recess 122CP while horizontally overlapping with the reinforcing fiber 112b. The recess 122CP provided at the outer wall 112S of the first through-hole portion 122 may indicate a portion where the reinforcing fiber 112b of the second insulating layer 112 is provided.

[0184] The vertical length of the recess 122CP provided at the outer wall 112S of the first through-hole portion 122 may correspond to the thickness of the reinforcing fiber 112b provided in the second insulating layer 112. Moreover, a plurality of recesses may be provided at the outer wall 112S of the first through-hole portion 122 and spaced apart in the vertical direction. The number of the plurality of recesses 122CP may correspond to the number of layers of the reinforcing fiber 112b provided in the second insulating layer 112. For example, one or two layers of the reinforcing fiber 112b may be provided in the second insulating layer 112, and one or two recesses 122CP may be provided at the outer wall 112S of the first through-hole portion 122 of the first electrode portion 120. Meanwhile, the inclined surface of the outer wall 112S of the first through-hole portion 122 may change in a portion corresponding to the recess 122CP. However, although not shown in the figure, the second insulating layer 112 may be provided with fillers in addition to the reinforcing fiber 112b. Therefore, in addition to the recess 122CP corresponding to the reinforcing fiber 112b, the outer wall 112S of the first through-hole portion 122 of the first electrode portion 120 may further include recesses and / or protrusions corresponding to the fillers.

[0185] Meanwhile, referring to Figure 4 , the second electrode portion 130 may include a second pad portion 131 and a second through-hole portion 132.

[0186] The second pad portion 131 of the second electrode portion 130 may be provided on the lower surface of the third insulating layer 113. At least a part of the lower surface of the second pad portion 131 of the second electrode portion 130 may be covered by the second insulating layer 112.

[0187] The second electrode portion 130 may include a second through-hole portion 132 that penetrates at least some regions of the third insulating layer 113 and is connected to the second pad portion 131.

[0188] The second through-hole portion 132 of the second electrode portion 130 may have an inclined surface. For example, the second through-hole portion 132 of the second electrode portion 130 may have an inclined surface whose width gradually decreases from the lower surface of the third insulating layer 113 toward the upper surface of the third insulating layer 113. For example, the inner angle of the side surface of the second through-hole portion 132 with respect to the lower surface of the second through-hole portion 132 may be an acute angle. The vertical cross-sectional shape of the second through-hole portion 132 of the second electrode portion 130 may be a trapezoidal shape. The upper surface of the second through-hole portion 132 of the second electrode portion 130 may have a horizontal width smaller than that of the lower surface of the second through-hole portion 132.

[0189] The second through-hole portion 132 of the second electrode portion 130 may be inclined in the same direction as the first through-hole portion 122 of the first electrode portion 120.

[0190] However, the inclined surface of the second through-hole portion 132 of the second electrode portion 130 may be different from the inclined surface of the first through-hole portion 122 of the first electrode portion 120.

[0191] Specifically, the second through-hole portion 132 of the second electrode portion 130 may be provided in the third insulating layer 113 that does not have reinforcing fibers. Therefore, when forming a through-hole penetrating the third insulating layer 113, the difference between the upper surface width and the lower surface width of the through-hole may be small.

[0192] Therefore, the inclined surface angle of the second through-hole portion 132 of the second electrode portion 130 may be greater than the inclined surface angle of the first through-hole portion 122 of the first electrode portion 120. For example, the slope of the side surface of the second through-hole portion 132 of the second electrode portion 130 with respect to the lower surface of the second through-hole portion 132 of the second electrode portion 130 may be greater than the inclined surface angle of the side surface of the first insulating layer 111 with respect to the lower surface of the first through-hole portion 122 of the first electrode portion 120. Moreover, the width of the second through-hole portion 132 of the second electrode portion 130 in the horizontal direction may be smaller than the width of the first through-hole portion 122 of the first electrode portion 120 in the horizontal direction. At this time, the second electrode portion 130 may include an electrode connected to a connection member 200 embedded in the fourth insulating layer 114. Moreover, the connection member 200 may be provided with fine terminals. Therefore, the embodiment can provide an electrode portion in the third insulating layer 113 that is connected to the terminal of the connection member 200. Thus, the embodiment can miniaturize the second electrode portion 130 connected to the connection member 200 while accurately positioning the second electrode portion 130 in a region corresponding to the terminal of the connection member 200. In addition, the embodiment can smoothly transmit a signal transmitted from the connection member 200 through the second electrode portion 130, thereby minimizing signal transmission loss and accordingly improving electrical characteristics.

[0193] Meanwhile, the second through-hole portion 132 of the second electrode portion 130 may not have a recess corresponding to the first through-hole portion 122 of the first electrode portion 120. For example, the second through-hole portion 132 of the second electrode portion 130 may not overlap with the reinforcing fibers in the horizontal direction. However, the third insulating layer 113 may be provided with a filler, and the outer surface of the second through-hole portion 132 may include recesses and / or protrusions in contact with the filler.

[0194] Meanwhile, referring to Figure 5 , the fourth insulating layer 114 may be provided with a third electrode portion 140. The third electrode portion 140 may include a third pad portion 141 and a third through-hole portion 142.

[0195] The third pad portions 141 of the third electrode portion 140 may be respectively provided on the upper surface and the lower surface of the fourth insulating layer 114. Moreover, the third through-hole portion 142 of the third electrode portion 140 may penetrate the fourth insulating layer 114 while being connected to the third pad portion 141 of the third insulating layer 113.

[0196] The third through-hole portion 142 of the third electrode portion 140 may include a plurality of inclined surfaces.

[0197] The third through-hole portion 142 of the third electrode portion 140 may include a first inclined surface 142S1 adjacent to the upper surface of the fourth insulating layer 114 and having a width gradually decreasing toward the lower surface of the fourth insulating layer 114. Moreover, the third through-hole portion 142 of the third electrode portion 140 may include a second inclined surface 142S2 adjacent to the lower surface of the fourth insulating layer 114 and having a width gradually decreasing toward the upper surface of the fourth insulating layer 114. The first inclined surface 142S1 and the second inclined surface 142S2 may be different from each other. For example, the first inclined surface 142S1 and the second inclined surface 142S2 may be inclined in different directions.

[0198] The embodiment may allow the third through-hole portion 142 of the third electrode portion 140 to include a plurality of inclined surfaces. Thereby, the embodiment can enable the third through-hole portion 142 of the third electrode portion 140 to easily penetrate the fourth insulating layer 114 having a relatively large thickness and relatively large reinforcing fibers. Thereby, the embodiment can solve the problem that the third through-hole portion 142 of the third electrode portion 140 does not penetrate the fourth insulating layer 114, and thus can improve the electrical reliability.

[0199] Meanwhile, the fourth insulating layer 114 may include a resin layer 114a and reinforcing fibers 114b. Moreover, the third through-hole portion 142 of the third electrode portion 140 may include a recess 142CP horizontally overlapping with the reinforcing fibers 114b of the fourth insulating layer 114.

[0200] At this time, the recess 122CP provided in the first through-hole 122 of the first electrode portion 120 may be different from the recess 142CP provided in the third through-hole 142 of the third electrode portion 140.

[0201] For example, the vertical length of the recess 142CP provided in the third through-hole 142 of the third electrode portion 140 in the vertical direction and / or the number of the recesses 142CP may be different from the vertical length of the recess 122CP provided in the first through-hole 122 of the first electrode portion 120 in the vertical direction and / or the number of the recesses 122CP.

[0202] Specifically, the vertical length of the recess 142CP provided in the third through-hole 142 of the third electrode portion 140 in the vertical direction may be greater than the vertical length of the recess 122CP provided in the first through-hole 122 of the first electrode portion 120 in the vertical direction. Moreover, the number of the recesses 142CP provided in the third through-hole 142 of the third electrode portion 140 may be greater than the number of the recesses 122CP provided in the first through-hole 122 of the first electrode portion 120.

[0203] Meanwhile, the fourth electrode portion 160 may include a fourth pad portion 161 and a fourth through-hole 162. The fourth pad portion 161 and the fourth through-hole 162 of the fourth electrode portion 160 may have a structure corresponding to the first pad portion 121 and the second through-hole 122 of the first electrode portion 120. For example, the fourth pad portion 161 and the fourth through-hole 162 of the fourth electrode portion 160 may have a structure symmetric to the first pad portion 121 and the second through-hole 122 of the first electrode portion 120.

[0204] Moreover, the circuit board may include a protruding electrode portion 170. The protruding electrode portion 170 may include a protruding portion 171 protruding onto the sixth insulating layer 116 and a through-hole 172 penetrating at least some regions of the sixth insulating layer 116.

[0205] The protruding electrode portion 170 may be a columnar bump connected to the semiconductor device.

[0206] That is, since the width of the terminals of the semiconductor device coupled to the circuit board and the pitch of the terminals are miniaturized, when the semiconductor device is mounted using a conductive adhesive such as solder, diffusion of the conductive adhesive may occur, and this may cause a problem in that a plurality of conductive adhesives are connected to each other. Accordingly, the embodiment may perform Thermal Compression Bonding to reduce the volume of the conductive adhesive. At this time, if the protruding electrode portion 170 is not provided on the circuit board, it may be difficult to reduce the volume of the conductive adhesive. This may be because the height of the electrode on which the conductive adhesive is provided is lower than the upper surface of the sixth insulating layer 116, and thus the volume of the conductive adhesive increases by the difference between the height of the electrode and the height of the insulating layer.

[0207] Accordingly, the embodiment may include a protruding electrode portion 170 having a protruding structure to ensure alignment with the terminals of the semiconductor device and having a diffusion prevention ability to prevent an intermetallic compound (IMC) formed between the conductive adhesive and the electrode portion from diffusing into the circuit board.

[0208] Meanwhile, the circuit board may include dummy electrodes 150. The dummy electrodes 150 may include a first dummy electrode 151 provided on the upper surface of the fourth insulating layer 114 and a second dummy electrode 152 provided on the lower surface of the fourth insulating layer 114.

[0209] Referring to Figure 6 , the dummy electrodes 150 may be provided to surround a through hole TH provided in the fourth insulating layer 114. For example, the first dummy electrode 151 of the dummy electrodes 150 may be provided to surround an upper region of the through hole TH. Moreover, the second dummy electrode 152 of the dummy electrodes 150 may be provided to surround a lower region of the through hole TH.

[0210] Each of the first dummy electrode 151 and the second dummy electrode 152 of the dummy electrodes 150 may have an annular shape. Each of the first dummy electrode 151 and the second dummy electrode 152 of the dummy electrodes 150 may have a closed-loop shape. Each of the first dummy electrode 151 and the second dummy electrode 152 of the dummy electrodes 150 may have a shape corresponding to the planar shape of the through hole TH.

[0211] The dummy electrode 150 may have a first width W1. The first width W1 of the dummy electrode 150 may satisfy the range of 80 μm to 120 μm. Preferably, the first width W1 of the dummy electrode 150 may satisfy the range of 85 μm to 115 μm. More preferably, the first width W1 of the dummy electrode 150 may satisfy the range of 90 μm to 110 μm. If the first width W1 of the dummy electrode 150 is less than 80 μm, damage to a part of the fourth insulating layer 114 may occur during the process of forming the through hole TH. Moreover, in order to prevent damage to a part of the fourth insulating layer 114, the position of the laser must be adjusted during the process of forming the through hole TH, and thus, the inner wall of the through hole TH may have an inclined surface significantly different from 90 degrees. Also, if the first width W1 of the dummy electrode 150 exceeds 120 μm, the dummy area in the fourth insulating layer 114 increases, and thus, it may be difficult to thin the semiconductor package.

[0212] Meanwhile, the width of the through hole TH may be greater than the width of the connection member 200. Preferably, the area of the through hole TH may be greater than the area of the connection member 200.

[0213] For example, the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connection member 200 may satisfy the range of 75 μm to 120 μm. Preferably, the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connection member 200 may satisfy the range of 75 μm to 120 μm. More preferably, the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connection member 200 may satisfy the range of 75 μm to 120 μm.

[0214] If the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connection member 200 is less than 75 μm, the connection member 200 may contact the side wall of the through hole TH due to process errors in the process of embedding the connection member 200, and thus the connection member 200 may be damaged. Also, if the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connection member 200 exceeds 120 μm, the dummy area increases the horizontal distance, and thus it may be difficult to thin the semiconductor package.

[0215] Meanwhile, referring to Figure 7 , the side wall 114S of the through hole TH may be perpendicular to the upper surface or the lower surface of the fourth insulating layer 114. This may be due to the positions of the first dummy electrode 151 and the second dummy electrode 152 provided in the fourth insulating layer 114.

[0216] The first dummy electrode 151 may include a side surface 151S surrounding the through hole TH. Moreover, the second dummy electrode 152 may include a side surface 152S surrounding the through hole TH.

[0217] Moreover, the side surface 151S of the first dummy electrode 151 can be positioned in the same plane as the side wall 114S of the through hole TH. Moreover, the side surface 152S of the second dummy electrode 152 can be positioned in the same plane as the side wall 114S of the through hole TH. In addition, the side surface 151S of the first dummy electrode 151 can be positioned in the same plane as the side surface 152S of the second dummy electrode 152.

[0218] In other words, the side surfaces of each of the first dummy electrode 151 and the second dummy electrode 152 can be vertically positioned in the same plane. Thus, the inner wall 114S of the through hole TH provided in the fourth insulating layer 114 can be positioned in the same plane as the side surfaces of each of the first dummy electrode 151 and the second dummy electrode 152. Thereby, the embodiment can have an upper and lower width substantially the same as that of the through hole TH. Therefore, the embodiment can minimize the increase in the dead zone caused by the difference between the upper width and the lower width of the through hole TH, and thus can make the semiconductor package thinner.

[0219] Meanwhile, according to the shape or application design of the connection member 200, the embodiment can allow the side wall 114S of the through hole TH to have a certain inclined surface.

[0220] For example, referring to Figure 8 , the side surface 151S of the first dummy electrode 151 can be set to be vertically misaligned with the side surface 152S of the second dummy electrode 152. The side surface 151S of the first dummy electrode 151 can be positioned closer to the connection member 200 than the side surface 152S of the second dummy electrode 152. Thereby, the side wall 114S of the through hole TH can have an inclined surface whose width gradually decreases from the lower surface to the upper surface of the fourth insulating layer 114.

[0221] For example, referring to Figure 9 , the side surface 151S of the first dummy electrode 151 can be set to be vertically misaligned with the side surface 152S of the second dummy electrode 152. The side surface 151S of the first dummy electrode 151 can be spaced farther from the connection member 200 than the side surface 152S of the second dummy electrode 152. Thereby, the side wall 114S of the through hole TH can have an inclined surface whose width gradually increases from the lower surface to the upper surface of the fourth insulating layer 114.

[0222] Meanwhile, as shown in the previous figures, the upper surface of the first dummy electrode 151 can be positioned in the same plane as the upper surface of the terminal 210 of the connection member 200. However, it is difficult to precisely match the thickness of the connection member 200 and the thickness of the fourth insulating layer 114, and it may be difficult to precisely match the thickness of the terminal 210 and the thickness of the first dummy electrode 151.

[0223] Thus, in the embodiment, the upper surface of the terminal 210 of the connection member 200 and the upper surface of the first dummy electrode 151 may have a step.

[0224] Referring Figure 10 , the upper surface of the terminal 210 of the connection member 200 may be positioned higher than the upper surface of the first dummy electrode 151 by a first height H1. At this time, the first height H1 may be less than the thickness of the first dummy electrode 151 in the vertical direction. Preferably, the first height H1 may be 8 μm or less. More preferably, the first height H1 may be 5 μm or less. Moreover, referring Figure 11 , the upper surface of the terminal 210 of the connection member 200 may be positioned lower than the upper surface of the first dummy electrode 151 by a first height H1. At this time, the first height H1 may be less than the thickness of the first dummy electrode 151 in the vertical direction. Preferably, the first height H1 may be 8 μm or less.

[0225] That is, if the step between the upper surface of the terminal 210 of the connection member 200 and the upper surface of the first dummy electrode 151 is greater than 8 μm, it may be difficult to ensure that the first electrode connected to the terminal 210 of the connection member 200 and the second electrode horizontally overlapping the first electrode in the third electrode portion 140 have a uniform height, and thus the mechanical reliability and physical reliability of the semiconductor package may deteriorate.

[0226] However, in the embodiment, if the upper surface of the terminal 210 of the connection member 200 is positioned lower than the upper surface of the first dummy electrode 151, voids may occur during the process of filling the through hole TH of the fourth insulating layer 114 with the third insulating layer 113. Therefore, the upper surface of the terminal 210 of the connection member 200 is positioned higher than the upper surface of the first dummy electrode 151, thereby minimizing the occurrence of voids.

[0227] Meanwhile, referring Figure 12 , compared with the Figure 2 circuit board, the circuit board of the second embodiment may have a different structure of the electrode portion.

[0228] For example, the circuit board may include a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, a fourth insulating layer 114, a fifth insulating layer 115, and a sixth insulating layer 116.

[0229] Moreover, the circuit board may include a connection member 200 embedded in the through hole TH provided in the fourth insulating layer 114.

[0230] Moreover, the circuit board may include a first electrode portion 120, and the first electrode portion 120 includes a first pad portion 121 and a first through portion 122. Moreover, the circuit board may include a second electrode portion 130, and the second electrode portion 130 includes a second pad portion 131 and a second through portion 132. Moreover, the circuit board may have a third electrode portion 140 including a third pad portion 141 and a third through portion 142. Moreover, the circuit board may have a fourth electrode portion 160 including a fourth pad portion 161 and a fourth through portion 162. Moreover, the circuit board may have a dummy electrode portion 150 including a first dummy electrode 151 and a second dummy electrode 152.

[0231] At this time, in the electrode portion of the second embodiment, the electrode portions provided in the second insulating layer 112 and the fifth insulating layer 115 and including the same insulating material may be different from the electrode portions of the first embodiment.

[0232] For example, the circuit board may have a first electrode portion 120 and a fourth electrode portion 160 provided at the outermost layer among the plurality of electrode portions. At this time, the first pad portion 121 of the first electrode portion 120 of the first embodiment may have a structure protruding below the lower surface of the second insulating layer 112. Moreover, the fourth pad portion 161 of the fourth electrode portion 160 of the first embodiment may have a structure protruding above the upper surface of the fifth insulating layer 115.

[0233] Differently, the first pad portion 121 of the first electrode portion 120 of the second embodiment may have a structure embedded in the second insulating layer 112. Moreover, the fourth pad portion 161 of the fourth electrode portion 160 of the second embodiment may have a structure embedded in the fifth insulating layer 115.

[0234] Here, the fact that the first pad portion has an embedded structure may mean that at least a part of the side surface of the first pad portion 121 is covered by the second insulating layer 112. Moreover, the fact that the first pad portion has an embedded structure may mean that the upper surface of the first pad portion 121 is positioned higher than the lower surface of the second insulating layer 112.

[0235] Moreover, the fact that the fourth pad portion has an embedded structure may mean that at least a part of the side surface of the fourth pad portion 141 is covered by the fifth insulating layer 115. Moreover, the fact that the fourth pad portion has an embedded structure may mean that the lower surface of the fourth pad portion 151 is positioned lower than the upper surface of the fifth insulating layer 115.

[0236] Accordingly, the embodiment can prevent the pad portions provided at the outermost layer of the circuit board from collapsing or peeling off by the structure of embedding the pad portions in the insulating layer, thereby being able to further optimize the pad portions. In addition, the embodiment can reduce the thickness of the circuit board by the embedding depth of the pad portions in the insulating layer, thereby being able to realize thinning of the semiconductor package.

[0237] Moreover, the through-holes provided in each of the electrode portions of the embodiment may be arranged to be misaligned rather than aligned on the same vertical line. Thereby, the embodiment can improve the design freedom in forming the through-holes.

[0238] Meanwhile, in Figure 12 it, the lower surface of the first pad portion 121 is shown to be located on the same plane as the lower surface of the second insulating layer 112, but it is not limited thereto.

[0239] For example, in another embodiment, the lower surface of the first pad portion 121 may be located at a position lower than the lower surface of the second insulating layer 112. In addition, in another embodiment, the upper surface of the fourth pad portion 161 may be higher than the upper surface of the fifth insulating layer 115. In this case, a conductive adhesive material may be provided on the lower surface of the first pad portion 121 and / or the upper surface of the fourth pad portion 161, and at this time, the first pad portion 121 and the fourth pad portion 161 may be used as the protruding electrodes in the first embodiment. Thereby, the alignment with the conductive adhesive material can be improved while preventing the diffusion of the conductive adhesive material.

[0240] Moreover, in another embodiment, the lower surface of the first pad portion 121 may be higher than the lower surface of the second insulating layer 112. Moreover, in another embodiment, the upper surface of the fourth pad portion 161 may be lower than the upper surface of the fifth insulating layer 115. In this embodiment, the volume of the conductive adhesive material provided on the first pad portion 121 and / or the fourth pad portion 161 may be increased compared with the previous embodiment while preventing the diffusion of the conductive adhesive material, thereby further improving the bonding strength with the semiconductor device.

[0241] The semiconductor package of the embodiment includes a first insulating layer, a second insulating layer provided on the first insulating layer, a third insulating layer provided on the second insulating layer, a fourth insulating layer embedded in the third insulating layer, and a fifth insulating layer provided on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are formed of different materials, the second insulating layer and the fifth insulating layer are formed of the same material, and the thickness in the vertical direction between the upper surface of the fourth insulating layer and the upper surface of the third insulating layer may be smaller than the thickness in the vertical direction of the second insulating layer. Thereby, the embodiment can reduce the thickness of the semiconductor package while preventing the semiconductor package from bending in a specific direction by using the third insulating layer.

[0242] Specifically, the third insulating layer may have a relatively low Young's modulus, thereby suppressing the occurrence of warpage acting on the semiconductor package and further preventing the semiconductor package from being significantly bent in a specific direction while absorbing the impact applied to the semiconductor package. Accordingly, the embodiment may solve the problem of deterioration of operating characteristics due to the significant bending of the semiconductor package in a specific direction, and may further solve the problem of damage to the connection member provided in the third insulating layer due to the impact. Moreover, the embodiment may use the third insulating layer to dispose the electrode portion connected to the connection member, thereby improving the alignment between the electrode portion and the connection member.

[0243] Moreover, the fourth insulating layer may include a through hole, and the connection member may be disposed in the through hole. Moreover, the first dummy electrode may be disposed on the upper surface of the fourth insulating layer, and the second dummy electrode may be disposed on the lower surface of the fourth insulating layer. At least one side surface of the first dummy electrode and the second dummy electrode may be located in the same plane as the side wall of the through hole. The first dummy electrode and the second dummy electrode may be electrodes for forming the through hole by a laser process. In addition, the embodiment may use the first dummy electrode and the second dummy electrode to make the upper width and the lower width of the through hole substantially the same, thereby reducing the area of the dead zone that increases the difference between the upper width and the lower width. Accordingly, the embodiment may reduce the thickness of the semiconductor package.

[0244] Moreover, the embodiment may change the shape of the through hole by misaligning the first dummy electrode and the second dummy electrode in the vertical direction. Accordingly, the embodiment may freely change the shape of the through hole according to the shape of the connection member, thereby increasing the design freedom.

[0245] Moreover, the embodiment may have a step between the upper surface of the terminal of the connection member and the upper surface of the first dummy electrode, and manage the step to keep it below a specific level. Accordingly, the embodiment may increase the connection alignment between the electrode portion and the terminal, and further minimize the voids generated during the process of filling the through hole with the insulating material.

[0246] On the other hand, when a circuit board having the above characteristics of the present invention is used in IT devices or home appliances such as smart phones, server computers, TVs, etc., functions such as signal transmission or power can be stably performed. For example, when the circuit board having the characteristics of the present invention performs the semiconductor package function, the circuit board may be used to safely protect the semiconductor chip from external moisture or contaminants, or alternatively, may solve the problems of leakage current, electrical short circuit between terminals, and electrical open circuit of the terminals provided to the semiconductor chip. Moreover, when responsible for the function of signal transmission, the noise problem can be solved. Accordingly, the circuit board having the above characteristics of the present invention can maintain the stable function of the IT device or the home appliance, so that the entire product and the circuit board applying the present invention can achieve function unity or technical linkage with each other.

[0247] When the circuit board having the features of the present invention described above is used in a transportation device such as a vehicle, the problem of distortion of signals transmitted to the transportation device can be solved. Alternatively, the safety of the transportation device can be further improved by securely protecting the semiconductor chip that controls the transportation device from external influences and solving the problems of leakage current or electrical short circuit between terminals or electrical open circuit of the terminals supplied to the semiconductor chip. Therefore, the transportation device and the circuit board applying the present invention can achieve functional integrity or technical linkage with each other.

[0248] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, those of ordinary skill in the art can combine or modify the features, structures, effects, etc. described in each embodiment with other embodiments. Therefore, it should be understood that the content related to such combinations and such modifications is included within the scope of the embodiments.

[0249] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art to which the embodiments belong can understand that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Moreover, it should be understood that the differences related to such changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: A first insulating layer; A second insulating layer, the second insulating layer being disposed on the first insulating layer; A third insulating layer, the third insulating layer being disposed on the second insulating layer; A fourth insulating layer, the fourth insulating layer being embedded in the third insulating layer; And A fifth insulating layer, the fifth insulating layer being disposed on the third insulating layer, Wherein, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are made of different materials, Wherein, the second insulating layer and the fifth insulating layer are made of the same material, and Wherein, the thickness in the vertical direction between the upper surface of the fourth insulating layer and the upper surface of the third insulating layer is less than the thickness of the second insulating layer in the vertical direction.

2. The circuit board according to claim 1, wherein, The thickness in the vertical direction between the lower surface of the fourth insulating layer and the lower surface of the third insulating layer is less than the thickness of the second insulating layer in the vertical direction.

3. The circuit board according to claim 1, wherein, The second insulating layer includes a first resin layer and a first reinforcing member disposed within the first resin layer.

4. The circuit board according to claim 3, wherein, The fourth insulating layer includes a second resin layer and a second reinforcing member disposed within the second resin layer, and Wherein, the number of layers or the thickness of the first reinforcing member is different from the number of layers or the thickness of the second reinforcing member.

5. The circuit board according to claim 4, wherein, The first reinforcing member and the second reinforcing member include glass fibers or reinforcing fibers different from the filler.

6. The circuit board according to claim 5, wherein The number of layers of the first reinforcing member is less than the number of layers of the second reinforcing member.

7. The circuit board according to claim 5, wherein, The thickness of a single layer of the first reinforcing member is less than the thickness of a single layer of the second reinforcing member.

8. The circuit board according to claim 5, wherein, The third insulating layer does not have a reinforcing member.

9. The circuit board according to claim 8, further comprising: A first electrode portion, the first electrode portion penetrating through at least some regions of the second insulating layer; A second electrode portion, the second electrode portion penetrating through at least some regions of the third insulating layer; And A third electrode portion, the third electrode portion penetrating through the fourth insulating layer.

10. The circuit board according to claim 9, wherein, The first electrode portion includes a first pad portion and a first through portion, and Wherein, the first through portion has an inclined surface, and the width of the inclined surface gradually decreases from the lower surface of the second insulating layer towards the upper surface of the second insulating layer.

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