Automatic Simulation Method and System for Combinational Logic Loops Based on 55nm Process

Abstract

The present invention belongs to the technical field of digital circuit simulation design, and particularly relates to a method and system for automatically simulating combinational logic loops based on a 55nm process. First, all strongly connected components in the test cases are found through depth-first search; then, the maximum flow-minimum cut theorem is used to find the strongly connected components that cannot have continuous oscillations and the strongly connected components that may generate continuous oscillations, and the oscillation conditions are analyzed; finally, registers are inserted at the nodes where oscillations may occur to destroy all the strongly connected components that may generate continuous oscillations, thereby realizing the automatic detection of unexpected combinational logic loops in digital gate circuits, analyzing the triggering conditions, and providing the addresses of the fewest register insertions for disconnecting the loops, helping designers discover design problems.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuit simulation design, and particularly relates to an automatic simulation method and system for combinational logic loops based on a 55nm process. Background Art

[0002] Combinational logic loops are commonly found in basic gate circuit modules. Unintended combinational logic loops may cause multiple driving or signal oscillation, resulting in increased circuit power consumption and functional errors. Combinational logic loops are difficult to analyze and calculate by static timing analysis tools, which may cause the simulator to enter an infinite loop.

[0003] At the 55nm process node, the reduction of the feature size of the gate circuit leads to an increase in leakage current and an acceleration of the signal propagation speed, which makes the timing problems caused by combinational logic loops more prominent. As a special structure that starts from a certain combinational logic unit and finally forms a closed path, the positive feedback type of combinational logic loops is commonly found in circuits such as latches and SRAM memory cells, while the negative feedback type is widely used in oscillator circuit design. It should be noted that in advanced process nodes, non-functional combinational logic loops may cause the following new risks:

[0004] 1. Difficult timing convergence: Due to the sub-microsecond characteristics of gate delay under the 55nm process, the loop may form an unpredictable cumulative propagation delay.

[0005] 2. Abnormal power consumption surge: The reduction of the process feature size causes the dynamic power consumption during loop oscillation to increase exponentially.

[0006] 3. Signal integrity degradation: The parasitic parameters of the metal interconnect layer will exacerbate the attenuation distortion of the loop signal.

[0007] There are two main technical bottlenecks in existing analysis methods: First, traditional static timing analysis tools are difficult to accurately model the non-linear transmission gate effect under the 55nm process; Second, existing loop detection algorithms do not consider the threshold voltage shift problem caused by advanced process manufacturing deviations, which may result in a misjudgment rate of up to 12.7%. Especially when dealing with complex SoCs containing multi-voltage domain designs, existing methods cannot effectively identify the potential risks of cross-voltage domain combinational logic loops. Summary of the Invention

[0008] The present invention provides an automatic simulation method and system for combinational logic loops based on a 55nm process.

[0009] The technical solution of the present invention is as follows:

[0010] The present invention provides an automatic simulation method for combinational logic loops based on a 55nm process, including the following steps:

[0011] S1: Obtain the gate instance data of the combinational logic circuit. Take each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph. Based on the directed graph, perform a depth-first search to identify strongly connected components.

[0012] S2: Use the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get a set of nodes. Analyze each node in the set of nodes separately, traverse forward, represent each node as a function of external inputs and the node itself, construct a logical expression, and judge the possibility of oscillation of the node according to the logical expression to obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate. Take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation.

[0013] S3: Insert registers at the nodes that may oscillate to break all strongly connected components.

[0014] In step S2, using the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get a set of nodes is specifically as follows:

[0015] Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity. After recording all in - points as super in - points and all out - points as super out - points, calculate the maximum flow value from the super in - points to the super out - points as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

[0016] The directed graph obtained in step S1 is implemented through the BuildGraph() function, specifically as follows:

[0017] After recording the name and the belonging gate number of each port, assign a unique number to each input and output port as the node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph.

[0018] In step S1, based on the directed graph, performing a depth - first search to identify strongly connected components is specifically as follows:

[0019] For unvisited nodes, call the dfs() function to obtain the DFS traversal sequence number and the backtracking value of the unvisited node.

[0020] Traverse the neighbor nodes of the unvisited node. If the neighbor node is unvisited, recursively process the neighbor node and take the minimum value of the backtracking value of the neighbor node and the unvisited node as the new backtracking value of the unvisited node.

[0021] If the neighbor node is in the stack, then use the minimum value of the DFS traversal sequence number of the neighbor node and the backtracking value of the unvisited node as the new backtracking value of the unvisited node;

[0022] When backtracking to an unvisited node, if the new backtracking value of the unvisited node is equal to the DFS traversal sequence number of the unvisited node, then all the nodes from the to the top of the stack in the stack form a strongly connected component.

[0023] Furthermore, the recording of the name of each port and the belonging gate number is implemented through the port and mpbh arrays; the connection relationship between the input port and the output port is recorded using the to array and the Edge structure.

[0024] The present invention also provides a combinational logic loop automatic simulation system based on a 55nm process, including:

[0025] Strongly connected component identification module: used to obtain the gate instance data of the combinational logic circuit, use each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input port and the output port to obtain a directed graph; based on the directed graph, perform a depth-first search to identify strongly connected components;

[0026] Analysis module: use the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes; analyze each node in the set of nodes separately, traverse forward, represent each node as a function of external inputs and the node, construct a logical formula, and judge the possibility of oscillation of the node according to the logical formula to obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation;

[0027] Repair module: used to insert registers at the nodes that may oscillate to destroy all strongly connected components.

[0028] The analysis module uses the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes, specifically:

[0029] Split each node of the strongly connected component into an in-point and an out-point, set the capacity between the in-point and the out-point split from the same node to 1, and set the capacity between nodes to positive infinity; after all in-points are recorded as super in-points and all out-points are recorded as super out-points, calculate the maximum flow value from the super in-point to the super out-point as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

[0030] The strongly connected component identification module performs a depth-first search, which is implemented through the dfs() function and the tarjan() function.

[0031] Beneficial effects: At the 55nm process node, the present invention first finds all strongly connected components in the test cases through depth-first search; then uses the maximum flow-minimum cut theorem to find the strongly connected components that cannot have continuous oscillations and the strongly connected components that may generate continuous oscillations, and analyzes the conditions for oscillations; finally, inserts registers at the nodes where oscillations may occur to break all the strongly connected components that may generate continuous oscillations, thereby realizing the automatic detection of unexpected combinational logic loops in digital gate circuits, analyzing the triggering conditions, providing the minimum register insertion addresses for disconnecting the loops, and helping designers discover design problems. Moreover, this method has a low time complexity, high detection efficiency, and high detection accuracy. Detailed implementation manner

[0032] The following embodiments are intended to illustrate the present invention rather than further limit the present invention.

[0033] At the 55nm process node, the present invention provides a method for automatically simulating combinational logic loops based on the 55nm process, including the following steps:

[0034] S1: Obtain the gate instance data of the combinational logic circuit, use each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input port and the output port to obtain a directed graph; based on the directed graph, perform a depth-first search to identify strongly connected components.

[0035] The specific operations are as follows:

[0036] First, read the simulation data through the vpi interface to obtain the gate instance information of the combinational logic circuit in the.v file. During this process, since the instances are independent of each other, multi-threading can be used to process different instances. Therefore, to speed up the reading speed, parallel traversal is used to accelerate the reading task using a multi-core CPU.

[0037] After reading the gate instances, construct a directed graph. Preferably, it is implemented through the BuildGraph() function. Specifically:

[0038] After recording the name and the belonging gate number of each port, assign a unique number to each input and output port as the node (V) of the graph, and construct the edge (E) of the graph according to the connection relationship between the input port and the output port to obtain a directed graph.

[0039] Among them, regarding recording port information, the name and the belonging gate number of each port are recorded through the port and mpbh arrays. The to array and the Edge structure are used to record the connection relationship between the ports.

[0040] The BuildGraph() function is as follows:

[0041] void BuildGraph(){ / / build graph

[0042] / / get V id

[0043] / / Number the ports for convenient graph construction

[0044] for(int i = 1;i<= r;i += 1){ / / Bind the gates to the output ports

[0045] if(!mp[outp[i]])mp[outp[i]]= ++tot,port[tot] = outp[i], mpbh[tot]= i;

[0046] }

[0047] for(int i = 1;i<= r;i += 1){

[0048] for(int j = 0;j<siz[i];j += 1) / / At this time, the unbound ones are all input ports that are not used as the output ports of the gates (i.e., the input ports of the entire circuit from the outside world), so they are not bound

[0049] if(!mp[inp[i][j]])mp[inp[i][j]]= ++tot,port[tot] = inp[i][j];

[0050] }

[0051] / / build E Build the graph

[0052] for(int i = 1;i<= r;i += 1)

[0053] for(int j = 0;j<siz[i];j += 1){ / / input ->output

[0054] int u = mp[inp[i][j]],v = mp[outp[i]];

[0055] to[u].push_back(Edge(v,type[i]));

[0056] }

[0057] }

[0058] Finally, based on the directed graph, perform a depth-first search to identify strongly connected components.

[0059] The depth-first search can be performed using the Tarjan algorithm. The specific operations are as follows:

[0060] For an unvisited node u, call the dfs() function to obtain the DFS traversal sequence number dfn[u] and the backtracking value low[u] of this unvisited node;

[0061] Traverse the neighbor node v of the unvisited node u. If the neighbor node is not visited, recursively process this neighbor node v, and use the minimum value of the backtracking values of this neighbor node and the unvisited node as the new backtracking value of the unvisited node, denoted as low[u]=min(low[u],low[v]);

[0062] If the neighbor node is in the stack, use the minimum value of the DFS traversal sequence number of this neighbor node and the backtracking value of the unvisited node as the new backtracking value of the unvisited node, denoted as low[u]=min(low[u],dfn[v]);

[0063] When backtracking to the unvisited node u, if the new backtracking value of the unvisited node is equal to the DFS traversal sequence number of this unvisited node, that is, low[u]==dfn[u], then all the nodes from u to the top of the stack in the stack form a strongly connected component.

[0064] In this process, two functions are used:

[0065] 1. dfs(int u): The depth-first search function is used to traverse the nodes in the graph and calculate the dfn and low values of each node through the Tarjan algorithm, so as to find the strongly connected components. The code is as follows:

[0066] void dfs(int u) {

[0067] dfn[u] = low[u]= ++tim; / / Allocate timestamp

[0068] st[++top] = u; / / Push into the stack

[0069] in[u] = 1; / / Mark as in the stack

[0070] for (int i = 0; i<to[u].size(); i += 1) {

[0071] int v = to[u][i].v; / / Adjacent node

[0072] if (!dfn[v]) { / / Not visited

[0073] dfs(v);

[0074] low[u] = min(low[u], low[v]); / / Update low[u]

[0075] } else if (in[v]) { / / Already in the stack

[0076] low[u] = min(low[u], dfn[v]); / / Update low[u]

[0077] }

[0078] }

[0079] if (low[u] == dfn[u]) { / / Find a strongly connected component

[0080] if (st[top] != u) { / / Size of the strongly connected component > 1

[0081] cnt++; / / Increase the strongly connected component number

[0082] while (st[top] != u) { / / Pop nodes from the stack

[0083] col[st[top]] = cnt; / / Assign a number

[0084] scc[cnt].push_back(st[top]); / / Record the node

[0085] in[st[top]] = 0; / / Mark not in the stack

[0086] top--;

[0087] }

[0088] col[u] = cnt; / / Assign a number

[0089] scc[cnt].push_back(u); / / Record the node

[0090] }

[0091] top--; / / Pop u

[0092] in[u] = 0; / / Mark not in the stack

[0093] }

[0094] }

[0095] 2. tarjan(): The main function that traverses all unvisited nodes and calls the dfs function to find all strongly connected components. The code is as follows:

[0096] void tarjan() {

[0097] for (int i = 1; i <= tot; i += 1) { / / Traverse all nodes

[0098] if (!dfn[i]) dfs(i); / / Call dfs if not visited

[0099] }

[0100] }

[0101] S2: Use the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get the node set. Analyze each node in the node set separately, traverse forward, represent each node as a function of external inputs and this node, construct a logical formula, judge the possibility of oscillation of this node according to the logical formula, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and take the union of the oscillation conditions of all nodes that may oscillate to get the external input conditions for oscillation.

[0102] After obtaining the strongly connected components, to simplify the operation and shorten the running time, a node set M needs to be obtained, requiring the minimum number of nodes in the set M and at least one node in the set M for each strongly connected component. For this purpose, the present invention uses the maximum flow - minimum cut theorem to solve, transforms this problem into a maximum flow problem, and obtains the minimum vertex cover by finding the minimum cut.

[0103] Preferably, using the maximum flow - minimum cut theorem, obtain the minimum vertex cover of all strongly connected components and get the node set, specifically:

[0104] Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity; after marking all in - points as super in - points and all out - points as super out - points, calculate the maximum flow value from the super in - point to the super out - point, which is used as the capacity of the minimum cut, that is, the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the node set.

[0105] After obtaining the node set M, analyze each found node separately and traverse forward. Since the entire circuit structure is a strongly connected component, each node can be traversed finally and return to the starting node. Represent each node as a function of external inputs and this node.

[0106] For example, for node A, it can be represented as: ;

[0107] Among them, , , are all externally input functional forms.

[0108] From this, the points that may oscillate in set M can be found, that is, if there exists a set I that satisfies:

[0109] F(I) = 0, K(I) = 0, and G(I) = 1;

[0110] Then node A may oscillate, and conversely, node A cannot oscillate. A strongly connected component containing a node that may oscillate may oscillate, and if not, it cannot oscillate.

[0111] From the logical formula, the oscillation conditions of all nodes that may oscillate can be directly obtained. Taking the union of the oscillation conditions of each node is the oscillation condition of the entire circuit.

[0112] S3: Insert registers (such as SR type) at all nodes that may oscillate, thereby destroying all strongly connected components that may oscillate, and the purpose of destroying all strongly connected components with the least number of inserted registers can be achieved. After inserting the registers, the entire logic loop will not oscillate under any external input conditions.

[0113] For easy understanding, a gate instance is given to specifically illustrate this analysis method. The gate instance information is as follows:

[0114] Module name is combLogic

[0115] 0: not1 I001_001 w_000_001 w_000_002

[0116] 1: and2 I001_002 w_000_002 w_003_001 w_000_003

[0117] 2: and2 I001_003 w_000_004 w_003_002 w_000_005

[0118] 3: and2 I001_004 w_001_006 w_000_005 w_003_003

[0119] 4: and2 I001_005 w_001_007 w_003_004 w_000_003

[0120] 5: and2 I001_006 w_001_008 w_000_001 w_000_004

[0121] 6: nand2 I001_007 w_000_005 w_001_009 w_001_010

[0122] 7: and2 I001_008 w_002_012 w_001_006 w_001_007

[0123] 8: nand2 I001_009 w_000_003 w_002_013 w_002_014

[0124] 9: nand2 I001_010 w_001_009 w_003_005 w_001_008

[0125] 10: and2 I002_012 w_001_010 w_002_012 w_003_006

[0126] 11: and2 I002_013 w_002_013 w_003_007 w_002_012

[0127] 12: not1 I002_014 w_002_014 w_002_015

[0128] 13: and2 I002_015 w_002_015 w_001_008 w_003_008

[0129] First, find all strongly connected components. The results are as follows:

[0130] w_000_001,w_001_008,w_001_009,w_000_005,w_001_006,w_002_012,w_002_013,w_000_003,w_000_002;

[0131] w_000_001,w_001_008,w_002_015,w_002_014,w_000_003,w_000_002;

[0132] w_000_003,w_001_007,w_002_012,w_001_010,w_000_005,w_000_004,w_001_008,w_002_015,w_002_014;

[0133] w_000_003, w_001_007, w_002_012, w_002_013;

[0134] w_000_004, w_001_008, w_001_009, w_000_005;

[0135] w_000_005, w_001_006, w_002_012, w_001_010;

[0136] Then, find the node set M that exists in all combinational logic loops and has the minimum number (minimum cut problem). The results are as follows:

[0137] w_000_003, w_000_005;

[0138] Analyze each of the found nodes (w_000_003, w_000_005) separately, and represent each node (w_000_003, w_000_005) as a function of external inputs and the current node. The results are as follows:

[0139] ;

[0140] The oscillation condition can be directly obtained from the logical formula. For the sake of easy expression, use Oscflag as a signal. When Oscflag = 1, the loop oscillates. In the above example, Oscflag is expressed as follows:

[0141] ;

[0142] Finally, insert registers at w_000_003 and w_000_005, which can break all strongly connected components with the least number of inserted registers.

[0143] The present invention first finds all strongly connected components in the test case through depth - first search; then uses the maximum - flow minimum - cut theorem to find the strongly connected components that cannot have continuous oscillation and the strongly connected components that may produce continuous oscillation, and analyzes the oscillation conditions; finally, inserts registers at the nodes that may oscillate to break all strongly connected components that may produce continuous oscillation, thereby realizing the automatic detection of unexpected combinational logic loops in digital gate circuits, analyzing the trigger conditions, providing the addresses of the least number of register insertions to break the loop, and helping designers discover design problems. And this method has a low time complexity, high detection efficiency, and high detection accuracy.

[0144] The present invention also provides a combinational logic loop automatic simulation system based on a 55nm process, including:

[0145] Strongly Connected Component Identification Module: It is used to obtain the gate instance data of the combinational logic circuit, take each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and output ports to obtain a directed graph; based on the directed graph, perform a depth-first search to identify strongly connected components;

[0146] Analysis Module: Using the maximum flow - minimum cut theorem, obtain the minimum vertex cover of all strongly connected components and get a set of nodes; analyze each node in the set of nodes separately, traverse forward, represent each node as a function of external inputs and the node, construct a logical formula, judge the possibility of oscillation of the node according to the logical formula, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation;

[0147] Repair Module: It is used to insert registers at the nodes that may oscillate to destroy all strongly connected components.

[0148] Furthermore, the Analysis Module uses the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get a set of nodes, specifically:

[0149] Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity; after recording all in - points as super in - points and all out - points as super out - points, calculate the maximum flow value from the super in - point to the super out - point as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

[0150] In addition, the Strongly Connected Component Identification Module performs a depth - first search, which is implemented through the dfs() function and the tarjan() function.

Claims

1. An automatic simulation method for combinational logic loops based on 55nm process, characterized in that, Including the following steps: S1: Obtain the gate instance data of the combinational logic circuit. Using each input and output port as a node of the graph, construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph; Based on the directed graph, perform a depth-first search to identify strongly connected components; S2: Use the maximum flow-minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes; Analyze each node in the set of nodes individually, traverse forward, represent each node as a function of external inputs and the node, construct a logical formula, judge the possibility of oscillation of the node according to the logical formula, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation; S3: Insert registers at the nodes that may oscillate to break all strongly connected components.

2. The automatic simulation method for combinational logic loops based on a 55nm process according to claim 1, wherein In the above S2, using the maximum flow-minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes, specifically: Split each node of the strongly connected component into an in-node and an out-node, set the capacity between the in-node and the out-node split from the same node to 1, and set the capacity between nodes to positive infinity; After recording all in-nodes as super in-nodes and all out-nodes as super out-nodes, calculate the maximum flow value from the super in-node to the super out-node as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

3. The automatic simulation method for the combinational logic loop based on the 55nm process according to claim 1, characterized in that, The directed graph obtained in the above S1 is implemented through the BuildGraph() function, specifically: After recording the name of each port and the associated gate number, assign a unique number to each input and output port as the node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph.

4. The automatic simulation method for combinational logic loops based on the 55nm process according to claim 1, characterized in that In the above S1, based on the directed graph, perform a depth-first search to identify strongly connected components, specifically: For unvisited nodes, call the dfs() function to obtain the DFS traversal sequence number and backtracking value of the unvisited node; Traverse the neighbor nodes of the unvisited node. If the neighbor node is not visited, recursively process the neighbor node, and take the minimum value of the backtracking value of the neighbor node and the unvisited node as the new backtracking value of the unvisited node; If the neighbor node is in the stack, take the minimum value of the DFS traversal sequence number of the neighbor node and the backtracking value of the unvisited node as the new backtracking value of the unvisited node; When backtracking to an unvisited node, if the new backtracking value of the unvisited node is equal to the DFS traversal sequence number of the unvisited node, all nodes from the node to the top of the stack form a strongly connected component.

5. The automatic simulation method of the combinational logic loop based on the 55nm process according to claim 3, wherein The recording of the name of each port and the associated gate number is implemented through the port and mpbh arrays; The connection relationship between the input ports and the output ports is recorded using the to array and the Edge structure.

6. A combinational logic loop automatic simulation system based on a 55nm process, characterized in that, Including: Strongly connected component identification module: Used to obtain the gate instance data of the combinational logic circuit. Using each input and output port as a node of the graph, construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph; Based on the directed graph, perform a depth-first search to identify strongly connected components; Analysis module: Using the maximum flow - minimum cut theorem, obtain the minimum vertex cover of all strongly connected components and get the node set; analyze each node in the node set individually, traverse forward, represent each node as a function of external inputs and the node itself, construct a logical expression, and based on the logical expression, determine the possibility of oscillation of the node, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, take the union of the oscillation conditions of all nodes that may oscillate to get the external input conditions for oscillation. Repair module: Used to insert registers at the nodes that may oscillate to break all strongly connected components.

7. The automatic simulation system of the combinational logic loop based on the 55nm process according to claim 6, wherein The analysis module uses the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get the node set, specifically: Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity; after marking all in - points as super in - points and all out - points as super out - points, calculate the maximum flow value from the super in - point to the super out - point, which is the capacity of the minimum cut, that is, the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the node set.

8. The automatic simulation system for combinational logic loops based on 55nm process according to claim 6, wherein The strongly connected component identification module performs a depth - first search, which is implemented by the dfs() function and the tarjan() function.