Memristor, spiking neuron with random dropout function, and neural network

Abstract

The present application discloses a memristor, a spiking neuron with a random dropout function, and a neural network, relating to the field of neural network technology. The memristor comprises a stacked active electrode layer, a resistive switching layer, and an inert electrode layer. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly varies between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. In this way, the memristor has three different resistive switching behaviors. When two memristors are connected in series, one utilizes the volatile and non-volatile digital switch resistive switching behaviors to implement the dropout function, while the other utilizes the volatile analog switch behavior to implement the LIF function. This constructs a spiking neuron and neural network with a probabilistically adjustable dropout function in hardware.

Description

Technical Field

[0001] The present application relates to the field of neural network technology, and in particular to a memristor, a pulse neuron with a random discard function, and a neural network. Background Art

[0002] Neurons are the fundamental units of neural networks, which implement complex information processing and decision-making through the combination of multiple layers of neurons. Dropout (random dropout) can reduce reliance on specific neurons by randomly dropping neurons, improving the generalization of neural network models. In recent years, it has begun to be applied in neuromorphic computing and brain-inspired chips. Current research has largely focused on the algorithmic level, using dropout to improve neural network performance. However, hardware implementation of dropout still faces many challenges. First, efficient randomness generation is required in hardware to simulate the random dropout of neurons, but the presence of noise complicates the generation of high-quality randomness. Second, hardware implementations must have adjustable probability, allowing for flexible adjustment of dropout probability to suit different task requirements. Finally, hardware implementations must balance low power consumption with high integration density, ensuring that dropout units can be seamlessly integrated into existing neural network hardware architectures.

[0003] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a memristor, a pulse neuron with a random discard function, and a neural network, aiming to solve the technical problem in the prior art that it is difficult to simulate the random discard function of neurons in hardware.

[0005] To achieve the above-mentioned objectives, the present application provides a memristor, which includes an active electrode layer, a resistive switching layer, and an inert electrode layer, wherein the resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has ion migration characteristics, and the memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer, and the digital switch resistive switching behavior of the memristor randomly changes between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior.

[0006] In one embodiment, the random performance probability of the resistive behavior of the volatile digital switch in the random change decreases with the increase of the limiting current, and the random performance probability of the resistive behavior of the non-volatile digital switch in the random change increases with the increase of the limiting current.

[0007] In one embodiment, when a positive voltage is applied to the active electrode layer, a conductive filament is formed in the resistive switching layer. The conductive filament breaks randomly. If the conductive filament breaks after the voltage is removed, the memristor obtains a volatile digital switch resistive switching behavior. If the conductive filament does not break after the voltage is removed, the memristor obtains a non-volatile digital switch resistive switching behavior.

[0008] The ion migration characteristics of the resistive switching layer enable the resistance value of the memristor to change according to the electric field strength and electric field direction, thereby obtaining a volatile analog switch resistive switching behavior.

[0009] In addition, to achieve the above objectives, the present application provides a spiking neuron with a random discarding function, the spiking neuron with a random discarding function comprising a first functional neuron and a second functional neuron, the first functional neuron and the second functional neuron being memristors as described above, the first functional neuron and the second functional neuron being connected in series via a common active electrode layer, the common active electrode layer applying a target voltage, and the inert electrode layer of the second functional neuron being grounded;

[0010] The first functional neuron is used to simulate a random discard process based on the randomly changing resistive behavior of the volatile digital switch and the resistive behavior of the non-volatile digital switch;

[0011] The second functional neuron is used to simulate the reaction process of a biological neuron receiving external stimulation based on the resistive switching behavior of a volatile analog switch.

[0012] In one embodiment, the target limiting current of the first functional neuron is set according to the target random performance probability of the resistive switching behavior of the volatile digital switch and the resistive switching behavior of the non-volatile digital switch in random changes, and the target random performance probability is set according to the target discard probability of the random discard.

[0013] In addition, to achieve the above-mentioned object, the present application provides a pulse neuron circuit with a random discarding function, wherein the pulse neuron circuit with a random discarding function includes a digital resistive memristor and an analog resistive memristor connected in series, wherein the digital resistive memristor and the analog resistive memristor are both memristors as described above, the digital resistive memristor is connected to a target voltage, and the analog resistive memristor is connected to an output terminal;

[0014] The analog resistive memristor is used to simulate the reaction process of biological neurons receiving external stimuli based on the resistive behavior of the volatile analog switch;

[0015] The digital resistive memristor is used to simulate a random discard process based on the randomly changing resistive behavior of a volatile digital switch and the resistive behavior of a non-volatile digital switch.

[0016] In one embodiment, the pulse neuron circuit with random discarding function further includes a switching element and a transistor, the digital resistive memristor and the analog resistive memristor are connected through the switching element, the first end of the transistor is respectively connected to the digital resistive memristor and the switching element, the second end of the transistor is grounded, the analog resistive memristor obtains the volatile analog switch resistive behavior when the transistor is turned off and the switching element is closed, and the digital resistive memristor obtains randomly changing volatile digital switch resistive behavior and non-volatile digital switch resistive behavior when the transistor is turned on and the switching element is disconnected.

[0017] Furthermore, to achieve the above-mentioned object, the present application provides a neural network with a random dropout function, wherein the neural network with a random dropout function comprises a hidden layer, wherein the hidden layer comprises a random dropout layer, wherein the random dropout layer comprises a plurality of pulse neurons with a random dropout function as described above arranged in an array;

[0018] The random drop layer is used to drop neurons according to a target drop probability when receiving external data, and determine effective neurons, so that the hidden layer performs feature extraction based on the effective neurons to obtain target features.

[0019] In one embodiment, the neural network with random dropout function further includes an input layer and an output layer, and the hidden layer is connected to the input layer and the output layer respectively;

[0020] The input layer is used to obtain the external data and input the external data into the hidden layer;

[0021] The output layer is used to generate a prediction result based on the target feature.

[0022] In addition, to achieve the above-mentioned purpose, the present application also provides a method for preparing a memristor, the method comprising:

[0023] providing a substrate;

[0024] depositing an active metal on the substrate to form an active electrode layer;

[0025] Transferring a functional material having ion migration characteristics onto the active electrode layer to form a resistive switching layer;

[0026] An inert metal is deposited on the resistive layer to form an inert electrode layer.

[0027] In one embodiment, the step of depositing an active metal on the substrate to form an active electrode layer includes:

[0028] performing patterning processing on the substrate based on a first preset pattern;

[0029] Depositing an active metal on the patterned substrate based on a first preset thickness to form the active electrode layer;

[0030] The step of depositing an inert metal on the resistive layer to form an inert electrode layer includes:

[0031] performing patterning processing on the resistive switching layer based on a second preset pattern;

[0032] Based on the second preset thickness, an inert metal is deposited on the patterned resistive layer to form the inert electrode layer.

[0033] The present application provides a memristor, comprising a stacked active electrode layer, a resistive switching layer, and an inert electrode layer, wherein the resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. The memristor in this application has three different resistive switching behaviors. After two memristors are connected in series, one uses the randomly changing resistive switching behaviors of volatile and non-volatile digital switches to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF (Leaky-Integrate-Fire) function, thereby constructing a spiking neuron and neural network with Dropout function in hardware. At the same time, the randomness of the resistive switching behaviors of volatile and non-volatile digital switches can be controlled by regulating the applied voltage, the applied voltage polarity and the limiting current, thereby realizing a probability-adjustable Dropout function, which solves the technical problem of difficulty in simulating the random dropout function of neurons in hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 A schematic structural diagram of an embodiment of a memristor provided in this application;

[0037] Figure 2A schematic diagram of a resistance change curve of a simulated switch resistance change behavior of a memristor provided in an embodiment of the present application;

[0038] Figure 3 Schematic diagram of the simulated LIF model of the memristor provided in the embodiment of the present application;

[0039] Figure 4 A schematic diagram of the pulse test current variation of the memristor provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of the resistive switching behavior of a volatile digital switch of a memristor provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram of the resistive switching behavior of a non-volatile digital switch of a memristor provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of the structure of an embodiment of a spiking neuron with a random discarding function provided by the present application;

[0043] Figure 8 This is a structural diagram of an embodiment of a pulse neuron circuit with a random discarding function provided by the present application;

[0044] Figure 9 A schematic diagram of the structure of an embodiment of a neural network provided in this application;

[0045] Figure 10 A schematic diagram of the Dropout layer of a neural network provided in an embodiment of the present application;

[0046] Figure 11 A schematic diagram of a two-layer network structure of a neural network provided in an embodiment of the present application;

[0047] Figure 12 This is a flow chart of an embodiment of a method for preparing a memristor provided in this application.

[0048] Description of Figure Numbers:

[0049] 10. Memristor; 11. Active electrode layer; 11a. Common active electrode layer; 12. Resistive layer; 12a. First resistive layer; 12b. Second resistive layer; 13. Inert electrode layer; 13a. First inert electrode layer; 13b. Second inert electrode layer; 14. Substrate; 100. Spiking neuron with random discarding function; 101. First functional neuron; 102. Second functional neuron; 200. Spiking neuron circuit with random discarding function; 201. Digital resistive memristor; 202. Analog resistive memristor; 203. Switching element; 204. Transistor; 1000. Neural network with random discarding function; 1001. Hidden layer; 1001a. Random discarding layer; 1002. Input layer; 1003. Output layer; V, applied target voltage.

[0050] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0052] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0053] The main solution of the embodiment of the present application is: to provide a memristor, including a stacked active electrode layer, a resistive switching layer and an inert electrode layer, the resistive switching layer having ion migration characteristics, the memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer, the memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer, and the digital switch resistive switching behavior of the memristor randomly changes between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior.

[0054] The present application provides a solution, designing a memristor with three different resistive switching behaviors. After two memristors are connected in series, one uses the randomly changing resistive switching behaviors of volatile and non-volatile digital switches to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF function, thereby constructing a spiking neuron and neural network with Dropout function in hardware. At the same time, the randomness of the resistive switching behaviors of the volatile and non-volatile digital switches can be controlled by regulating the applied voltage, the applied voltage polarity, and the limiting current, thereby realizing a probability-adjustable Dropout function, solving the technical problem of difficulty in simulating the random dropout function of neurons in hardware.

[0055] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0056] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] The present application embodiment provides a memristor, referring to Figure 1 , Figure 1 This is a structural diagram of an embodiment of a memristor provided in this application.

[0058] In this embodiment, the memristor 10 includes an active electrode layer 11, a resistive switching layer 12, and an inert electrode layer 13. The resistive switching layer 12 is located above the active electrode layer 11, and the inert electrode layer 13 is located above the resistive switching layer 12, forming a sandwich structure. Furthermore, the active electrode layer 11 is typically disposed above a substrate 14.

[0059] It should be noted that the resistive switching layer 12 is made of a functional material having ion migration properties. In other words, the resistive switching layer 12 in this embodiment has ion migration properties. The active electrode layer 11 is typically an active electrode made of an active metal, and the inert electrode layer 13 is typically an inert electrode made of an inert metal.

[0060] It is understood that the memristor 10 can obtain volatile analog switch resistive switching behavior through the resistive switching layer 12. Simultaneously, the memristor 10 can obtain digital switch resistive switching behavior by applying a positive voltage to the active electrode layer 11. The digital switch resistive switching behavior of the memristor 10 randomly varies between volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior. Thus, the memristor 10 in this embodiment has three different resistive switching behaviors: volatile analog switch resistive switching behavior, volatile digital switch resistive switching behavior, and non-volatile digital switch resistive switching behavior.

[0061] It should be understood that in this embodiment, the ion migration characteristics of the resistive layer 12 cause the resistance of the memristor 10 to change according to the electric field strength, obtaining a volatile analog switch resistive behavior. Since the functional material of the resistive layer 12 has ion migration characteristics (the phenomenon of ions migrating through a medium under specific conditions), the ions in the functional material will migrate directionally under the action of the electric field, causing the ions to accumulate at the electrode, thereby changing the barrier height between the functional material and the electrode, achieving a change in the resistance of the memristor 10, and having a resistive effect. This also means that by changing the direction and strength of the electric field, a memristor 10 with analog switch behavior can be obtained. Due to the concentration gradient in the functional material after ion migration, when the electric field is removed, the ions will migrate back, resulting in a volatile change in resistance. Therefore, in this mode, the resistance of the memristor 10 will change with changes in the electric field strength and direction. At this time, the resistive behavior of the memristor 10 is manifested as a volatile analog switch resistive behavior, and its resistive curve is as shown in FIG. Figure 2 shown.

[0062] It should be noted that the LIF model is a mathematical model used to simulate the behavior of biological neurons. A neuron is regarded as a capacitor that can accumulate current through the membrane. When a neuron receives input signals from other neurons, these signals are injected into the capacitor as instantaneous current, causing the membrane potential to gradually increase. In the absence of external input, the membrane potential will gradually drop back to the resting potential over time. Once the membrane potential reaches or exceeds a certain threshold, the neuron will "fire", that is, generate an action potential and transmit this signal to other neurons. The characteristics of the resistive behavior of volatile analog switches are highly consistent with the LIF model. Reference Figure 3 , consider the active electrode layer as dendrite A, the inert electrode layer as dendrite B, and the resistive layer as the axon. Dendrite A receives signals from other neurons and converts them into electrical signals. When the membrane potential reaches the threshold, the neuron triggers an action potential, which is transmitted along the axon to the axon terminal. The axon terminal releases neurotransmitters, which bind to the receptors on the membrane of the postsynaptic dendrite B, change its membrane potential, and complete the emission of the action potential.

[0063] In a specific implementation, the continuous modulation function of the conductance of the memristor 10 under a pulse test can be used to simulate the LIF function. Figure 4When the pulse voltage continues to stimulate, the conductance of memristor 10 slowly increases, similar to the increase in neuronal membrane potential when stimulated. When the pulse stimulation continues, the conductance of memristor 10 increases to the threshold, causing the neuron to fire an action potential. Due to the volatility of memristor 10, the device conductance spontaneously decreases, returning to the resting potential. Therefore, the resistive switching behavior of a volatile analog switch based on this resistive switching mechanism can simulate the life-in-the-loop (LIF) function of biological neurons—that is, the process by which biological neurons respond to external stimuli. Using memristor 10 as a spiking neuron that can simulate the LIF function, its natural nonlinear response and low power consumption can be leveraged to build efficient neuromorphic hardware. For example, this can be applied to spiking neural networks (SNNs) that simulate biological neural networks, transmitting information through the timing and frequency of pulses.

[0064] It is understood that this embodiment utilizes the active electrode layer 11 to implement the digital switching resistive behavior of the memristor 10. When a positive voltage is applied, the active electrode layer 11 is oxidized into ions, which migrate toward the negative electrode under the action of the electric field and are reduced to atoms at the negative electrode, forming conductive filaments (typically nano-conductive filaments) in the resistive layer 12. At this point, the memristor 10 enters a low-resistance state. When a negative voltage is applied to the active electrode layer 11, the current density in the filaments increases, causing the filaments to partially fuse. Furthermore, the atoms in the resistive layer 12 are oxidized into ions, causing the filaments to break, and the memristor 10 enters a high-resistance state. Due to the migration of ions formed in the active electrode layer 11 under the action of the electric field and the dynamic formation and breakage of nano-conductive filaments, the memristor 10 can rapidly switch between high-resistance and low-resistance states, achieving digital switching resistive behavior. Digital switching resistive behavior includes both volatile digital switching resistive behavior and non-volatile digital switching resistive behavior. The radius of the formed conductive filaments plays a significant role in the volatility and non-volatility of memristor 10. When the conductive filament radius is small (less than or equal to a certain value), the conductive filaments spontaneously break after the electric field is removed, and memristor 10 exhibits volatility. When the conductive filament radius is large (greater than a certain value), the conductive filaments maintain their original shape after the electric field is removed, requiring a reverse electric field to break them, and memristor 10 exhibits non-volatility. It can be seen that the breakage of the conductive filaments is random. If the conductive filaments break after the voltage is removed, the memristor 10 exhibits volatile digital switch resistive switching behavior. If the conductive filaments do not break after the voltage is removed, the memristor 10 exhibits non-volatile digital switch resistive switching behavior. During voltage writing, due to the randomness of the conductive filament formation and breakage, the volatility and non-volatility exhibited by the memristor 10 are also random, not exhibiting a single characteristic. Furthermore, when voltage is written, whether the memristor 10 remains in a low-resistance state is also random. This means that the memristor 10 possesses both volatility and non-volatility. At this point, the memristor 10 exhibits both volatile and non-volatile digital switching behaviors. Forming conductive filaments using the active electrode layer 11 requires a large positive voltage. Prior to this, the resistive switching mechanism of the memristor 10 is dominated by the ion migration characteristics of the functional material.

[0065] It should be understood that by controlling some key conditions, the transition between volatility and non-volatility can be achieved. In this embodiment, the probability of random performance of the volatile digital switch resistive behavior in random changes decreases with the increase of the limiting current, and the probability of random performance of the non-volatile digital switch resistive behavior in random changes increases with the increase of the limiting current. The random performance probability is the probability of randomly performing a certain resistive behavior, the random performance probability of the volatile digital switch resistive behavior is the probability that the memristor 10 randomly performs the volatile digital switch resistive behavior, and the random performance probability of the non-volatile digital switch resistive behavior is the probability that the memristor 10 randomly performs the non-volatile digital switch resistive behavior. Reference Figure 5 When the set limit current is small, the memristor 10 exhibits volatile digital switch resistance behavior, which means that when the voltage is removed, the resistance of the memristor 10 will spontaneously return to the high resistance state. Figure 6 When the set limiting current is large, the memristor 10 exhibits non-volatile digital switch resistive switching behavior, requiring a negative voltage to break the formed conductive filaments and return the memristor 10 to a high-resistance state. In this embodiment, by increasing the limiting current, the memristor 10 can transition from volatile digital switch resistive switching behavior to non-volatile digital switch resistive switching behavior. This transition is not a sudden change upon reaching a threshold. In a specific implementation, the volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior of the memristor 10 under different limiting currents are random behaviors with specific probabilities. That is, when a certain limiting current is set, the volatility and non-volatility of the memristor 10 are both present. At this time, the volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior exhibited by the memristor 10 are random, that is, the digital switch resistive switching behavior of the memristor 10 randomly changes between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. Increasing the limiting current increases the probability that memristor 10 will exhibit non-volatility, meaning it is more likely to exhibit non-volatile digital switch behavior. Decreasing the limiting current increases the probability that memristor 10 will exhibit volatility, meaning it is more likely to exhibit volatile digital switch behavior. By setting an appropriate limiting current, after voltage is written, the current high and low resistance values ​​of memristor 10 are probabilistic. When memristor 10 is in a low-resistance state, it is on, allowing current and information to flow. When it is in a high-resistance state, it is off. By exploiting the random variations in the volatile and non-volatile digital switch behaviors of memristor 10, it is possible to simulate the dropout function, i.e., the process of randomly dropping neurons.

[0066] This embodiment provides a memristor comprising a stacked active electrode layer, a resistive switching layer, and an inert electrode layer. The resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly varies between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. The memristor in this embodiment has three different resistive switching behaviors. The randomly varying volatile and non-volatile digital switch resistive switching behaviors can be used to implement a dropout function, and the volatile analog switch behavior can be used to implement a life-in-the-loop (LIF) function, thereby constructing spiking neurons and neural networks with dropout functions in hardware.

[0067] The present application embodiment provides a pulse neuron with a random discarding function, referring to Figure 7 , Figure 7 This is a schematic structural diagram of an embodiment of a pulse neuron with random discarding function provided by this application.

[0068] In this embodiment, the pulse neuron 100 with random discard function includes a first functional neuron 101 and a second functional neuron 102. The first functional neuron 101 and the second functional neuron 102 are both memristors 10 in the above embodiment, including an active electrode layer, a resistive switching layer and an inert electrode layer. The specific structure can be referred to Figure 1 , which will not be described in detail here. In this embodiment, the first functional neuron 101 and the second functional neuron 102 are connected in series via a common active electrode layer. The common active electrode layer applies a target voltage, and the inert electrode layer (second inert electrode layer 13b) of the second functional neuron 102 is grounded. The first functional neuron 101 includes a common active electrode layer 11a, a first resistive layer 12a, and a first inert electrode layer 13a. The second functional neuron 101 includes a common active electrode layer 11a, a second resistive layer 12b, and a second inert electrode layer 13b. The entire spiking neuron 100 includes, from bottom to top, a common active electrode layer 11a, a first resistive layer 12a, a first inert electrode layer 13a, a second resistive layer 12b, and a second inert electrode layer 13b.

[0069] It can be understood that the first functional neuron 101 is used to simulate the random discard process based on the randomly changing resistive behavior of the volatile digital switch and the non-volatile digital switch; the second functional neuron 102 is used to simulate the reaction process of the biological neuron receiving external stimuli based on the resistive behavior of the volatile analog switch.

[0070] It should be noted that this embodiment utilizes the volatile analog switch resistive behavior of the second functional neuron 102 to simulate the LIF function, and utilizes the volatile digital switch resistive behavior and non-volatile digital switch resistive behavior of the first functional neuron 101 to simulate the dropout function. Since both the digital resistive memristor 201 and the analog resistive memristor 202 are memristors 10, each memristor 10 can be used to simulate a neuron. By simulating the LIF function, the simulation of a spiking neuron can be achieved. Connecting two memristors 10 in series can simulate both the LIF function and the dropout function, thereby realizing a spiking neuron with a dropout function.

[0071] It is understood that the target voltage is the voltage set to be applied by the first functional neuron 101. The polarity of the target voltage can be positive or negative, and the magnitude of the target voltage can be set according to actual needs and is not specifically limited. The target current limit is the set current limit for the first functional neuron 101. The target current limit for the first functional neuron 101 is set based on the target random behavior probability of the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior in random variations. The target random behavior probability is the probability that the first functional neuron 101 will randomly exhibit a certain resistive switching behavior. The target random behavior probability of the volatile digital switch resistive switching behavior is the probability that the first functional neuron 101 will randomly exhibit the volatile digital switch resistive switching behavior. The target random behavior probability of the non-volatile digital switch resistive switching behavior is the probability that the first functional neuron 101 will randomly exhibit the non-volatile digital switch resistive switching behavior. The target random behavior probability is set based on the target drop probability for random drop. The target drop probability is the set probability that a spiking neuron will be dropped. The specific value is set based on actual needs and is not specifically limited.

[0072] In a specific implementation, by adjusting the magnitude and polarity of the target voltage, the resistive switching behavior of the digital switch can be obtained. Furthermore, by setting a limiting current, randomly varying volatile and non-volatile resistive switching behaviors of the digital switch can be obtained. Further, by adjusting the magnitude of the limiting current, the random probability of the volatile and non-volatile resistive switching behaviors of the digital switch can be controlled. Therefore, by adjusting the magnitude of the limiting current and the magnitude and polarity of the target voltage, a first functional neuron 101 with a digital switch resistive switching behavior having a target random probability of behavior can be obtained, which is used to implement the dropout function in the neural network.

[0073] It should be understood that by utilizing the resistive switching layer with ion migration characteristics in the second functional neuron 102, volatile analog switch resistive switching behavior is achieved, thereby simulating the LIF function of biological neurons. In this embodiment, the first functional neuron 101 and the second functional neuron 102 are connected in series. The first functional neuron 101 has a dropout function, and the second functional neuron 102 simulates the LIF function. This allows the spiking neuron 100 with dropout function to be implemented through hardware.

[0074] This embodiment provides a spiking neuron with a dropout function, comprising a first functional neuron and a second functional neuron, the first functional neuron and the second functional neuron being connected in series via a common active electrode layer, to which a target voltage is applied, and the inert electrode layer of the second functional neuron being grounded. The first functional neuron is configured to simulate a random dropout process based on the randomly varying resistive switching behavior of a volatile digital switch and the resistive switching behavior of a non-volatile digital switch; the second functional neuron is configured to simulate the reaction process of a biological neuron to an external stimulus based on the resistive switching behavior of a volatile analog switch. This embodiment designs a memristor with three different resistive switching behaviors. When the two memristors are connected in series, one implements the dropout function using the randomly varying resistive switching behavior of the volatile and non-volatile digital switches, while the other implements the LIF function using the volatile analog switch behavior. This hardware constructs a spiking neuron with a dropout function. Furthermore, the randomness of the resistive switching behavior of the volatile and non-volatile digital switches can be controlled by regulating the applied voltage, applied voltage polarity, and limiting current, thereby achieving a probabilistically adjustable dropout function.

[0075] The embodiment of the present application provides a pulse neuron circuit with a random discarding function, referring to Figure 8 , Figure 8 This is a structural diagram of an embodiment of a pulse neuron circuit with random discarding function provided by the present application.

[0076] In this embodiment, the pulse neuron circuit 200 with random discard function includes a digital resistive memristor 201 and an analog resistive memristor 202 connected in series. Both the digital resistive memristor 201 and the analog resistive memristor 202 use the memristor 10 in the above embodiment, including an active electrode layer 11, a resistive layer 12 and an inert electrode layer 13. The specific structure can be referred to Figure 1 The digital resistive memristor 201 is connected to the target voltage, and the analog resistive memristor 102 is connected to the output terminal.

[0077] It can be understood that the analog resistive memristor 202 is used to simulate the reaction process of biological neurons receiving external stimuli based on the resistive behavior of the volatile analog switch; the digital resistive memristor 201 is used to simulate the random discard process based on the randomly changing resistive behavior of the volatile digital switch and the resistive behavior of the non-volatile digital switch.

[0078] It should be noted that this embodiment utilizes the volatile analog switch resistive behavior of the analog resistive memristor 202 to simulate the LIF function, and utilizes the volatile digital switch resistive behavior and non-volatile digital switch resistive behavior of the digital resistive memristor 201 to simulate the dropout function. Since both the digital resistive memristor 201 and the analog resistive memristor 202 are memristors 10, it can be considered that the spiking neuron circuit 200 is composed of two identical memristors 10 connected in series.

[0079] It is understandable that the target voltage is the voltage set to be applied to the digital resistive memristor 201. The polarity of the target voltage can be a positive voltage or a negative voltage. The magnitude of the target voltage can be set according to actual needs and is not specifically limited thereto. The target current limit is the set current limit of the digital resistive memristor 201. The target current limit of the digital resistive memristor 201 is set according to the target random performance probability of the volatile digital switch resistive behavior and the non-volatile digital switch resistive behavior in random changes. The target random performance probability is the probability that the digital resistive memristor 201 needs to randomly exhibit a certain resistive behavior. The target random performance probability of the volatile digital switch resistive behavior is the probability that the digital resistive memristor 201 needs to randomly exhibit the volatile digital switch resistive behavior. The target random performance probability of the non-volatile digital switch resistive behavior is the probability that the digital resistive memristor 201 needs to randomly exhibit the non-volatile digital switch resistive behavior. The target random performance probability is set according to the target drop probability of the target neuron. The target drop probability is the probability that the set target neuron needs to be dropped. The specific value is set according to actual needs and is not specifically limited.

[0080] In a specific implementation, by adjusting the magnitude and polarity of the target voltage, the resistive switching behavior of the digital switch can be obtained. Furthermore, by setting a limiting current, randomly varying volatile and non-volatile resistive switching behaviors of the digital switch can be obtained. Further, by adjusting the magnitude of the limiting current, the random probability of the volatile and non-volatile resistive switching behaviors of the digital switch can be controlled. Therefore, by adjusting the magnitude of the limiting current and the magnitude and polarity of the target voltage, a digital resistive memristor 201 with a digital switch resistive switching behavior having a target random probability of behavior can be obtained, which can be used to implement the dropout function in a neural network.

[0081] It should be understood that by utilizing the resistive switching layer with ion migration characteristics in the analog resistive memristor 202 to obtain volatile analog switch resistive switching behavior, it is possible to simulate the LIF function of biological neurons. In this embodiment, the digital resistive memristor 201 and the analog resistive memristor 202 are connected in series. The digital resistive memristor 201 has a dropout function, and the analog resistive memristor 202 simulates the LIF function. This allows the spiking neuron circuit 200 with a dropout function to be implemented in hardware.

[0082] Furthermore, in addition to the digital resistive memristor 201 and the analog resistive memristor 202 connected in series, the spiking neuron circuit 200 also includes a switch element 203 and a transistor (bipolar transistor) 102. The digital resistive memristor 201 and the analog resistive memristor 202 are connected via the switch element 203. The first end of the transistor 204 is connected to the digital resistive memristor 201 and the switch element 203, respectively, and the second end of the transistor 204 is grounded. The transistor 204 is typically an NPN transistor, with the first end of the transistor 204 typically being a collector and the second end of the transistor 204 typically being an emitter. The base of the transistor 204 is connected to a corresponding component according to actual needs. The transistor 204 has a current limiting function in the circuit.

[0083] It can be understood that analog resistive memristor 202 exhibits volatile analog switch resistive behavior when transistor 204 is off and switch element 203 is closed, while digital resistive memristor 201 exhibits randomly varying volatile digital switch resistive behavior and non-volatile digital switch resistive behavior when transistor 204 is on and switch element 203 is open. When analog resistive memristor 202 exhibits volatile analog switch resistive behavior, continuous stimulation with a pulse voltage can simulate the LIF function of neurons.

[0084] This embodiment provides a spiking neuron circuit with a random dropout function, comprising a digital resistive memristor and an analog resistive memristor connected in series. The analog resistive memristor is used to simulate the reaction process of biological neurons receiving external stimuli based on the resistive behavior of a volatile analog switch. The digital resistive memristor is used to simulate the process of randomly dropping target neurons based on the randomly changing resistive behavior of a volatile digital switch and the resistive behavior of a non-volatile digital switch. This embodiment designs a memristor with three different resistive behaviors. When two memristors are connected in series, one implements the dropout function using the randomly changing resistive behavior of the volatile and non-volatile digital switches, while the other implements the life-in-place function using the volatile analog switch behavior. This constructs a spiking neuron with a dropout function in hardware. Furthermore, the randomness of the resistive behavior of the volatile and non-volatile digital switches can be controlled by regulating the applied voltage, applied voltage polarity, and limiting current, thereby achieving a probability-adjustable dropout function.

[0085] The present application embodiment provides a neural network, referring to Figure 9 , Figure 9 A schematic diagram of the structure of an embodiment of a neural network provided in this application.

[0086] In this embodiment, the neural network 1000 includes a hidden layer 1001, the hidden layer 1001 includes a random dropout layer 1001a, and the random dropout layer 1001a includes a plurality of pulse neurons 100 arranged in an array. The specific structure of the pulse neuron 100 can be referred to Figure 7 , I will not go into details here.

[0087] It should be noted that the random variations in the resistive switching behavior of the volatile and non-volatile digital switches of the memristor 10 can be applied to neural networks to implement a neural network 1000 with dropout functionality. Dropout is a regularization technique designed to prevent model overfitting. Its core idea is to randomly "turn off" some neurons in the network during training, forcing the network to learn more robust features. In each training iteration, each neuron is temporarily disabled (its output is set to zero) with probability p, while the outputs of the remaining neurons are scaled by a weight of 1 / (1-p) / 1 / (1-p) to maintain overall activation strength. Under a suitable current limit, through voltage writing, volatility and non-volatility are probabilistic, and the high and low resistance states of the memristor 10 after writing are also probabilistic. Using the high and low resistance states as switches also means that the switching of the memristor 10 is probabilistic, and subsequent current conduction is allowed only when the memristor 10 is in the on state. Therefore, the volatile and non-volatile probabilistic resistive switching behaviors of the memristor 10 can be used as a switch and applied as a Dropout layer in the neural network 1000 to achieve weight update. Figure 10 Based on the memristor 10 as the weight connection, the memristor 10 is regarded as a switch, and the probabilistic transition between the volatile digital switch resistive behavior and the non-volatile digital switch resistive behavior is regarded as a Dropout layer. When the non-volatile digital switch resistive behavior is exhibited, the synaptic weight of the previous neuron can be forward propagated; when the volatile digital switch resistive behavior is exhibited, the synaptic weight is updated to 0, realizing the Dropout function.

[0088] It can be understood that the random drop layer 1001a is used to drop neurons according to the target drop probability when receiving external data, and determine effective neurons, so that the hidden layer 1001 performs feature extraction based on the effective neurons to obtain target features.

[0089] It should be noted that external data refers to the data input into neural network 1000. Valid neurons are neurons that have not been discarded. By discarding some neurons according to a set target dropout probability, valid neurons can perform feature extraction normally, while the output of discarded neurons is zero, thereby reducing the neural network's reliance on specific neurons. Target features are the features ultimately extracted.

[0090] Furthermore, neural network 1000 includes an input layer 1002 and an output layer 1003, with hidden layer 1001 connected to both layers. Input layer 1002 is used to obtain external data and input it into the hidden layer; output layer 1003 is used to generate prediction results based on target features.

[0091] As can be understood, input layer 1002 receives external data, hidden layer 1001 extracts features from the data, and the output layer generates the final prediction results. The random dropout layer 1001a, as a regularization technique, is typically located in the hidden layer. By randomly dropping neurons, it can prevent overfitting of the model and improve its generalization ability.

[0092] In specific implementation, the multi-mode of the memristor 10 is combined to realize the LIF function by utilizing the resistive behavior of the volatile analog switch, and the dropout function is realized by utilizing the probabilistic transition between the resistive behavior of the volatile digital switch and the resistive behavior of the non-volatile digital switch. Figure 11A two-layer fully connected neural network was designed, using the LIF activation function. The number of neurons in the two layers was 100 and 150, respectively. A dropout probability (target dropout probability) was set for each layer except the output layer. The MNIST dataset was used for training, with only 1000 examples in the training set and the remaining examples as the test set. Without a dropout probability, the training accuracy reached 100%, but the test accuracy was only 85.55%, indicating overfitting. However, with a dropout probability of 0.5, after 100 rounds of training, the training and test accuracy were similar, significantly reducing overfitting.

[0093] This embodiment provides a neural network, including a hidden layer, the hidden layer including a random drop layer, the random drop layer including a plurality of spiking neurons arranged in an array; the random drop layer is configured to, upon receiving external data, drop neurons according to a target drop probability and determine valid neurons, so that the hidden layer can perform feature extraction based on the valid neurons to obtain target features. This embodiment designs a memristor with three different resistive switching behaviors. Two memristors are connected in series, one of which implements a dropout function using the randomly changing resistive switching behavior of volatile and non-volatile digital switches, and the other implements a life-in-place (LIF) function using the behavior of a volatile analog switch, thereby constructing a spiking neuron with a dropout function in hardware. Furthermore, a neural network with a dropout function is constructed using the spiking neurons arranged in an array. Furthermore, the randomness of the resistive switching behavior of the volatile and non-volatile digital switches can be controlled by regulating the applied voltage, the applied voltage polarity, and the limiting current, thereby achieving a probability-adjustable dropout function.

[0094] The present invention provides a method for preparing a memristor. Figure 12 , Figure 12 This is a flow chart of an embodiment of a method for preparing a memristor provided in this application.

[0095] In this embodiment, the method for preparing a memristor includes steps S10 to S40:

[0096] Step S10, providing a substrate;

[0097] It should be noted that the substrate can be obtained according to actual needs, and the substrate is cleaned and dried.

[0098] Step S20, depositing an active metal on the substrate to form an active electrode layer;

[0099] In a feasible implementation, step S20 may include: patterning the substrate based on a first preset pattern; and depositing an active metal on the patterned substrate based on a first preset thickness to form the active electrode layer.

[0100] It should be noted that the first preset pattern is the preset pattern of the active electrode layer, and the first preset thickness is the preset thickness of the active electrode layer, which can include thicknesses at different positions. The first preset pattern and the first preset thickness can be flexibly adjusted according to actual needs, and there is no specific limitation on this.

[0101] It is understood that this embodiment utilizes a patterning technique to pattern a substrate according to a first predetermined pattern, and then utilizes a thin film deposition technique to deposit an active metal on the patterned substrate to a first predetermined thickness, thereby forming a final active electrode layer. The active electrode layer in this embodiment can be considered an active electrode formed of an active metal. The active metal may include potassium (K), calcium (Ca), sodium (Na), magnesium (Mg), aluminum (Al), zinc (Zn), iron (Fe), tin (Sn), lead (Pb), lithium (Li), and the like. The active metal can be selected based on actual needs and is not specifically limited thereto.

[0102] Step S30, transferring a functional material having ion migration characteristics onto the active electrode layer to form a resistive switching layer;

[0103] It should be noted that the resistive layer is prepared using functional materials with ion migration properties. The functional materials can be perovskite solar cells, solid electrolytes, hydrogel electrolytes, etc., which can be selected according to actual needs and are not specifically limited.

[0104] Step S40: depositing an inert metal on the resistive layer to form an inert electrode layer.

[0105] In a feasible implementation, step S40 may include: patterning the resistive layer based on a second preset pattern; and depositing an inert metal on the patterned resistive layer based on a second preset thickness to form the inert electrode layer.

[0106] It should be noted that the second preset pattern is the preset pattern of the inert electrode layer, and the second preset thickness is the preset thickness of the inert electrode layer, which can include thicknesses at different positions. Both the second preset pattern and the second preset thickness can be flexibly adjusted according to actual needs, and no specific limitation is imposed on this.

[0107] It is understood that this embodiment utilizes a patterning technique to pattern the resistive switching layer according to a second predetermined pattern. Subsequently, a thin film deposition technique is used to deposit an inert metal on the patterned resistive switching layer to a second predetermined thickness, thereby forming a final inert electrode layer. The inert electrode layer can be considered an inert electrode formed of an inert metal. The inert metal can be gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), etc., and can be selected based on actual needs and is not specifically limited thereto.

[0108] It should be understood that after forming the inert electrode layer, a memristor can be obtained. The specific structure of the memristor can be referred to Figure 1 Furthermore, during testing, voltage is usually applied to the active electrode, while the inert electrode remains grounded.

[0109] This embodiment provides a method for fabricating a memristor, comprising providing a substrate; depositing an active metal on the substrate to form an active electrode layer; transferring a functional material having ion migration properties onto the active electrode layer to form a resistive switching layer; and depositing an inert metal on the resistive switching layer to form an inert electrode layer. The memristor fabricated in this embodiment exhibits three different resistive switching behaviors. The randomly varying resistive switching behaviors of volatile and nonvolatile digital switches enable a dropout function, while the volatile analog switch behavior enables a life-in-place (LIF) function. This allows for the construction of spiking neurons and neural networks with dropout functionality in hardware.

[0110] The memristor preparation method provided in this application is capable of preparing the memristor described in the aforementioned embodiments, resolving the technical issue of the difficulty in simulating the random discard function of neurons in hardware. Compared to the prior art, the memristor preparation method provided in this application achieves the same beneficial effects as those provided in the aforementioned embodiments, and other technical features of the memristor preparation method are the same as those disclosed in the aforementioned embodiments, which are not further elaborated here.

[0111] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the preparation method of the memristor of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0112] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0113] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0114] The above are only some embodiments of the present application and are not intended to limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A spiking neuron with random dropout function, characterized in that The pulse neuron with random discard function includes a first functional neuron and a second functional neuron, and the first functional neuron and the second functional neuron are both memristors as follows: The memristor includes an active electrode layer, a resistive switching layer, and an inert electrode layer. The resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. The volatile digital switch resistive switching behavior is The probability of random behavior in the random change decreases with an increase in the limiting current, and the probability of random behavior of the non-volatile digital switch resistive switching behavior in the random change increases with an increase in the limiting current; when a positive voltage is applied to the active electrode layer, a conductive filament is formed in the resistive switching layer, and the breaking of the conductive filament is random. If the conductive filament breaks after the voltage is removed, the memristor obtains a volatile digital switch resistive switching behavior; if the conductive filament does not break after the voltage is removed, the memristor obtains a non-volatile digital switch resistive switching behavior; The ion migration characteristics of the resistive switching layer enable the resistance value of the memristor to change according to the electric field strength and electric field direction, thereby obtaining a volatile analog switch resistive switching behavior; The first functional neuron and the second functional neuron are connected in series via a common active electrode layer, a target voltage is applied to the common active electrode layer, and the inert electrode layer of the second functional neuron is grounded; The first functional neuron is used to simulate a random discard process based on the randomly changing resistive behavior of the volatile digital switch and the resistive behavior of the non-volatile digital switch; The second functional neuron is used to simulate the reaction process of a biological neuron receiving external stimulation based on the resistive switching behavior of a volatile analog switch.

2. The spiking neuron with random discarding function according to claim 1, wherein The target limiting current of the first functional neuron is set according to the target random performance probability of the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior in random changes, and the target random performance probability is set according to the target discard probability of the random discard.

3. A pulse neuron circuit with random discarding function, characterized in that The pulse neuron circuit with random discard function includes a digital resistive memristor and an analog resistive memristor connected in series, wherein the digital resistive memristor and the analog resistive memristor are both memristors as follows: The memristor includes an active electrode layer, a resistive switching layer, and an inert electrode layer. The resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. The volatile digital switch resistive switching behavior is The probability of random behavior in the random change decreases with an increase in the limiting current, and the probability of random behavior of the non-volatile digital switch resistive switching behavior in the random change increases with an increase in the limiting current; when a positive voltage is applied to the active electrode layer, a conductive filament is formed in the resistive switching layer, and the breaking of the conductive filament is random. If the conductive filament breaks after the voltage is removed, the memristor obtains a volatile digital switch resistive switching behavior; if the conductive filament does not break after the voltage is removed, the memristor obtains a non-volatile digital switch resistive switching behavior; The ion migration characteristics of the resistive switching layer enable the resistance value of the memristor to change according to the electric field strength and electric field direction, thereby obtaining a volatile analog switch resistive switching behavior; The digital resistive memristor is connected to the target voltage, and the analog resistive memristor is connected to the output end; The analog resistive memristor is used to simulate the reaction process of biological neurons receiving external stimuli based on the resistive behavior of the volatile analog switch; The digital resistive memristor is used to simulate a random discard process based on the randomly changing resistive behavior of a volatile digital switch and the resistive behavior of a non-volatile digital switch.

4. The pulse neuron circuit with random discarding function as described in claim 3, wherein the pulse neuron circuit with random discarding function further includes a switching element and a transistor, the digital resistive memristor and the analog resistive memristor are connected through the switching element, the first end of the transistor is respectively connected to the digital resistive memristor and the switching element, the second end of the transistor is grounded, the analog resistive memristor obtains the volatile analog switch resistive behavior when the transistor is turned off and the switching element is closed, and the digital resistive memristor obtains randomly changing volatile digital switch resistive behavior and non-volatile digital switch resistive behavior when the transistor is turned on and the switching element is disconnected.

5. A neural network with random dropout function, characterized in that The neural network with random dropout function comprises a hidden layer, the hidden layer comprises a random dropout layer, and the random dropout layer comprises a plurality of pulse neurons with random dropout function according to claim 1 or 2 arranged in an array; The random drop layer is used to drop neurons according to a target drop probability when receiving external data, and determine effective neurons, so that the hidden layer performs feature extraction based on the effective neurons to obtain target features.

6. The neural network with random dropout function according to claim 5, wherein: The neural network with random dropout function further includes an input layer and an output layer, and the hidden layer is connected to the input layer and the output layer respectively; The input layer is used to obtain the external data and input the external data into the hidden layer; The output layer is used to generate a prediction result based on the target feature.

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