Control circuit of Gamma driving circuit and display device

Abstract

The invention discloses a control circuit and device of a Gamma driving circuit, and generally relates to the technical field of display panels. The Gamma driving circuit comprises a multi-stage amplifier and a plurality of signal lines, wherein the amplifier is used for controlling the signal lines to output different gray-scale signals; the control circuit comprises a signal input control circuit, a logic control circuit and a bleeder circuit. The signal input control circuit is connected with the first input end and the logic control circuit and outputs a first control signal to the logic control circuit; the logic control circuit is connected with the signal input control circuit, the bleeder circuit and the amplifier, generates a second control signal and a third control signal according to the first control signal, transmits the second control signal to the amplifier, and transmits the third control signal to the bleeder circuit; and the bleeder circuit is connected with the signal line and the logic control circuit, and releases the residual signal in the signal line under the control of the third control signal.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of display panels, and in particular, to a control circuit for a Gamma driving circuit and a display device. Background Art

[0002] With the development of display technology, the display effect of display panels is getting better and better, having great advantages in terms of color richness, display resolution, and display signal response speed and accuracy.

[0003] Generally, the display signal of a display panel is transmitted through a Gamma driving circuit. Based on this, the response speed and accuracy of the display signal are also related to the Gamma driving circuit. In the related art, the electrical signals of each frame displayed by the display panel in the Gamma driving circuit are usually different. When there is a certain signal difference (such as a voltage difference) between the electrical signals of the previous frame and the current frame, it is easy to have residual signals of the previous frame remaining in the current frame. During the process of the display panel quickly changing frames, it will affect the electrical signal of the current frame, resulting in display deviation. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the related art, it is desirable to provide a control circuit for a Gamma driving circuit and a display device, which can ensure rapid discharge while not causing abnormal display of the Gamma driving circuit due to the discharge, that is, the discharge does not affect the display effect of the display panel after the normal Gamma driving circuit transmits the display signal.

[0005] In a first aspect, a control circuit for a Gamma driving circuit is provided: The Gamma driving circuit includes: a multi-stage amplifier and multiple signal lines, and the amplifier is used to control the signal lines to output different grayscale signals; The control circuit includes: a signal input control circuit, a logic control circuit, and a discharge circuit; The signal input control circuit is connected to a first input end and the logic control circuit, and outputs a first control signal to the logic control circuit; The logic control circuit is connected to the signal input control circuit, the discharge circuit, and the amplifier, generates a second control signal and a third control signal according to the first control signal, and transmits the second control signal to the amplifier and the third control signal to the discharge circuit; The discharge circuit is connected to the signal line and the logic control circuit, and releases the residual signal in the signal line under the control of the third control signal.

[0006] In this application, the Gamma driving circuit includes multiple - stage amplifiers and multiple signal lines. The amplifiers can be used to control the signal lines to output different grayscale signals. The control circuit includes a signal input control circuit, a logic control circuit, and a current - discharging circuit. The relationships among the circuits in the control circuit are as follows: The signal input control circuit is connected to the first input end and the logic control circuit, and outputs a first control signal to the logic control circuit; The logic control circuit is connected to the aforementioned signal input control circuit, the current - discharging circuit, and the amplifier. It can generate a second control signal and a third control signal with opposite logic in the same time sequence according to the first control signal, transmit the second control signal to the aforementioned amplifier, and transmit the third control signal to the current - discharging circuit; The aforementioned current - discharging circuit is connected to the aforementioned signal line and the aforementioned logic control circuit. It can release the residual signal in the signal line under the control of the third control signal. In this way, the control circuit of the Gamma driving circuit can ensure fast current - discharging while not causing abnormal driving of the Gamma driving circuit due to current - discharging, that is, the current - discharging does not affect the display effect of the display panel after the normal Gamma driving circuit transmits the display signal.

[0007] Optionally, in the control circuit of the Gamma driving circuit provided in this application, the second control signal and the third control signal are logically opposite in the same time sequence.

[0008] Optionally, in the control circuit of the Gamma driving circuit provided in this application, the signal input control circuit includes a first inverter and a first node. The first inverter is coupled to the first input end and the first node, and is configured to perform logical inversion on the level signal corresponding to the first input signal received at the first input end to control the potential of the first node.

[0009] Optionally, in the control circuit of the Gamma driving circuit provided in this application, the signal input control circuit further includes a first output sub - circuit, a second output sub - circuit, a first input sub - circuit, a second node, and a control sub - circuit; The first output sub - circuit is coupled to the second node, the second voltage input end, and the first output signal end, and is configured to generate the first control signal from the second level signal of the second voltage input end under the control of the potential of the second node, and transmit the first control signal to the logic control circuit; The second output sub - circuit is coupled to the first node, the first voltage input end, and the first output signal end, and is configured to generate the first control signal from the first level signal of the first voltage input end under the control of the potential of the first node, and transmit the first control signal to the logic control circuit.

[0010] The first input sub-circuit is coupled to the first node, the first voltage input terminal, and the second node, and is configured to control the potential of the second node under the control of the potential of the first node; The control sub-circuit is coupled to the second node, the second voltage input terminal, and the first output signal terminal, and is configured to control the potential of the second node under the control of the potential of the output signal provided at the first output signal terminal.

[0011] Optionally, in the control circuit of the Gamma driving circuit provided in the present application, the first output sub-circuit includes: a fourth transistor, a control end of the fourth transistor is coupled to the second node, a first pole of the fourth transistor is coupled to the second voltage input terminal, and a second pole of the fourth transistor is coupled to the first output signal terminal; The first input sub-circuit includes: a second inverter and a first transistor; An input terminal of the second inverter is coupled to the first node; A control end of the first transistor is coupled to an output end of the second inverter, a first pole of the first transistor is coupled to the first voltage input terminal, and a second pole of the first transistor is coupled to the second node; The second output sub-circuit includes: a second transistor; a control end of the second transistor is coupled to the first node, a first pole of the second transistor is coupled to the first voltage input terminal, and a second pole of the second transistor is coupled to the first output signal terminal; The control sub-circuit includes a third transistor, a control end of the third transistor is coupled to the first output signal terminal, a first pole of the third transistor is coupled to the second voltage input terminal, and a second pole of the third transistor is coupled to the second node.

[0012] Optionally, in the control circuit of the Gamma driving circuit provided in the present application, the signal control input circuit further includes a buffer signal module, the buffer signal module is connected to the first signal output terminal, and is configured to receive a first control signal output from the first signal output terminal; The buffer signal module includes a third inverter and a fourth inverter; An input terminal of the third inverter is connected to the first output signal terminal, an input terminal of the fourth inverter is connected to an output terminal of the third inverter, and an output terminal of the fourth inverter is connected to the second output signal terminal.

[0013] Optionally, in the control circuit of the Gamma driving circuit provided in the present application, the first transistor is a first N-type transistor, the fourth transistor is a fourth P-type transistor, the second transistor is a second N-type transistor, and the third transistor is a third P-type transistor.

[0014] Optionally, in the control circuit of the Gamma driving circuit provided in the present application, the logic control circuit includes a first logic control sub-circuit and a second logic control sub-circuit, and the first logic control sub-circuit and the second logic control sub-circuit are connected in parallel; The first logic control sub-circuit is configured to generate the second control signal and transmit the second control signal to the Gamma amplifier; The second logic control sub-circuit is configured to generate the third control signal and transmit the third control signal to the bleed circuit.

[0015] Optionally, in the control circuit of the Gamma driving circuit provided in the present application, the second logic control sub-circuit includes: a fifth inverter, a first NAND gate, a first NOR gate, a sixth inverter, a seventh inverter, a tenth inverter, an eleventh inverter, a second intermediate node, and a third intermediate node; the first logic control sub-circuit includes: a second NAND gate, an eighth inverter, a ninth inverter, a second NOR gate, a fourth intermediate node, a fifth intermediate node, a twelfth inverter, and a thirteenth inverter; The first input terminal of the first NAND gate is connected to the output terminal of the fifth inverter, the second input terminal of the first NAND gate is connected to the fifth intermediate node, and the output terminal of the first NAND gate is connected to the second intermediate node; The first input terminal of the first NOR gate is connected to the output terminal of the seventh inverter, the second input terminal of the first NOR gate is connected to the second intermediate node, and the output terminal of the first NOR gate is coupled to the third control signal output terminal of the second logic control sub-circuit; The first input terminal of the second NAND gate is connected to the first control signal output terminal, the second input terminal of the second NAND gate is connected to the third intermediate node, and the output terminal of the second NAND gate is connected to the fourth intermediate node; The first input terminal of the second NOR gate is connected to the ninth inverter, the second input terminal of the second NOR gate is connected to the fourth intermediate node, and the output terminal of the second NOR gate is coupled to the second control signal output terminal of the first logic control sub-circuit.

[0016] Optionally, in the control circuit of the Gamma driving circuit provided in the present application, the second logic control sub-circuit further includes a first delay module, a second delay module, a sixth intermediate node, and a seventh intermediate node, the sixth intermediate node is disposed between the sixth inverter and the seventh inverter, the seventh intermediate node is disposed between the seventh inverter and the first NOR gate, the first delay module is coupled to the sixth intermediate node, and the second delay module is coupled to the seventh intermediate node; The first logic control sub - circuit includes a third delay module, a fourth delay module, an eighth intermediate node, and a ninth intermediate node. The eighth intermediate node is disposed between the eighth inverter and the ninth inverter, and the ninth intermediate node is disposed between the ninth inverter and the second NOR gate. The third delay module is coupled to the eighth intermediate node, and the fourth delay module is coupled to the ninth intermediate node.

[0017] Optionally, in the control circuit of the Gamma driving circuit provided in this application, the current - discharging circuit includes at least one resistor and at least one transistor. The at least one resistor is connected to a target signal line among the signal lines. A first pole of the at least one transistor is coupled to the at least one resistor, a second pole of the at least one transistor is coupled to the first voltage input terminal, and a control terminal of the at least one transistor is connected to the logic control circuit.

[0018] Optionally, in the control circuit of the Gamma driving circuit provided in this application, the target signal line is at least one signal line among the signal lines.

[0019] Optionally, in the control circuit of the Gamma driving circuit provided in this application, when the target signal line is multiple signal lines among the signal lines, the gray - scale voltage difference between any two adjacent signal lines corresponding to the target signal lines is less than or equal to a preset gray - scale voltage difference threshold.

[0020] Optionally, in the control circuit of the Gamma driving circuit provided in this application, when the target signal line is multiple signal lines among the signal lines, the target signal line includes a first signal line, a second signal line, and a third signal line. The gray - scale voltage value of the second signal line is any gray - scale voltage value between the gray - scale voltage value of the first signal line and the gray - scale voltage value of the third signal line, and the second signal line includes at least one signal line.

[0021] Optionally, in the control circuit of the Gamma driving circuit provided in this application, when the target signal line includes a first signal line, a second signal line, and a third signal line, the first signal line is the signal line with the largest gray - scale voltage value among the signal lines, the third signal line is the signal line with the smallest gray - scale voltage value among the signal lines, and the second signal line is the signal line with an intermediate gray - scale voltage value between the first signal line and the third signal line.

[0022] Optionally, in the control circuit of the Gamma driving circuit provided in this application, each target signal line in the Gamma driving circuit is in series with a resistor, and different target signal lines correspond to resistors with the same or different resistance values. The different resistance values of the resistors correspond to the gray - scale voltage values of the different target signal lines.

[0023] In a second aspect, a display device including a control circuit with a Gamma driving circuit is provided, and the device includes the control circuit of the aforementioned first aspect.

[0024] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings: Figure 1 Schematic diagram of the related art circuit for the embodiment of the present application; Figure 2 Circuit structure diagram of a control circuit for a Gamma driving circuit provided by the embodiment of the present application; Figure 3 Schematic diagram of the signal input control circuit provided by the embodiment of the present application; Figure 4 Schematic diagram of the logic control circuit provided by the embodiment of the present application; Figure 5 One of the working timing diagrams of the logic control circuit provided by the embodiment of the present application; Figure 6 Another working timing diagram of the logic control circuit provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention and not to limit the invention. Additionally, it should be noted that for the convenience of description, only the parts related to the invention are shown in the drawings.

[0027] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0028] With the development of display technology, the display effect of the display panel is getting better and better, and it has great advantages in terms of color richness, display resolution, and display signal response speed and accuracy.

[0029] Generally, the display signal of the display panel is transmitted through a Gamma driving circuit. Based on this, the response speed and accuracy of the display signal are also related to the Gamma driving circuit. As Figure 1 shown, Figure 1 is a conventional Gamma driving circuit In the related art, the traditional Gamma driver circuit mainly consists of three - stage circuits: ① The first stage: The high voltage of the Gamma driver circuit can correspond to the highest gray - scale voltage (VGMP), and the low voltage of the Gamma driver circuit can correspond to the lowest gray - scale voltage (VGSP). For each Band voltage selection, that is, VGMP / VGSP, through 256 resistor strings, voltage division is performed to generate the VGMP / VGSP voltages set for each Band; ② The second stage: The Gamma amplifier (OP) controls the enabling of the Gamma circuit through GMA_EN as a driving signal to enable it to be driven. GMA_EN is a MUX2:1 selector. When the MUX selects the output as DVDD (High), the Gamma OP conducts; when the MUX selects the output as GND (LOW), the Gamma OP turns off; ③ The third stage: Based on a certain Band, resistor - string voltage division is performed. There are a total of 16 Gamma OPs, and there are 7 resistor strings between each Gamma OP, for a total of 128 resistor strings, further realizing the voltage division of the resistors to generate a more refined Gamma voltage.

[0030] However, the above - mentioned traditional Gamma driver circuit has the following problems: ① Because the Gamma data of each frame is different and there is residue of the Gamma data of each frame in the signal line, the current Gamma driver circuit can only discharge through the slow discharge of the OP, with extremely low efficiency, and it is easy to have the situation that the Gamma data of the previous frame affects the display of the next frame; ② When one or both of the signals DVDD or GND are in an abnormal power - on state, the situation of an unknown GMA_EN state will occur.

[0031] Based on this, the present application proposes a control circuit and device for a Gamma driver circuit, which can ensure the fast discharge of the Gamma OP while not causing abnormal display of the Gamma driver circuit due to the discharge, that is, the discharge does not affect the display effect of the display panel after the normal Gamma driver circuit transmits the display signal. Specifically, the present application sets up a signal input control circuit, a logic control circuit, and a discharge circuit for the Gamma driver circuit to achieve protection of the circuit during abnormal power - on and off while realizing fast discharge. Among them, the signal input control circuit can convert the input digital signal into an analog positive voltage signal, and the logic control circuit transmits the analog positive voltage signal to a multi - stage amplifier to control the multi - stage amplifier to transmit the driving display signal; the logic control circuit can be used to ensure that only one of the multi - stage amplifier transmitting the display signal and the discharge circuit is executed within the same timing, so as to realize the control of the Gamma driver circuit and also the selection of the fast - discharge method, and can ensure that the residual data in the signal line of the previous frame is discharged in time before the arrival of the next - frame data, achieving fast response and display.

[0032] Figure 2This is a schematic diagram of a control circuit for a Gamma driving circuit provided by an embodiment of the present application. As Figure 2 shown, the above Gamma driving circuit includes: a multi-stage amplifier and multiple signal lines, and the above amplifier is used to control the above signal lines to output different grayscale signals.

[0033] In the embodiment of the present application, the above amplifier can be a Gamma OP amplifier. As Figure 2 shown, Figure 2 it includes a multi-stage amplifier 21, and each amplifier is connected to a signal line 22 of a different grayscale signal.

[0034] In the embodiment of the present application, the above control circuit includes: a signal input control circuit, a logic control circuit, and a current discharge circuit. As Figure 2 shown, Figure 2 it includes a signal input control circuit 23, a logic control circuit 24, and a current discharge circuit 25.

[0035] Next, the functions and structures of different circuits in the above control circuit will be introduced.

[0036] In the embodiment of the present application, the above signal input control circuit is connected to the first input end and the above logic control circuit, and outputs a first control signal to the above logic control circuit.

[0037] Exemplarily, the signal input to the above first input end is a driving signal of a display panel.

[0038] It can be understood that the signal input control circuit is used to convert the first input signal input from the first input end. Generally, the first input signal is a control signal for driving a display panel.

[0039] Exemplarily, the above signal input control circuit can convert the third-level signal of the received first input signal into a second-level signal and output it. Further, the third-level signal can be a digital voltage signal (DVDD), and the second-level signal can be a positive power supply signal (AVDD) of an analog circuit. Generally, both the third-level signal and the second-level signal are high-level signals.

[0040] That is, the signal input control circuit is used to convert the first input signal from DVDD into AVDD and output it.

[0041] Exemplarily, the above signal input control circuit can also achieve outputting the first-level signal of the received first input signal still as the first-level signal. Further, the first-level signal can be a low-level GND signal. It can be understood that the level of the third-level signal is higher than the level of the first-level signal and lower than the level of the second-level signal.

[0042] AsFigure 2 As shown Figure 2 In the signal input control circuit 23 in Figure 2 , it receives the third-level signal DVDD input from the first input terminal GMA_EN_LV, converts the DVDD into AVDD, and then outputs the AVDD to the logic control circuit 24 connected to the signal input control circuit 23; when the signal input control circuit 23 receives a low-level signal input from the first input terminal GMA_EN_LV, it does not change the low-level signal and outputs the low-level signal to the logic control circuit 24 connected to the signal input control circuit 23.

[0043] In the embodiment of the present application, the above-mentioned logic control circuit is connected to the above-mentioned signal input control circuit, the above-mentioned current discharge circuit, and the above-mentioned amplifier, generates a second control signal and a third control signal according to the above-mentioned first control signal, transmits the above-mentioned second control signal to the above-mentioned amplifier, and transmits the above-mentioned third control signal to the above-mentioned current discharge circuit.

[0044] Optionally, in the embodiment of the present application, the above-mentioned second control signal and the above-mentioned third control signal are logically opposite within the same time sequence.

[0045] It can be understood that, in the embodiment of the present application, in order to ensure that the current discharge process of the subsequent current discharge circuit and the process of driving the display panel will not be started simultaneously, this logic control circuit is provided. This logic control circuit is used to ensure that only one of the current discharge circuit and the amplifier will receive a start signal within the same time sequence, that is, through the control of this logic control circuit, when the amplifier starts and executes the display of the display panel, the current discharge circuit receives a shutdown signal; when the current discharge circuit starts and executes the current discharge process of the amplifier residual data signal, the amplifier receives a shutdown signal.

[0046] Exemplarily, the above-mentioned second control signal is a signal for controlling the start of the amplifier and executing the driving of the display panel. For example, as Figure 2 shown, the second control signal can be the GMA_OP_P8V signal output from one end of the signal input control circuit.

[0047] Exemplarily, the above-mentioned third control signal is a data signal for controlling the start of the current discharge circuit and executing the current discharge of the amplifier residual data signal. For example, as Figure 2 shown, the third control signal can be the PD_EN_P8V signal.

[0048] As Figure 2 shown, in Figure 2The middle logic control circuit 24 is connected to the current discharging circuit 25 and the amplifier 21. When receiving the first control signal output by the signal input control circuit 23 for the foregoing signal input, it performs logic processing on the first control signal, resulting in two situations: 1) After the signal input control circuit 23 outputs the second level signal AVDD, the GMA_OP_P8V signal is output from the second control signal output terminal of the logic control circuit 24 to the amplifier 21, that is, the second control signal is output, and at the same time, the low level GND signal is output from the third control signal output terminal of the logic control circuit 24 to the current discharging circuit 25; 2) After the signal input control circuit 23 outputs the low level GND signal, the low level GND signal is output from the second control signal output terminal of the logic control circuit 24 to the amplifier 21, and at the same time, the PD_EN_P8V signal, that is, the third control signal, is output from the third control signal output terminal of the logic control circuit 24 to the current discharging circuit.

[0049] In this way, by setting a logic circuit after the signal input control circuit, that is, setting the signal input control circuit before the logic circuit, this circuit setting method can prevent problems of the signal input control circuit from spreading to the logic circuit during abnormal power-on and power-off, because when the logic circuit accesses the level signal, it only accesses the second level signal AVDD or the first level signal GND. Therefore, the output will only be two signals with opposite logics, thereby ensuring that the circuit is not turned on simultaneously, preventing the occurrence of abnormal power-on and power-off, and ensuring the stability and correctness of the signals output by the Gamma driving circuit.

[0050] In the embodiment of the present application, the foregoing current discharging circuit is connected to the foregoing signal line and the foregoing logic control circuit, and under the control of the foregoing third control signal, releases the residual number signal in the foregoing signal line.

[0051] It can be understood that for the current discharging circuit, it is used to release the residual current signal in the signal line.

[0052] Specifically, the current discharging circuit can be connected to all signal lines to perform residual signal release, or can be connected to some signal lines to perform residual signal release. Both of these methods can achieve the purpose of releasing the residual data signal in the amplifier. The embodiment of the present application does not limit this. The connection method between the current discharging circuit and the signal line can be specifically referred to the subsequent description of the current discharging circuit.

[0053] As Figure 2 shown, in Figure 2 the current discharging circuit 25 is connected to the foregoing logic control circuit 24 and is connected to 3 signal lines among all the signal lines, that is, some signal lines. When receiving the PD_EN_P8V signal, that is, the foregoing third control signal, it releases the residual data signal of the signal line.

[0054] In the circuit provided by the embodiment of the present application, the Gamma driving circuit includes an amplifier and multiple signal lines. The amplifier can be used to control the signal lines to output different grayscale signals. The control circuit includes a signal input control circuit, a logic control circuit, and a current discharging circuit. The relationships among the circuits in the control circuit are as follows: The signal input control circuit is connected to the first input end and the logic control circuit, and outputs a first control signal to the logic control circuit; the logic control circuit is connected to the aforementioned signal input control circuit, the current discharging circuit, and the amplifier. It can generate a second control signal and a third control signal with opposite logics in the same time sequence according to the first control signal, transmit the second control signal to the aforementioned amplifier, and transmit the third control signal to the current discharging circuit; the aforementioned current discharging circuit is connected to the aforementioned signal line and the aforementioned logic control circuit, and it can release the residual signal in the signal line under the control of the third control signal. In this way, the control circuit of the Gamma driving circuit can ensure fast current discharging while not causing abnormal driving of the Gamma driving circuit due to current discharging, that is, the current discharging does not affect the display effect of the display panel after the normal Gamma driving circuit transmits the display signal.

[0055] In another embodiment of the present application, the aforementioned signal input control circuit includes: a first inverter and a first node. The first inverter is coupled to the first input end and the first node, and is configured to perform logical reverse control on the potential of the first node for the level signal corresponding to the first input signal after receiving the first input signal input from the first input end.

[0056] Exemplarily, the aforementioned signal input control circuit can be a third level signal DVDD to second level signal AVDD conversion circuit, simply referred to as a level conversion circuit (Level Shift circuit, LSH circuit).

[0057] Generally, the first input signal received by the signal input control circuit includes two level signals, one is the aforementioned third level signal DVDD, and the other is a low level signal GND. These two signals are received at different time sequences. The purpose of the signal input control circuit is to ensure that the third level signal DVDD is converted into the second level signal AVDD, while the low level signal still outputs as a low level signal.

[0058] To achieve this purpose, an inverter, that is, the first inverter, is set at the starting position of the signal input control circuit. The first inverter performs logical reverse control on the potential of the first node for the level signal corresponding to the first input signal. Further, the signal output to the first node will be divided into two parallel sub - circuits starting from the first node to perform different control methods on the signal generated by the first node to ensure that the final signal input control circuit can achieve the above - mentioned purpose.

[0059] Such as Figure 3The specific circuit structure of the LSH shown, the LSH circuit includes a first inverter I1 and a first node N1, and the first inverter I1 is coupled to the first input terminal GMA_EN_LV and the first node N1.

[0060] In another embodiment of the present application, the above signal input control circuit is further described.

[0061] Exemplarily, the above signal input control circuit further includes a first output sub - circuit, a second output sub - circuit, a first input sub - circuit, a control sub - circuit, and a second node.

[0062] Exemplarily, as described above, after the first node, the above signal input control circuit is divided into two parallel sub - circuits, and the output parts of these two parallel sub - circuits include a first output sub - circuit and a second output sub - circuit.

[0063] Exemplarily, the above first output sub - circuit is coupled to the second node, the second voltage input terminal, and the first output signal terminal, and is configured to generate the above first control signal from the second - level signal of the second voltage input terminal under the control of the potential of the second node, and transmit the first control signal to the above logic control circuit. As Figure 3 shown, in Figure 3 it includes a first output sub - circuit A, and the first output sub - circuit A is coupled to the second node N2, the second voltage input terminal AVDD, and the first output signal terminal M.

[0064] Exemplarily, the above second - level signal can be the level signal corresponding to AVDD.

[0065] In one example, when the signal received by the signal input control circuit from the first input terminal is the level signal corresponding to the third - level signal DVDD for driving the display panel, the above first output sub - circuit can output the level signal corresponding to the second - level signal AVDD.

[0066] It should be noted that, as can be seen from the above, the first input terminal may input two different signals. Therefore, when the signal received by the first input terminal is the first - level signal GND, the first output sub - circuit is in a non - conducting state, while the second output sub - circuit is in a conducting state.

[0067] Exemplarily, the first control signal generated from the second - level signal of the second voltage input terminal is the second - level signal AVDD, that is, through the second voltage input terminal, the low - voltage control signal input from the first input terminal can be converted into a medium - voltage control signal. It should be noted that the above conversion process is completed by directly outputting the second - level signal through the second voltage input terminal.

[0068] Exemplarily, the above-mentioned second output sub-circuit is coupled to the above-mentioned first node, the first voltage input terminal, and the output signal terminal, and is configured to generate the above-mentioned first control signal from the first level signal of the above-mentioned first voltage input terminal under the control of the potential of the above-mentioned first node, and transmit the above-mentioned first control signal to the above-mentioned logic control circuit. In Figure 3 it includes a second output sub-circuit B, and this second output sub-circuit B is coupled to the first node N1, the first voltage input terminal GND, and the first output signal terminal M.

[0069] Since the signal input to the first inverter mentioned above may include the third level signal DVDD or the first level signal GND. Based on this, the signal of the above-mentioned first node N1 can include two kinds of signals, one is a high-level signal and the other is a low-level signal. For the second output sub-circuit, different level signals can control the second output sub-circuit to output the first control signal or not to output the first control signal.

[0070] Further, when the second output sub-circuit does not output the first control signal, the first output sub-circuit outputs the first control signal.

[0071] Exemplarily, the first input sub-circuit is coupled to the above-mentioned first node, the first voltage input terminal, and the second node, and is configured to control the potential of the above-mentioned second node under the control of the potential of the above-mentioned first node. As Figure 3 shown, in Figure 3 it includes a first input sub-circuit C, and this first input sub-circuit C is coupled to the first node N1, the first voltage input terminal GND, and the second node N2.

[0072] It can be understood that the first input sub-circuit performs a second inversion on the potential of the first node N1, so that the potential passing through the second inverter I2 is consistent with the potential corresponding to the first input terminal. When the potential after the second inversion, that is, the potential output by the second inverter I2, is a low level, the first input sub-circuit can be controlled not to conduct subsequently; when the potential output by the second inverter I2 is a high level, the transistor M1 in the first input sub-circuit can be controlled to conduct, and further the potential of the second node N2 is the same as the first level signal, which is a low level.

[0073] Exemplarily, the signal input control circuit further includes a control sub-circuit, which is coupled to the above-mentioned second node, the above-mentioned second voltage input terminal, and the above-mentioned first output signal terminal, and is configured to control the potential of the above-mentioned second node under the control of the potential of the output signal provided by the above-mentioned first output signal terminal. As Figure 3 shown, in Figure 3 it includes a control sub-circuit D, and this control sub-circuit D is coupled to the second node N2, the second voltage input terminal AVDD, and the first output signal terminal M.

[0074] In another embodiment of the present application, a further description is made of the specific components of the above signal input control circuit.

[0075] Exemplarily, the above first output sub-circuit includes: a fourth transistor. The control terminal of the above fourth transistor is coupled to the above second node, the first pole of the above fourth transistor is coupled to the above second voltage input terminal, and the second pole of the above fourth transistor is coupled to the above first output signal terminal. As Figure 3 shown, the above fourth transistor M4, the control terminal of the fourth transistor M4 is the gate of the transistor M4, and the gate of the transistor M4 is coupled to the second node N2. The first pole of the above fourth transistor M4 is the drain; the second pole of the above fourth transistor M4 is the source. Among them, the source of the above fourth transistor M4 is coupled to the input terminal AVDD, the drain of the above fourth transistor M4 is coupled to the first signal output terminal M, and under the control of the potential of the second node N2 at the gate of the fourth transistor M4, the source of the fourth transistor M4 can receive the second-level signal AVDD, and output the second-level signal AVDD from the first signal output terminal M through the drain of the fourth transistor M4.

[0076] Further, as Figure 3 shown, the above first output sub-circuit A includes: a fourth transistor M4, a second node N2, a second voltage input terminal AVDD, and a first output signal terminal M. Among them, the transistor M4 is coupled to the second node N2, the second voltage input terminal AVDD, and the first output signal terminal M.

[0077] Exemplarily, the above first input sub-circuit includes: the input terminal of the second inverter I2 is coupled to the first node N1, the control terminal of the first transistor M1 is the gate, and the gate of the first transistor M1 is coupled to the output terminal of the second inverter I2. The first pole of the first transistor M1 is the source, and the second pole of the first transistor M1 is the drain. Among them, the drain of the first transistor M1 is coupled to the first voltage input terminal GND, that is, the ground terminal, and the source of the above first transistor M1 is coupled to the second node N2.

[0078] Exemplarily, the above second output sub-circuit includes: a second transistor. The control terminal of the above second transistor is coupled to the above first node, the first pole of the above second transistor is coupled to the above first voltage input terminal, and the second pole of the above second transistor is coupled to the above output signal terminal.

[0079] As Figure 3 shown, Figure 3The second output subcircuit B includes a second transistor M2. The control terminal of the second transistor M2 is the gate of the transistor M2, the first pole of the second transistor M2 is the source, and the second pole of the second transistor M2 is the drain. The source of the second transistor M2 is coupled to the first output signal terminal M, and the drain of the second transistor is coupled to the first voltage input terminal GND, that is, the ground terminal.

[0080] Exemplarily, the control subcircuit includes a third transistor. The second input subcircuit includes a third transistor. The control terminal of the third transistor is coupled to the first output signal terminal, the first pole of the third transistor is coupled to the second voltage input terminal, and the second pole of the third transistor is coupled to the second node.

[0081] Such as Figure 3 shown, in Figure 3 it includes a third transistor M3. The control terminal of the third transistor M3 is the gate, and the gate of the third transistor M3 is coupled to the first output signal terminal M. The first pole of the third transistor is the drain, and the second pole of the third transistor M3 is the source. Wherein, the source of the third transistor M3 is coupled to the second voltage input terminal, that is, coupled to AVDD, and the drain of the third transistor M3 is coupled to the second node N2.

[0082] Exemplarily, the third transistor may be a PMOS transistor, effective at a low level.

[0083] In another embodiment of the present application, the signal control input circuit further includes a buffer signal module. The buffer signal module is connected to the first signal output terminal and is used to receive the first control signal output by the first signal output terminal.

[0084] Exemplarily, the buffer signal module includes a third inverter and a fourth inverter. As Figure 3 shown, the buffer signal module E is connected to the first signal output terminal M.

[0085] Exemplarily, the input terminal of the third inverter is connected to the first signal output terminal, the input terminal of the fourth inverter is connected to the output terminal of the third inverter, and the output terminal of the fourth inverter is connected to the second output signal terminal.

[0086] Such as Figure 3 shown, specifically, the input terminal of the third inverter I3 is connected to the first signal output terminal M, the input terminal of the fourth inverter I4 is connected to the output terminal of the third inverter I3, and the output terminal of the fourth inverter I4 is connected to the second output signal terminal OUT.

[0087] In another embodiment of the present application, the first transistor is a first N-type transistor, the fourth transistor is a fourth P-type transistor, the second transistor is a second N-type transistor, and the third transistor is a third P-type transistor.

[0088] Exemplarily, the N-type transistor is an NMOS transistor, and the P-type transistor is a PMOS transistor.

[0089] It can be understood that the gate of the NMOS transistor can be turned on by a high level, while the gate of the PMOS transistor can be turned on by a low level.

[0090] Next, for Figure 3 two cases of the overall working process of the LSH circuit in, one is that the first input terminal GMA_EN_LV inputs a third-level signal, and the other is that the first input terminal GMA_EN_LV inputs a first-level signal. Among them, the third-level signal is a high-level signal (the third-level signal DVDD), and the first-level signal (GND). These two cases are introduced separately as follows.

[0091] The first case: When the first input terminal GMA_EN_LV inputs a third-level signal, that is, in the case of the third-level signal DVDD signal, this third-level signal DVDD signal belongs to a high-level signal. After passing through the first inverter I1, the level signal is inverted and converted into a low-level signal. Then, the first node N1 is at a low-level signal, and this low-level signal will be simultaneously transmitted to the first input sub-circuit and the second output sub-circuit respectively.

[0092] For the first input sub-circuit, the first input sub-circuit sequentially includes a second inverter I2 and a first transistor M1 in the signal transmission order. The second inverter I2 inverts the low-level signal here and converts it into a high-level signal. Since the first transistor M1 is an NMOS, the high-level signal is effective. At this time, the first transistor M1 is turned on, and the low-level signal at the ground terminal GND of the first transistor M1 is written into the second node N2, and the second node N2 is at a low level. The fourth transistor M4 is a PMOS, and it is turned on effectively by a low level. Then, the fourth transistor M4 is turned on, and the second-level signal AVDD of the fourth transistor M4 is output from the first output signal terminal M. When the first output signal terminal M is at a high level, the third transistor M3 is turned off.

[0093] For the second output sub-circuit, the second transistor M2 is an NMOS transistor, and it is effective at a high level. The first node N1 is at a low level, so the second transistor M2 is turned off.

[0094] The second case: When the first input terminal GMA_EN_LV inputs the first level signal GND, after passing through the first inverter I1, the low-level signal is inverted and converted into a high-level signal. Then, the first node N1 is at a high-level signal, and this high-level signal will be simultaneously transmitted to the first input sub-circuit and the second output sub-circuit respectively.

[0095] For the first input sub-circuit, the first input sub-circuit sequentially includes a second inverter I2 and a first transistor M1 in the signal transmission order. Then, the second inverter I2 inverts the high-level signal here and converts it into a low-level signal. Since the first transistor M1 is an NMOS transistor, the high-level signal is effective, and at this time, the first transistor M1 is turned off.

[0096] For the second output sub-circuit, the second transistor M2 is an NMOS transistor, and the high-level is effective. When the gate of the second transistor M2 is coupled to the first node N1, the second transistor M2 receives the level signal at the first node N1 as a high level, then the second transistor M2 is turned on. The first level signal GND of the first voltage input terminal is output from the first output signal terminal M. When the first output signal terminal M is at a low level, the third transistor M3 is turned on, and the second level signal AVDD output from the second voltage input terminal AVDD is written to the N2 node. The N2 node is at a high level, and the fourth transistor M4 is turned off.

[0097] Next, the working timing process of the buffer module in the overall working timing of the LSH circuit will be introduced.

[0098] Combined with the foregoing description of the overall working process of the LSH circuit, 1) when the first signal output terminal M is at a low-level signal, after passing through the third inverter I3 and the fourth inverter I4 twice, the reverse potential remains unchanged and is still a low-level signal; 2) when the first signal output terminal M is at a high-level signal, after passing through the third inverter I3 and the fourth inverter I4 twice, the reverse potential remains unchanged and is still a high-level signal. Thus, the signal control input circuit realizes the level conversion of the third level signal DVDD to the second level signal AVDD. The above-mentioned third inverter and fourth inverter can play a role in buffering signals.

[0099] In another embodiment of the present application, the above-mentioned logic control circuit includes a first logic control sub-circuit and a second logic control sub-circuit, and the above-mentioned first logic control sub-circuit and the above-mentioned second logic control sub-circuit are connected in parallel.

[0100] Exemplarily, the above-mentioned first logic control sub-circuit is used to generate the above-mentioned second control signal and transmit the above-mentioned second control signal to the above-mentioned Gamma amplifier.

[0101] Exemplarily, the above-mentioned second logic control sub-circuit is used to generate the above-mentioned third control signal and transmit the above-mentioned third control signal to the above-mentioned current discharge circuit.

[0102] It can be understood that from the foregoing content, after generating the above-mentioned first control signal, in order to ensure that the subsequent Gamma amplifier and the current discharge circuit are not driven simultaneously, this logic control circuit is set so that within the same timing, the current discharge circuit is not driven when the Gamma amplifier is driven, and the Gamma amplifier is not driven when the current discharge circuit is driven. Further, this logic control circuit includes two parallel logic control sub-circuits (the first logic control sub-circuit and the second logic control sub-circuit), and the two parallel logic control sub-circuits will output control signals simultaneously, which are the second control signal and the third control signal respectively. The above-mentioned second control signal and the above-mentioned third control signal are logically opposite in the same timing, specifically, the levels are opposite in the same timing.

[0103] When the second control signal is a high-level signal, the third control signal is a low-level signal; when the second control signal is a low-level signal, the third control signal is a high-level signal.

[0104] The specific structures of the first logic control sub-circuit and the second logic control sub-circuit in the logic control circuit are introduced as follows: Exemplarily, the second logic control sub-circuit includes: a fifth inverter, a first NAND gate, a first NOR gate, a sixth inverter, a seventh inverter, a tenth inverter, an eleventh inverter, a second intermediate node, and a third intermediate node.

[0105] The first logic control sub-circuit includes: a second NAND gate, an eighth inverter, a ninth inverter, a second NOR gate, a fourth intermediate node, a fifth intermediate node, a twelfth inverter, and a thirteenth inverter.

[0106] Exemplarily, the first input terminal of the first NAND gate is connected to the output terminal of the above-mentioned fifth inverter, the second input terminal of the first NAND gate is connected to the fifth intermediate node, and the output terminal of the first NAND gate is connected to the second intermediate node.

[0107] Exemplarily, the first input terminal of the first NOR gate is connected to the output terminal of the seventh inverter, the second input terminal of the first NOR gate is connected to the second intermediate node, and the output terminal of the first NOR gate is coupled to the third control signal output terminal of the second logic control sub-circuit.

[0108] Exemplarily, the first input terminal of the second NAND gate is connected to the first control signal output terminal, the second input terminal of the second NAND gate is connected to the third intermediate node, and the output terminal of the second NAND gate is connected to the third intermediate node.

[0109] Exemplarily, a first input terminal of the second NOR gate is connected to the ninth inverter, a second input terminal of the second NOR gate is connected to the fourth intermediate node, and an output terminal of the second NOR gate is coupled to a second control signal output terminal of the first logic control sub - circuit.

[0110] Exemplarily, the second intermediate node is a node between the first NAND gate and the sixth inverter, and the third intermediate node is a node between the seventh inverter and the first NOR gate.

[0111] Exemplarily, the fourth intermediate node is a node between the second NAND gate and the eighth inverter, and the fifth intermediate node is a node between the ninth inverter and the second NOR gate.

[0112] Below Figure 4 shown Figure 4 is the circuit diagram of the second logic control sub - circuit and the circuit diagram of the first logic control sub - circuit as described above. It can be seen from Figure 4 the circuit that it includes a second logic control sub - circuit 41 and a first logic control sub - circuit 51. Among them, the difference between the second logic control sub - circuit 41 and the first logic control sub - circuit 51 is that the second logic control sub - circuit 41 adds an inverter compared with the first logic control sub - circuit 51, so that the output logics of the second logic control sub - circuit 41 and the first logic control sub - circuit 51 are just opposite.

[0113] The second logic control sub - circuit 41 is connected to a first control signal output terminal GMA_EN1 of the signal input control circuit. After the output terminal GMA_EN1 of the signal input control circuit, it successively includes a fifth inverter I5, a first NAND gate nand1, a sixth inverter I6, a seventh inverter I7, and a first NOR gate nor2. There is a second intermediate node N4 between the first NAND gate nand1 and the sixth inverter I6, and there is a third intermediate node N5 between the seventh inverter I7 and the first NOR gate nor2.

[0114] The first logic control sub - circuit 51 is connected to a first control signal output terminal GMA_EN1 of the signal input control circuit. After that, it successively includes a second NAND gate nand2, an eighth inverter I8, a ninth inverter I9, and a second NOR gate nor2. There is a fourth intermediate node N6 between the second NAND gate nand2 and the eighth inverter I8, and there is a fifth intermediate node N7 between the ninth inverter I9 and the second NOR gate nor.

[0115] Further, two inverters are connected in sequence after the first NOR gate nor1 in the second logic control sub-circuit 41, namely the tenth inverter I10 and the eleventh inverter I11, which can be used to buffer the signal output by the first NOR gate nor1 in the second logic control sub-circuit 41; two inverters are connected in sequence after the second NOR gate nor2 in the second logic control sub-circuit 41, namely the twelfth inverter I12 and the thirteenth inverter I13, which can be used to buffer the signal output by the second NOR gate nor2 in the first logic control sub-circuit 51. The third control signal output terminal 242 of the eleventh inverter I11 of the second logic control sub-circuit 41 is connected to the current bleeding circuit, and the second control signal output terminal 241 of the thirteenth inverter I14 of the first logic control sub-circuit 51 is connected to the Gamma amplifier.

[0116] First, the truth table of the NAND gate nand (as shown in Table 1 below) and the truth table of the NOR gate nor (as shown in Table 2 below) will be introduced.

[0117]

[0118] Table 1

[0119] Table 2 It can be understood that in Table 1 and Table 2 above, 0 represents low level and 1 represents high level.

[0120] Based on the differences in the truth tables of the NAND gate nand and the NOR gate nor, two logic gates are respectively set for the first logic control sub-circuit and the second logic control sub-circuit. These two logic gates include a NAND gate and a NOR gate; at the same time, the first logic control sub-circuit is provided with one more inverter than the second logic control sub-circuit, and finally the levels output by the first logic control sub-circuit and the second logic control sub-circuit are opposite, ensuring that only one of the first logic control sub-circuit connected to the Gamma amplifier and the first logic control sub-circuit connected to the current bleeding circuit outputs a high-level signal, that is, only one of the Gamma amplifier and the current bleeding circuit will be triggered.

[0121] As can be known from the foregoing introduction to the signal input control circuit, the signals output by the signal input control circuit include that the output first control signal is the second level signal AVDD or the first level signal GND. The following is the specific situation of the above first logic control sub-circuit and second logic control sub-circuit when the first control signal is in different signals: As Figure 5 and Figure 6 shown, in Figure 5 and Figure 6Both include the timing diagram of the second logic control sub-circuit 41 and the timing diagram of the first logic control sub-circuit 51.

[0122] Figure 5 For showing the scenario where the AVDD signal is output by the signal input control circuit, it can be seen that for the second logic control sub-circuit 41, the logical signal value corresponding to the AVDD signal is 1. Then in the second logic control sub-circuit 41, after passing through the fifth inverter I5, the logical value becomes 0. This logical value is input to the first input terminal of the first NAND gate nand1. At the same time, the second input terminal of nor1 receives the logical value 0 of N7. Then the logical value output by the first NAND gate nand1 to the second node N3 is 1. After passing through the sixth inverter I6 and the seventh inverter I7, the logical value reaching the third intermediate node N5 is 1. This logical value 1 is input to the first input terminal of the first NOR gate nor1, and the second input terminal of the first NOR gate nor1 is connected to the second intermediate node N4. Finally, the logical value output by the first NOR gate nor1 is 0. After passing through two more inverters I10 and I11, the output logical value is 0, that is, the third control signal output terminal outputs the third control signal PD-EN-P8V as a low level, which means the current discharge circuit will not be triggered.

[0123] In Figure 5 In the scenario where the AVDD signal is output by the signal input control circuit, the second input terminal of the first logic control sub-circuit 51 receives the logical value 1 corresponding to the medium voltage control signal GMA_EN. This logical value 1 is input to the first input terminal of the second NAND gate nand2. At the same time, the logical value of the third intermediate node N5 is input to the second input terminal of the second NAND gate nand2. Then the logical value output by the second NAND gate nand2 is 0. After passing through the eighth inverter I8 and the ninth inverter I9, the logical value output to the fifth intermediate node N7 is still 0. Then the first input terminal of the second NOR gate nor2 receives the logical value 0 of the fifth intermediate node N7, and the second input segment of the second NOR gate nor2 receives the logical value 0 of the fourth intermediate node N6. Finally, the second NOR gate nor2 outputs a logical value of 1. After passing through two more inverters I12 and I13, the output logical value is 1, that is, the second control signal output terminal outputs the second control signal GMA_OP_P8V as a high level, which means the Gamma amplifier will be triggered.

[0124] Figure 6The scenario for showing the GND signal output by the signal input control circuit is as follows. It can be seen that for the second logic control sub-circuit 41, the logical signal value corresponding to the low-level signal is 0. Then in the second logic control sub-circuit 41, after passing through the fifth inverter I5, the logical value becomes 1. This logical value is input to the first input terminal of the first NAND gate nand1. At the same time, the logical value of the fifth intermediate node N7 is received at the second input terminal of the first NAND gate nand1. Then the logical value output by the first NAND gate nand1 to the second intermediate node N3 is 0. After passing through the sixth inverter I6 and the seventh inverter I7, the logical value at the third intermediate node N5 is 0. This logical value 0 is input to the first input terminal of the first NOR gate nor1, and the second input terminal of the first NOR gate nor1 is connected to the second node N3. Finally, the logical value output by the first NOR gate nor1 is 1. After passing through two more inverters I10 and I11, the output logical value is 1, that is, the third control signal output terminal outputs the third control signal PD-EN-P8V as a high level, which means that the current discharge circuit will be triggered.

[0125] In Figure 6 In the scenario where the signal input control circuit outputs a low-level signal, the second input terminal of the first logic control sub-circuit 51 receives the logical value 0 corresponding to the low-level signal. This logical value 0 is input to the first input terminal of the second NAND gate nand2. At the same time, the logical value of the third intermediate node N5 is input to the second input terminal of the second NAND gate nand2. Then the logical value output by the second NAND gate nand2 is 1. After passing through the eighth inverter I8 and the ninth inverter I9, the logical value output to the fifth intermediate node N7 remains 1. Then the first input terminal of the second NOR gate nor2 receives the logical value 1 of the fifth intermediate node N7, and the second input segment of the second NOR gate nor2 receives the logical value 1 of the fourth intermediate node N6. Finally, the second NOR gate nor2 outputs a logical value of 0. After passing through two more inverters I12 and I13, the output logical value is 0, that is, the second control signal output terminal outputs the second control signal GMA_OP_P8V as a low level, which means that the Gamma amplifier will not be triggered.

[0126] Optionally, the second logic control sub-circuit includes a first delay module, a second delay module, a sixth intermediate node, and a seventh intermediate node. The sixth intermediate node is disposed between the sixth inverter and the seventh inverter, and the seventh intermediate node is disposed between the seventh inverter and the first NOR gate. The first delay module is coupled to the sixth intermediate node, and the second delay module is coupled to the seventh intermediate node.

[0127] The first logic control sub-circuit includes a third delay module, a fourth delay module, an eighth intermediate node, and a ninth intermediate node. The eighth intermediate node is disposed between the eighth inverter and the ninth inverter, and the ninth intermediate node is disposed between the ninth inverter and the second NOR gate. The third delay module is coupled to the eighth intermediate node, and the fourth delay module is coupled to the ninth intermediate node.

[0128] As Figure 4 shown, Figure 4 it includes a first delay module 41, a second delay module 42, a third delay module 43, and a fourth delay module 44. Among them, the first delay module 41 is coupled to the sixth intermediate node N8, the second delay module 42 is coupled to the seventh intermediate node N9, the third delay module 43 is coupled to the eighth intermediate node N10, and the fourth delay module 44 is coupled to the ninth intermediate node N11.

[0129] Exemplarily, the above-mentioned first delay module is a first capacitor formed by connecting the source and drain of a fifth P-type transistor together; the above-mentioned second delay module is a second capacitor formed by connecting the source and drain of a sixth P-type transistor together; the above-mentioned third delay module is a third capacitor formed by connecting the source and drain of a seventh P-type transistor together; the above-mentioned fourth delay module is a fourth capacitor formed by connecting the source and drain of an eighth P-type transistor together.

[0130] The above-mentioned first delay module and second delay module can form a resistor-capacitor delay (RC delay) in the first logic control sub-circuit to meet the expected timing phase requirements; correspondingly, the third delay module and the fourth delay module can form a resistor-capacitor delay (RC delay) in the second logic control sub-circuit to meet the expected timing phase requirements.

[0131] In another embodiment of the present application, the above-mentioned discharge circuit includes at least one resistor and at least one transistor. The at least one resistor is connected to a target signal line in the signal lines. A first pole of the at least one transistor is coupled to the at least one resistor, a second pole of the at least one transistor is coupled to the first voltage input terminal, and a control terminal of the at least one transistor is connected to the logic control circuit.

[0132] It can be understood that the discharge circuit is composed of several circuits connected to the target signal line. Specifically, the number of circuits included in the discharge circuit is greater than or equal to the number of signal lines of the target signal line.

[0133] To ensure the discharge effect, a resistor needs to be set for each circuit connected to the target signal line.

[0134] In one example, for the target signal line, the resistance value of the discharge circuit corresponding to each signal line in the target signal line can be greater than 20 kΩ. This resistance value can be composed of a single resistor or multiple resistors.

[0135] Exemplarily, the above transistor can be the switch of the discharge circuit. Among them, the first pole of the transistor is the drain of the transistor and is coupled to at least one resistor. The second pole of the transistor is the source of the transistor and is coupled to the first voltage input terminal, that is, the ground terminal. The control terminal of the transistor is the gate of the transistor and is coupled to the logic control circuit, and controls the conduction or cut-off of the transistor according to the level signal of the third control signal output by the logic control circuit.

[0136] Optionally, in the embodiments of the present application, the above target signal line is at least one signal line among the above signal lines.

[0137] It can be understood that the target signal line can include one signal line among the above signal lines or multiple signal lines. The embodiments of the present application do not limit this.

[0138] Optionally, in the embodiments of the present application, when there are multiple target signal lines, the gray scale interval values between the multiple signal lines can be uniform. Exemplarily, when the target signal line is multiple signal lines among the signal lines, the gray scale voltage difference between any two adjacent signal lines in the target signal line is less than or equal to a preset gray scale voltage difference threshold.

[0139] It can be understood that each signal line corresponds to a gray scale voltage value. Then, when there are multiple target signal lines and the gray scale voltage values between each are evenly spaced, the gray scale voltage intervals between any two adjacent signal lines in the target signal line are subtracted from each other to form a gray scale voltage difference. The multiple gray scale voltage differences are close to 0, that is, less than or equal to a preset gray scale voltage difference threshold. For example, as Figure 2 shown, it is set that the target signal line includes three signal lines, namely VGMA【0】, VGMA

[512] , and VGMA

[1024] . Among them, the gray scale voltage difference 1 is obtained by subtracting VGMA【0】 from VGMA

[512] , and the gray scale voltage difference 2 is obtained by subtracting VGMA

[512] from VGMA

[1024] . The difference between the gray scale voltage difference 1 and the gray scale voltage difference 2 is less than the preset gray scale voltage difference threshold and can be close to 0, for example.

[0140] And as Figure 2 stated, a resistor is provided for each circuit connected to the target signal line. Figure 2 Among them, the resistor of the discharge circuit connected to the signal line VGMA

[1024] is R1, the resistor of the discharge circuit connected to the signal line VGMA

[512] is R2, and the resistor of the discharge circuit connected to the signal line VGMA【0】 is R3.

[0141] Exemplarily, the above preset grayscale voltage difference threshold can be preset or can be set customarily, and the embodiments of the present application do not limit this.

[0142] Optionally, in the embodiments of the present application, when there are multiple target signal lines, the grayscale intervals between the multiple signal lines can be uneven. Exemplarily, when the target signal lines are multiple signal lines among the signal lines, the target signal lines include a first signal line, a second signal line, and a third signal line, the grayscale voltage value of the second signal line is any grayscale voltage value between the grayscale voltage value of the first signal line and the grayscale voltage value of the third signal line, and the second signal line includes at least one signal line.

[0143] It can be understood that during the process of setting the target signal lines, multiple uneven target signal lines can be arbitrarily set and connected to the current discharge circuit for current discharge.

[0144] In this way, according to the actual current discharge requirements, a current discharge circuit can be arranged for the signal lines that are prone to accumulating residual data to release the residual data, so as to ensure that the overall current discharge method is scientific and highly practical.

[0145] Optionally, in the embodiments of the present application, when there are multiple target signal lines, the distribution mode of the grayscale values of the multiple signal lines is high, medium, and low. Exemplarily, when the target signal lines include a first signal line, a second signal line, and a third signal line, the first signal line is the signal line with the largest grayscale voltage value among the signal lines, the third signal line is the signal line with the smallest grayscale voltage value among the signal lines, and the second signal line is the signal line with the intermediate grayscale voltage value between the first signal line and the third signal line.

[0146] It can be understood that during the process of setting the target signal lines, three signal lines with high, medium, and low voltage differences can be arbitrarily set as the target signal lines. These three target signal lines include the signal line with the largest grayscale voltage value, the signal line with the smallest grayscale voltage value, and the signal line with the grayscale voltage value between the signal line with the largest grayscale voltage value and the signal line with the smallest grayscale voltage value, and are connected to the current discharge circuit for current discharge.

[0147] For example, as Figure 2As shown in the figure, the target signal lines are set to include three signal lines, namely the third signal line VGMA【0】, the second signal line VGMA

[512] , and the first signal line VGMA

[1024] . Among them, the first signal line VGMA

[1024] is the signal line with the largest gray-scale voltage value among the signal lines, the third signal line VGMA【0】 is the signal line with the smallest gray-scale voltage value among the signal lines, and the second signal line VGMA

[512] is the signal line with the intermediate gray-scale voltage value between the first signal line and the third signal line.

[0148] In this way, by evenly arranging the signal lines that need to discharge current, it is simple and fast to set up a plurality of signal lines for discharging current. While ensuring that the discharge circuit can discharge current for the signal lines, the efficiency of arranging the discharge circuit is improved.

[0149] Optionally, in the embodiments of the present application, the discharge circuit includes resistors. The voltages of the signal lines are made different through the resistors. Different signal lines have different resistors, and adjacent target signal lines are signal lines with a consistent resistance interval.

[0150] Exemplarily, each target signal line in the Gamma driving circuit is connected in series with a resistor. Different target signal lines correspond to resistors with the same or different resistance values. The different resistance values of the resistors correspond to the gray-scale voltage values of the different target signal lines.

[0151] Exemplarily, as described above, each signal line in the target signal lines needs to be connected in series with a resistor to complete rapid discharge of current.

[0152] In one example, the resistor connected in series with each signal line can be set to the maximum resistor within a preset range. For example, if the maximum resistor is 20KΩ, then each signal line can be connected in series with this maximum resistor.

[0153] Furthermore, the resistance values of multiple signal lines among the above-mentioned target signal lines can be the same or different, and the resistance value is proportional to the magnitude of the gray-scale voltage value connected thereto.

[0154] In this way, by flexibly setting the resistors, without being restricted to the number and magnitude of the resistance values of the resistors, more choices and greater flexibility are available during the process of setting resistors for the discharge circuit, which is beneficial to reducing the setting cost and improving the setting efficiency.

[0155] The present application also provides a display device including a control circuit of a Gamma driving circuit, and the control circuit of the Gamma driving circuit in the first aspect described above.

[0156] Among the several modules or units mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0157] It should be noted that for the details not disclosed in the display device including the control circuit with the Gamma driving circuit in the embodiments of the present application, please refer to the details disclosed in the above embodiments of the present application, and will not be elaborated here.

[0158] The above description is only the preferred embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the foregoing disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

Claims

1. A control circuit for a Gamma driving circuit, characterized in that, The Gamma driving circuit includes: a multi-stage amplifier and multiple signal lines, and the amplifier is used to control the signal lines to output different grayscale signals; The control circuit includes: a signal input control circuit, a logic control circuit, and a current discharge circuit; The signal input control circuit is connected to the first input end and the logic control circuit, and outputs a first control signal to the logic control circuit; The logic control circuit is connected to the signal input control circuit, the current discharge circuit, and the amplifier. According to the first control signal, a second control signal and a third control signal are generated, and the second control signal is transmitted to the amplifier, and the third control signal is transmitted to the current discharge circuit; The current discharge circuit is connected to the signal line and the logic control circuit, and under the control of the third control signal, releases the residual signal in the signal line.

2. The circuit according to claim 1, wherein The second control signal and the third control signal are logically opposite in the same time sequence.

3. The circuit according to claim 1, characterized in that, The signal input control circuit includes a first inverter and a first node. The first inverter is coupled to the first input end and the first node, and is configured to perform a logical reverse control on the potential of the first node for the level signal corresponding to the first input signal after receiving the first input signal input from the first input end.

4. The circuit according to claim 3, wherein The signal input control circuit further includes a first output sub-circuit, a second output sub-circuit, a first input sub-circuit, a second node, and a control sub-circuit; The first output sub-circuit is coupled to the second node, the second voltage input end, and the first output signal end, and is configured to generate the first control signal from the second level signal of the second voltage input end under the control of the potential of the second node, and transmit the first control signal to the logic control circuit; The second output sub-circuit is coupled to the first node, the first voltage input end, and the first output signal end, and is configured to generate the first control signal from the first level signal of the first voltage input end under the control of the potential of the first node, and transmit the first control signal to the logic control circuit; The first input sub-circuit is coupled to the first node, the first voltage input end, and the second node, and is configured to control the potential of the second node under the control of the potential of the first node; The control sub-circuit is coupled to the second node, the second voltage input end, and the first output signal end, and is configured to control the potential of the second node under the control of the potential of the output signal provided by the first output signal end.

5. The circuit according to claim 4, wherein The first output sub-circuit includes: a fourth transistor, the control end of the fourth transistor is coupled to the second node, the first pole of the fourth transistor is coupled to the second voltage input end, and the second pole of the fourth transistor is coupled to the first output signal end; The first input sub-circuit includes: a second inverter and a first transistor; The input end of the second inverter is coupled to the first node; The control terminal of the first transistor is coupled to the output terminal of the second inverter. The first pole of the first transistor is coupled to the first voltage input terminal. The second pole of the first transistor is coupled to the second node. The second output sub - circuit includes: a second transistor. The control terminal of the second transistor is coupled to the first node. The first pole of the second transistor is coupled to the first voltage input terminal. The second pole of the second transistor is coupled to the first output signal terminal. The control sub - circuit includes a third transistor. The control terminal of the third transistor is coupled to the first output signal terminal. The first pole of the third transistor is coupled to the second voltage input terminal. The second pole of the third transistor is coupled to the second node.

6. The circuit according to claim 4, wherein The signal control input circuit further includes a buffer signal module. The buffer signal module is connected to the first signal output terminal for receiving the first control signal output from the first signal output terminal. The buffer signal module includes a third inverter and a fourth inverter. The input terminal of the third inverter is connected to the first output signal terminal. The input terminal of the fourth inverter is connected to the output terminal of the third inverter. The output terminal of the fourth inverter is connected to the second output signal terminal.

7. The circuit according to claim 5, wherein The first transistor is a first N - type transistor. The fourth transistor is a fourth P - type transistor. The second transistor is a second N - type transistor. The third transistor is a third P - type transistor.

8. The circuit according to claim 1, wherein The logic control circuit includes a first logic control sub - circuit and a second logic control sub - circuit, which are connected in parallel. The first logic control sub - circuit is used to generate the second control signal and transmit the second control signal to the Gamma amplifier. The second logic control sub - circuit is used to generate the third control signal and transmit the third control signal to the current bleeding circuit.

9. The circuit according to claim 8, wherein The second logic control sub - circuit includes: a fifth inverter, a first NAND gate, a first NOR gate, a sixth inverter, a seventh inverter, a tenth inverter, an eleventh inverter, a second intermediate node, and a third intermediate node. The first logic control sub - circuit includes: a second NAND gate, an eighth inverter, a ninth inverter, a second NOR gate, a fourth intermediate node, a fifth intermediate node, a twelfth inverter, and a thirteenth inverter. The first input terminal of the first NAND gate is connected to the output terminal of the fifth inverter. The second input terminal of the first NAND gate is connected to the fifth intermediate node. The output terminal of the first NAND gate is connected to the second intermediate node. The first input terminal of the first NOR gate is connected to the output terminal of the seventh inverter. The second input terminal of the first NOR gate is connected to the second intermediate node. The output terminal of the first NOR gate is coupled to the third control signal output terminal of the second logic control sub - circuit. The first input terminal of the second NAND gate is connected to the first control signal output terminal. The second input terminal of the second NAND gate is connected to the third intermediate node. The output terminal of the second NAND gate is connected to the fourth intermediate node. The first input terminal of the second NOR gate is connected to the ninth inverter, the second input terminal of the second NOR gate is connected to the fourth intermediate node, and the output terminal of the second NOR gate is coupled to the second control signal output terminal of the first logic control sub - circuit.

10. The circuit according to claim 9, wherein, The second logic control sub - circuit further includes a first delay module, a second delay module, a sixth intermediate node, and a seventh intermediate node. The sixth intermediate node is disposed between the sixth inverter and the seventh inverter, and the seventh intermediate node is disposed between the seventh inverter and the first NOR gate. The first delay module is coupled to the sixth intermediate node, and the second delay module is coupled to the seventh intermediate node; The first logic control sub - circuit includes a third delay module, a fourth delay module, an eighth intermediate node, and a ninth intermediate node. The eighth intermediate node is disposed between the eighth inverter and the ninth inverter, and the ninth intermediate node is disposed between the ninth inverter and the second NOR gate. The third delay module is coupled to the eighth intermediate node, and the fourth delay module is coupled to the ninth intermediate node.

11. The circuit according to claim 1, characterized in that, The discharge circuit includes at least one resistor and at least one transistor. The at least one resistor is connected to a target signal line among the signal lines. The first pole of the at least one transistor is coupled to the at least one resistor, the second pole of the at least one transistor is coupled to the first voltage input terminal, and the control terminal of the at least one transistor is connected to the logic control circuit.

12. The circuit according to claim 11, wherein The target signal line is at least one signal line among the signal lines.

13. The circuit according to any one of claims 11-12, characterized in that, When the target signal line is multiple signal lines among the signal lines, the gray - scale voltage difference between any two adjacent signal lines corresponding to the target signal lines is less than or equal to a preset gray - scale voltage difference threshold.

14. The circuit according to any one of claims 11-12, characterized in that, When the target signal line is multiple signal lines among the signal lines, the target signal line includes a first signal line, a second signal line, and a third signal line. The gray - scale voltage value of the second signal line is any gray - scale voltage value between the gray - scale voltage value of the first signal line and the gray - scale voltage value of the third signal line, and the second signal line includes at least one signal line.

15. The circuit according to any one of claims 11-12, characterized in that, When the target signal line includes a first signal line, a second signal line, and a third signal line, the first signal line is the signal line with the largest gray - scale voltage value among the signal lines, the third signal line is the signal line with the smallest gray - scale voltage value among the signal lines, and the second signal line is the signal line with an intermediate gray - scale voltage value between the first signal line and the third signal line.

16. The circuit according to any one of claims 11-12, characterized in that, Each target signal line in the Gamma driving circuit is in series with a resistor, and different target signal lines correspond to resistors with the same or different resistance values. The different resistance values of the resistors correspond to the gray - scale voltage values of the different target signal lines.

17. A display device including a control circuit with a Gamma driving circuit, characterized in that, The display device of the control circuit of the Gamma driving circuit includes the control circuit according to any one of claims 1 - 16.

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