Gate driving circuit, driving method thereof, display substrate and display device

Abstract

A gate drive circuit includes a first operational circuit, a second operational circuit, a first conversion circuit and a second conversion circuit. The first operational circuit is configured to generate a write switching signal by a logical operation. The first conversion circuit is connected with the first operational circuit and is configured to process the write-in switch signal and generate a write-in switch driving signal provided for the pixel circuit. The second conversion circuit is connected with the first operational circuit and is configured to process the write-in switch signal and provide the processed signal to the enable input end of the second operational circuit. And the second operation circuit is connected with the second conversion circuit and is configured to generate a display switch signal through logical operation under the triggering of the signal output by the second conversion circuit. Wherein the signal transmission delay duration of the second conversion circuit is greater than the signal transmission delay duration of the first conversion circuit.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and particularly relates to a gate driving circuit, a driving method thereof, a display substrate, and a display device. Background Art

[0002] Micro Organic Light-Emitting Diode (abbreviated as Micro-OLED) is a micro display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED is a new display technology that combines semiconductor process technology and OLED display technology to fabricate OLED display devices on a wafer substrate. Due to the advantages of both semiconductor process technology and OLED display technology, silicon-based OLED not only has a high pixel density (Pixels Per Inch, abbreviated as PPI), but also has advantages such as high brightness, low power consumption, high response speed, high color gamut, and high thermal stability. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of this application provide a gate driving circuit, a driving method thereof, a display substrate, and a display device.

[0005] On the one hand, this embodiment provides a gate driving circuit, including: a first operation circuit, a second operation circuit, a first conversion circuit, and a second conversion circuit. The first operation circuit is configured to generate a write switch signal through logical operations; the first conversion circuit is connected to the first operation circuit and is configured to process the write switch signal to generate a write switch driving signal provided to the pixel circuit. The second conversion circuit is connected to the first operation circuit and is configured to process the write switch signal and provide the processed signal to the enable input terminal of the second operation circuit. The second operation circuit is connected to the second conversion circuit and is configured to generate a display switch signal through logical operations under the trigger of the signal output by the second conversion circuit. Wherein, the signal transmission delay duration of the second conversion circuit is greater than that of the first conversion circuit.

[0006] In some exemplary embodiments, the write switch signal includes: alternating first and second pulse signals; the active level of the first pulse signal is configured to control the gate electrode of the driving transistor of the pixel circuit to write a bias voltage, and the active level of the second pulse signal is configured to control the gate electrode of the driving transistor of the pixel circuit to write a data voltage; the duration of the active level of the first pulse signal is less than or equal to the duration of the active level of the second pulse signal. The active level of the display switch signal is configured to control the driving transistor of the pixel circuit to perform self-discharge. Within one frame period, the end time of the active level of the first pulse signal of the write switch signal is earlier than or equal to the start time of the active level of the display switch signal; the end time of the active level of the display switch signal is later than the end time of the active level of the second pulse signal of the write switch signal.

[0007] In some exemplary embodiments, the gate driving circuit further includes: a third conversion circuit, connected to the second operation circuit, configured to process the display switch signal to generate a display switch driving signal provided to the pixel circuit.

[0008] In some exemplary embodiments, the write switch driving signal includes alternating first and second pulse signals; the write switch signal includes alternating first and second pulse signals; the output signal of the second conversion circuit includes alternating first and second pulse signals. There is a first delay duration between the end time of the active level of the first pulse signal of the write switch driving signal and the start time of the active level of the display switch driving signal; there is a second delay duration between the start time of the active level of the first pulse signal of the write switch signal and the start time of the active level of the first pulse signal of the output signal of the second conversion circuit; the ratio of the second delay duration to the first delay duration is greater than 0.9 and less than 1.1.

[0009] In some exemplary embodiments, the second conversion circuit includes: N inverters connected in series, where N is an even number greater than 0.

[0010] In some exemplary embodiments, the second conversion circuit includes: six inverters connected in series.

[0011] In some exemplary embodiments, each inverter in the second conversion circuit includes: a transistor group, the transistor group includes a P-type transistor and an N-type transistor, the gate electrode of the P-type transistor is connected to the gate electrode of the N-type transistor, the second pole of the P-type transistor is connected to the second pole of the N-type transistor, the first pole of the P-type transistor is connected to the first power supply line, and the first pole of the N-type transistor is connected to the ground wire.

[0012] In some exemplary embodiments, the first conversion circuit includes: a first level converter and a first row driving enhancer. The first level converter is configured to perform a voltage domain conversion on the write switch signal. The first row driving enhancer is connected to the first level converter and is configured to enhance the signal processed by the first level converter.

[0013] In some exemplary embodiments, the first arithmetic circuit includes: a first NAND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a first NOR gate, a second NOR gate, a third NOR gate, and a two-way selector. The first input terminal of the first NAND gate is configured to receive a second timing signal, the second input terminal of the first NAND gate is configured to receive a third timing signal, the output terminal of the first NAND gate is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is configured to receive a first timing signal, the output terminal of the first NOR gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate is configured to receive a fourth timing signal, the output terminal of the second NOR gate is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the second input terminal of the two-way selector; the input terminal of the fourth inverter is configured to receive a second reset signal, the output terminal of the fourth inverter is connected to the second input terminal of the third NOR gate, the first input terminal of the third NOR gate is configured to receive a first reset signal, the output terminal of the third NOR gate is connected to the control terminal of the two-way selector; the first input terminal of the two-way selector is configured to receive a first timing signal, and the output terminal of the two-way selector serves as the output terminal of the first arithmetic circuit.

[0014] In some exemplary embodiments, the second arithmetic circuit includes: a latch, a fourth NOR gate, and a second NAND gate. The enable input terminal of the latch is connected to the output terminal of the second conversion circuit. The data input terminal of the latch is configured to receive a second timing signal. The output terminal of the latch is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth NOR gate is configured to receive a ratio control signal. The output terminal of the fourth NOR gate is connected to the first input terminal of the second NAND gate. The second input terminal of the second NAND gate is configured to receive a second reset signal. The output terminal of the second NAND gate serves as the output terminal of the second arithmetic circuit.

[0015] In some exemplary embodiments, the latch includes: a fifteenth inverter, a third NAND gate, a fourth NAND gate, a fifth NAND gate, and a sixth NAND gate. The input terminal of the fifteenth inverter is connected to the first input terminal of the third NAND gate, serving as the data input terminal of the latch. The output terminal of the fifteenth inverter is connected to the first input terminal of the fourth NAND gate. The second input terminal of the third NAND gate is connected to the second input terminal of the fourth NAND gate, serving as the enable input terminal of the latch. The output terminal of the third NAND gate is connected to the first input terminal of the fifth NAND gate, and the output terminal of the third NAND gate is connected to the second input terminal of the sixth NAND gate. The second input terminal of the fifth NAND gate is connected to the output terminal of the sixth NAND gate, serving as the inverted output terminal of the latch. The first input terminal of the sixth NAND gate is connected to the output terminal of the fifth NAND gate, serving as the output terminal of the latch.

[0016] In some exemplary embodiments, the fourth NOR gate includes: a sixteenth P-type transistor, a seventeenth P-type transistor, a sixteenth N-type transistor, and a seventeenth N-type transistor. The gate electrode of the sixteenth P-type transistor is connected to the gate electrode of the sixteenth N-type transistor, serving as the second input terminal of the fourth NOR gate. The gate electrode of the seventeenth P-type transistor is connected to the gate electrode of the seventeenth N-type transistor, serving as the first input terminal of the fourth NOR gate. The first pole of the sixteenth P-type transistor is connected to the first power supply line. The second pole of the sixteenth P-type transistor is connected to the first pole of the seventeenth P-type transistor. The second pole of the seventeenth P-type transistor is connected to the second pole of the sixteenth N-type transistor and the second pole of the seventeenth N-type transistor, serving as the output terminal of the fourth NOR gate. The first pole of the sixteenth N-type transistor and the first pole of the seventeenth N-type transistor are both connected to the ground wire.

[0017] In some exemplary embodiments, the second NAND gate includes: an eighteenth P-type transistor, a nineteenth P-type transistor, an eighteenth N-type transistor, and a nineteenth N-type transistor. The gate electrode of the eighteenth P-type transistor is connected to the gate electrode of the eighteenth N-type transistor and serves as the first input terminal of the second NAND gate; the gate electrodes of the nineteenth P-type transistor and the nineteenth N-type transistor are connected and serve as the second input terminal of the second NAND gate. The first poles of the eighteenth P-type transistor and the nineteenth P-type transistor are connected to a first power supply line; the second poles of the eighteenth P-type transistor, the nineteenth P-type transistor, and the second pole of the eighteenth N-type transistor are connected and serve as the output terminal of the second NAND gate; the first pole of the nineteenth N-type transistor is connected to a ground wire, and the second pole of the nineteenth N-type transistor is connected to the first pole of the eighteenth N-type transistor.

[0018] In some exemplary embodiments, the gate driving circuit further includes: a first test circuit and a second test circuit. The first test circuit is connected to the output terminal of the first arithmetic circuit, and the second test circuit is connected to the output terminal of the second arithmetic circuit; the first test circuit includes two inverters connected in series; the second test circuit includes two inverters connected in series.

[0019] On the other hand, the present embodiment provides a driving method for a gate driving circuit, which is applied to the gate driving circuit as described above. The driving method includes: the first arithmetic circuit generates a write switch signal through logical operation, the first conversion circuit processes the write switch signal to generate a write switch driving signal provided to the pixel circuit; the second conversion circuit processes the write switch signal and provides the processed signal to the enable input terminal of the second arithmetic circuit. The second arithmetic circuit generates a display switch signal through logical operation under the trigger of the signal output by the second conversion circuit. Wherein, the signal transmission delay duration of the second conversion circuit is greater than the signal transmission delay duration of the first conversion circuit.

[0020] On the other hand, the present embodiment provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel circuit and at least one scan signal line. The scan signal line is configured to provide a scan signal to the connected pixel circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scan signal line in the display area, and at least one gate driving circuit includes the gate driving circuit as described above.

[0021] On the other hand, the present embodiment provides a display device, including the display substrate as described above.

[0022] Other features and advantages of the present application will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present application. Other advantages of the present application may be realized and obtained by the solutions described in the description and the drawings. Description of the Drawings

[0023] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the description. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0024] Figure 1 It is a schematic structural diagram of a silicon-based OLED display device;

[0025] Figure 2 It is a schematic plan view of a display area in a silicon-based OLED display device;

[0026] Figure 3 It is a schematic cross-sectional view of a display area in a silicon-based OLED display device;

[0027] Figure 4A and Figure 4B It is an equivalent circuit diagram of a pixel circuit;

[0028] Figure 5A is Figure 4A a driving timing diagram of the pixel circuit shown;

[0029] Figure 5B is Figure 4B a driving timing diagram of the pixel circuit shown;

[0030] Figure 6 It is a schematic structural diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0031] Figure 7 It is an exemplary structural diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0032] Figure 8 It is a working principle diagram of a first operation circuit and a first conversion circuit according to at least one embodiment of the present disclosure;

[0033] Figure 9 It is a working principle diagram of a second conversion circuit, a second operation circuit and a third conversion circuit according to at least one embodiment of the present disclosure;

[0034] Figure 10 It is a timing diagram of a latch of a second conversion circuit and a second operation circuit according to at least one embodiment of the present disclosure;

[0035] Figure 11The timing diagram of the second arithmetic circuit when the proportion of the emission time in at least one embodiment of the present disclosure is 100%;

[0036] Figure 12 The schematic diagram of the operation of the latch of the second arithmetic circuit in at least one embodiment of the present disclosure;

[0037] Figure 13 is Figure 12 The timing diagram of the operation of the latch shown;

[0038] Figure 14 The equivalent circuit diagram of the second conversion circuit and the second arithmetic circuit in at least one embodiment of the present disclosure. Detailed implementation manners

[0039] This application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in this application. Although many possible combinations of features are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0040] This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in this application can also be combined with any conventional features or elements to form a unique invention solution. Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any suitable combination. Therefore, except for the limitations made according to the appended claims and their equivalent replacements, the embodiments are not subject to other limitations. In addition, various modifications and changes can be made within the protection scope of the appended claims.

[0041] The drawing ratio in the present disclosure can be used as a reference in actual processes, but is not limited thereto. For example: the aspect ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0042] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than for quantitative limitation. "Multiple" in this specification means two or more numbers.

[0043] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of the present disclosure. The positional relationship of components changes appropriately according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be replaced appropriately according to the circumstances.

[0044] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be construed in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0045] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0046] In this specification, in order to distinguish the two poles of a transistor other than the gate electrode, one of the poles is directly described as the first pole and the other as the second pole. Among them, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap. Therefore, in this specification, the "source electrode" and "drain electrode" can swap with each other.

[0047] In this specification, "electrically connected" includes cases where constituent elements are connected together through an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as it can transmit electrical signals between the constituent elements to be connected. Examples of the "element having some electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0048] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes a state where the angle is 85° or more and 95° or less.

[0049] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0050] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, rounded edges, and deformations, etc.

[0051] In this specification, the effective level includes the level for turning on a transistor. For example, the effective level for turning on a P-type transistor is a low level, and the effective level for turning on an N-type transistor is a high level.

[0052] "About", "substantially", "approximately" in this specification mean not strictly defining the boundary and allowing cases within the process and measurement errors.

[0053] Figure 1 It is a schematic structural diagram of a silicon-based OLED display device. As Figure 1As shown, the silicon-based OLED display device may include a display area and a non-display area. The display area may include a plurality of scan signal lines, a plurality of data signal lines, and a plurality of sub-pixels PXij forming a plurality of pixel rows and a plurality of pixel columns. The plurality of scan signal lines are respectively disposed in the plurality of pixel rows, and the plurality of data signal lines are respectively disposed in the plurality of pixel columns. Each sub-pixel PXij may at least include a pixel circuit and a light-emitting device. The pixel circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel circuit of each sub-pixel PXij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel PXij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column, and the pixel circuits of the sub-pixel PXij are respectively connected to the i-th scan signal line and the j-th data signal line. Herein, i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC for short), a gate driver (GD for short), and a source driver (SD for short). The display driver circuit may at least include a timing controller (TCON for short). The timing controller is configured to generate the timing signals required by the gate driver, such as including a start signal (STV) and a clock signal (CKV), etc., and send the timing signals to the gate driver. The gate driver is respectively connected to the plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel circuits to implement the display line-by-line scanning function. The source driver is respectively connected to the plurality of data signal lines in the display area, and the source driver is configured to provide the required data signals (data) to the connected pixel circuits to implement the switching and control of the display screen.

[0054] In one example, the silicon-based OLED display device may be a single-chip display architecture (One Chip), integrating the gate driver, the source driver, the clock control unit, the image processing unit, and the storage unit, etc. on the same chip. The chip of the One Chip architecture includes both digital and analog parts and belongs to a mixed-signal chip.

[0055] In another example, the silicon-based OLED display device can be a two-chip display architecture. The gate driving device and the data driving device can be integrated in the display substrate. The clock control unit, the image processing unit, the Mobile Industry Processor Interface (MIPI for short), and the storage unit can be integrated in one chip, and this chip can be bonded and connected to the display substrate through a Chip On Chip (COC for short) process.

[0056] Figure 2 It is a schematic plan view of a display area in a silicon-based OLED display device. As Figure 2 shown, in a plane parallel to the display device, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include: a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 that emits light of a third color. Each of the three sub-pixels may include a pixel circuit and a light-emitting device. The pixel circuits in the sub-pixels are respectively connected to the scanning signal line and the data signal line. The pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and output a corresponding current to the light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel where it is located.

[0057] In some examples, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light.

[0058] In some examples, the planar shape of the light-emitting device of the sub-pixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The light-emitting devices of the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or pyramid shape, etc., and the present disclosure does not limit this here. In other possible embodiments, the pixel unit may include four sub-pixels, and the present disclosure does not limit this here.

[0059] Figure 3 It is a schematic cross-sectional view of a display area in a silicon-based OLED display device, Figure 3 schematically showing a structure for achieving full color by using white light + color film method. As Figure 3As shown in the figure, in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on a side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on a side of the color filter structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on a side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementation manners, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0060] In some examples, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be fabricated on the silicon substrate 101 through silicon semiconductor processes. The driving circuit layer 102 may include a plurality of circuit units, and the circuit units may at least include pixel circuits. The pixel circuits are respectively connected to a scan signal line and a data signal line. The pixel circuits may include a plurality of transistors and storage capacitors, Figure 3 and only one transistor is taken as an example herein. The transistor may include: a gate electrode G, a first pole S, and a second pole D. The gate electrode G, the first pole S, and the second pole D may be respectively connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W-via), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0061] In some examples, the light-emitting structure layer 103 may include a plurality of light-emitting devices. The light-emitting devices may at least include an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor through a connection electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power supply line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In some examples, the organic light-emitting layer may include a light-emitting layer (abbreviated as EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some examples, for the light-emitting devices that emit white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0062] In some examples, the first encapsulation layer 104 and the second encapsulation layer 106 can adopt the thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color film structure layer 105 can at least include: a red filter unit, a blue filter unit, and a green filter unit; the red filter unit is disposed in the red sub-pixel to filter the white light emitted by the light-emitting device into red light; the blue filter unit is disposed in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light; the green filter unit is disposed in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover plate layer 107 can be made of glass or a flexible plastic such as colorless polyimide.

[0063] Figure 4A and Figure 4B is an equivalent circuit diagram of a pixel circuit. As Figure 4A and Figure 4B shown, the pixel circuit can be a 4T2C structure, and can include 4 transistors (for example, including a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and 2 storage capacitors (for example, including a first capacitor C1 and a second capacitor C2). The pixel circuit can be connected to 6 signal lines (for example, including a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DL, a first pixel power supply line ELVDD, and a second pixel power supply line VSS1).

[0064] In some examples, the pixel circuit can include a first pixel node N1, a second pixel node N2, and a third pixel node N3. The first pixel node N1 is respectively connected to the second pole of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1. The second pixel node N2 is respectively connected to the second pole of the second transistor T2, the first pole of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2. The third pixel node N3 is respectively connected to the second pole of the third transistor T3 and the second pole of the fourth transistor T4.

[0065] In some examples, the first transistor T1 can be referred to as a write switch transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first pole of the first transistor T1 is connected to the data signal line DL, and the second pole of the first transistor T1 is connected to the first pixel node N1.

[0066] In some examples, the second transistor T2 may be referred to as a Display Switch transistor. The gate electrode of the second transistor T2 is connected to the second scan signal line S2. The first pole of the second transistor T2 is connected to the first pixel power line ELVDD. The second pole of the second transistor T2 is connected to the second pixel node N2.

[0067] In some examples, the third transistor T3 may be referred to as a Driver transistor. The gate electrode of the third transistor T3 is connected to the first pixel node N1. The first pole of the third transistor T3 is connected to the second pixel node N2. The second pole of the third transistor T3 is connected to the third pixel node N3.

[0068] In some examples, the fourth transistor T4 may be referred to as an Auto Zero transistor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line S3. The first pole of the fourth transistor T4 is connected to the second pixel power line VSS1. The second pole of the fourth transistor T4 is connected to the third pixel node N3.

[0069] In some examples, the first end of the first capacitor C1 is connected to the first pixel node N1. The second end of the first capacitor C1 is connected to the second pixel node N2. The first end of the second capacitor C2 is connected to the second pixel node N2. The second end of the second capacitor C2 is connected to the first pixel power line ELVDD.

[0070] In some examples, the light-emitting device EL may be an organic light-emitting diode (OLED), including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode). The first pole of the light-emitting device EL is connected to the third pixel node N3. The second pole of the light-emitting device EL is connected to the common voltage line VCOM.

[0071] In some examples, the signal of the first pixel power line ELVDD may be a continuously provided high-level signal. The signals of the second pixel power line VSS1 and the common voltage line VCOM may be continuously provided low-level signals.

[0072] In some examples, the first transistor T1 to the fourth transistor T4 may be P-type transistors (PMOS), or may be N-type transistors (NMOS). For example, as Figure 4BAs shown, the first transistor T1 to the fourth transistor T4 are all P-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield. In some examples, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may all include a bottom gate (which may also be referred to as a back gate); the bottom gates of the first transistor T1, the second transistor T2, and the third transistor T3 may all be connected to the third pixel power supply line AVDD, and the bottom gate of the fourth transistor T4 may be connected to the second pixel power supply line VSS1. The signal of the third pixel power supply line AVDD may be a continuously provided high-level signal. For example, the signal of the third pixel power supply line AVDD is the same as that of the first pixel power supply line ELVDD.

[0073] In some examples, the first transistor T1 to the fourth transistor T4 may include P-type transistors and N-type transistors. For example, the first transistor T1 to the third transistor T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as Figure 4A shown. In some examples, the first transistor T1, the second transistor T2, and the third transistor T3 may all include a bottom gate, and the bottom gates of the three transistors are all connected to the third pixel power supply line AVDD.

[0074] Figure 5A is Figure 4A a driving timing diagram of the pixel circuit shown. Figure 5B is Figure 4B a driving timing diagram of the pixel circuit shown. In Figure 5A , the signal of the third scan signal line S3 is a high-level signal (that is, the effective level of the third scan signal is high level), causing the fourth transistor T4 to conduct; in Figure 5B , the signal of the third scan signal line S3 is a low-level signal (that is, the effective level of the third scan signal is low level), causing the fourth transistor T4 to conduct.

[0075] In some examples, as Figure 5A and Figure 5B shown, the working process of the pixel circuit may include the following stages.

[0076] The first stage A1 is from time t0 to time t1, which can be called the initialization stage. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, causing the first transistor T1, the second transistor T2, and the fourth transistor T4 to conduct. The conduction of the first transistor T1 causes the bias voltage Vofs output by the data signal line DL to be written into the first capacitor C1, and the potential Vg of the first pixel node N1 (i.e., the gate electrode of the third transistor T3) is Vg = Vofs. The conduction of the second transistor T2 causes the first pixel power supply voltage ELVdd output by the first pixel power supply line ELVDD to be written into the second pixel node N2, and the potential Vs of the second pixel node N2 (i.e., the first pole of the third transistor T3) is Vs = ELVdd. At this time, the stored voltage Vini of the first capacitor C1 is Vini = ELVdd - Vofs, and the potential Vd of the third pixel node N3 (i.e., the second pole of the third transistor T3) is Vd = Vg + Vth, preparing for the discharge in the next stage. Among them, ELVdd - Vofs > |Vth|, and Vth is the threshold voltage of the third transistor T3.

[0077] The second stage A2 is from time t1 to time t2, which can be called the self-discharge stage. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 continues to conduct. The signal of the first scan signal line S1 changes from a low-level signal to a high-level signal, causing the first transistor T1 to disconnect first, and the first pixel node N1 floats. Subsequently, the signal of the second scan signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to disconnect. The second pixel node N2 forms a loop through the conducting third transistor T3, the third pixel node N3, and the conducting fourth transistor T4 and starts to discharge, and the potential of the second pixel node N2 drops. Because the first pixel node N1 floats, the voltage difference across the first capacitor C1 remains unchanged, so the potential of the first pixel node N1 drops as the potential of the second pixel node N2 drops. Due to the body effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, so the equivalent threshold voltage |Vth_EF| of the third transistor T3 gradually increases as the potential of the second pixel node N2 drops. The equivalent threshold voltage |Vth_EF| of the third transistor T3 is |Vth_EF| = α(ELVdd - Vs) + |Vth|, where α is the body effect coefficient. When the equivalent threshold voltage |Vth_EF| of the third transistor T3 increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 disconnects, and the second pixel node N2 stops discharging. At this time, |Vth_EF| = α(ELVdd - Vs) + |Vth| = Vini, Vs = AVdd + (|Vth| - Vini) / α, Vg = AVdd + (|Vth| - Vini) / α - Vini. Among them, AVdd is the third pixel power supply voltage output by the third pixel power supply line AVDD.

[0078] The third stage A3 is from time t2 to time t3, which can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 remains off continuously. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 remains on continuously. The signal of the first scan signal line S1 changes from a high-level signal to a low-level signal, turning on the first transistor T1. The conduction of the first transistor T1 causes the data voltage Vdata output by the data signal line DL to be written into the first pixel node N1, and the potential of the first pixel node N1 changes from Vofs to Vdata. Since the second pixel node N2 is floating, △Vs=(1 - b)△Vg, where b = c2 / (c1 + c2), c1 is the capacitance value of the first capacitor C1, and c2 is the capacitance value of the second capacitor C2. At this time, the voltage of the second pixel node N2 becomes: AVdd-(Vini - |Vth|) / a+(1 - b)(Vdata - AVdd+(Vini - |Vth|) / a+Vini)=Vdata+Vini - bVdata + bAVdd-(b(Vini - |Vth|)) / a - bVini. At this time, |Vgs|=(1-(b / a)-b)Vini+(b / a)|Vth|+b(ELVDD - Vdata). This stage can achieve threshold compensation.

[0079] The fourth stage A4 is after time t4, which can be called the light-emitting stage. The signals of the second scan signal line S2 and the third scan signal line S3 are low-level signals, and the signal of the first scan signal line S1 is a high-level signal, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. The conduction of the second transistor T2 causes the first pixel power supply voltage output by the first pixel power supply line ELVDD to provide a driving voltage to the first pole of the light-emitting device EL through the conducting second transistor T2 and the third transistor T3, driving the light-emitting device EL to emit light. The driving current It can be seen that when Ioled is independent of |Vth|, that is, the threshold voltage compensation is completed. Where K is the current coefficient of the third transistor.

[0080] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring the display brightness uniformity of the display product, and improving the display effect of the entire display product.

[0081] In some examples, such as Figure 5A and Figure 5BAs shown, in the first stage A1, the first pulse width (which can also be referred to as the first pulse duration) Δτ1 of the first scan signal provided by the first scan signal line S1 determines the duration during which the bias voltage Vofs is written from the data signal line DL to the first capacitor C1. If the first pulse duration Δτ1 is too short, the potential Vg of the first pixel node N1 will be less than Vofs, thereby affecting the voltage Vini of the first capacitor C1 and ultimately resulting in an increase in the driving current.

[0082] In some examples, such as Figure 5A and Figure 5B As shown, in the second stage A2, there is a first delay duration Δτ2 between the rising edge of the effective level (i.e., the high level) of the second scan signal provided by the second scan signal line S2 and the rising edge of the first pulse of the first scan signal in the first stage A1. If Δτ2 is less than 0, that is, the rising edge of the effective level of the second scan signal is before the rising edge of the first pulse of the first scan signal, causing the second transistor T2 to turn off in advance and start discharging. When the data signal line DL charges the first end of the first capacitor C1, the second end of the first capacitor C1 starts to discharge, and the voltage Vgs across the two ends of the first capacitor C1 ≠ ELVdd - Vofs, and the driving current of the light-emitting device will also change, resulting in a change in the brightness of the light-emitting device. If Δτ2 is equal to or greater than 0, it can ensure the duration of charging the first capacitor C1 from the data signal line DL and can also ensure that Vgs = Vini. When Δτ2 is equal to 0, the self-discharge duration Δτ3 (i.e., the duration between the rising edge of the effective level of the second scan signal and the falling edge of the second pulse of the first scan signal) can be increased as much as possible.

[0083] However, there will be differences between the first scan signal line and the second scan signal line in actual design. The resistance and parasitic capacitance of the first scan signal line and the second scan signal line will be different, resulting in inconsistent RC loading of the first scan signal line and the second scan signal line. When the difference in RC loading between the first scan signal line and the second scan signal line is large, it may cause a delay in the first scan signal, resulting in the problem of self-discharge starting before the bias voltage Vofs is fully written, causing the pixel circuit to not operate in the normal working state and affecting the display effect. Moreover, the inconsistency of the first delay duration Δτ2 between the first scan signal and the second scan signal of different row pixel circuits will affect the display uniformity of the display substrate.

[0084] This embodiment provides a gate driving circuit including: a first operation circuit, a second operation circuit, a first conversion circuit, and a second conversion circuit. The first operation circuit is configured to generate a write switch signal through logical operations. The first conversion circuit is connected to the first operation circuit and is configured to process the write switch signal to generate a write switch driving signal provided to the pixel circuit. The second conversion circuit is connected to the first operation circuit and is configured to process the write switch signal and provide the processed signal to the enable input terminal of the second operation circuit. The second operation circuit is connected to the second conversion circuit and is configured to generate a display switch signal through logical operations triggered by the signal output by the second conversion circuit. Among them, the signal transmission delay duration of the second conversion circuit is greater than that of the first conversion circuit. In the gate driving circuit provided in this embodiment, the signal transmission delay duration of the second conversion circuit is greater than that of the first conversion circuit, which can ensure the phase relationship between the write switch signal and the display switch signal generated by the gate driving circuit, avoid the situation that the pixel circuit starts to discharge before the bias voltage charging is completed, and thus improve the accuracy of the display signal input and output.

[0085] In some examples, the first scan signal can be referred to as a write switch (WS) driving signal and is configured to control the conduction and disconnection of the first transistor T1 in the pixel circuit. The second scan signal can be referred to as a display switch (DS) driving signal and is configured to control the conduction and disconnection of the second transistor T2 in the pixel circuit. The third scan signal can be referred to as an auto zero (AZ) driving signal and is configured to control the conduction and disconnection of the fourth transistor T4 in the pixel circuit.

[0086] In some exemplary embodiments, the write switch signal may include: an alternating first pulse signal and a second pulse signal. The active level of the first pulse signal may be configured to control the writing of a bias voltage to the gate electrode of the driving transistor of the pixel circuit, and the active level of the second pulse signal may be configured to control the writing of a data voltage to the gate electrode of the driving transistor of the pixel circuit. The duration of the active level of the first pulse signal may be less than or equal to the duration of the active level of the second pulse signal. The active level of the display switch signal may be configured to control the driving transistor of the pixel circuit to perform self-discharge. Within one frame period, the end time of the active level of the first pulse signal of the write switch signal may be earlier than or equal to the start time of the active level of the display switch signal, and the end time of the active level of the display switch signal is later than the end time of the active level of the second pulse signal of the write switch signal. In some examples, the first pulse signal of the write switch signal may be a low-level pulse signal, and the active level of the display switch signal may be a high level. The rising edge of the first pulse signal of the write switch signal may be earlier than the rising edge of the active level of the display switch signal. However, the present embodiment does not limit this. In some other examples, the first pulse signal of the write switch signal may be a high-level pulse signal, and the active level of the display switch signal may be a low level.

[0087] In this example, one frame period refers to the process required to complete a complete image, which may include the time interval between the start of one image frame and the start of the next image frame.

[0088] In some exemplary embodiments, the first conversion circuit may include: a first level converter and a first row driving enhancer. The first level converter is configured to perform a voltage domain conversion on the write switch signal; the first row driving enhancer is connected to the first level converter and is configured to enhance the signal processed by the first level converter.

[0089] In some exemplary embodiments, the gate driving circuit may further include: a third conversion circuit, which is connected to the second arithmetic circuit and is configured to process the display switch signal to generate a display switch driving signal provided to the pixel circuit.

[0090] In some examples, the write switch driving signal is obtained by voltage domain conversion and signal enhancement of the write switch signal, and can be provided to the pixel circuit as the first scan signal. The first scan signal can be configured to control the conduction and disconnection of the first transistor T1 in the pixel circuit. The display switch driving signal is obtained by voltage domain conversion and signal enhancement of the display switch signal, and can be provided to the pixel circuit as the second scan signal. The second scan signal can be configured to control the conduction and disconnection of the second transistor T2 in the pixel circuit. The display reset driving signal is obtained by voltage domain conversion and signal enhancement of the display reset signal, and can be provided to the pixel circuit as the third scan signal. The third scan signal can be configured to control the conduction and disconnection of the fourth transistor T4 in the pixel circuit. During the process that the first conversion circuit outputs the write switch driving signal according to the write switch signal, the phase of the write switch signal and the write switch driving signal can be guaranteed to be the same; during the process that the third conversion circuit outputs the display switch driving signal according to the display switch signal, the phase of the display switch driving signal and the display switch signal can be guaranteed to be the same.

[0091] In some exemplary embodiments, the second conversion circuit may include: N inverters connected in series, and the value of N may be an even number greater than 0. For example, the second conversion circuit may include: six inverters connected in series. In some examples, connecting six inverters in series can achieve a signal transmission delay duration of 120 nanoseconds (ns), which can ensure that the signal transmission delay duration is greater than that of the first conversion circuit. However, this embodiment is not limited thereto. In other examples, the second conversion circuit may adopt other circuit designs that play a delaying role. For example, the second conversion circuit may include: a bent trace. By setting the trace to be bent, the trace length can be increased, thereby increasing the signal transmission delay. Another example is that the second conversion circuit may include: a plurality of diodes connected in series, wherein the gates and drains of the diodes may be short-circuited. Another example is that the second conversion circuit may include: a parallel capacitor.

[0092] In some exemplary embodiments, the second arithmetic circuit may include: a latch, a fourth NOR gate, and a second NAND gate. The enable input terminal of the latch is connected to the output terminal of the second conversion circuit. The data input terminal of the latch is configured to receive the second timing signal. The output terminal of the latch is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth NOR gate is configured to receive the duty ratio control signal. The output terminal of the fourth NOR gate is connected to the first input terminal of the second NAND gate. The second input terminal of the second NAND gate is configured to receive the second reset signal. The output terminal of the second NAND gate serves as the output terminal of the second arithmetic circuit. The second arithmetic circuit provided in this example can generate a display switch signal triggered by the signal output by the second conversion circuit, and can ensure the phase relationship between the write switch signal and the display switch signal.

[0093] In some exemplary embodiments, the write switch driving signal includes alternating first pulse signals and second pulse signals; the write switch signal includes alternating first pulse signals and second pulse signals; the output signal of the second conversion circuit includes alternating first pulse signals and second pulse signals. There is a first delay duration between the end moment of the effective level of the first pulse signal of the write switch driving signal and the start moment of the effective level of the display switch driving signal. There is a second delay duration between the start moment of the effective level of the first pulse signal of the write switch signal and the start moment of the effective level of the first pulse signal of the output signal of the second conversion circuit. The ratio of the second delay duration to the first delay duration can be greater than 0.9 and less than 1.1. For example, the second delay duration can be equal to the first delay duration. In this example, the second conversion circuit is used to delay the write switch signal, which can ensure that the effective level of the display switch signal output by the second arithmetic circuit is later than the effective level of the first pulse signal of the write switch signal.

[0094] In some exemplary embodiments, the gate driving circuit may further include: a first test circuit and a second test circuit. The first test circuit is connected to the output terminal of the first arithmetic circuit, and the second test circuit is connected to the output terminal of the second arithmetic circuit. The first test circuit may include two inverters connected in series. The second test circuit may include two inverters connected in series. In this example, by providing the first test circuit, it can be detected whether the first arithmetic circuit is working properly, and by providing the second test circuit, it can be detected whether the second arithmetic circuit is working properly.

[0095] The solutions of this embodiment will be illustrated by some examples below.

[0096] In some examples, the gate driving device may be disposed in the non-display area, may be located on one side of the pixel row direction of the display area, or may be respectively located on both sides of the pixel row direction of the display area. The gate driving device may include a plurality of cascaded gate driving circuits, and at least one gate driving circuit may be connected to the scan signal lines in a pixel row in the display area to provide scan signals to the connected scan signal lines. When the gate driving device is disposed on both sides of the pixel row direction of the display area, the scan signal lines in the pixel row may be driven by two gate driving circuits to form a bilateral driving structure, which can ensure the driving ability of high pixel density and avoid distortion of the driving signal.

[0097] Figure 6 It is a schematic structural diagram of the gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 6As shown in the figure, the gate driving circuit may include: a first operation circuit 211, a second operation circuit 212, a first conversion circuit 221, a second conversion circuit 222, and a third conversion circuit 223. The output terminal of the first operation circuit 211 may be connected to the first conversion circuit 221 and the second conversion circuit 222. The first operation circuit 211 may be configured to generate a write switch signal through a logic operation. The first conversion circuit 221 may be configured to process the write switch signal to generate a write switch driving signal WS provided to the pixel circuit. The second conversion circuit 222 may be configured to process the write switch signal and provide the processed signal to the enable input terminal of the second operation circuit 212. The second operation circuit 212 may be configured to generate a display switch signal through a logic operation triggered by the signal output by the second conversion circuit 222. The third conversion circuit 223 is connected to the second operation circuit 212 and may be configured to process the display switch signal to generate a display switch driving signal DS provided to the pixel circuit.

[0098] Figure 7 This is an example structural diagram of the gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 7 shown, the gate driving circuit of this example may include: a shift register circuit 100, a first operation circuit 211, a second operation circuit 212, a third operation circuit 213, a first conversion circuit 221, a second conversion circuit 222, a third conversion circuit 223, and a fourth conversion circuit 224.

[0099] In some examples, the shift register circuit 100 may be a shift register circuit composed of D Flip Flops. The shift register circuit 100 is connected to the display driving circuit and receives an initial setting signal generated by the display driving circuit. The initial setting signal may include a start signal STV (which may also be referred to as an initial input signal) and a clock signal CKV. The flip flop is configured to perform shift register on the received initial input signal to preliminarily generate a timing signal that can be shifted row by row. For example, the initial input signal may include: a first initial input signal, a second initial input signal, a third initial input signal, and a fourth initial input signal. The timing signal may include: a first timing signal generated according to the first initial input signal, a second timing signal generated according to the second initial input signal, a third timing signal generated according to the third initial input signal, and a duty ratio control signal generated according to the fourth initial input signal.

[0100] In some examples, the first operation circuit 211 and the first conversion circuit 221 can form a write switch drive signal generation circuit. The first operation circuit 211 is connected to the shift register circuit 100 and is configured to perform a logic operation on the received timing signals (such as including the first timing signal, the second timing signal, the third timing signal, and the duty ratio control signal) to generate a write switch signal; the first conversion circuit 221 can be configured to perform a voltage domain conversion and signal enhancement on the write switch signal to generate a write switch drive signal WS and output it to at least one row of pixel circuits.

[0101] In some examples, the second conversion circuit 222, the second operation circuit 212, and the third conversion circuit 223 can form a display switch drive signal generation circuit. The second conversion circuit 222 is connected to the first operation circuit 211, and the second operation circuit 212 is connected to the shift register circuit 100. The second operation circuit 212 can be configured to perform a logic operation on the received timing signals (such as including the second timing signal and the duty ratio control signal) to generate a display switch signal under the trigger of the signal output by the second conversion circuit 222; the third conversion circuit 223 can be configured to perform a voltage domain conversion and signal enhancement on the display switch signal to generate a display switch drive signal DS and output it to at least one row of pixel circuits.

[0102] In some examples, the third operation circuit 213 and the fourth conversion circuit 224 can form a display reset drive signal generation circuit. The third operation circuit 213 can be connected to the shift register circuit 100 and is configured to perform a logic operation on the received timing signals (such as including the second timing signal, the third timing signal, and the duty ratio control signal) to generate a display reset signal; the third conversion circuit 223 can be configured to perform a voltage domain conversion and signal enhancement on the display reset signal to generate a display reset drive signal AZ and output it to at least one row of pixel circuits.

[0103] In some examples, the first conversion circuit 221 can include: a first level converter 2211 and a first row drive enhancer 2212. The output end of the first operation circuit 211 is connected to the input end of the first level converter 2211, and the output end of the first level converter 2211 is connected to the output end of the first row drive enhancer 2212. The first operation circuit 211 is configured to generate a write switch signal through a logic operation, the first level converter 2211 is configured to perform a voltage domain conversion on the write switch signal, and the first row drive enhancer 2212 is configured to perform signal enhancement on the signal output by the first level converter 2211.

[0104] In some examples, the third conversion circuit may include a second level shifter and a second line driving enhancer. The output terminal of the second arithmetic circuit 212 is connected to the input terminal of the second level shifter, and the output terminal of the second level shifter is connected to the output terminal of the second line driving enhancer. The second arithmetic circuit 212 is configured to generate a display switching signal through a logic operation. The second level shifter is configured to perform a voltage domain conversion on the display switching signal. The second line driving enhancer is configured to enhance the signal output by the second level shifter.

[0105] In some examples, the fourth conversion circuit 224 may include a third level shifter and a third line driving enhancer. The output terminal of the third arithmetic circuit 213 is connected to the input terminal of the third level shifter, and the output terminal of the third level shifter is connected to the output terminal of the third line driving enhancer. The third arithmetic circuit 213 is configured to generate a display reset signal through a logic operation. The third level shifter is configured to perform a voltage domain conversion on the display reset signal. The third line driving enhancer is configured to enhance the signal output by the third level shifter.

[0106] In some examples, since signals such as the start signal and the clock signal are output by the display driving circuit and their voltage domains are inconsistent with the pixel circuit voltage domain, by converting through the level shifter and introducing the required voltage (0V to -2V & -5V), it is possible to ensure that the voltage of the output gate driving signal matches the pixel circuit.

[0107] In some examples, the first arithmetic circuit 211, the second arithmetic circuit 212, and the third arithmetic circuit 213 may form a logic operation circuit. In some examples, the start signal STV may be referred to as a frame start signal and has a period of one frame. The clock signal CKV may be referred to as a line driving clock signal and has a period of one line.

[0108] In some examples, the output terminal of the first arithmetic circuit 211 is connected to the input terminal of the second conversion circuit 222. The output terminal of the second conversion circuit 222 may be connected to the enable input terminal of the second arithmetic circuit 212. The second arithmetic circuit 212 may be configured to generate a display switching signal through a logic operation under the trigger of the signal output by the second conversion circuit 222, such that the end time of the effective level of the first pulse signal of the write switching signal is earlier than or equal to the start time of the effective level of the display switching signal. The signal transmission delay duration of the second conversion circuit 222 is greater than the signal transmission delay duration of the first conversion circuit 221. In this way, it is possible to ensure the phase relationship between the write switch driving signal WS obtained from the write switch signal and the display switch driving signal DS obtained from the display switching signal, and avoid the situation where the pixel circuit starts to discharge before the bias voltage charging is completed, thereby improving the accuracy of the display signal input and output.

[0109] Figure 8 This is the working schematic diagram of the first arithmetic circuit and the first conversion circuit of at least one embodiment of the present disclosure. In some examples, as Figure 8 shown, the first arithmetic circuit 211 may include: 9 parts, and the 9 parts are respectively 4 inverters (abbreviated as INV X), 3 NOR gates (abbreviated as NOR), 1 NAND gate (abbreviated as NAND), and 1 two-way selector (MUX2). As Figure 8 shown, the first arithmetic circuit 211 may include: a first NAND gate 511, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, and a two-way selector 530.

[0110] In some examples, the first input terminal of the first NAND gate 511 is configured to receive a second timing signal B_Qn, for example, receive the second timing signal through the second input terminal of the logic arithmetic circuit; the second input terminal is configured to receive a third timing signal C_Qn, for example, receive the third timing signal through the third input terminal of the logic arithmetic circuit; the output terminal of the first NAND gate 511 is connected to the input terminal of the first inverter 401, the output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501, the second input terminal of the first NOR gate 501 is configured to receive a first timing signal A_Qn, for example, receive the first timing signal through the first input terminal of the logic arithmetic circuit, the output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, the output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502, the second input terminal of the second NOR gate 502 is configured to receive a fourth timing signal CKV4, for example, receive the fourth timing signal through the clock signal terminal of the logic arithmetic circuit, the output terminal of the second NOR gate 502 is connected to the input terminal of the third inverter 403, and the output terminal of the third inverter 403 is connected to the second input terminal of the two-way selector 530. The input terminal of the fourth inverter 404 is configured to receive a second reset signal LF_PUSLE2, for example, receive the second reset signal through the second reset terminal of the logic arithmetic circuit, the output terminal of the fourth inverter 404 is connected to the second input terminal of the third NOR gate 503, the first input terminal of the third NOR gate 503 is configured to receive a first reset signal LF_PUSLE1, for example, receive the first reset signal through the first reset terminal of the logic arithmetic circuit, and the output terminal of the third NOR gate 503 is connected to the control terminal of the two-way selector 530. The first input terminal of the two-way selector 530 is configured to receive a first timing signal A_Qn, for example, receive the first timing signal through the first input terminal of the logic arithmetic circuit, and the output terminal of the two-way selector 530 serves as the output terminal OUT_WS of the first arithmetic circuit 211.

[0111] In some examples, the working principle of the first arithmetic circuit 211 is as follows: the first NAND gate 511 and the first inverter 401 perform an AND operation on the second timing signal B_Qn and the third timing signal C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the AND operation result and the first timing signal A_Qn. The second NOR gate 502 and the third inverter 403 perform an OR operation on the OR operation result and the fourth timing signal CKV4. The fourth inverter 404 performs an inversion process on the second reset signal LF_PUSLE2. The third NOR gate 503 performs a NOR operation on the inversion process result and the first reset signal LF_PUSLE1. The output signal of the third NOR gate 503 serves as the control signal of the two-way selector 530. When the third NOR gate 503 outputs a high level, the output terminal of the two-way selector 530 outputs the first timing signal A_Qn. When the third NOR gate 503 outputs a low level, the output terminal of the two-way selector 530 outputs the output signal of the third inverter 403. The write switch signal output by the first arithmetic circuit 211 can be provided to the second conversion circuit.

[0112] In some examples, such as Figure 8 shown, the first conversion circuit may include: a first level converter 2211 and a first row driving enhancer 2212. The input terminal of the first level converter 2211 is connected to the output terminal OUT_WS of the first arithmetic circuit 211. The first output terminal of the first level converter 2211 is connected to the first input terminal of the first row driving enhancer 2212. The second output terminal of the first level converter 2211 is connected to the second input terminal of the first row driving enhancer 2212. The output terminal of the first row driving enhancer 2212 can serve as the output terminal OUT1 of the write switch driving signal generation circuit. The first level converter 2211 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the ground line GND. The first row driving enhancer 2212 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the first enable line DR1_EN.

[0113] In some examples, such as Figure 8 shown, the gate driving circuit may further include: a first test circuit 241. The first test circuit 241 may include a fifth inverter 405 and a sixth inverter 406. The input terminal of the fifth inverter 405 may be connected to the output terminal OUT_WS of the first arithmetic circuit 211. The output terminal of the fifth inverter 405 is connected to the input terminal of the sixth inverter 406. The output terminal of the sixth inverter 406 serves as the output terminal TEST_WS of the first test circuit 241. The output signal of the output terminal TEST_WS of the first test circuit 241 can be led out from the display substrate through a trace, which is convenient for detecting whether the first arithmetic circuit 211 is working properly.

[0114] Figure 9The working schematic diagram of the second conversion circuit, the second operation circuit, and the third conversion circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 9 shown, the second conversion circuit 222 may include six inverters connected in series, that is, including: the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, the tenth inverter 410, the eleventh inverter 411, and the twelfth inverter 412. The second operation circuit 212 may include: a latch 520, a fourth NOR gate 504, and a second NAND gate 512. The input end of the second conversion circuit 222 may be connected to the output end OUT_WS of the first operation circuit 211, and the output end of the second conversion circuit 222 may be connected to the enable input end EN of the latch 520 of the second operation circuit 212.

[0115] In some examples, the input end of the seventh inverter 407 is connected to the output end OUT_WS of the first operation circuit, and the output end of the seventh inverter 407 is connected to the input end of the eighth inverter 408. The output end of the eighth inverter 408 is connected to the input end of the ninth inverter 409. The output end of the ninth inverter 409 is connected to the input end of the tenth inverter 410. The output end of the tenth inverter 410 is connected to the input end of the eleventh inverter 411. The output end of the eleventh inverter 411 is connected to the input end of the twelfth inverter 412.

[0116] In some examples, the output end of the twelfth inverter 412 serves as the output end of the second conversion circuit 222 and is connected to the enable input end EN of the latch 520. The data input end D of the latch 520 is configured to receive the second timing signal B_Qn, for example, by receiving the second timing signal through the second input end of the logic operation circuit; the output end Q of the latch 520 is connected to the second input end of the fourth NOR gate 504. The first input end of the fourth NOR gate 504 is configured to receive the duty ratio control signal D_Qn’, for example, by receiving the duty ratio control signal through the duty ratio control end of the logic operation circuit. The output end of the fourth NOR gate 504 is connected to the first input end of the second NAND gate 512. The second input end of the second NAND gate 512 is configured to receive the second reset signal LF_PUSLE2, for example, by receiving the second reset signal through the second reset end of the logic operation circuit. The output end of the second NAND gate 512 serves as the output end OUT_DS of the second operation circuit 212.

[0117] In some examples, the output terminal OUT_DS of the second operation circuit 212 is connected to the input terminal of the second level converter 2231, and a display switch signal is output to the second level converter 2231. The first output terminal of the second level converter 2231 is connected to the first input terminal of the second row driving booster 2232, and the second output terminal of the second level converter 2231 is connected to the second input terminal of the second row driving booster 2232. The output terminal of the second row driving booster 2232 serves as the output terminal OUT2 of the display switch driving signal generation circuit, and outputs a display switch driving signal, for example. The second level converter 2231 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the ground line GND. The second row driving booster 2232 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the second enable line DR2_EN.

[0118] In some examples, the gate driving circuit may further include: a second test circuit 242. The second test circuit 242 may be connected to the output terminal OUT_DS of the second operation circuit 212. The second test circuit 242 may include two inverters connected in series, for example, including a thirteenth inverter 413 and a fourteenth inverter 414. The input terminal of the thirteenth inverter 413 may serve as the input terminal of the second test circuit 242 and be connected to the output terminal OUT_DS of the second operation circuit 212. The output terminal of the thirteenth inverter 413 is connected to the input terminal of the fourteenth inverter 414. The output terminal of the fourteenth inverter 414 may serve as the output terminal TEST_DS of the second test circuit 242. The output signal of the output terminal TEST_DS of the second test circuit 242 may be led out from the display substrate through a trace, which is convenient for detecting whether the second operation circuit 212 is working properly.

[0119] In some examples, by arranging an even number of inverters connected in series, the second conversion circuit 222 can delay the signal (i.e., the write switch signal) of the output terminal OUT_WS of the first operation circuit and ensure that the waveform of the output signal remains unchanged, and the signal transmission delay duration of the second conversion circuit 222 is greater than that of the first conversion circuit. In this way, it can be ensured that the end moment of the first pulse signal of the write switch driving signal output by the first conversion circuit is earlier than or equal to the start moment of the effective level of the display switch driving signal output by the third conversion circuit, thereby avoiding the situation that the pixel circuit starts self-discharging before the bias voltage is completed due to the delay of the write switch driving signal, and thus improving the accuracy of the input and output of the display signal.

[0120] In some examples, the operating principle of the second arithmetic circuit 212 is as follows: The output signal of the second conversion circuit 222 is input to the enable input terminal EN of the latch 520 as the enable signal of the latch 520, and the second timing signal B_Qn is used as the input signal of the latch 520. When the enable signal at the enable input terminal EN is at a low level, the output of the latch 520 remains unchanged; when the enable signal at the enable input terminal EN is at a high level, the output of the latch 520 changes with the second timing signal.

[0121] Figure 10 This is the timing diagram of the latch of the second conversion circuit and the second arithmetic circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 10 shown, the write switch signal output from the output terminal OUT_WS of the first arithmetic circuit may include alternating first pulse signals and second pulse signals; the enable signal includes alternating first pulse signals and second pulse signals. Among them, there is a second delay duration Δτ4 between the starting moment of the effective level of the first pulse signal of the write switch signal and the starting moment of the effective level of the first pulse signal of the enable signal input to the enable input terminal EN. The second delay duration Δτ4 may be the same as the first delay duration Δτ2. In this example, the second delay duration Δτ4 may be the duration between the falling edge of the first pulse signal of the write switch signal and the falling edge of the first pulse signal of the enable signal.

[0122] Subsequently, the fourth NOR gate 504 performs a NOR operation on the duty ratio control signal D_Qn’ and the output signal of the latch 520, and the second NAND gate 512 performs a NAND operation on the NOR operation result and the second reset signal LF_PULSE2. Its logical expression can be: wherein, “+” represents a logical OR operation, “&” represents a logical AND operation, and the overline represents a logical NOT operation. The above logical expression can be simplified to OUT_DS = D_Qn’ + Q + LF_PULSE2’. Among them, LF_PULSE2’ may be the inverted signal of the second reset signal LF2, and Q is the output signal of the latch 520. In the normal operating state, OUT_DS = D_Qn’ + Q; when global reset is required, OUT_DS = 0 for global reset. When the duty ratio of the light emitting time is 100%, the duty ratio control signal D_Qn’ remains at a low level, then OUT_DS = Q = B_Qn, as Figure 11 shown. When it is necessary to adjust the duty ratio of the light emitting time, it can be achieved by adjusting the duty ratio of the duty ratio control signal D_Qn’. Therefore, the display switch signal can be determined by the second timing signal B_Qn. The rising edge of the display switch signal provided by the output terminal OUT_DS will move synchronously with the rising edge of the first pulse signal of the write switch signal provided by the output terminal OUT_WS of the first arithmetic circuit, so as to ensure the relative relationship between the display switch signal and the write switch signal.

[0123] In some examples, the delay of the inverter in the second conversion circuit for the write switch signal can be divided into a rising-edge delay and a falling-edge delay. Among them, the rising-edge delay duration can be referred to as tr, and the falling-edge delay duration can be referred to as tf. Since the write switch signal includes two alternating pulse signals, the inverter in the second conversion circuit will have a delay for the rising edges of both pulse signals of the write switch signal, and the delay duration can be tr for both. The purpose of the rising-edge delay of the second conversion circuit for the first pulse signal of the write switch signal is as follows: The output signal of the second conversion circuit serves as the enable signal of the latch. When the output signal of the second conversion circuit is at a high level, the display switch signal can normally output a high level. Even if there is a delay difference (assumed to be Δt1) caused by wire routing or logic gates, and the high level of the display switch signal of a certain row is advanced relative to the write switch signal of this row, the function triggered by the high level of the latch can ensure that the high level of the output display switch signal lags behind the rising-edge delay duration tr of the high level of the output write switch signal. Among them, Δt1 < tr < Δt2, Δt1 is the delay duration caused by wire routing or the difference in the number of gate circuits passed through, generally in the order of 10 ns to 100 ns; Δt2 is the designed delay time, generally in the order of 400 ns to 800 ns. For example, the range of the rising-edge delay duration tr can be 100 ns < tr < 400 ns. In some examples, the layout design width of the display switch drive signal generation circuit is the same as the layout design width of one row of pixels, that is, the length or width of the inverter is limited by the pixel width. Therefore, under this limitation, the delay duration of a single inverter is generally about 20 ns. In this example, by connecting six inverters in series, a total delay duration of about 120 ns can be achieved, which can meet the requirements of the delay difference caused by wire routing or the number of logic gates and the requirements of the designed delay duration.

[0124] Figure 12 This is the working principle diagram of the latch of the second arithmetic circuit of at least one embodiment of the present disclosure. In some examples, such as Figure 12As shown, the latch may include: the fifteenth inverter 415, the third NAND gate 513, the fourth NAND gate 514, the fifth NAND gate 515, and the sixth NAND gate 516. The input terminal of the fifteenth inverter 415 is connected to the first input terminal of the third NAND gate 513, serving as the input terminal D of the latch. The output terminal of the fifteenth inverter 415 is connected to the first input terminal of the fourth NAND gate 514. The second input terminal of the third NAND gate 513 is connected to the second input terminal of the fourth NAND gate 514 and serves as the enable input terminal EN of the latch. The output terminal of the third NAND gate 513 is connected to the first input terminal of the fifth NAND gate 515, and the connection point between the two is the first node B1. The output terminal of the fourth NAND gate 514 is connected to the second input terminal of the sixth NAND gate 516, and the connection point between the two is the second node B2. The output terminal of the fifth NAND gate 515 is connected to the first input terminal of the sixth NAND gate 516 and serves as the output terminal Q of the latch. The second input terminal of the fifth NAND gate 515 is connected to the output terminal of the sixth NAND gate 516 and serves as the inverted output terminal Q_ of the latch.

[0125] Figure 13 is Figure 12 The working timing diagram of the latch shown. In some examples, when a low level is input at the enable input terminal EN, the output of the latch remains unchanged; when a high level is input at the enable input terminal EN, the output of the latch changes with the signal of the data input terminal D. Taking the low level as 0 and the high level as 1 as an example, the working process of the latch is described below.

[0126] In some examples, in the first stage A11, when the enable input terminal EN is 1 and the data input terminal D is 0, the first node B1 is 1 and the second node B2 is 0; for the sixth NAND gate 516, when the second node B2 is 0, the second input terminal of the sixth NAND gate 516 is 0. Regardless of whether the first input terminal of the sixth NAND gate 516 inputs 0 or 1, the output of the inverted output terminal Q_ is 1; for the fifth NAND gate 515, both input terminals are 1, so the output terminal Q is 0. The first stage A11 can also be referred to as the D-latch reset operation stage.

[0127] In the second stage A12, when the enable input terminal EN is 0, regardless of whether the data input terminal D inputs 0 or 1, the first node B1 and the second node B2 are both 1. At this time, the fifth NAND gate 515 and the sixth NAND gate 516 are equivalent to inverters and maintain the output. The second stage A12 can also be referred to as the hold stage or the latch 1-bit binary number stage.

[0128] In the third stage A13, the enable input terminal EN is 1, the data input terminal D is 1, the first node B1 is 0, and the second node B2 is 1; when the first node B1 is 0, the first input terminal of the fifth NAND gate 515 is 0, and regardless of whether the second input terminal is 0 or 1, the output terminal Q outputs 1; for the sixth NAND gate 516, both input terminals are 1, and the output of the inverted output terminal Q_ is 0. The third stage can also be called the D latch set to 1 stage.

[0129] The purpose of the fifteenth inverter 415 included in the latch of this example is to meet the constraint conditions of the latch and avoid SR = 1. The latch of this example can avoid the high level of the display switch signal being earlier than the first pulse of the write switch signal and avoid the high level of the display switch signal covering the first low-level pulse of the write switch signal.

[0130] Figure 14 It is an equivalent circuit diagram of the second conversion circuit and the second arithmetic circuit of at least one embodiment of the present disclosure. In some examples, as Figure 14 shown, the second NAND gate 512 may include two P-type transistors and two N-type transistors, each inverter may include 1 P-type transistor and 1 N-type transistor, and the fourth NOR gate 504 may include two P-type transistors and 2 N-type transistors. The latch 520 may include the fifteenth inverter 415 and four NAND gates, and a total of 9 P-type transistors and 9 N-type transistors.

[0131] In some examples, the seventh inverter 407 may include a first P-type transistor P1 and a first N-type transistor N1. The gate electrodes of the first P-type transistor P1 and the first N-type transistor N1 are both connected to the output terminal OUT_WS of the first arithmetic circuit; the first pole of the first P-type transistor P1 is connected to the first power supply line VDD; the second pole of the first P-type transistor P1 is connected to the second pole of the first N-type transistor N1 and serves as the output terminal of the seventh inverter 407; the first pole of the first N-type transistor N1 is connected to the ground wire GND.

[0132] In some examples, the eighth inverter 408 may include a second P-type transistor P2 and a second N-type transistor N2. The gate electrodes of the second P-type transistor P2 and the second N-type transistor N2 are both connected to the output terminal of the seventh inverter 407; the first pole of the second P-type transistor P2 is connected to the first power supply line VDD; the second pole of the second P-type transistor P2 is connected to the second pole of the second N-type transistor N2 and serves as the output terminal of the eighth inverter 408; the first pole of the second N-type transistor N2 is connected to the ground wire GND.

[0133] In some examples, the ninth inverter 409 may include a third P-type transistor P3 and a third N-type transistor N3. The gate electrodes of the third P-type transistor P3 and the third N-type transistor N3 are both connected to the output terminal of the eighth inverter 408; the first pole of the third P-type transistor P3 is connected to the first power supply line VDD; the second pole of the third P-type transistor P3 is connected to the second pole of the third N-type transistor N3, serving as the output terminal of the ninth inverter 409; the first pole of the third N-type transistor N3 is connected to the ground wire GND.

[0134] In some examples, the tenth inverter 410 may include a fourth P-type transistor P4 and a fourth N-type transistor N4. The gate electrodes of the fourth P-type transistor P4 and the fourth N-type transistor N4 are both connected to the output terminal of the ninth inverter 409; the first pole of the fourth P-type transistor P4 is connected to the first power supply line VDD; the second pole of the fourth P-type transistor P4 is connected to the second pole of the fourth N-type transistor N4, serving as the output terminal of the tenth inverter 410; the first pole of the fourth N-type transistor N4 is connected to the ground wire GND.

[0135] In some examples, the eleventh inverter 411 may include a fifth P-type transistor P5 and a fifth N-type transistor N5. The gate electrodes of the fifth P-type transistor P5 and the fifth N-type transistor N5 are both connected to the output terminal of the tenth inverter 410; the first pole of the fifth P-type transistor P5 is connected to the first power supply line VDD; the second pole of the fifth P-type transistor P5 is connected to the second pole of the fifth N-type transistor N5, serving as the output terminal of the eleventh inverter 411; the first pole of the fifth N-type transistor N5 is connected to the ground wire GND.

[0136] In some examples, the twelfth inverter 412 may include a sixth P-type transistor P6 and a sixth N-type transistor N6. The gate electrodes of the sixth P-type transistor P6 and the sixth N-type transistor N6 are both connected to the output terminal of the eleventh inverter 411; the first pole of the sixth P-type transistor P6 is connected to the first power supply line VDD; the second pole of the sixth P-type transistor P6 is connected to the second pole of the sixth N-type transistor N6, serving as the output terminal of the twelfth inverter 412; the first pole of the sixth N-type transistor N6 is connected to the ground wire GND.

[0137] In some examples, the fifteenth inverter 415 may include a seventh P-type transistor P7 and a seventh N-type transistor N7. The gate electrodes of the seventh P-type transistor P7 and the seventh N-type transistor N7 are connected and configured to receive the second timing signal B_Qn; the first pole of the seventh P-type transistor P7 is connected to the first power supply line VDD; the second pole of the seventh P-type transistor P7 is connected to the second pole of the seventh N-type transistor N7, serving as the output terminal of the fifteenth inverter 415; the first pole of the seventh N-type transistor N7 is connected to the ground wire GND.

[0138] In some examples, the fourth NAND gate 514 may include an eighth P-type transistor P8, a ninth P-type transistor P9, an eighth N-type transistor N8, and a ninth N-type transistor N9. The gate electrode of the eighth P-type transistor P8 is connected to the gate electrode of the eighth N-type transistor N8, serving as the second input terminal of the fourth NAND gate 514, and is connected to the output terminal of the fifteenth inverter 415; the gate electrode of the ninth P-type transistor P9 is connected to the gate electrode of the ninth N-type transistor N9, serving as the first input terminal of the fourth NAND gate 514, and is connected to the output terminal of the twelfth inverter 412. The first poles of the eighth P-type transistor P8 and the ninth P-type transistor P9 are both connected to the first power supply line VDD. The second poles of the eighth P-type transistor P8, the ninth P-type transistor P9, and the second pole of the eighth N-type transistor N8 are connected, serving as the output terminal of the fourth NAND gate 514. The first pole of the ninth N-type transistor N9 is connected to the ground line GND, and the second pole of the ninth N-type transistor N9 is connected to the first pole of the eighth N-type transistor N8.

[0139] In some examples, the third NAND gate 513 may include a tenth P-type transistor P10, an eleventh P-type transistor P11, a tenth N-type transistor N10, and an eleventh N-type transistor N11. The gate electrode of the tenth P-type transistor P10 is connected to the gate electrode of the tenth N-type transistor N10, serving as the second input terminal of the third NAND gate 513, configured to receive the second timing signal B_Qn; the gate electrode of the eleventh P-type transistor P11 is connected to the gate electrode of the eleventh N-type transistor N11, serving as the first input terminal of the third NAND gate 513, and is connected to the output terminal of the twelfth inverter 412. The first poles of the tenth P-type transistor P10 and the eleventh P-type transistor P11 are both connected to the first power supply line VDD. The second poles of the tenth P-type transistor P10, the eleventh P-type transistor P11, and the second pole of the tenth N-type transistor N11 are connected, serving as the output terminal of the third NAND gate 513. The first pole of the eleventh N-type transistor N11 is connected to the ground line GND, and the second pole of the eleventh N-type transistor N11 is connected to the first pole of the tenth N-type transistor N10.

[0140] In some examples, the fifth NAND gate 515 may include a twelfth P-type transistor P12, a thirteenth P-type transistor P13, a twelfth N-type transistor N12, and a thirteenth N-type transistor N13. The gate electrode of the twelfth P-type transistor P12 is connected to the gate electrode of the twelfth N-type transistor N12, serving as the second input terminal of the fifth NAND gate 515, and is connected to the output terminal of the sixth NAND gate 516; the gate electrode of the thirteenth P-type transistor P13 is connected to the gate electrode of the thirteenth N-type transistor N13, serving as the first input terminal of the fifth NAND gate 515, and is connected to the output terminal of the third NAND gate 513. The first poles of the twelfth P-type transistor P12 and the thirteenth P-type transistor P13 are both connected to the first power supply line VDD, and the second pole of the twelfth P-type transistor P12, the second pole of the thirteenth P-type transistor P13, and the second pole of the twelfth N-type transistor N12 are connected, serving as the output terminal of the fifth NAND gate 515. The first pole of the thirteenth N-type transistor N13 is connected to the ground wire GND, and the second pole of the thirteenth N-type transistor N13 is connected to the first pole of the twelfth N-type transistor N12.

[0141] In some examples, the sixth NAND gate 516 may include a fourteenth P-type transistor P14, a fifteenth P-type transistor P15, a fourteenth N-type transistor N14, and a fifteenth N-type transistor N15. The gate electrode of the fourteenth P-type transistor P14 is connected to the gate electrode of the fourteenth N-type transistor N14, serving as the second input terminal of the sixth NAND gate 516, and is connected to the output terminal of the fifth NAND gate 515; the gate electrode of the fifteenth P-type transistor P15 is connected to the gate electrode of the fifteenth N-type transistor N15, serving as the first input terminal of the sixth NAND gate 516, and is connected to the output terminal of the fourth NAND gate 514. The first poles of the fourteenth P-type transistor P14 and the fifteenth P-type transistor P15 are both connected to the first power supply line VDD, and the second pole of the fourteenth P-type transistor P14, the second pole of the fifteenth P-type transistor P15, and the second pole of the fourteenth N-type transistor N14 are connected, serving as the output terminal of the sixth NAND gate 516. The first pole of the fifteenth N-type transistor N15 is connected to the ground wire GND, and the second pole of the fifteenth N-type transistor N15 is connected to the first pole of the fourteenth N-type transistor N14.

[0142] In some examples, the fourth NOR gate 504 may include a sixteenth P-type transistor P16, a seventeenth P-type transistor P17, a sixteenth N-type transistor N16, and a seventeenth N-type transistor N17. The gate electrode of the sixteenth P-type transistor P16 is connected to the gate electrode of the sixteenth N-type transistor N16 and serves as the second input terminal of the fourth NOR gate 504; the gate electrode of the seventeenth P-type transistor P17 is connected to the gate electrode of the seventeenth N-type transistor N17 and serves as the first input terminal of the fourth NOR gate 504, configured to receive a duty ratio control signal D_Qn'. The first pole of the sixteenth P-type transistor P16 is connected to the first power supply line VDD, and the second pole of the sixteenth P-type transistor P16 is connected to the first pole of the seventeenth P-type transistor P17; the second pole of the seventeenth P-type transistor P17 is connected to the second poles of the sixteenth N-type transistor N16 and the seventeenth N-type transistor N17 and serves as the output terminal of the fourth NOR gate 504; the first poles of the sixteenth N-type transistor N16 and the seventeenth N-type transistor N17 are both connected to the ground line GND.

[0143] In some examples, the second NAND gate 512 may include an eighteenth P-type transistor P18, a nineteenth P-type transistor P19, an eighteenth N-type transistor N18, and a nineteenth N-type transistor N19. The gate electrode of the eighteenth P-type transistor P18 is connected to the gate electrode of the eighteenth N-type transistor N18 and serves as the first input terminal of the second NAND gate 512; the gate electrodes of the nineteenth P-type transistor P19 and the nineteenth N-type transistor N19 are connected and serve as the second input terminal of the second NAND gate 512, configured to receive a second reset signal LF_PUSLE2; the first poles of the eighteenth P-type transistor P18 and the nineteenth P-type transistor P19 are connected to the first power supply line VDD; the second pole of the eighteenth P-type transistor P18, the second pole of the nineteenth P-type transistor P19, and the second pole of the eighteenth N-type transistor N18 are connected and serve as the output terminal of the second NAND gate 512; the first pole of the nineteenth N-type transistor N19 is connected to the ground line GND, and the second pole of the nineteenth N-type transistor N19 is connected to the first pole of the eighteenth N-type transistor N18.

[0144] This embodiment also provides a driving method for a gate driving circuit, which is applied to the gate driving circuit as described above. The driving method includes: a first operation circuit generates a writing switch signal through logical operation, a first conversion circuit processes the writing switch signal to generate a writing switch driving signal provided to the pixel circuit; a second conversion circuit processes the writing switch signal and provides the processed signal to the enable input terminal of a second operation circuit, and the second operation circuit generates a display switch signal through logical operation under the trigger of the signal output by the second conversion circuit. Wherein, the signal transmission delay duration of the second conversion circuit is greater than that of the first conversion circuit. The driving method of the gate driving circuit in this example can refer to the description of the foregoing embodiments, so it will not be elaborated here.

[0145] This embodiment also provides a display substrate, which includes a display area and a non-display area; the display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the gate driving circuit as described in the foregoing embodiment.

[0146] This exemplary embodiment of the present disclosure also provides a display device, which includes the foregoing display substrate. The display device of the present disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights and rangefinders, etc.

[0147] Although the disclosed embodiments of the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content shown and described herein. Various modifications, substitutions or omissions can be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A gate driving circuit, characterized in that, Comprising: A first arithmetic circuit, a second arithmetic circuit, a first conversion circuit, and a second conversion circuit; The first arithmetic circuit is configured to generate a write switch signal through a logic operation; The first conversion circuit is connected to the first arithmetic circuit and is configured to process the write switch signal to generate a write switch drive signal provided to the pixel circuit; The second conversion circuit is connected to the first arithmetic circuit and is configured to process the write switch signal and provide the processed signal to the enable input terminal of the second arithmetic circuit; The second arithmetic circuit is connected to the second conversion circuit and is configured to generate a display switch signal through a logic operation under the trigger of the signal output by the second conversion circuit; Wherein, the signal transmission delay duration of the second conversion circuit is greater than the signal transmission delay duration of the first conversion circuit.

2. The gate driving circuit according to claim 1, wherein The write switch signal includes: alternating first pulse signals and second pulse signals; the effective level of the first pulse signal is configured to control the gate electrode of the driving transistor of the pixel circuit to write a bias voltage, and the effective level of the second pulse signal is configured to control the gate electrode of the driving transistor of the pixel circuit to write a data voltage; the duration of the effective level of the first pulse signal is less than or equal to the duration of the effective level of the second pulse signal; The effective level of the display switch signal is configured to control the driving transistor of the pixel circuit to perform self-discharge; Within one frame period, the end moment of the effective level of the first pulse signal of the write switch signal is earlier than or equal to the start moment of the effective level of the display switch signal; the end moment of the effective level of the display switch signal is later than the end moment of the effective level of the second pulse signal of the write switch signal.

3. The gate driving circuit according to claim 1, wherein The gate driving circuit further includes: a third conversion circuit, the third conversion circuit is connected to the second arithmetic circuit and is configured to process the display switch signal to generate a display switch drive signal provided to the pixel circuit.

4. The gate driving circuit according to claim 3, wherein The write switch drive signal includes alternating first pulse signals and second pulse signals; the write switch signal includes alternating first pulse signals and second pulse signals; the output signal of the second conversion circuit includes alternating first pulse signals and second pulse signals; There is a first delay duration between the end moment of the effective level of the first pulse signal of the write switch drive signal and the start moment of the effective level of the display switch drive signal; There is a second delay duration between the start moment of the effective level of the first pulse signal of the write switch signal and the start moment of the effective level of the first pulse signal of the output signal of the second conversion circuit; the ratio of the second delay duration to the first delay duration is greater than 0.9 and less than 1.

1.

5. The gate driving circuit according to claim 1, wherein The second conversion circuit includes: N inverters connected in series, and the value of N is an even number greater than 0.

6. The gate driving circuit according to claim 5, wherein The second conversion circuit includes: six inverters connected in series.

7. The gate driving circuit according to claim 5 or 6, characterized in that Each inverter in the second conversion circuit includes: a transistor group, which includes a P-type transistor and an N-type transistor. The gate electrode of the P-type transistor is connected to the gate electrode of the N-type transistor. The second pole of the P-type transistor is connected to the second pole of the N-type transistor. The first pole of the P-type transistor is connected to the first power supply line, and the first pole of the N-type transistor is connected to the ground wire.

8. The gate driving circuit according to claim 1, wherein The first conversion circuit includes: a first level converter and a first row driving enhancer; the first level converter is configured to perform voltage domain conversion on the write switch signal; the first row driving enhancer is connected to the first level converter and is configured to enhance the signal processed by the first level converter.

9. The gate driving circuit according to claim 1, wherein The first arithmetic circuit includes: a first NAND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a first NOR gate, a second NOR gate, a third NOR gate, and a two-way selector; The first input terminal of the first NAND gate is configured to receive a second timing signal, the second input terminal of the first NAND gate is configured to receive a third timing signal, the output terminal of the first NAND gate is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is configured to receive a first timing signal, the output terminal of the first NOR gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate is configured to receive a fourth timing signal, the output terminal of the second NOR gate is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the second input terminal of the two-way selector; the input terminal of the fourth inverter is configured to receive a second reset signal, the output terminal of the fourth inverter is connected to the second input terminal of the third NOR gate, the first input terminal of the third NOR gate is configured to receive a first reset signal, and the output terminal of the third NOR gate is connected to the control terminal of the two-way selector; the first input terminal of the two-way selector is configured to receive a first timing signal, and the output terminal of the two-way selector serves as the output terminal of the first arithmetic circuit.

10. The gate driving circuit according to claim 1, wherein The second arithmetic circuit includes: a latch, a fourth NOR gate, and a second NAND gate; The enable input terminal of the latch is connected to the output terminal of the second conversion circuit. The data input terminal of the latch is configured to receive a second timing signal. The output terminal of the latch is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth NOR gate is configured to receive a duty ratio control signal. The output terminal of the fourth NOR gate is connected to the first input terminal of the second NAND gate. The second input terminal of the second NAND gate is configured to receive a second reset signal. The output terminal of the second NAND gate serves as the output terminal of the second arithmetic circuit.

11. The gate driving circuit according to claim 10, wherein The latch includes: a fifteenth inverter, a third NAND gate, a fourth NAND gate, a fifth NAND gate, and a sixth NAND gate; The input terminal of the fifteenth inverter is connected to the first input terminal of the third NAND gate, serving as the data input terminal of the latch; the output terminal of the fifteenth inverter is connected to the first input terminal of the fourth NAND gate; the second input terminal of the third NAND gate is connected to the second input terminal of the fourth NAND gate, serving as the enable input terminal of the latch; The output terminal of the third NAND gate is connected to the first input terminal of the fifth NAND gate, and the output terminal of the third NAND gate is connected to the second input terminal of the sixth NAND gate; the second input terminal of the fifth NAND gate is connected to the output terminal of the sixth NAND gate, serving as the inverted output terminal of the latch; the first input terminal of the sixth NAND gate is connected to the output terminal of the fifth NAND gate, serving as the output terminal of the latch.

12. The gate driving circuit according to claim 10, wherein The fourth NOR gate includes: a sixteenth P-type transistor, a seventeenth P-type transistor, a sixteenth N-type transistor, and a seventeenth N-type transistor; The gate electrode of the sixteenth P-type transistor is connected to the gate electrode of the sixteenth N-type transistor, serving as the second input terminal of the fourth NOR gate; the gate electrode of the seventeenth P-type transistor is connected to the gate electrode of the seventeenth N-type transistor, serving as the first input terminal of the fourth NOR gate; The first pole of the sixteenth P-type transistor is connected to the first power supply line, and the second pole of the sixteenth P-type transistor is connected to the first pole of the seventeenth P-type transistor; the second pole of the seventeenth P-type transistor is connected to the second poles of the sixteenth N-type transistor and the seventeenth N-type transistor, serving as the output terminal of the fourth NOR gate; the first poles of the sixteenth N-type transistor and the seventeenth N-type transistor are both connected to the ground wire.

13. The gate driving circuit according to claim 10, wherein, The second NAND gate includes: an eighteenth P-type transistor, a nineteenth P-type transistor, an eighteenth N-type transistor, and a nineteenth N-type transistor; The gate electrode of the eighteenth P-type transistor is connected to the gate electrode of the eighteenth N-type transistor, serving as the first input terminal of the second NAND gate; the gate electrodes of the nineteenth P-type transistor and the nineteenth N-type transistor are connected, serving as the second input terminal of the second NAND gate; The first poles of the eighteenth P-type transistor and the nineteenth P-type transistor are connected to the first power supply line; the second poles of the eighteenth P-type transistor, the nineteenth P-type transistor, and the second pole of the eighteenth N-type transistor are connected, serving as the output terminal of the second NAND gate; the first pole of the nineteenth N-type transistor is connected to the ground wire, and the second pole of the nineteenth N-type transistor is connected to the first pole of the eighteenth N-type transistor.

14. The gate driving circuit according to claim 1, wherein The gate driving circuit further includes: a first test circuit and a second test circuit, the first test circuit is connected to the output terminal of the first arithmetic circuit, and the second test circuit is connected to the output terminal of the second arithmetic circuit; the first test circuit includes two inverters connected in series; the second test circuit includes two inverters connected in series.

15. A driving method for a gate driving circuit, characterized in that Applied to the gate driving circuit according to any one of claims 1 to 14; the driving method includes: The first arithmetic circuit generates a write switch signal through a logical operation, and the first conversion circuit processes the write switch signal to generate a write switch driving signal provided to the pixel circuit; The second conversion circuit processes the write switch signal and provides the processed signal to the enable input terminal of the second arithmetic circuit. The second arithmetic circuit generates a display switch signal through a logical operation under the trigger of the signal output by the second conversion circuit; Wherein, the signal transmission delay duration of the second conversion circuit is greater than that of the first conversion circuit.

16. A display substrate, characterized in that, It includes a display area and a non-display area; the display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the gate driving circuit according to any one of claims 1 to 15.

17. A display device, characterized in that, It includes the display substrate according to claim 16.

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